ASC protection circuit based on hardware circuit control, inverter, controller and vehicle

Abstract

The invention discloses an ASC protection circuit based on hardware circuit control, an inverter, a controller and a vehicle, and relates to the technical field of ASC protection, the ASC protection circuit comprises a charging delay module, an analog quantity to PWM signal conversion module and a PWM signal output module; the charging delay module takes an FLT fault signal as input, and when the FLT fault signal is at a high level, the charging delay module is charged through the FLT fault signal, so that the voltage of the analog-to-PWM signal conversion module is gradually increased to a first target voltage, and the duty ratio of a PWM signal output by the analog-to-PWM signal conversion module is gradually increased to a target duty ratio; and a PWM signal output end of the analog quantity to PWM signal conversion module is connected with the PWM signal output module, so that a signal output by the PWM signal output module controls the three-phase full-bridge IGBT, and the three-phase full-bridge IGBT is gradually transited to an ASC state. According to the invention, the large current peak can be effectively reduced while the vehicle enters the ASC state.

Description

Technical Field

[0001] The present invention relates to the technical field of ASC protection, and particularly to an ASC protection circuit, an inverter, a controller and a vehicle based on hardware circuit control. Background Art

[0002] The safety issue of new energy vehicles has always been a key concern for practitioners and consumers. As the power source of the vehicle, the safety of the electric drive system is even more crucial. Once a failure occurs in the electric drive system, it may result in a loss of power at best and vehicle damage and casualties at worst. Therefore, when a failure occurs in the electric drive system, it is necessary to actively protect the electric drive system. Among them, the two most common active protection measures are open circuit protection (FreeWheeling) and active short circuit (ASC).

[0003] When the vehicle is in a high-speed driving state, due to the excessive speed of the main drive motor, if blindly entering the FreeWheeling state at this time, it will cause a large amount of the main drive motor's generated current to flow back to the main drive inverter, resulting in a rapid increase in the bus voltage of the main drive inverter, exceeding the device withstand voltage value, and ultimately causing the main drive inverter to explode. If the vehicle suddenly enters the ASC state during high-speed driving, a short-term and huge current spike will often be generated on the main drive motor and flow back to the main drive inverter. If this current spike exceeds the safe operating area (SOA) of the insulated gate bipolar transistor (IGBT) module inside the main drive inverter, it will cause the IGBT to explode, resulting in the failure of the main drive inverter.

[0004] Therefore, when the vehicle is in a high-speed out-of-control state, how to achieve the two goals of the vehicle entering the ASC state while avoiding the large current spike generated by suddenly entering the ASC state is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0005] An embodiment of the present invention provides an ASC protection circuit, an inverter, a controller and a vehicle based on hardware circuit control, which can effectively reduce the large current spike while the vehicle enters the ASC state.

[0006] In a first aspect, the present invention provides an ASC protection circuit based on hardware circuit control, including a charging delay module, an analog-to-PWM signal conversion module and a PWM signal output module;

[0007] The charging delay module takes the FLT fault signal as the input. When the FLT fault signal is at a high level, the charging delay module is charged through the FLT fault signal, causing the voltage of the analog-to-PWM signal conversion module to gradually rise to the first target voltage, and the duty cycle of the PWM signal output by the analog-to-PWM signal conversion module to gradually increase to the target duty cycle;

[0008] The PWM signal output terminal of the analog-to-PWM signal conversion module is connected to the PWM signal output module, so that the signal output by the PWM signal output module controls the three-phase full-bridge IGBT, causing the three-phase full-bridge IGBT to gradually transition to the ASC state.

[0009] In some examples, the charging delay module includes a triode Q1, a first resistor R1, and a second capacitor C2;

[0010] The base of the triode Q1 is connected to the FLT fault signal, the emitter of the triode Q1 is connected to one end of the first resistor R1, the collector of the triode Q1 is connected to the first target voltage, the other end of the first resistor R1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded.

[0011] In some examples, the analog-to-PWM signal conversion module includes a first chip;

[0012] The VIN input terminal of the first chip is connected to one end of the second capacitor C2, and the VCC terminal of the first chip is connected to the second target voltage.

[0013] In some examples, the PWM signal output module includes a second chip;

[0014] The PWM signal output terminal of the first chip is connected to the input terminal of the second chip, the enable terminal of the second chip is connected to the FLT fault signal, and the output terminal of the second chip controls the on and off of each IGBT module in the three-phase full-bridge IGBT.

[0015] In some examples, the analog-to-PWM signal conversion module further includes: a first chip power supply capacitor C1;

[0016] The first chip power supply capacitor C1 is connected to the first chip.

[0017] In some examples, the PWM signal output module further includes a third chip power supply capacitor C3;

[0018] The third chip power supply capacitor C3 is connected to the second chip.

[0019] In some examples, the ASC protection circuit further includes: a second grounding resistor R2;

[0020] One end of the second grounding resistor R2 is connected to one end of the second capacitor C2 and the other end of the first resistor R1;

[0021] The other end of the second grounding resistor R2 is connected to the other end of the second capacitor C2 and grounded.

[0022] In a second aspect, the present invention provides a main drive inverter including any one of the above ASC protection circuits;

[0023] The three-phase terminals UVW of the permanent magnet synchronous motor in the main drive inverter are connected to the UVW terminals of the three-phase full-bridge IGBT, and the signal output by the PWM signal output module serves as the gate control signal of the three-phase full-bridge IGBT.

[0024] In a third aspect, the present invention provides a motor controller including the above main drive inverter.

[0025] In a fourth aspect, the present invention provides a vehicle including the above motor controller.

[0026] Generally speaking, compared with the prior art by the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0027] (1) The ASC protection circuit of the present invention is applied to the protection functions of the automotive main drive inverter and the main drive motor; when the vehicle is in a high-speed out-of-control state, the hardware circuit inside the vehicle main drive inverter directly controls the IGBT power module, so that even in the state where the software control instruction is out of control, the main drive inverter and the main drive motor can still orderly enter the ASC state; generally, entering the ASC state often generates huge current spikes on the main drive inverter and the main drive motor. The present invention can effectively reduce the large current spikes, thereby playing a protective role for the main drive inverter and the main drive motor.

[0028] (2) The IGBT is orderly controlled through the hardware circuit in the main drive inverter, so that the three-phase windings of the motor are actively short-circuited together to achieve effective and reliable motor protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1It is a schematic diagram of the ASC protection circuit controlled by a hardware circuit provided by an embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of the ASC protection circuit controlled by a hardware circuit provided by an embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram of the correspondence between the input VIN signal and the output PWM signal of the first chip U1 provided by an embodiment of the present invention;

[0033] Figure 4 It is a schematic diagram of the main drive inverter including the ASC protection circuit provided by an embodiment of the present invention;

[0034] Figure 5 It is a schematic diagram of the spike current generated when entering the ASC safe state provided by an embodiment of the present invention;

[0035] Figure 6 It is a schematic diagram of no spike current generated when entering the ASC safe state provided by an embodiment of the present invention. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0037] In the following description, specific embodiments of the present invention will be described with reference to steps and symbols executed by one or more computers, unless otherwise specified. Therefore, these steps and operations will be mentioned several times as being executed by a computer. As used herein, computer execution includes operations of a computer processing unit representing electronic signals in a structured form of data. This operation transforms the data or maintains it in a position in the computer's memory system, which can be reconfigured or otherwise changed in a manner well known to those skilled in the art to change the operation of the computer. The data structure in which the data is maintained is a physical location in the memory, which has specific characteristics defined by the data format. However, the principles of the present invention are described in the above text, which does not represent a limitation. Those skilled in the art will understand that the following various steps and operations can also be implemented in hardware.

[0038] As used herein, the terms "module" or "unit" may be regarded as software objects executed on the computing system. Different components, modules, engines, and services herein may be regarded as implementation objects on the computing system. The devices and methods herein are preferably implemented in software, but may also be implemented in hardware, all within the scope of protection of the present invention.

[0039] Those skilled in the art of this technology can understand that, unless specifically stated otherwise, the singular forms "a", "an", "" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present invention means the presence of features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of one or more related listed items.

[0040] In the first embodiment of the present invention, an ASC protection circuit based on hardware circuit control is provided, as Figure 1 shown, including: a charging delay module 101, an analog-to-PWM signal conversion module 102, and a PWM signal output module 103;

[0041] The charging delay module 101 takes the FLT fault signal as an input. When the FLT fault signal is at a high level, the charging delay module 101 is charged through the FLT (i.e., Fault) fault signal, so that the voltage of the analog-to-PWM signal conversion module 102 gradually rises to a first target voltage, and the duty cycle of the pulse width modulation signal (PulseWidth Modulation, PWM) signal output by the analog-to-PWM signal conversion module 102 gradually increases to a target duty cycle;

[0042] The PWM signal output terminal of the analog-to-PWM signal conversion module 102 is connected to the PWM signal output module 103, so that the signal output by the PWM signal output module 103 controls the three-phase full-bridge IGBT, and the three-phase full-bridge IGBT gradually transitions to the ASC state.

[0043] In some instances, as Figure 2 shown, the charging delay module 101 includes a triode Q1, a first resistor R1, and a second capacitor C2;

[0044] The base of the triode Q1 is connected to the FLT fault signal. The emitter of the triode Q1 is connected to one end of the first resistor R1. The collector of the triode Q1 is connected to the first target voltage. The other end of the first resistor R1 is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is grounded.

[0045] In some examples, such as Figure 2 shown, the analog-to-PWM signal conversion module 102 includes a first chip;

[0046] The VIN input terminal of the first chip is connected to one end of the second capacitor C2. The power supply voltage (VoltCurrent Condenser, VCC) terminal of the first chip is connected to the second target voltage.

[0047] In some examples, such as Figure 2 shown, the PWM signal output module 103 includes a second chip;

[0048] The PWM signal output terminal of the first chip is connected to the input terminal of the second chip. The enable terminal of the second chip is connected to the FLT fault signal. The output terminal of the second chip controls the on and off of each IGBT module in the three-phase full-bridge IGBT.

[0049] In some examples, such as Figure 2 shown, the analog-to-PWM signal conversion module 102 further includes: a first chip power supply capacitor C1;

[0050] The first chip power supply capacitor C1 is connected to the first chip.

[0051] In some examples, such as Figure 2 shown, the PWM signal output module 103 further includes a third chip power supply capacitor C3;

[0052] The third chip power supply capacitor C3 is connected to the second chip.

[0053] In some examples, such as Figure 2 shown, the above ASC protection circuit further includes: a second grounding resistor R2;

[0054] One end of the second grounding resistor R2 is connected to one end of the second capacitor C2 and the other end of the first resistor R1;

[0055] The other end of the second grounding resistor R2 is connected to the other end of the second capacitor C2 and grounded.

[0056] Through the above technical solutions in the embodiments of the present invention, when the vehicle is out of control, there will be such as Figure 3The FLT (i.e., Fault) fault signal in it, by introducing the control of the FLT signal to the triode Q1, enables the +5V power supply (i.e., the first target voltage) to charge the RC delay circuit composed of R1 and C2, causing the voltage of the VIN pin of the first chip U1 to slowly rise from 0V to 5V (i.e., the first target voltage). Correspondingly, the PWM duty cycle signal output by the PWM pin of the first chip U1 will also gradually increase from 0% to 100% (as Figure 3 shown). For the second chip U2, when the FLT signal is normal, it is at a low level, and the U2 enable signals ENA and ENB are also at a low level, and the U2 chip prohibits output. At this time, the hardware circuit cannot control the IGBT through the six signals UB, VB, WB, UT, VT, and WT; but when the FLT signal is triggered, it is at a high level. At this time, the hardware circuit can take over the control of the IGBT, and the PWM signal gradually increases from 0% to 100%. This gradual change process can effectively reduce the huge spike current generated when suddenly entering the ASC state, enabling the IGBT to gradually transition to the ASC state (as Figure 4 shown), so as to achieve the protection effect on the main drive inverter and the main drive motor.

[0057] In the second embodiment of the present invention, a hardware protection circuit triggered based on the FLT fault signal is provided, which is independent of the space vector pulse width modulation (SVPWM) control of the single-chip microcomputer software, as Figure 2 shown. The invention mainly includes a triode Q1, an RC charging delay circuit composed of a first resistor R1 and a second capacitor C2, a second grounding resistor R2, a conversion chip U1 for converting analog quantity to PWM signal, a PWM signal output chip U2, and two chip power supply capacitors, a first power supply capacitor C1 and a third power supply capacitor C3. The connection method of each component in the circuit can refer to the description of Embodiment 1.

[0058] In the embodiment of the present invention, through the above protection circuit: the +5V power supply conducts through the triode Q1 and flows through the first resistor R1 to charge the second capacitor C2. The two form an RC charging circuit. The voltage on the second capacitor C2 follows the time formula U = 5*(1 - e^(-t / R*C)). It can be charged to 3.16V in 10ms, 4.32V in 20ms, 4.75V in 30ms, and fully charged to 5V in 100ms. The principle of the first U1 chip is to convert the input analog quantity of 0 - 5V (i.e., VIN) into an output signal with a duty cycle of 0 - 100% (i.e., PWM). Therefore, the duty cycle corresponding to 10ms is 63%, the duty cycle corresponding to 20ms is 86%, the duty cycle corresponding to 30ms is 95%, and the duty cycle corresponding to 100ms is 100%. When the duty cycle reaches 100%, the IGBT completely enters the ASC safe state. The invention of this protection circuit makes the process of the IGBT switching to the ASC state smoother, avoids the generation of peak current, and effectively protects the IGBT power device.

[0059] The detailed control method of the above ASC protection circuit in the embodiment of the present invention is as follows:

[0060] 1. When a high-speed moving vehicle suddenly gets out of control, and then the FLT signal is triggered. The voltage of the FLT signal changes from 0V to 5V.

[0061] 2. At this time, the FLT signal makes the triode Q1 conduct; at the same time, the FLT signal also enables the second chip U2, enabling the second chip U2 to work normally (in the normal working state, the pin voltages of the chip are A1 = YA1, A2 = YA2, A3 = YA3, B1 = YB1, B2 = YB2, B3 = YB3). The six signals UB, VB, WB, UT, VT, WT output can be used to control the on and off of the IGBT (conducting at high level and turning off at low level).

[0062] 3. After Q1 conducts, the +5V power supply charges the second capacitor C2 through the current-limiting resistor R1. The voltage of the C2 capacitor (equivalent to the VIN pin voltage of the second chip U1) will slowly rise from 0V to 5V. The voltage on the second capacitor C2 follows the time formula U = 5*(1 - e^(-t / R*C)). It can be charged to 3.16V in 10ms, 4.32V in 20ms, 4.75V in 30ms, and fully charged to 5V in 100ms. The VIN pin voltage will form a first-order charging curve.

[0063] 4. When the input pin VIN voltage of the chip U1 slowly rises from 0V to 5V, the duty cycle of the output pin PWM will also gradually rise from 0% to 100% (as Figure 3) Through calculation, the output duty cycle corresponding to 10 ms is 63%, the output duty cycle corresponding to 20 ms is 86%, the output duty cycle corresponding to 30 ms is 95%, and the output duty cycle corresponding to 100 ms is 100%. Therefore, the input signals Duty of A1, A2, and A3 of the second chip U2 will form a duty cycle signal with a gradually increasing duty cycle (0% → 63% → 86% → 95% → 100%). Similarly, the output signals UB, VB, and WB of YA1, YA2, and YA3 of the second chip U2 are also the same duty cycle signal with a gradually increasing duty cycle;

[0064] 5. At this time, the input signals B1, B2, and B3 of the second chip U2 are equal to 0V due to being grounded. Therefore, the corresponding output signals UT, VT, and WT output low levels, and these 3 signals keep the 3 upper bridges of the IGBT in the off state (as Figure 4 );

[0065] 6. As described before, the input signals Duty of A1, A2, and A3 of the second chip U2 will gradually transition from 0V to 5V. Then, the corresponding 3 signals UB, VB, and WB will also gradually transition from 0V to 5V; Therefore, the 3 lower bridges of the IGBT will gradually transition from the off state to the on state (as Figure 4 ), and finally reach the safe state of ASC;

[0066] In the third embodiment of the present invention, a main drive inverter including the ASC protection circuit of the above embodiment is provided. As Figure 4 shown, the three-phase terminals UVW of the permanent magnet synchronous motor in the main drive inverter are connected to the UVW terminals of the three-phase full-bridge IGBT. The signal output by the PWM signal output module is used as the gate control signal of the three-phase full-bridge IGBT. The turn-on and turn-off of the three-phase full-bridge IGBT are controlled by these 6 gate signals UT, UB, VT, VB, WT, and WB. And as Figure 2 in the hardware circuit, these 6 gate signals can be controlled to make the lower three bridges of UB, VB, and WB conduct and the upper three bridges of UT, VT, and WT disconnect, so that the three-phase terminals UVW of the motor are short-circuited, and finally enter the ASC safe state. Figure 2The main principle of the hardware circuit: When the +5V power supply conducts through the triode Q1, it flows through the first resistor R1 to charge the second capacitor C2. The two form an RC charging circuit. The voltage on the second capacitor C2 follows the time formula U = 5*(1 - e^(-t / R*C)). It can be charged to 3.16V in 10ms, 4.32V in 20ms, 4.75V in 30ms, and fully charged to 5V in 100ms. The principle of the U1 chip is to convert the input analog quantity (VIN) from 0 to 5V into an output signal (PWM) with a duty cycle from 0 to 100%. Therefore, the duty cycle corresponding to 10ms is 63%, the duty cycle corresponding to 20ms is 86%, the duty cycle corresponding to 30ms is 95%, and the duty cycle corresponding to 100ms is 100%. When the duty cycle reaches 100%, the IGBT completely enters the ASC safety state. The invention of this control circuit makes the process of the IGBT switching to the ASC state smoother, avoids the generation of peak current, and effectively protects the IGBT power device.

[0067] The embodiment of the present invention passes through Figure 4 The detailed control method shown is as follows:

[0068] 1. When a high-speed vehicle suddenly gets out of control, the FLT signal is triggered. The voltage of the FLT signal changes from 0V to 5V;

[0069] 2. At this time, the FLT signal makes the triode Q1 conduct; at the same time, the FLT signal also enables the second chip U2, enabling the second chip U2 to work normally (in the normal working state, the pin voltages of the chip are A1 = YA1, A2 = YA2, A3 = YA3, B1 = YB1, B2 = YB2, B3 = YB3). The six signals UB, VB, WB, UT, VT, and WT output can be used to control the on and off of the IGBT (high level conducts, low level turns off);

[0070] 3. After Q1 conducts, the +5V power supply charges the second capacitor C2 through the current-limiting resistor R1. The voltage of the C2 capacitor (equivalent to the VIN pin voltage of the second chip U1) will slowly rise from 0V to 5V. The voltage on the second capacitor C2 follows the time formula U = 5*(1 - e^(-t / R*C)). It can be charged to 3.16V in 10ms, 4.32V in 20ms, 4.75V in 30ms, and fully charged to 5V in 100ms. The VIN pin voltage will form a first-order charging curve;

[0071] 4. When the input pin VIN voltage of the chip U1 slowly rises from 0V to 5V, the duty cycle of the output pin PWM will also gradually rise from 0% to 100% (as Figure 3), It can be calculated that the output duty cycle corresponding to 10 ms is 63%, the output duty cycle corresponding to 20 ms is 86%, the output duty cycle corresponding to 30 ms is 95%, and the output duty cycle corresponding to 100 ms is 100%. Therefore, the input signals Duty of A1, A2, and A3 of the second chip U2 will form a duty cycle signal with a gradually increasing duty cycle (0% → 63% → 86% → 95% → 100%). Similarly, the output signals UB, VB, and WB of YA1, YA2, and YA3 of the second chip U2 are also the same duty cycle signal with a gradually increasing duty cycle;

[0072] 5. At this time, the input signals B1, B2, and B3 of the second chip U2 are grounded and equal to 0V. Therefore, the corresponding output signals UT, VT, and WT output low levels, and these 3 signals keep the 3 upper bridges of the IGBT in the off state (as Figure 4 );

[0073] 6. As mentioned before, the input signals Duty of A1, A2, and A3 of the second chip U2 will gradually transition from 0V to 5V. Then, the corresponding 3 signals UB, VB, and WB will also gradually transition from 0V to 5V; Therefore, the 3 lower bridges of the IGBT will gradually transition from the off state to the on state (as Figure 4 ), and finally reach the safe state of ASC;

[0074] It should be emphasized that: This invention can effectively reduce the huge peak current generated when entering ASC. Generally, the conventional method of entering the ASC state is to directly switch the lower three bridges of the IGBT from the off state to the continuous on state. Therefore, a peak current of 2 times or even higher will be generated (as Figure 5 ), and this current peak has the risk of exceeding the safe operating area of the IGBT. Over time, it will cause the IGBT to explode and fail. However, in this invention, the IGBT gradually transitions from the off state of the lower three bridges to the on state. This method can very effectively solve the problem of current peaks (as Figure 6 ), avoid the risk of IGBT explosion, and effectively extend the service life of the electric drive system.

[0075] In the fourth embodiment of the present invention, a motor controller including the above main area inverter is also provided.

[0076] In the fifth embodiment of the present invention, a vehicle including the above motor controller is also provided.

[0077] In several embodiments provided by the present invention, it should be understood that the disclosed devices, etc., can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation.

[0078] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0079] In addition, each functional unit in various embodiments of the present invention may be integrated into a processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a hardware plus software functional unit.

[0080] The above integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above software functional unit stored in a storage medium includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute some steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0081] The above has introduced in detail an ASC protection circuit, an inverter, a controller, and a vehicle based on hardware circuit control provided by the embodiments of the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An ASC protection circuit based on hardware circuit control, characterized in that, Including: A charging delay module, an analog-to-PWM signal conversion module, and a PWM signal output module; The charging delay module takes the FLT fault signal as an input. When the FLT fault signal is at a high level, the charging delay module is charged through the FLT fault signal, causing the voltage of the analog-to-PWM signal conversion module to gradually rise to a first target voltage, and the duty cycle of the PWM signal output by the analog-to-PWM signal conversion module to gradually increase to a target duty cycle; The PWM signal output terminal of the analog-to-PWM signal conversion module is connected to the PWM signal output module, enabling the signal output by the PWM signal output module to control the three-phase full-bridge IGBT, causing the three-phase full-bridge IGBT to gradually transition to the ASC state.

2. The ASC protection circuit according to claim 1, wherein The charging delay module includes a triode Q1, a first resistor R1, and a second capacitor C2; The base of the triode Q1 is connected to the FLT fault signal, the emitter of the triode Q1 is connected to one end of the first resistor R1, the collector of the triode Q1 is connected to the first target voltage, the other end of the first resistor R1 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is grounded.

3. The ASC protection circuit according to claim 2, wherein The analog-to-PWM signal conversion module includes a first chip; The VIN input terminal of the first chip is connected to one end of the second capacitor C2, and the VCC terminal of the first chip is connected to a second target voltage.

4. The ASC protection circuit according to claim 3, wherein The PWM signal output module includes a second chip; The PWM signal output terminal of the first chip is connected to the input terminal of the second chip, the enable terminal of the second chip is connected to the FLT fault signal, and the output terminal of the second chip controls the on / off of each IGBT module in the three-phase full-bridge IGBT.

5. The ASC protection circuit according to claim 4, wherein The analog-to-PWM signal conversion module further includes: a first chip power supply capacitor C1; The first chip power supply capacitor C1 is connected to the first chip.

6. The ASC protection circuit according to claim 5, wherein The PWM signal output module further includes a third chip power supply capacitor C3; The third chip power supply capacitor C3 is connected to the second chip.

7. The ASC protection circuit according to claim 6, characterized in that, The ASC protection circuit further includes: a second grounding resistor R2; One end of the second grounding resistor R2 is connected to one end of the second capacitor C2 and the other end of the first resistor R1; The other end of the second grounding resistor R2 is connected to the other end of the second capacitor C2 and grounded.

8. A main drive inverter including the ASC protection circuit according to any one of claims 1 to 7; The three-phase terminals UVW of the permanent magnet synchronous motor in the main drive inverter are connected to the UVW terminals of the three-phase full-bridge IGBT, and the signal output by the PWM signal output module serves as the gate control signal of the three-phase full-bridge IGBT.

9. A motor controller including the main area inverter according to claim 8.

10. A vehicle including the motor controller according to claim 9.

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