Level shift circuit with dV / dt noise resistance

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an anti-dV / dt noise level shift circuit which comprises a power rail conversion module, a positive feedback latch module, a dynamic current branch module and a bias current circuit module. The power rail conversion module converts a control signal from a low-level voltage area to a high-level voltage area. The positive feedback latch module stabilizes an output signal at a set level value; the dynamic current branch module provides current to charge a node capacitor, so that the dv / dt noise resistance of the level shift circuit is improved; the bias current circuit module provides bias current for the positive feedback latch module, controls latch strength and reduces delay time. According to the level shift circuit, by means of dynamic current and diode voltage clamping, the dV / dt noise resistance of the circuit is greatly enhanced, and under the normal condition, operation of the level shift circuit cannot be affected, and extra quiescent current cannot be consumed.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a level-shifting circuit with anti-dV / dt noise. Background Art

[0002] A level-shifting circuit is a key circuit module in analog integrated circuits and is widely used in half-bridge drive circuits and DC-DC converters. It can realize the conversion of a control signal from a low-voltage domain to a high-voltage domain. However, the dV / dt change caused by the fast switching of MOS power transistors can be coupled to the level-shifting circuit through a bootstrap capacitor, which may cause the output of the level-shifting circuit to flip and lead to a logic error in the drive circuit. Therefore, it is very necessary to implement a level-shifting circuit with anti-dV / dt noise. Summary of the Invention

[0003] To solve the above technical problems, the present invention provides a level-shifting circuit with anti-dV / dt noise, including: a power rail conversion module, a positive feedback latch module, a dynamic current branch module, and a bias current circuit module;

[0004] The power rail conversion module converts the control signal from a low-level voltage region to a high-level voltage region;

[0005] The positive feedback latch module stabilizes the output signal at a set level value;

[0006] The dynamic current branch module provides current to charge the node capacitor and improves the anti-dv / dt noise ability of the level-shifting circuit;

[0007] The bias current circuit module provides a bias current for the positive feedback latch module to control the latching strength and reduce the delay time.

[0008] Advantages of the Present Invention

[0009] By using dynamic current and diode voltage clamping, the present invention greatly enhances the anti-dV / dt noise ability of the circuit, and under normal circumstances, does not affect the operation of the level-shifting circuit and does not consume additional static current. Description of the Drawings

[0010] Figure 1 It is a schematic diagram of a level-shifting circuit with anti-dV / dt noise according to the present invention. Detailed Embodiment

[0011] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0012] Figure 1 The schematic diagram of a level-shifting circuit with anti-dV / dt noise is given. The circuit includes a power supply rail conversion module, a positive feedback latch module, a dynamic current branch module, and a bias current circuit module. Among them, the power supply rail conversion module converts the control signal from the low-level voltage region to the high-level voltage region; the positive feedback latch module stabilizes the output signal at the set level value; the dynamic current branch module provides current to charge the node capacitor, improving the anti-dv / dt noise ability of the level-shifting circuit; the bias current circuit module provides a bias current for the positive feedback latch module to control the latch strength and reduce the delay time.

[0013] The power supply rail conversion module includes a second NMOS transistor, a third NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a first N-type LDMOS transistor, a second N-type LDMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a first capacitor, a second capacitor, a fourth resistor, and a fifth resistor.

[0014] The gate of the second NMOS transistor is connected to SW, its source is connected to SW, and its drain is connected to the gates and drains of the third PMOS transistor, the fourth PMOS transistor, the twelfth PMOS transistor, the eighth PMOS transistor, the eleventh PMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor; the gate of the third NMOS transistor is connected to the gates and drains of the fourth NMOS transistor and the fifth PMOS transistor, its source is connected to SW, and its drain is connected to the upper end of the fourth resistor, the drain of the fourth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor; the gate of the tenth NMOS transistor is connected to the gates and drains of the ninth NMOS transistor and the eighth PMOS transistor, its source is connected to SW, and its drain is connected to the drain of the ninth PMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, and the lower end of the fifth resistor; the gate and source of the eleventh NMOS transistor are connected to SW, and its drain is connected to the gates of the ninth PMOS transistor, the tenth PMOS transistor, the second PMOS transistor, the fifth PMOS transistor, the fifteenth PMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor; the gate of the twelfth NMOS transistor is connected to LD1, its source is connected to the drain of the thirteenth NMOS transistor, and its drain is connected to the source of the first N-type LDMOS transistor and the drain of the sixteenth PMOS transistor; the gate of the thirteenth NMOS transistor is connected to LD1, its source is connected to GND, and its drain is connected to the source of the twelfth NMOS transistor; the gate of the fourteenth NMOS transistor is connected to LD2, its source is connected to the drain of the fifteenth NMOS transistor, and its drain is connected to the source of the second N-type LDMOS transistor and the drain of the seventeenth PMOS transistor; the gate of the fifteenth NMOS transistor is connected to LD2, its source is connected to GND, and its drain is connected to the source of the fourteenth NMOS transistor; the gate of the first N-type LDMOS transistor is connected to VCC, its source is connected to the drain of the sixteenth PMOS transistor and the drain of the twelfth NMOS transistor, and its drain is connected to the gates and drains of the third PMOS transistor, the fourth PMOS transistor, the twelfth PMOS transistor, the eighth PMOS transistor, the eleventh PMOS transistor, the drain of the second NMOS transistor, and the upper plate of the first capacitor; the gate of the second N-type LDMOS transistor is connected to VCC, its source is connected to the drain of the seventeenth PMOS transistor and the drain of the fourteenth NMOS transistor, and its drain is connected to the gates and drains of the tenth PMOS transistor, the ninth PMOS transistor, the second PMOS transistor, the fifth PMOS transistor, the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, and the upper plate of the second capacitor;The gate and drain of the third PMOS transistor are connected to the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, and its source is connected to BST; the gate of the fourth PMOS transistor is connected to the gate and drain of the third PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the upper end of the fourth resistor, the drain of the third NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor; the gate of the ninth PMOS transistor is connected to the gate and drain of the tenth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the drain of the tenth NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, and the lower end of the fifth resistor; the gate and drain of the tenth PMOS transistor are connected to the gate of the ninth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, and its source is connected to BST; the gate and source of the sixteenth PMOS transistor are connected to VCC, and its drain is connected to the drain of the twelfth NMOS transistor and the source of the first N-type LDMOS transistor; the gate and source of the seventeenth PMOS transistor are connected to VCC, and its drain is connected to the drain of the fourteenth NMOS transistor and the source of the second N-type LDMOS transistor; the upper plate of the first capacitor is connected to the drain of the first N-type LDMOS transistor, the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, and the drain of the second NMOS transistor, and its lower plate is connected to GND; the upper plate of the second capacitor is connected to the drain of the second N-type LDMOS transistor, the gate and drain of the tenth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, and the drain of the eleventh NMOS transistor, and its lower plate is connected to GND; the upper end of the fourth resistor is connected to HLSP, and its lower end is connected to SW; the upper end of the fifth resistor is connected to BST, and its lower end is connected to HLSN.;

[0015] The positive feedback latch module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor.

[0016] The gate of the fifth NMOS transistor is connected to the gates of the thirteenth PMOS transistor and the fourteenth PMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, and the drain of the tenth NMOS transistor. Its source is connected to the drain of the seventh NMOS transistor, and its drain is connected to the drain of the thirteenth PMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, the drain of the third NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fourteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, and the drain of the third NMOS transistor. Its source is connected to the drain of the eighth NMOS transistor, and its drain is connected to the drain of the fourteenth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, and the drain of the tenth NMOS transistor. The gate of the seventh NMOS transistor is connected to the gate and drain of the first NMOS transistor and the gate of the eighth NMOS transistor. Its source is connected to SW, and its drain is connected to the source of the fifth NMOS transistor. The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, the gate, and drain of the first NMOS transistor. Its source is connected to SW, and its drain is connected to the source of the sixth NMOS transistor. The gate of the sixth PMOS transistor is connected to the gate and drain of the first PMOS transistor and the gate of the seventh PMOS transistor. Its source is connected to BST, and its drain is connected to the source of the thirteenth PMOS transistor. The gate of the seventh PMOS transistor is connected to the gate and drain of the first PMOS transistor and the gate of the sixth PMOS transistor. Its source is connected to BST, and its drain is connected to the source of the fourteenth PMOS transistor. The gate of the thirteenth PMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the lower end of the fifth resistor, the drain end of the ninth PMOS transistor, and the drain end of the tenth NMOS transistor. Its source is connected to the drain of the sixth PMOS transistor, and its drain is connected to the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, the drain of the third NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor. The gate of the fourteenth PMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, and the drain of the third NMOS transistor. Its source is connected to the drain of the seventh PMOS transistor, and its drain is connected to the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, and the drain of the tenth NMOS transistor.

[0017] The dynamic current branch module includes a fourth NMOS transistor, a ninth NMOS transistor, a second PMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a fifteenth PMOS transistor.

[0018] The gate and drain of the fourth NMOS transistor are connected to the gate of the third NMOS transistor and the drain of the fifth PMOS transistor, and its source is connected to SW; the gate and drain of the ninth NMOS transistor are connected to the gate of the tenth NMOS transistor and the drain of the eighth PMOS transistor, and its source is connected to SW; the gate of the second PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate of the ninth PMOS transistor, the gate and drain of the tenth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the source of the twelfth PMOS transistor; the gate of the fifth PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the ninth PMOS transistor, the gate and drain of the tenth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the gate and drain of the fourth NMOS transistor and the gate of the third NMOS; the gate of the eighth PMOS transistor is connected to the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the gate and drain of the ninth NMOS transistor and the gate of the tenth NMOS transistor; the gate of the eleventh PMOS transistor is connected to the gate of the eighth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, its source is connected to BST, and its drain is connected to the source of the fifteenth PMOS transistor; the gate and drain of the twelfth PMOS transistor are connected to the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, its source is connected to the drain of the second PMOS transistor; the gate and drain of the fifteenth PMOS transistor are connected to the gate and drain of the tenth PMOS transistor, the gate of the ninth PMOS transistor, the drain of the eleventh NMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, its source is connected to the drain of the eleventh PMOS transistor.

[0019] The bias current circuit module includes a first NMOS transistor, a first PMOS transistor, a first resistor, a second resistor, and a third resistor.

[0020] The gate and drain of the first NMOS transistor are connected to the lower end of the second resistor and the gates of the seventh NMOS transistor and the eighth NMOS transistor, and its source is connected to the upper end of the third resistor; the gate and drain of the first PMOS transistor are connected to the upper end of the second resistor and the gates of the sixth PMOS transistor and the seventh PMOS transistor, and its source is connected to the lower end of the first resistor; the upper end of the first resistor is connected to BST, and its lower end is connected to the source of the first PMOS transistor; the upper end of the second resistor is connected to the gate and drain of the first PMOS transistor and the gates of the sixth PMOS transistor and the seventh PMOS transistor, and its lower end is connected to the gate and drain of the first NMOS transistor and the gates of the seventh NMOS transistor and the eighth NMOS transistor; the upper end of the third resistor is connected to the source of the first NMOS transistor, and its lower end is connected to SW.

[0021] Among them, the signal input logic signal LD1 and the signal input logic signal LD2 are pulse signals with opposite phases. When the signal input logic signal LD1 is at a high level and the signal input logic signal LD2 is at a low level, the node X is at a low level at this time, the third PMOS transistor and the fourth PMOS transistor are turned on, and the node power rail output signal HLSP is inverted from the switch node voltage SW to the bootstrap capacitor voltage BST. The node power rail output signal HLSP is at a high potential, the fourteenth PMOS transistor is turned off, and the sixth NMOS transistor is turned on. The node power rail output signal HLSN is inverted from the bootstrap capacitor voltage BST to the switch node voltage SW. When the potential of the switch node voltage SW increases due to dv / dt noise, the potential of the bootstrap capacitor voltage BST also increases immediately, and the current I1 increases. At this time, the dynamic current branch will provide a dynamic current to charge the node X and the node Y, increasing the voltages of the node X and the node Y, and improving the ability of the level shift circuit to resist dv / dt noise.

[0022] Specific working principle: The signal input logic signal LD1 and the signal input logic signal LD2 are pulse signals with opposite phases. The signal power rail output signal HLSP and the signal power rail output signal HLSN are respectively initialized to the switch node voltage SW and the bootstrap capacitor voltage BST potential by the fourth resistor and the fifth resistor. The first resistor, the third resistor, the first PMOS transistor, and the first NMOS transistor form a bias current circuit of the level shift circuit, providing current for the positive feedback level shift circuit. The latch structure current is obtained by the sixth PMOS transistor, the seventh PMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor through the bias circuit. When the upper power transistor is to be turned on, the signal input logic signal LD1 flips from low level to high level, and the twelfth NMOS transistor and the thirteenth NMOS transistor conduct. At this time, the first N-type LDMOS transistor conducts and pulls down the potential of the X node, the current I1 increases, and the current generated by the fourth PMOS transistor through the current mirror also increases accordingly. Therefore, the signal power rail output signal HLSP flips from the potential of the switch node voltage SW to the potential of the bootstrap capacitor voltage BST. The signal input logic signal LD2 flips from high level to low level, and the fourteenth NMOS transistor and the fifteenth NMOS transistor turn off. At this time, the second N-type LDMOS transistor also turns off, and the Y node is in a high impedance state. Therefore, the flip of the signal power rail output signal HLSN at this time is controlled by the signal power rail output signal HLSP. The signal power rail output signal HLSP flips to high level, the fourteenth PMOS transistor turns off, and the sixth NMOS transistor conducts. Therefore, the signal power rail output signal HLSN flips from the potential of the bootstrap capacitor voltage BST to the potential of the switch node voltage SW. The output logic signal of this level shift circuit is obtained from the signal power rail output signal HLSN through an inverter.

[0023] Working principle for achieving the ability to resist dv / dt noise: When the potential of the switch node voltage SW increases due to dv / dt noise, the potential of the bootstrap capacitor voltage BST also increases accordingly. Since the current I1 increases, it causes the potential of the node power rail output signal HLSP to increase, thus generating an incorrect trigger signal. Therefore, a dynamic current branch composed of the second PMOS transistor, the twelfth PMOS transistor, the eleventh PMOS transistor, and the fifteenth PMOS transistor is used to resist the interference of noise. When the potential of the bootstrap capacitor voltage BST increases, the second PMOS transistor, the twelfth PMOS transistor, the eleventh PMOS transistor, and the fifteenth PMOS transistor conduct. At this time, the dynamic current branch will provide a dynamic current to charge the node X and the node Y through the first capacitor and the second capacitor respectively, increasing the voltages of the node X and the node Y, thereby reducing the current I1 and restoring the normal potential of the node potential power rail output signal HLSP, improving the ability of the level shift circuit to resist dv / dt noise.

[0024] Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An electric level shift circuit with anti-dV / dt noise, characterized in that, Comprising: A power rail conversion module, a positive feedback latch module, a dynamic current branch module, and a bias current circuit module; The power rail conversion module converts the control signal from a low voltage region to a high voltage region; The positive feedback latch module stabilizes the output signal at a set level value; The dynamic current branch module provides current to charge the node capacitance, improving the ability of the level shift circuit to resist dv / dt noise; The bias current circuit module provides a bias current for the positive feedback latch module, controlling the latch strength and reducing the delay time.

2. The level shifting circuit with anti-dV / dt noise according to claim 1, wherein, The power rail conversion module includes: a second NMOS transistor, a third NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a first N-type LDMOS transistor, a second N-type LDMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a first capacitor, a second capacitor, a fourth resistor, and a fifth resistor; The gate and source of the second NMOS transistor are connected to the switch node voltage SW, and its drain is connected to the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor; The gate of the third NMOS transistor is connected to the gate and drain of the fourth NMOS transistor and the drain of the fifth PMOS transistor, its source is connected to the switch node voltage SW, and its drain is connected to the upper end of the fourth resistor, the drain of the fourth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor; The gate of the tenth NMOS transistor is connected to the gate and drain of the ninth NMOS transistor and the drain of the eighth PMOS transistor, its source is connected to the switch node voltage SW, and its drain is connected to the drain of the ninth PMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, and the lower end of the fifth resistor; The gate and source of the eleventh NMOS transistor are connected to the switch node voltage SW, and its drain is connected to the gate of the ninth PMOS transistor, the gate and drain of the tenth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor; The gate of the twelfth NMOS transistor is connected to the input logic signal LD1, its source is connected to the drain of the thirteenth NMOS transistor, and its drain is connected to the source of the first N-type LDMOS and the drain of the sixteenth PMOS transistor; The gate of the thirteenth NMOS transistor is connected to the input logic signal LD1, its source is connected to the ground terminal GND, and its drain is connected to the source of the twelfth NMOS transistor; The gate of the fourteenth NMOS transistor is connected to the input logic signal LD2, its source is connected to the drain of the fifteenth NMOS transistor, and its drain is connected to the source of the second N-type LDMOS and the drain of the seventeenth PMOS transistor; The gate of the fifteenth NMOS transistor is connected to the input logic signal LD2, its source is connected to GND, and its drain is connected to the source of the fourteenth NMOS transistor; The gate of the first N-type LDMOS transistor is connected to the internal power supply voltage VCC, its source is connected to the drain of the sixteenth PMOS transistor and the drain of the twelfth NMOS transistor, and its drain is connected to the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, and the upper plate of the first capacitor; The gate of the second N-type LDMOS transistor is connected to the internal power supply voltage VCC, its source is connected to the drain of the seventeenth PMOS transistor and the drain of the fourteenth NMOS transistor, and its drain is connected to the gate and drain of the tenth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, and the upper plate of the second capacitor; The gate and drain of the third PMOS transistor are connected to the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, and its source is connected to the bootstrap capacitor voltage BST; The gate of the fourth PMOS transistor is connected to the gate and drain of the third PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the upper end of the fourth resistor, the drain of the third NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor; The gate of the ninth PMOS transistor is connected to the gate and drain of the tenth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the drain of the tenth NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, and the lower end of the fifth resistor; The gate and drain of the tenth PMOS transistor are connected to the gate of the ninth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor, and its source is connected to the bootstrap capacitor voltage BST; The gate and source of the sixteenth PMOS transistor are connected to the internal power supply voltage VCC, and its drain is connected to the drain of the twelfth NMOS transistor and the source of the first N-type LDMOS transistor; The gate and source of the seventeenth PMOS transistor are connected to the internal power supply voltage VCC, and its drain is connected to the drain of the fourteenth NMOS transistor and the source of the second N-type LDMOS transistor; The upper plate of the first capacitor is connected to the drain of the first N-type LDMOS transistor, the gate and drain of the third PMOS transistor, the gate of the fourth PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the eighth PMOS transistor, the gate of the eleventh PMOS transistor, and the drain of the second NMOS transistor, and its lower plate is connected to the ground terminal GND; The upper plate of the second capacitor is connected to the drain of the second N-type LDMOS transistor, the gate and drain of the tenth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, and the drain of the eleventh NMOS transistor, and its lower plate is connected to GND; The upper end of the fourth resistor is connected to the power rail output signal HLSP, and its lower end is connected to the switch node voltage SW; The upper end of the fifth resistor is connected to the bootstrap capacitor voltage BST, and its lower end is connected to the power rail output signal HLSN.

3. The level-shifting circuit with anti-dV / dt noise according to claim 1, characterized in that The positive feedback latch module includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor; The gate of the fifth NMOS transistor is connected to the gate of the thirteenth PMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, and the drain of the tenth NMOS transistor. Its source is connected to the drain of the seventh NMOS transistor, and its drain is connected to the drain of the thirteenth PMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, the drain of the third NMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the sixth NMOS transistor; The gate of the sixth NMOS transistor is connected to the gate of the fourteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, and the drain of the third NMOS transistor. Its source is connected to the drain of the eighth NMOS transistor, and its drain is connected to the drain of the fourteenth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, and the drain of the tenth NMOS transistor; The gate of the seventh NMOS transistor is connected to the gate and drain of the first NMOS transistor and the gate of the eighth NMOS transistor. Its source is connected to the switch node voltage SW, and its drain is connected to the source of the fifth NMOS transistor; The gate of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor and the gate and drain of the first NMOS transistor. Its source is connected to the switch node voltage SW, and its drain is connected to the source of the sixth NMOS transistor; The gate of the sixth PMOS transistor is connected to the gate and drain of the first PMOS transistor and the gate of the seventh PMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the source of the thirteenth PMOS transistor; The gate of the seventh PMOS transistor is connected to the gate and drain of the first PMOS transistor and the gate of the sixth PMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the source of the fourteenth PMOS transistor; The gate of the thirteenth PMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fourteenth PMOS transistor, the drain of the sixth NMOS transistor, the lower end of the fifth resistor, the drain terminal of the ninth PMOS transistor, the drain terminal of the tenth NMOS transistor, its source is connected to the drain of the sixth PMOS transistor, and its drain is connected to the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, the drain of the third NMOS transistor, the gate of the fourteenth PMOS transistor, the gate of the sixth NMOS transistor; The gate of the fourteenth PMOS transistor is connected to the gate of the sixth NMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the fourth PMOS transistor, the upper end of the fourth resistor, the drain of the third NMOS transistor, its source is connected to the drain of the seventh PMOS transistor, and its drain is connected to the drain of the sixth NMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the fifth NMOS transistor, the lower end of the fifth resistor, the drain of the ninth PMOS transistor, the drain of the tenth NMOS transistor.

4. The level shifting circuit with anti-dV / dt noise according to claim 1, wherein The dynamic current branch module includes: a fourth NMOS transistor, a ninth NMOS transistor, a second PMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a fifteenth PMOS transistor; The gate and drain of the fourth NMOS transistor are connected to the gate of the third NMOS transistor and the drain of the fifth PMOS transistor, and its source is connected to the switch node voltage SW; The gate and drain of the ninth NMOS transistor are connected to the gate of the tenth NMOS transistor and the drain of the eighth PMOS transistor, and its source is connected to the switch node voltage SW; The gate of the second PMOS transistor is connected to the gate of the fifth PMOS transistor, the gate of the ninth PMOS transistor, the gate and drain of the tenth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, the drain of the second N-type LDMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the source of the twelfth PMOS transistor; The gate of the fifth PMOS transistor is connected to the gate of the second PMOS transistor, the gate of the ninth PMOS transistor, the gate and drain of the tenth PMOS transistor, the gate and drain of the fifteenth PMOS transistor, the drain of the eleventh NMOS transistor, the upper plate of the second capacitor, the drain of the second N-type LDMOS transistor, its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the gate and drain of the fourth NMOS transistor and the gate of the third NMOS; The gate of the eighth PMOS transistor is connected to the gates and drains of the third PMOS transistor, the fourth PMOS transistor, the gates and drains of the twelfth PMOS transistor, the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor. Its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the gates and drains of the ninth NMOS transistor and the tenth NMOS transistor; The gate of the eleventh PMOS transistor is connected to the gates of the eighth PMOS transistor, the twelfth PMOS transistor, the gates and drains of the third PMOS transistor, the fourth PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor. Its source is connected to the bootstrap capacitor voltage BST, and its drain is connected to the source of the fifteenth PMOS transistor; The gates and drains of the twelfth PMOS transistor are connected to the gates and drains of the third PMOS transistor, the fourth PMOS transistor, the eighth PMOS transistor, the eleventh PMOS transistor, the drain of the second NMOS transistor, the upper plate of the first capacitor, and the drain of the first N-type LDMOS transistor. Its source is connected to the drain of the second PMOS transistor; The gates and drains of the fifteenth PMOS transistor are connected to the gates and drains of the tenth PMOS transistor, the ninth PMOS transistor, the drain of the eleventh NMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, the upper plate of the second capacitor, and the drain of the second N-type LDMOS transistor. Its source is connected to the drain of the eleventh PMOS transistor.

5. The level shift circuit with anti-dV / dt noise according to claim 1, wherein The bias current circuit module includes: a first NMOS transistor, a first PMOS transistor, a first resistor, a second resistor, and a third resistor; The gate and drain of the first NMOS transistor are connected to the lower end of the second resistor, the gate of the seventh NMOS transistor, and the gate of the eighth NMOS transistor. Its source is connected to the upper end of the third resistor; The gate and drain of the first PMOS transistor are connected to the upper end of the second resistor, the gate of the sixth PMOS transistor, and the gate of the seventh PMOS transistor. Its source is connected to the lower end of the first resistor; The upper end of the first resistor is connected to the bootstrap capacitor voltage BST, and its lower end is connected to the source of the first PMOS transistor; The upper end of the second resistor is connected to the gate and drain of the first PMOS transistor, the gate of the sixth PMOS transistor, and the gate of the seventh PMOS transistor. Its lower end is connected to the gate and drain of the first NMOS transistor, the gate of the seventh NMOS transistor, and the gate of the eighth NMOS transistor; The upper end of the third resistor is connected to the source of the first NMOS transistor, and its lower end is connected to the switch node voltage SW.

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