Calibration circuit, calibration method, external signal interface chip and electronic equipment

Abstract

The invention relates to a calibration circuit, a calibration method, an external signal interface chip and electronic equipment, the calibration circuit comprises a reference voltage modulation module and a time delay module, the first end of the reference voltage modulation module is connected with a first connection point, the second end of the reference voltage modulation module is connected with a second connection point, and the time delay module is connected with the first connection point. The reference voltage modulation module is used for calibrating the reference voltage of the external signal interface chip; the input end of the delay module is used for receiving a sampling clock signal, the output end of the delay module is connected with the control end of the comparator, and the delay module is used for calibrating the sampling clock signal of the external signal interface chip. According to the calibration circuit disclosed by the embodiment of the invention, the reference voltage and the sampling clock signal of the external signal interface chip can be effectively calibrated, so that the data transmission stability is ensured, and the accuracy and the reliability of the external signal interface chip are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technologies, and in particular, to a calibration circuit, a calibration method, an external signal interface chip, and an electronic device. Background Art

[0002] With the increasingly rapid development of high-speed communication systems, external signal interface chips (PHYs) are widely used in various memory chips. For example, the fifth-generation double data rate synchronous dynamic random access memory (DDR), the fifth-generation low-power double data rate synchronous dynamic random access memory (LPDDR), flash memory (NAND), etc. Compared with the fourth-generation memory chips, the highest data transfer rate required for the fourth-generation memory chips only reaches 3200MT / s or 4266MT / s, and its data transfer rate is approximately half of that of the fifth-generation memory chips. The receiving circuit design in the fourth-generation memory chips usually adopts a static comparator. The advantage of the static comparator is that its structure design is simple, the circuit timing requirements are not high, and the data signal is linearly amplified by the static comparator. However, the static comparator has low efficiency in optimizing the jitter of the data eye diagram, and in order to meet the bandwidth requirements, the static power consumption of the circuit is relatively large. In view of this, the receiving circuit of the fifth-generation memory chips will adopt a dynamic comparator. The dynamic comparator can be applied to high-speed input / output communication systems, and the static power consumption of the dynamic comparator is relatively low. However, the disadvantages of the dynamic comparator are that it is sensitive to noise and deviation, and in addition, the dynamic comparator requires a sampling clock, and has high requirements for the circuit timing.

[0003] Furthermore, for the design of the external signal interface chip in the related art, eight or more data signal line ports are often used in the chip to read and write data simultaneously, and the reference voltage for comparison is connected to multiple data signal line ports at the same time. Due to the deviation between each data signal line port, the same reference voltage is not suitable for each data signal line port, so the amplitude of the output signal of the receiving circuit of the data signal line port is reduced, and the eye height of the eye diagram becomes worse. If a dynamic comparator is used in the receiving circuit of the input / output port (IO), the sampling clock of the dynamic comparator will also be connected to multiple data signal line ports. Due to the layout and wiring of the layout, it cannot be guaranteed that the sampling edges in all data signal line ports are consistent. For a relatively low data transfer rate, there is enough margin in the height and width of the data eye diagram itself for sampling. However, for a communication scenario with a relatively high data transfer rate, it is very important to calibrate the reference voltage and the sampling clock used for comparing with the data signal. Summary of the Invention

[0004] In view of this, the present disclosure provides a calibration circuit, a calibration method, an external signal interface chip, and an electronic device.

[0005] According to one aspect of the present disclosure, a calibration circuit is provided. The calibration circuit is applied to an external signal interface chip. The receiving circuit of the external signal interface chip includes an amplifier and a comparator. The inverting input terminal of the amplifier is used to receive a reference voltage, and the non-inverting input terminal of the amplifier is used to receive an external data signal. The non-inverting output terminal of the amplifier is connected to the non-inverting input terminal of the comparator at a first connection point, and the inverting output terminal of the amplifier is connected to the inverting input terminal of the comparator at a second connection point. The calibration circuit includes a reference voltage modulation module and a delay module. The first end of the reference voltage modulation module is connected to the first connection point, and the second end of the reference voltage modulation module is connected to the second connection point. The reference voltage modulation module is used to calibrate the reference voltage of the external signal interface chip. The input terminal of the delay module is used to receive a sampling clock signal, and the output terminal of the delay module is connected to the control terminal of the comparator. The delay module is used to calibrate the sampling clock signal of the external signal interface chip.

[0006] In a possible implementation manner, based on the calibration circuit, calibration is performed in the following manner, including: obtaining an eye diagram of the data signal based on the first connection point and the second connection point; adjusting the reference voltage modulation module of the calibration circuit to calibrate the reference voltage to maximize the eye width of the eye diagram; and / or adjusting the delay module of the calibration circuit to calibrate the sampling clock signal so that the comparator samples the position with the maximum eye height in the eye diagram.

[0007] In a possible implementation manner, the reference voltage modulation module includes an adjustable current source, a first transistor, and a second transistor. The first end of the adjustable current source is used to receive a power signal, and the second end of the adjustable current source is connected to the first end of the first transistor and the first end of the second transistor. The second end of the first transistor is connected to the first connection point, and the second end of the second transistor is connected to the second connection point. The control terminal of the first transistor is used to receive a first control signal, and the control terminal of the second transistor is used to receive a second control signal. The first control signal and the second control signal are used to modulate the reference voltage, and the adjustable current source is used to determine the modulation range of the reference voltage.

[0008] In a possible implementation manner, when the first control signal turns on the first transistor and the second control signal turns off the second transistor, the voltage at the first connection point is increased; when the first control signal turns off the first transistor and the second control signal turns on the second transistor, the voltage at the second connection point is increased.

[0009] In a possible implementation, the reference voltage modulation module includes a current source, a third transistor, and a fourth transistor. The first end of the current source is configured to receive a power signal. The second end of the current source is connected to the first ends of the third transistor and the fourth transistor. The second end of the third transistor is connected to the first connection point. The second end of the fourth transistor is connected to the second connection point. The control end of the third transistor is configured to receive the data signal. The control end of the fourth transistor is configured to receive the reference voltage. Wherein, the reference voltage is modulated by changing the sizes of the third transistor and the fourth transistor.

[0010] In a possible implementation, the reference voltage modulation module includes a first adjustable resistor and a second adjustable resistor. The first end of the first adjustable resistor is connected to the first connection point. The first end of the second adjustable resistor is connected to the second connection point. The second ends of the first adjustable resistor and the second adjustable resistor are grounded. Wherein, the reference voltage is modulated by changing the resistance values of the first adjustable resistor and the second adjustable resistor.

[0011] In a possible implementation, the delay module includes a plurality of buffers connected in series in sequence, and a multiplexer. Wherein, the input end of the first buffer among the plurality of buffers connected in series in sequence serves as the input end of the delay module for receiving the sampling clock signal. The output ends of the plurality of buffers are respectively connected to the plurality of input ends of the multiplexer. The output end of the multiplexer serves as the output end of the delay module and is connected to the control end of the comparator.

[0012] According to another aspect of the present disclosure, an external signal interface chip is provided. The external signal interface chip includes a plurality of receiving circuits that share the same reference voltage, and each receiving circuit is respectively connected to a calibration circuit as described above.

[0013] According to another aspect of the present disclosure, a calibration method is provided. The method is applied to the calibration circuit as described above. The method includes: obtaining the eye diagram of the data signal based on the first connection point and the second connection point; adjusting the reference voltage modulation module of the calibration circuit to calibrate the reference voltage to maximize the eye width of the eye diagram; and / or adjusting the delay module of the calibration circuit to calibrate the sampling clock signal so that the comparator samples the position with the maximum eye height in the eye diagram.

[0014] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes the calibration circuit as described above.

[0015] According to another aspect of the present disclosure, a chip is provided. The chip includes the calibration circuit as described above.

[0016] The calibration circuit of the embodiments of the present disclosure includes a reference voltage modulation module and a delay module. The reference voltage modulation module is used to calibrate the reference voltage of the external signal interface chip, and the delay module is used to calibrate the sampling clock signal of the external signal interface chip. According to the calibration circuit of the embodiments of the present disclosure, the reference voltage and the sampling clock signal of the external signal interface chip can be effectively calibrated to ensure the stability of data transmission and improve the accuracy and reliability of the external signal interface chip.

[0017] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings included in and constituting a part of this specification illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0019] Figure 1 Schematic diagram showing an eye diagram according to an embodiment of the present disclosure.

[0020] Figure 2 Schematic circuit diagram of an external signal interface chip in the related art.

[0021] Figure 3 Schematic diagram showing a data signal line port in the related art.

[0022] Figure 4 Schematic diagram showing a calibration circuit according to an embodiment of the present disclosure.

[0023] Figure 5 Schematic circuit diagram showing a reference voltage modulation module according to an embodiment of the present disclosure.

[0024] Figure 6 Schematic circuit diagram showing a reference voltage modulation module according to another embodiment of the present disclosure.

[0025] Figure 7 Schematic circuit diagram showing a reference voltage modulation module according to another embodiment of the present disclosure.

[0026] Figure 8 Schematic circuit diagram showing a delay module according to an embodiment of the present disclosure.

[0027] Figure 9 Schematic circuit diagram showing an external signal interface chip according to an embodiment of the present disclosure.

[0028] Figure 10 Flowchart showing a calibration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Identical reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0030] As used herein, the terms "comprising," "including," "having," or variations thereof are open-ended and include one or more stated features, wholes, elements, steps, components, or functions, but do not exclude the existence or addition of one or more other features, wholes, elements, steps, components, functions, or groups thereof.

[0031] When an element is referred to as being "connected," "coupled," "responsive," or variations thereof to another element, it can be directly connected, coupled, or responsive to the other element, or intervening elements may be present.

[0032] Although the terms first, second, third, etc. may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Thus, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0033] The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment illustrated herein as "exemplary" should not be construed as being superior to or better than other embodiments.

[0034] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0035] For the convenience of understanding the technical solutions of the present disclosure, the professional names or terms involved below are first explained herein.

[0036] An eye diagram is an image formed by overlapping each symbol waveform obtained by scanning through the afterglow effect of an oscilloscope, and is used to evaluate the integrity of a data signal. Since it is the result of cumulatively and superposing the bit positions of a serial signal in an afterglow manner, the shape of the superposed graph looks very much like an eye, hence the name eye diagram.

[0037] Figure 1 A schematic diagram showing an eye diagram according to an embodiment of the present disclosure, as Figure 1As shown, the eye height represents the maximum opening height of the eye diagram in the vertical direction (amplitude axis), and the eye width refers to the maximum opening width of the eye diagram in the horizontal direction (time axis), that is, the effective time window of the signal at the optimal sampling point. Among them, the eye diagram contains rich information. The influence of inter-symbol interference and noise can be observed from the eye diagram, which reflects the overall characteristics of the digital signal, so as to estimate the quality of the communication system. For example, the transmitted signal of a high-speed interconnect system can be analyzed. In addition, this graph can also be used to adjust the communication system to reduce inter-symbol interference and improve the transmission performance of the communication system.

[0038] The external signal interface chip (PHY), also known as the port physical layer, refers to the chip that interfaces with external signals.

[0039] Exemplarily, for the external signal interface chip integrated in the fourth-generation memory chip in the related art, its operating manual sets the power supply voltage VDDQ (such as 1.2V or 1.1V). Due to the influence of system terminal impedance matching, the voltage range of the data signal is relatively high (such as 0.5*VDDQ~VDDQ or 0~0.5*VDDQ), and the data transmission rate is not very high (such as 3200MT / s, 4266MT / s). The data signal passes through the transmission line and is connected to the input end of the receiving circuit of multiple data signal line ports in the external signal interface chip. Since the height and width of the data eye diagram have sufficient margins, it means that in the current signal transmission environment, the signal has enough space and tolerance to cope with various interferences and changes. Therefore, the same reference voltage can be used for multiple data signal line ports. If the receiving circuit adopts the double-edge sampling mode of dynamic comparator sampling, when the sampling rate is not very high (such as 1.6GHz, 2.4GHz), it is possible to support using the same sampling clock for multiple receiving circuits, and the bit error rate of data transmission will not increase.

[0040] Figure 2 The circuit schematic diagram of the external signal interface chip in the related art is shown, as Figure 2 As shown, the external signal interface chip may include a reference voltage generation circuit, a clock circuit, multiple data signal line ports DQ, and a clock signal line port DQS.

[0041] Among them, the reference voltage generation circuit includes multiple series-connected resistors and an operational amplifier. The multiple resistors are used to divide the voltage of the power supply to provide multiple voltage division nodes (such as the connection point of any two adjacent resistors). The non-inverting input terminal of the operational amplifier can be selectively connected to a certain voltage division node, and the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier to provide the reference voltage VREF for the receiving circuit RX in the data signal line port DQ.

[0042] The clock circuit includes a logic circuit module and a buffer. The output terminal, the first input terminal of the logic circuit module, and the input terminal of the buffer are interconnected. The second input terminal of the logic circuit module is used to receive the reference clock refclk, and the output terminal of the buffer serves as the output terminal of the clock circuit, which is used to provide a sampling clock signal clk for each data signal line port DQ and the clock signal line port DQS.

[0043] Optionally, the logic circuit module can be composed of a Phase-Locked Loop (PLL), a Phase Interpolator (PI), and a Duty Cycle Corrector (DCC). By working together, they generate a clock signal. For example, the PLL can generate a preliminary clock signal based on the reference clock refclk, and through a feedback mechanism, use the phase interpolator and the duty cycle corrector to adjust the frequency and phase of the clock signal. Among them, the phase interpolator can adjust the phase of the clock signal, and the duty cycle corrector can adjust the duty cycle of the clock signal. In this way, the logic circuit module generates a sampling clock signal clk that can control the phase.

[0044] The data signal line port DQ and the clock signal line port DQS are unit circuits related to read and write signals in the external signal interface chip. Each data signal line port DQ and the clock signal line port DQS include a transmission circuit TX and a reception circuit RX, and multiple data signal line ports DQ work simultaneously as a group. Among them, the transmission circuit TX includes a buffer driver, and the buffer driver is used to transmit the internal signal to the external module according to the indication of the sampling clock signal clk. The reception circuit RX can be composed of a comparator. The first input terminal of the comparator is used to receive the external data signal Data (or the sampling clock signal clk), the second input terminal of the comparator is used to receive the reference voltage VREF, the control terminal of the comparator is used to receive the sampling clock signal clk, and the output terminal of the comparator is used to provide the input signal after sampling and comparison for the internal System on Chip (SoC).

[0045] But as Figure 2The external signal interface chip shown cannot meet the storage chips with higher transmission rates. For example, the fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR), the fifth-generation Low Power Double Date Rate SDRAM (LPDDR), NAND flash, etc. For the external signal interface chips used in storage chips with higher transmission rates, their data transmission rates will increase exponentially. After passing through the channel, the signals reaching the data signal line port DQ will attenuate exponentially with the frequency. The rate of the sampling clock will increase exponentially. In addition, due to factors such as inter-symbol interference and crosstalk, the eye height and eye width of the data signal eye diagram received by the receiving circuit RX will both become smaller, and the sampling error rate will also increase exponentially. Therefore, the reference voltage and sampling clock for the data signal line port DQ applicable to the fourth-generation storage chips need to be optimized to support data signals with higher transmission rates.

[0046] For the faster fifth-generation storage chips, the external signal interface chips they use can also include multiple data signal line ports DQ and a clock signal line port DQS. The data signal line port DQ is used for reading and writing data information, and the clock signal line port DQS is used for reading and writing sampling clock signals. The data signal line ports DQ can be grouped in sets of eight, ten, or even more.

[0047] Figure 3 A schematic diagram of the data signal line port in the related art is shown, as Figure 3 shown, each data signal line port DQ can include a receiving circuit RX and a transmitting circuit TX. The receiving circuit RX is used to read data information and can be composed of comparators. To support higher data transmission rates (for example, a data rate of 6400 MT / s), a dynamic comparator can be selected for sampling. For example, the receiving circuit RX can include a pre-amplifier pre-amp and a dynamic sampling comparator. The inverting input terminal of the pre-amplifier pre-amp is used to receive the reference voltage VREF, the non-inverting input terminal of the pre-amplifier pre-amp is used to receive the external data signal data, the non-inverting output terminal of the pre-amplifier pre-amp is connected to the non-inverting input terminal of the dynamic sampling comparator at the connection point OP1, the inverting output terminal of the pre-amplifier pre-amp is connected to the inverting input terminal of the dynamic sampling comparator at the connection point ON1, and the control terminal of the dynamic sampling comparator is used to receive the sampling clock signal clk. The pre-amplifier pre-amp can include a linear equalization circuit and a feedback equalization circuit, both of which can amplify the data signal data first and then output it to the sampling comparator for sampling. The transmitting circuit TX can refer to the above text and will not be elaborated here.

[0048] For a communication system with a higher transmission rate, taking the fifth-generation low-power double-data-rate dynamic random access memory (LPDDR5) as an example, the data signal voltage range is between 0 and 0.5V, and the data rate supports up to 6400MT / s. To adapt to high-speed data transmission, the requirements of the receiving circuit RX in the data signal line port for the data eye diagram are as follows: when the power supply voltage VDDQ for the input / output port buffer is set to 0.5V and the data rate reaches 6400MT / s, the receiving circuit RX of the data signal line port has a pulse response width of 0.45 unit intervals (UI) and a pulse signal response amplitude of + / -70mV.

[0049] Therefore, when designing a high-speed external signal interface chip, it is required that the receiving circuit RX amplifies the amplitude of the received data eye diagram, optimizes the eye diagram jitter, then performs sampling and comparison, and then transmits it to the system-on-chip. During this process, for the linearly amplified eye diagram, how to ensure that the sampling clock of the dynamic sampling comparator can obtain the maximum amplitude of the eye diagram, and how to set the reference voltage for sampling to ensure that the eye width of the eye diagram reaches the maximum value are one of the design difficulties of the communication system in the high-speed storage chip. Another key point of the design is that when the communication system is working properly, for the communication at the physical layer, since the reference voltage of each data signal line port of the external signal interface chip comes from the same circuit, how to adapt to each data signal line port is also a difficulty, that is: how to use a sampling clock to adapt to each data signal line port to ensure that the rising edge or falling edge of the clock can align with the highest amplitude of each eye diagram during sampling.

[0050] In view of this, embodiments of the present disclosure provide a calibration circuit for calibrating the reference voltage and sampling clock signal of an external signal interface chip to ensure data transmission stability and improve the accuracy and reliability of the external signal interface chip.

[0051] Figure 4 The schematic diagram of the calibration circuit according to an embodiment of the present disclosure is shown. As Figure 4 shown, the calibration circuit is applied to an external signal interface chip. The receiving circuit in the data signal line port DQ of the external signal interface chip includes an amplifier 2 and a comparator 3. The data signal line port DQ is not Figure 4 shown, and its exemplary structure can be seen in Figure 3 , and the present application does not limit the specific structure of the data signal line port DQ. The inverting input terminal of the amplifier 2 is used to receive the reference voltage VREF, the non-inverting input terminal of the amplifier 2 is used to receive the external data signal DATA, the non-inverting output terminal of the amplifier 2 is connected to the non-inverting input terminal of the comparator 3 at the first connection point OP, and the inverting output terminal of the amplifier 2 is connected to the inverting input terminal of the comparator 3 at the second connection point ON.

[0052] Among them, the exemplary descriptions of the amplifier 2 and the comparator 3 can be referred to Figure 3 , and the specific structures of the amplifier 2 and the comparator 3 are not limited in this application. The reference voltage VREF of the external signal interface chip can be generated by, for example Figure 2 the reference voltage generation circuit shown or other optional reference voltage generation circuits, and sent to the inverting input terminal of the amplifier 2 in the receiving circuit. For example, assuming that the power supply voltage VDDQ is 0.5V, the voltage range of the data signal DATA is 0 to 0.5×VDDQ, and the default value of the reference voltage VREF is 0.25×VDDQ, the reference voltage generation circuit can be used to set the reference voltage VREF to 0.25×VDDQ. The specific value of the reference voltage VREF is not limited in the embodiments of the present disclosure.

[0053] The calibration circuit includes a reference voltage modulation module 4 and a delay module 5. The first end of the reference voltage modulation module 4 is connected to the first connection point OP, and the second end of the reference voltage modulation module 4 is connected to the second connection point ON. The reference voltage modulation module 4 is used to calibrate the reference voltage VREF of the external signal interface chip to maximize the eye width of the eye diagram collected at the input terminal of the comparator 3 (that is, the eye diagram collected from the first connection point OP and the second connection point ON). After being sampled and compared by the comparator 3, the output signal OUT is sent to the on-chip integrated system inside.

[0054] The input terminal of the delay module 5 is used to receive the sampling clock signal clk, and the output terminal of the delay module 5 is connected to the control terminal of the comparator 3. The delay module 5 is used to calibrate the sampling clock signal clk of the external signal interface chip and send the calibrated sampling clock signal clkout to the control terminal of the comparator 3.

[0055] It should be noted that although the calibration circuit is introduced above by taking Figure 4 as an example, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly deform it according to the actual application scenario as long as the reference voltage VREF and the sampling clock signal clk of the receiving circuit RX can be calibrated.

[0056] In a possible implementation manner, based on the calibration circuit, calibration is performed in the following manner, including: obtaining the eye diagram of the data signal DATA based on the first connection point OP and the second connection point ON; adjusting the reference voltage modulation module 4 of the calibration circuit to calibrate the reference voltage VREF to maximize the eye width of the eye diagram; and / or adjusting the delay module 5 of the calibration circuit to calibrate the sampling clock signal clk to make the comparator 3 sample the position with the maximum eye height in the eye diagram.

[0057] Exemplarily, the external signal interface chip may include a plurality of data signal line ports DQ, and each data signal line port DQ may be joined with a separately modulated reference voltage and a sampling clock signal.

[0058] When there is a deviation in the common-mode level of the data signal DATA of a certain data signal line port DQ in the external signal interface chip compared with the reference voltage VREF, the reference voltage modulation module 4 can be used to modulate the differential signal at the output end of the modulation amplifier 2, eliminate the common-mode deviation of the differential signal, and optimize the eye width of the data signal DATA for sampling.

[0059] The delay module 5 can be used to modulate the sampling clock signal, so that each data signal line port DQ can collect the position with the maximum eye height, reduce the bit error rate of reading data, set different-time edges for each data signal line port DQ, ensure that each data signal line port DQ can read data correctly, and improve the accuracy and reliability of the functions of the external signal interface chip.

[0060] The reference voltage modulation module 4 and the delay module 5 are introduced exemplarily as follows.

[0061] In the related art, the reference voltage VREF of all data signal line ports DQ in the external signal interface chip is the same and cannot be modulated separately. In contrast, in order to reduce the bit error rate of reading data of the data signal line port DQ, in the embodiments of the present disclosure, by setting the reference voltage modulation module 4, the reference voltage VREF is independently modulated in the receiving circuit RX of each data signal line port DQ.

[0062] Figure 5 The circuit schematic diagram of the reference voltage modulation module according to an embodiment of the present disclosure is shown. As Figure 5 shown, the reference voltage modulation module 4 includes an adjustable current source OFST_BIAS<2:0>, a first transistor M1, and a second transistor M2. The first end of the adjustable current source OFST_BIAS<2:0> is used to receive a power supply signal. The second end of the adjustable current source OFST_BIAS<2:0> is connected to the first end of the first transistor M1 and the first end of the second transistor M2. The second end of the first transistor M1 is connected to the first connection point OP, and the second end of the second transistor M2 is connected to the second connection point ON. The control end of the first transistor M1 is used to receive a first control signal OFST_P, and the control end of the second transistor M2 is used to receive a second control signal OFST_N. The first control signal OFST_P and the second control signal OFST_N are used to modulate the reference voltage VREF, and the adjustable current source OFST_BIAS<2:0> is used to determine the modulation range of the reference voltage VREF.

[0063] Among them, in response to the first control signal OFST_P, the first transistor M1 is turned on, and in response to the second control signal OFST_N, the second transistor M2 is turned off, raising the voltage at the first connection point OP; in response to the first control signal OFST_P being turned off, the first transistor M1 is turned off, and in response to the second control signal OFST_N, the second transistor M2 is turned on, raising the voltage at the second connection point ON.

[0064] It should be understood that for the control terminals of the first transistor M1 and the second transistor M2, the gate is used. The first end can be the source, and the second end can be the drain; alternatively, the first end can be the drain, and the second end can be the source. There is no specific distinction here. Specifically, whether to choose NMOS (N-type transistor) or PMOS (P-type transistor) can be set according to the actual application scenario. For example, according to the voltage range of the input data signal DATA, it can be determined whether to choose NMOS or PMOS; if the voltage range of the input data signal DATA is relatively large, NMOS can be selected; if the voltage range of the input data signal DATA is relatively small, PMOS can be selected. Further, in specific implementation, NMOS is turned on under the action of a high-level signal and turned off under the action of a low-level signal. PMOS is turned off under the action of a high-level signal and turned on under the action of a low-level signal.

[0065] For example, assume that the power supply voltage VDDQ is 0.5V, the voltage range of the data signal DATA is 0 to 0.5×VDDQ, the default value of the reference voltage VREF is 0.25×VDDQ, the amplifier 2 selects PMOS as the input pair transistors, and the current source of the amplifier 2 is also a PMOS current mirror. Then, the adjustable current source OFST_BIAS<2:0> also uses a PMOS current source, and the first transistor M1 and the second transistor M2 use PMOS. Among them, the PMOS source can be used as the first end, and the PMOS drain can be used as the second end.

[0066] In this way, when the first control signal OFST_P = 0 and the second control signal OFST_N = 1, the first transistor M1 is turned on, the second transistor M2 is turned off, and the voltage at the first connection point OP rises; on the contrary, when the first control signal OFST_P = 1 and the second control signal OFST_N = 0, the first transistor M1 is turned off, the second transistor M2 is turned on, and the voltage at the second connection point ON rises.

[0067] Similarly, if the voltage range of the data signal DATA is greater than 0 to 0.5×VDDQ, the first transistor M1 and the second transistor M2 can be NMOS transistors. Among them, the drain of the NMOS transistor can be used as the first terminal, and the source of the NMOS transistor can be used as the second terminal. When the first control signal OFST_P = 1 and the second control signal OFST_N = 0, the first transistor M1 is turned on and the second transistor M2 is turned off, and the voltage at the first connection point OP increases; conversely, when the first control signal OFST_P = 0 and the second control signal OFST_N = 1, the first transistor M1 is turned off and the second transistor M2 is turned on, and the voltage at the second connection point ON increases.

[0068] It should be understood that "1" represents a high-level signal and "0" represents a low-level signal. The high-level signal and the low-level signal are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. The present disclosure does not limit the magnitude of the voltage applied to the gates of the respective transistors during specific implementation.

[0069] In the above process, the magnitude of the adjustable current source OFST_BIAS<2:0> can be changed, thereby changing the modulation range of the reference voltage VREF. Among them, the larger the adjustable current source OFST_BIAS<2:0>, the greater the corresponding voltage change; the smaller the adjustable current source OFST_BIAS<2:0>, the smaller the corresponding voltage change.

[0070] It can be seen that by adjusting the first control signal OFST_P, the second control signal OFST_N, and the adjustable current source OFST_BIAS<2:0>, the reference voltage VREF is modulated so that the comparator 2 can collect the signal with the largest eye width and reduce the sampling error rate.

[0071] Figure 6 FIG. shows a circuit schematic diagram of a reference voltage modulation module according to another embodiment of the present disclosure. As Figure 6 shown, the reference voltage modulation module 4 includes a current source OFST_BIAS, a third transistor M3, and a fourth transistor M4. The first terminal of the current source OFST_BIAS is used to receive a power supply signal. The second terminal of the current source OFST_BIAS is connected to the first terminal of the third transistor M3 and the first terminal of the fourth transistor M4. The second terminal of the third transistor M3 is connected to the first connection point OP, and the second terminal of the fourth transistor M4 is connected to the second connection point ON. The control terminal of the third transistor M3 is used to receive the data signal DATA, and the control terminal of the fourth transistor M4 is used to receive the reference voltage VREF. Among them, the reference voltage VREF is modulated by changing the sizes of the third transistor M3 and the fourth transistor M4.

[0072] Among them, for the control terminals of the third transistor M3 and the fourth transistor M4, they are gates, the first terminal can be the source, and the second terminal can be the drain; or, the first terminal can be the drain and the second terminal can be the source. Specific distinctions are not made here. Specifically, whether to select an NMOS (N-type transistor) or a PMOS (P-type transistor) can be set according to the actual application scenario. For example, according to the voltage range of the input data signal DATA, it can be determined whether to select an NMOS or a PMOS; if the voltage range of the input data signal DATA is relatively large, an NMOS can be selected; if the voltage range of the input data signal DATA is relatively small, a PMOS can be selected.

[0073] Furthermore, in specific implementation, if the third transistor M3 and the fourth transistor M4 are NMOS, the drain of the NMOS can be used as the first terminal, and the source of the NMOS can be used as the second terminal. The NMOS conducts under the action of a high-level signal and cuts off under the action of a low-level signal. If the third transistor M3 and the fourth transistor M4 are PMOS, the source of the PMOS can be used as the first terminal, and the drain of the PMOS can be used as the second terminal. The PMOS cuts off under the action of a high-level signal and conducts under the action of a low-level signal.

[0074] The larger the size of the fourth transistor M4, when the fourth transistor M4 conducts, the smaller the divided current flowing through the fourth transistor M4, and the voltage at the second connection point ON increases; the smaller the size of the fourth transistor M4, when the fourth transistor M4 conducts, the larger the divided current flowing through the fourth transistor M4, and the voltage at the second connection point ON decreases.

[0075] Similarly, the larger the size of the third transistor M3, when the third transistor M3 conducts, the smaller the divided current flowing through the third transistor M3, and the voltage at the first connection point OP increases; the smaller the size of the third transistor M3, when the third transistor M3 conducts, the larger the divided current flowing through the third transistor M3, and the voltage at the first connection point OP decreases.

[0076] It can be seen that by adjusting the sizes of the third transistor M3 and the fourth transistor M4, the load impedance at the output end of the amplifier 2 can be changed, thereby modulating the reference voltage VREF so that the comparator 2 can collect the signal with the largest eye width and reduce the sampling error rate. As an example, during the chip design process, the sizes of the third transistor M3 and the fourth transistor M4 can be adjusted according to needs until the eye width obtained by simulation (or observed with an oscilloscope) meets the requirements. The third transistor M3 and the fourth transistor M4 can also be respectively set as multiple series or parallel transistors, and by adjusting the number of transistors connected, it is equivalent to adjusting the sizes of the third transistor M3 and the fourth transistor M4.

[0077] Figure 7A circuit schematic diagram of a reference voltage modulation module according to another embodiment of the present disclosure is shown. As Figure 7 shown, the reference voltage modulation module 4 includes a first adjustable resistor R1 and a second adjustable resistor R2. The first end of the first adjustable resistor R1 is connected to the first connection point OP, and the first end of the second adjustable resistor R2 is connected to the second connection point ON. The second ends of the first adjustable resistor R1 and the second adjustable resistor R2 are grounded. Wherein, the reference voltage VREF is modulated by changing the resistance values of the first adjustable resistor R1 and the second adjustable resistor R2.

[0078] Wherein, the larger the resistance value of the first adjustable resistor R1, the larger the voltage divided by the first adjustable resistor R1, and the voltage at the first connection point OP increases; the smaller the resistance value of the first adjustable resistor R1, the smaller the voltage divided by the first adjustable resistor R1, and the voltage at the first connection point OP decreases.

[0079] Similarly, the larger the resistance value of the second adjustable resistor R2, the larger the voltage divided by the second adjustable resistor R2, and the voltage at the second connection point ON increases; the smaller the resistance value of the second adjustable resistor R2, the smaller the voltage divided by the second adjustable resistor R2, and the voltage at the second connection point ON decreases.

[0080] It can be seen that by adjusting the resistance values of the first adjustable resistor R1 and the second adjustable resistor R2, the load impedance at the output end of the amplifier 2 can be adjusted, thereby modulating the reference voltage VREF, so that the comparator 2 can collect the signal with the largest eye width and reduce the sampling error rate.

[0081] Comparing the above three solutions, Figure 5 the power consumption of the shown reference voltage modulation module 4 is relatively large and the accuracy is not high enough, but the modulation range of the reference voltage VREF is larger; Figure 6 the modulation range of the shown reference voltage modulation module 4 is relatively small, the output parasitic capacitance will increase, and the output bandwidth will decrease, but the power consumption is low; Figure 7 the modulation range of the shown reference voltage modulation module 4 is relatively small, but the design is simple. In actual applications, it can be selected according to the actual application scenario.

[0082] By setting the reference voltage modulation module 4 at the output end of the amplifier 2, when there is a deviation between the common-mode level of the data signal DATA and the reference voltage VREF, the differential signal at the output end of the amplifier 2 is modulated to eliminate the common-mode deviation of the differential signal and optimize the eye width of the data signal DATA for sampling, so that the comparator 2 can collect the signal with the largest eye width and reduce the sampling error rate. The adjustable factors in the reference voltage modulation module 4 can be adjusted by observing the eye diagrams collected at the first connection point OP and the second connection point ON (for example Figure 5The adjustable current sources OFST_BIAS<2:0>, the first control signal OFST_P, and the second control signal OFST_N in Figure 6 the sizes of the third transistor M3 and the fourth transistor M4 in Figure 7 the resistance values of the first adjustable resistor R1 and the second adjustable resistor R2 in, etc., so that the eye width of the eye diagram meets the requirements.

[0083] It should be noted that although the reference voltage modulation module 4 is introduced by taking Figures 5 to 7 as an example as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly deform it according to the actual application scenario.

[0084] In a possible implementation manner, the delay module 5 includes a plurality of buffers connected in series in sequence, and a multiplexer. Among them, the input end of the first buffer in the plurality of buffers connected in series in sequence is used as the input end of the delay module 5 to receive the sampling clock signal clk. The output ends of the plurality of buffers are respectively connected to the multiple input ends of the multiplexer. The output end of the multiplexer is used as the output end of the delay module 5 and is connected to the control end of the comparator 3.

[0085] Through a plurality of buffers connected in series in sequence, the sampling clock signal clk will experience different delays during the transmission process. Each buffer will introduce a certain delay. After the plurality of buffers are connected in series, the total delay amount is the accumulation of the delay amounts of each buffer. The function of the multiplexer is to select one of the outputs of the plurality of buffers as the final output, so as to realize the flexible adjustment of the delay amount. For example, if a smaller delay is required, the output passing through fewer buffers is selected; if a larger delay is required, the output passing through more buffers is selected.

[0086] The sampling clock signal clk generated by the clock circuit is transmitted to each data signal line port DQ via the signal line. Since the lengths of the signal lines reaching each data signal line port DQ are different, there is a delay in the sampling edge of each data signal line port DQ. Since the width of the signal that can be resolved by the data eye diagram decreases with the increase of the transmission rate, the error rate of simultaneously reading the data signal DATA by multiple data signal line ports DQ will increase accordingly. Based on this, the embodiment of the present disclosure adds the delay module 5 to the data signal line port DQ. The sampling clock signal clk generated by the clock circuit is input into each data signal line port DQ. The buffer in the data signal line port DQ modulates different clock edges and outputs them to the control end of the comparator 3, so that each comparator 3 can sample the position with the maximum eye height in the eye diagram. In this way, the error rate of the data signal line port DQ reading the data signal DATA is reduced, and the error rate of the external signal interface chip also decreases accordingly.

[0087] Figure 8 A circuit schematic diagram of a delay module according to an embodiment of the present disclosure is shown. As Figure 8 shown, the delay module 5 includes n + 1 buffers 6 connected in series in sequence, and a multiplexer 7 with n + 1 inputs. n is a positive integer, and the specific value of n in the embodiments of the present disclosure is not limited.

[0088] Among them, the input terminal of the first buffer among the n + 1 buffers 6 connected in series in sequence serves as the input terminal of the delay module 5 for receiving the sampling clock signal clk. The output terminals of multiple buffers are respectively connected to multiple input terminals of the multiplexer 7. For example, the output terminal of the first buffer is connected to the first input terminal of the multiplexer 7 for using the delayed signal delay_0 as an alternative signal of the multiplexer 7; the output terminal of the second buffer is connected to the second input terminal of the multiplexer 7 for using the delayed signal delay_1 as an alternative signal of the multiplexer 7; and so on. The output terminal of the (n + 1)-th buffer is connected to the (n + 1)-th input terminal of the multiplexer 7 for using the delayed signal delay_n as an alternative signal of the multiplexer 7. The multiplexer 7 is used to select one delayed signal from the n + 1 delayed signals delay_0 to delay signal delay_n as the calibrated sampling clock signal clkout and send it to the control terminal of the comparator 3.

[0089] Among them, the multiplexer 7 can be composed of multiple two-to-one selectors, and the circuit structure of the multiplexer 7 in the embodiments of the present disclosure is not specifically limited. The delay times of the n + 1 delayed signals delay_0 to delay signal delay_n increase in sequence, and the specific delay times in the embodiments of the present disclosure are not limited.

[0090] It should be noted that although the delay module 5 is introduced above by taking Figure 8 as an example, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, users can flexibly deform it according to the actual application scenario. In the application, the output of the delay module 5 and the corresponding eye diagram can be shown by an oscilloscope, etc. When the comparator 3 controlled by the output of the delay module 5 does not sample the position with the maximum eye height of the eye diagram, the delay module 5 is adjusted.

[0091] Figure 9 A circuit schematic diagram of an external signal interface chip according to an embodiment of the present disclosure is shown. As Figure 9 shown, the external signal interface chip includes multiple receiving circuits RX, and multiple receiving circuits share the same reference voltage VREF. Each receiving circuit RX is respectively connected to a calibration circuit as described above.

[0092] It should be understood that the number of receiving circuits RX in the present disclosure is not specifically limited and can be set according to the actual application scenario. Among them, for the reference voltage generation circuit, the clock circuit, the data signal line port DQ, and the clock signal line port DQS, reference can be made specifically to the above, and details will not be repeated here.

[0093] An independent reference voltage modulation circuit 4 can be added to each receiving circuit RX. While multiple receiving circuits RX share the same reference voltage VREF, each receiving circuit RX can finely adjust its respective reference voltage VREF through the independent reference voltage modulation module 4. The receiving circuit RX adopts a structure of an amplifier 2 cascaded with a comparator 3. In order to optimize the amplifier 2, a reference voltage modulation circuit 4 for modulating the differential output signal can be added at the output end of the amplifier 2 to modulate the common-mode range of the output signal of each amplifier 2 respectively, ensuring that the eye width of the data eye diagram at the input end of the comparator 3 in each receiving circuit RX is maximized, which is beneficial to reducing the sampling error rate. The implementation manner of the reference voltage modulation circuit 4 includes modulating the magnitude of the current source, or the size of the input pair transistors, or the size of the load resistor, etc. For details, reference can be made to the above, and details will not be repeated here.

[0094] An independent delay module 5 can be added to each receiving circuit RX. In the external signal interface chip, the same controllable sampling clock signal clk is shared, and the sampling clock signal clk comes from the clock circuit. Due to different wiring lengths on the layout, the time for the sampling clock signal clk to enter each receiving circuit RX will be deviated. Therefore, an independent delay module 5 is added to each receiving circuit RX. The delay module 5 of each receiving circuit RX can finely adjust the edge of the sampling clock signal clk for each word to obtain a calibrated sampling clock signal clkout, which is beneficial to each clock signal line port DQ to read the data signal DATA as simultaneously as possible and reduce the error rate of data transmission.

[0095] In this way, for the external signal interface chip of the embodiment of the present disclosure, the read / write signal data rate supports 6400MT / s and higher. When multiple clock signal line ports DQ read random data information simultaneously, the reference voltage VREF for comparison and the edge of the sampling clock signal clk in the receiving circuit RX can be modulated separately for each clock signal line port DQ, improving the stability and accuracy of data transmission.

[0096] Figure 10 The flowchart showing the calibration method according to an embodiment of the present disclosure is as Figure 10 shown. The method is applied to the calibration circuit as described above, and the method includes:

[0097] In step S11, based on the first connection point and the second connection point, obtain the eye diagram of the data signal;

[0098] In step S12, adjust the reference voltage modulation module of the calibration circuit to calibrate the reference voltage to maximize the eye width of the eye diagram; and / or, adjust the delay module of the calibration circuit to calibrate the sampling clock signal so that the comparator samples the position with the maximum eye height in the eye diagram.

[0099] In a possible implementation manner, the present disclosure also provides an electronic device, and the electronic device includes the calibration circuit as described above.

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of an instruction, and the module, the segment of a program, or the part of an instruction contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0101] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skilled persons in the technical field to understand the embodiments disclosed herein.

Claims

1. A calibration circuit, characterized in that, The calibration circuit is applied to an external signal interface chip. The receiving circuit of the external signal interface chip includes an amplifier and a comparator. The inverting input terminal of the amplifier is used to receive a reference voltage, and the non-inverting input terminal of the amplifier is used to receive an external data signal. The non-inverting output terminal of the amplifier is connected to the non-inverting input terminal of the comparator at a first connection point, and the inverting output terminal of the amplifier is connected to the inverting input terminal of the comparator at a second connection point; The calibration circuit includes a reference voltage modulation module and a delay module. The first end of the reference voltage modulation module is connected to the first connection point, and the second end of the reference voltage modulation module is connected to the second connection point. The reference voltage modulation module is used to calibrate the reference voltage of the external signal interface chip; The input terminal of the delay module is used to receive a sampling clock signal, and the output terminal of the delay module is connected to the control terminal of the comparator. The delay module is used to calibrate the sampling clock signal of the external signal interface chip.

2. The calibration circuit according to claim 1, wherein Based on the calibration circuit, calibration is performed in the following manner, including: Based on the first connection point and the second connection point, obtain the eye diagram of the data signal; Adjust the reference voltage modulation module of the calibration circuit to calibrate the reference voltage to maximize the eye width of the eye diagram; and / or, adjust the delay module of the calibration circuit to calibrate the sampling clock signal so that the comparator samples the position with the maximum eye height in the eye diagram.

3. The calibration circuit according to claim 1 or 2, characterized in that, The reference voltage modulation module includes an adjustable current source, a first transistor, and a second transistor. The first end of the adjustable current source is used to receive a power signal, and the second end of the adjustable current source is connected to the first end of the first transistor and the first end of the second transistor. The second end of the first transistor is connected to the first connection point, and the second end of the second transistor is connected to the second connection point. The control terminal of the first transistor is used to receive a first control signal, and the control terminal of the second transistor is used to receive a second control signal. The first control signal and the second control signal are used to modulate the reference voltage, and the adjustable current source is used to determine the modulation range of the reference voltage.

4. The calibration circuit according to claim 3, wherein Turn on the first transistor in response to the first control signal, turn off the second transistor with the second control signal, and raise the voltage at the first connection point; Turn off the first transistor in response to the first control signal, turn on the second transistor with the second control signal, and raise the voltage at the second connection point.

5. The calibration circuit according to claim 1 or 2, characterized in that, The reference voltage modulation module includes a current source, a third transistor, and a fourth transistor. The first end of the current source is used to receive a power signal, and the second end of the current source is connected to the first end of the third transistor and the first end of the fourth transistor. The second end of the third transistor is connected to the first connection point, and the second end of the fourth transistor is connected to the second connection point. The control terminal of the third transistor is used to receive the data signal, and the control terminal of the fourth transistor is used to receive the reference voltage. Among them, the reference voltage is modulated by changing the sizes of the third transistor and the fourth transistor.

6. The calibration circuit according to claim 1 or 2, characterized in that The reference voltage modulation module includes a first adjustable resistor and a second adjustable resistor. The first end of the first adjustable resistor is connected to the first connection point, and the first end of the second adjustable resistor is connected to the second connection point. The second ends of the first adjustable resistor and the second adjustable resistor are grounded. Wherein, the reference voltage is modulated by changing the resistance values of the first adjustable resistor and the second adjustable resistor.

7. The calibration circuit according to claim 1 or 2, characterized in that The delay module includes a plurality of buffers connected in series in sequence, and a multiplexer. Wherein, the input end of the first buffer among the plurality of buffers connected in series in sequence serves as the input end of the delay module for receiving the sampling clock signal. The output ends of the plurality of buffers are respectively connected to the plurality of input ends of the multiplexer. The output end of the multiplexer serves as the output end of the delay module and is connected to the control end of the comparator.

8. An external signal interface chip, characterized in that The external signal interface chip includes a plurality of receiving circuits. The plurality of receiving circuits share the same reference voltage. Each receiving circuit is respectively connected to a calibration circuit according to any one of claims 1 to 7.

9. A calibration method, characterized in that, The method is applied to the calibration circuit according to any one of claims 1 to 7, and the method includes: Based on the first connection point and the second connection point, obtain the eye diagram of the data signal; Adjust the reference voltage modulation module of the calibration circuit to calibrate the reference voltage to maximize the eye width of the eye diagram; and / or, adjust the delay module of the calibration circuit to calibrate the sampling clock signal so that the comparator samples the position with the maximum eye height in the eye diagram.

10. An electronic device, characterized in that, The electronic device includes the calibration circuit according to any one of claims 1 to 7.

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