Analog front-end circuit and signal filtering method for light volume change tracing method

Abstract

An analog front-end circuit for photovolumetric variation mapping includes a current control circuit and a monitoring circuit both coupled to a first node, and further includes a read circuit coupled to the first node through the monitoring circuit. The current control circuit generates a first sub-current which is a part of an input current flowing to the first node. In the tracking period, the monitoring circuit controls the current control circuit to determine the magnitude of the first sub-current so as to control the voltage of the first node to track the reference voltage. In a sensing period after the tracking period, the monitoring circuit controls the current control circuit to maintain the first sub-current determined by the tracking period. After holding the first sub-current, the monitoring circuit provides a second sub-current of a portion of the input current, and the reading circuit converts the second sub-current to the output voltage.

Description

Technical Field

[0001] The present disclosure relates to photoplethysmography, and particularly to an analog front-end circuit and a signal filtering method for photoplethysmography. Background Art

[0002] Photoplethysmography (PPG) is an optical method for measuring heart rate and blood oxygen saturation. In photoplethysmography, light-emitting diodes (LEDs) emit light towards the user's skin, and an optical sensor measures the light reflected by the user's blood and body tissues and converts it into an electrical current signal. However, the DC component of the electrical current signal may be dominated by slowly changing ambient light (e.g., light from a light bulb), while the AC component of the electrical current signal may be dominated by rapidly changing ambient light (e.g., light changes caused by the user's activities). To improve the accuracy of photoplethysmography, the electrical current signal components caused by ambient light should be filtered out to facilitate the back-end circuit analysis of the AC component and the DC component of the electrical current signal regarding blood and body tissues. Summary of the Invention

[0003] The present disclosure provides an analog front-end circuit for photoplethysmography, which includes a first current control circuit, a monitoring circuit, and a reading circuit. The first current control circuit is coupled to a first node and is configured to generate a first sub-current. The first sub-current is a part of the input current flowing into the first node. The monitoring circuit is coupled to the first node and is configured to receive a reference voltage. During a tracking period, the monitoring circuit is configured to control the first current control circuit to determine the magnitude of the first sub-current so as to control the voltage of the first node to track the reference voltage. The reading circuit is coupled to the first node through the monitoring circuit. During a sensing period after the tracking period, the monitoring circuit is configured to control the first current control circuit to maintain the first sub-current having the magnitude of the first sub-current determined during the tracking period. After maintaining the first sub-current, the monitoring circuit is configured to transfer a second sub-current from the first node to the reading circuit, such that the reading circuit is configured to convert the second sub-current into an output voltage. The second sub-current is a part of the input current.

[0004] The present disclosure provides a signal filtering method for photoplethysmography. The signal filtering method includes the following steps: during a tracking period, monitoring, by a monitoring circuit, a voltage of a first node and a reference voltage, wherein an input current flows into the first node; during the tracking period, controlling, by the monitoring circuit, a first current control circuit coupled to the first node to determine a magnitude of a first sub-current, wherein the first sub-current is a part of the input current and is generated by the first current control circuit; during a sensing period after the tracking period, controlling, by the monitoring circuit, the first current control circuit to maintain the first sub-current at the magnitude of the first sub-current determined during the tracking period; and after maintaining the first sub-current, converting, by a reading circuit coupled to the first node via the monitoring circuit, a second sub-current transmitted from the first node to the reading circuit by the monitoring circuit into an output voltage, wherein the second sub-current is a part of the input current.

[0005] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a simplified functional block diagram of an analog front-end circuit for photoplethysmography according to an embodiment of the present disclosure.

[0007] Figure 2 is a schematic diagram of an input current according to an embodiment of the present disclosure.

[0008] Figure 3 is a flowchart of a signal filtering method for photoplethysmography.

[0009] Figure 4 is a schematic diagram of a first current control circuit according to an embodiment of the present disclosure.

[0010] Figure 5 is a schematic diagram of a reading circuit according to an embodiment of the present disclosure.

[0011] Figure 6 is a schematic diagram of a reading circuit according to an embodiment of the present disclosure.

[0012] Figure 7 is a waveform schematic diagram of a reading circuit according to an embodiment of the present disclosure.

[0013] Figure 8 is a waveform schematic diagram of a reading circuit according to an embodiment of the present disclosure.

[0014] Figure 9 is a schematic diagram of a second current control circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The current embodiments of the present disclosure will now be described in detail, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to indicate the same or similar elements.

[0016] Figure 1 FIG. 5 is a simplified functional block diagram of an analog frontend circuit 100 for photoplethysmography (PPG) according to an embodiment of the present disclosure. The analog frontend circuit 100 includes a first current control circuit 110, a monitoring circuit 120, a reading circuit 130, and a second current control circuit 140. The analog frontend circuit 100 is configured to convert an input current I_in into an output voltage Vout, where the input current I_in is generated by an optical sensor (not shown in the figure) converting the sensed input absorbed light into a current signal. An analog-to-digital converter (ADC) 101 is configured to convert the output voltage Vout, where a digital signal processor (DSP) 103 is configured to receive and analyze the output of the analog-to-digital converter 101 to obtain physiological information PI (e.g., the user's heart rate, blood oxygen saturation, etc.). The digital signal processor 103 is also configured to implement feedback control of the analog frontend circuit 100 based on the analysis of the output of the analog-to-digital converter 101, which will be described in more detail in the following paragraphs.

[0017] Please refer to Figure 2 , where Figure 2 FIG. 6 is a schematic diagram of the input current I_in according to an embodiment of the present disclosure. When the photoplethysmography light source (e.g., an LED, Figure 1When the plethysmography light source is disabled (not shown) without generating reflected light to the optical sensor, the input current I_in at this time includes an ambient AC component Iac_amb and an ambient DC component Idc_amb. The ambient AC component Iac_amb and the ambient DC component Idc_amb are respectively caused by rapidly changing ambient light and slowly changing ambient light absorbed by the optical sensor. In addition, when the plethysmography light source is enabled and the reflection of the user's blood and / or tissue generates light reflected to the optical sensor, in addition to the ambient AC component Iac_amb and the ambient DC component Idc_amb, the input current I_in also includes a reflected AC component Iac_rfl and a reflected DC component Idc_rfl. The reflected AC component Iac_rfl is determined by the reflected light caused by the dynamic changes (i.e., changes over time) of the user's blood, subcutaneous tissue (subcutis), or bone. The reflected DC component Idc_rfl is determined by the reflected light caused by the static state (i.e., not changing over time) of the user's blood, subcutaneous tissue, or bone.

[0018] Please refer to Figure 1 and Figure 3 , where Figure 3 is a flowchart of signal filtering method 300 for plethysmography. In step S310 performed during the tracking period, the monitoring circuit 120 coupled to the first node N1 and used to receive the reference voltage Vref monitors the voltage of the first node N1 and the reference voltage Vref, where the input current I_in flows into the first node N1. The tracking period is a period when the plethysmography light source is disabled, so the input current I_in during the tracking period only includes the ambient AC component Iac_amb and the ambient DC component Idc_amb.

[0019] In step S320 performed during the tracking period, the monitoring circuit 120 controls the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1 for using the voltage of the first node N1 to track the reference voltage Vref. The first current control circuit 110 is coupled to the first node N1 and is used to generate the first sub-current I_sub1. The input current I_in flowing into the first node N1 is then shunted into multiple partial sub-currents (such as the first sub-current I_sub1, the second sub-current I_sub2, and the third sub-current I_sub3), and a part of the sub-currents is the first sub-current I_sub1. Specifically, during the tracking period, the monitoring circuit 120 sets the voltage of the first node N1 to the reference voltage Vref through the virtual short effect of the amplifier 122, and dynamically controls the first current control circuit 110 using the control signal Seao to draw most of the input current I_in as the first sub-current I_sub1, where the control signal Seao is generated by the monitoring circuit 120 based on the voltage of the first node N1 and the reference voltage Vref. Therefore, the second sub-current I_sub2 formed by the shunting of the input current I_in flows from the first node N1 into the monitoring circuit 120, and the second sub-current I_sub2 has a very small current and hardly changes the voltage of the first node N1, so that the voltage of the first node N1 is maintained at the reference voltage Vref. In other words, the first current control circuit 110 and the monitoring circuit 120 form a tracking loop, and this tracking loop continuously tracks the change of the ambient light. As the ambient light changes, the monitoring circuit 120 controls the first current control circuit 110 to adjust the first sub-current I_sub1 so that the first sub-current I_sub1 changes with the ambient light. Therefore, the first sub-current I_sub1 is approximately the sum of the ambient AC component Iac_amb and the ambient DC component Idc_amb, and the second sub-current I_sub2 is substantially zero.

[0020] In step S330 performed during the sensing period after the tracking period, the monitoring circuit 120 controls the first current control circuit 110 to hold the first sub-current I_sub1 so that the current of the first sub-current I_sub1 is maintained at the magnitude determined during the previous tracking period. The sensing period is the period when the photo plethysmography light source is enabled. Therefore, the input current I_in during the sensing period includes the ambient AC component Iac_amb, the ambient DC component Idc_amb, the reflected AC component Iac_rfl, and the reflected DC component Idc_rfl.

[0021] In step S340, which is performed after the first sub-current I_sub1 is maintained at a fixed magnitude, the reading circuit 130 is used to convert the second sub-current I_sub2 into an output voltage Vout. The reading circuit 130 is coupled to the first node N1 through the monitoring circuit 120, and the second sub-current I_sub2 is part of the input current I_in. The second sub-current I_sub2 is transmitted from the first node N1 to the reading circuit 130 via the monitoring circuit 120.

[0022] In step S350, during the sensing period, the second current control circuit 140 coupled to the first node N1 is used to generate a third sub-current I_sub3. The second current control circuit 140 is also used to determine the magnitude of the third sub-current I_sub3 according to the magnitude of the second sub-current I_sub2 in the previous sensing period, which will be described in more detail in the following paragraphs. The third sub-current I_sub3 is approximated to the reflected DC component Idc_rfl through the feedback control of the digital signal processor 103, and the third sub-current I_sub3 is part of the input current I_in.

[0023] Therefore, the first current control circuit 110 filters out the ambient DC component Idc_amb through the first sub-current I_sub1, and the second current control circuit 140 filters out the reflected DC component Idc_rfl through the third sub-current I_sub3. The second sub-current I_sub2 approximates the combination of the ambient AC component Iac_amb and the reflected AC component Iac_rfl. Since the second sub-current I_sub2 is small, the reading circuit 130 can be implemented to have a large gain (e.g., selecting a resistor with a large resistance value to form Figure 5 the storage array 530) when converting the second sub-current I_sub2 into the output voltage Vout, without the risk of the output voltage Vout exceeding the dynamic range of the analog-to-digital converter 101.

[0024] The following details step S310. The monitoring circuit 120 includes an amplifier 122, a sample-and-hold circuit 124, and a switch array 126. The amplifier 122, the sample-and-hold circuit 124, and the switch array 126 cooperate to perform step S310. The amplifier 122 includes a first input terminal (e.g., non-inverting input terminal), a second input terminal (e.g., inverting input terminal, labeled as the second node N2), and an output terminal (labeled as the third node N3). The second input terminal of the amplifier 122 is coupled to the reading circuit 130. In some embodiments, the amplifier 122 can be implemented by using an operational amplifier (OPAMP) or an operational transconductance amplifier (OTA).

[0025] The sample-and-hold circuit 124 is coupled to the output terminal of the amplifier 122. The sample-and-hold circuit 124 is configured to sample the output of the amplifier 122 (labeled as the control signal Seao), and is also configured to output the sampled output of the amplifier 122 to the first current control circuit 110 to control the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1. Specifically, the sample-and-hold circuit 124 includes a sampling switch SW and a sampling capacitor SC. The sampling capacitor SC includes a first end and a second end, wherein the first end of the sampling capacitor SC is coupled to the first current control circuit 110, and the second end of the sampling capacitor SC is configured to receive a first operating voltage (e.g., ground voltage). The sampling switch SW is coupled between the output terminal of the amplifier 122 and the first end of the sampling capacitor SC. The sampling switch SW conducts during the tracking period, enabling the sampling capacitor SC to sample the control signal Seao. On the other hand, the sampling switch SW turns off during the sensing period, enabling the sampling capacitor SC to hold the sampled control signal Seao.

[0026] The switch array 126 is coupled to the first node N1, the first input terminal and the second input terminal of the amplifier 122, and is configured to receive a reference voltage Vref. In some embodiments, the switch array 126 may be implemented by using two single-pole double-throw (SPDT) switches. During the tracking period, the switch array 126 is configured to connect the first node N1 to the first input terminal of the amplifier 122 to provide the second sub-current I_sub2 to the first input terminal of the amplifier 122. During the tracking period, the switch array 126 is further configured to provide the reference voltage Vref to the second input terminal of the amplifier 122. Therefore, during the tracking period, the amplifier 122 sets the first node N1 to the reference voltage Vref through the virtual short-circuit effect between the first input terminal and the second input terminal of the amplifier 122. The control signal Seao reflects the difference between the voltage of the first node N1 and the reference voltage Vref. For example, when the voltage of the first node N1 is different and higher than the reference voltage Vref, the control signal Seao may have a high voltage, and when the voltage of the first node N1 is different and lower than the reference voltage Vref, the control signal Seao may have a low voltage, but the present disclosure is not limited thereto.

[0027] Therefore, the steps performed during the tracking period in step S310 include: receiving the second sub-current I_sub2 and the reference voltage Vref through the switch array 126; and transmitting the second sub-current I_sub2 and the reference voltage Vref to the first input terminal and the second input terminal of the amplifier 122, respectively.

[0028] The following details step S320. The monitoring circuit 120 and the first current control circuit 110 are configured to cooperate to perform step S320. The first current control circuit 110 includes a transistor M1. The transistor M1 includes a first end, a second end, and a control end, and the first sub-current I_sub1 flows through the transistor M1. The first end of the transistor M1 is coupled to the first node N1. The second end of the transistor M1 is configured to receive a first operating voltage (e.g., a ground voltage). The control end of the transistor M1 is coupled to the monitoring circuit 120 (i.e., the first end of the sampling capacitor SC) to receive the control signal Seao generated by the monitoring circuit 120 based on the voltage of the first node N1 and the reference voltage Vref.

[0029] As described above, the sampling switch SW is turned on during the tracking period. Therefore, the sampling capacitor SC samples the output of the amplifier 122 (i.e., the control signal Seao) and outputs the sampled output of the amplifier 122 to the control end of the transistor M1, such that the transistor M1 dynamically determines the magnitude of the first sub-current I_sub1 according to the output of the amplifier 122.

[0030] Therefore, the steps S320 performed during the tracking period include: sampling the output of the amplifier 122 through the sample-and-hold circuit 124 coupled to the output terminal of the amplifier 122 and the first current control circuit 110; and outputting the sampled output of the amplifier 122 to the first current control circuit 110 through the sample-and-hold circuit 124 to control the first current control circuit 110 to determine the magnitude of the first sub-current I_sub1. From another perspective, the steps S320 include: generating a control signal Seao based on the voltage of the first node N1 and the reference voltage Vref through the monitoring circuit 120; and determining the magnitude of the first sub-current I_sub1 using the transistor M1 of the first current control circuit 110 according to the control signal Seao.

[0031] The following details the steps S330. During the sensing period after the tracking period, the switch array 126 is used to connect the first node N1 to the second input terminal of the amplifier 122 to provide the second sub-current I_sub2 to the second input terminal of the amplifier 122, so that the second sub-current I_sub2 is also provided to the reading circuit 130. During the sensing period, the switch array 126 is also used to provide the reference voltage Vref to the first input terminal of the amplifier 122. In addition, the sampling switch SW of the sample-and-hold circuit 124 is turned off, so that the sampling capacitor SC holds the sampled output of the amplifier 122 (i.e., the control signal Seao) during the tracking period. Therefore, the first end of the sampling capacitor SC outputs a fixed voltage to the control terminal of the transistor M1 to control the transistor M1 to maintain the magnitude of the first sub-current I_sub1 determined during the tracking period.

[0032] Therefore, the steps S330 performed during the sensing period include: turning off the sampling switch SW of the sample-and-hold circuit 124; and outputting the sampled output of the amplifier 122 to the first current control circuit 110 through the first end of the sampling capacitor SC of the sample-and-hold circuit 124 to control the first current control circuit 110 to maintain the magnitude of the first sub-current I_sub1 determined during the tracking period.

[0033] Please refer to Figure 4 , where Figure 4 is a schematic diagram of the first current control circuit 400 according to an embodiment of the present disclosure. In some embodiments, Figure 1 the first current control circuit 110 in Figure 4The first current control circuit 400 therein. The first current control circuit 400 includes a transistor M1' and a first current mirror CM1. The transistor M1' includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor M1' is used to receive a second operating voltage (e.g., a high voltage VDD), and the second operating voltage is higher than the first operating voltage (e.g., a ground voltage). The control terminal of the transistor M1' is coupled to the monitoring circuit 120 to receive a control signal Seao generated by the monitoring circuit 120 based on the voltage of the first node N1 and the reference voltage Vref. Specifically, the control terminal of the transistor M1' is coupled to the first terminal of a sampling capacitor SC of the sample and hold circuit 124.

[0034] The first current mirror CM1 includes an input terminal and an output terminal. The input terminal of the first current mirror CM1 is coupled to the second terminal of the transistor M1'. The output terminal of the first current mirror CM1 is coupled to the first node N1, and a first sub-current I_sub1 flows through the output terminal of the first current mirror CM1. The output of the amplifier 122 (i.e., the control signal Seao) controls the conduction degree of the transistor M1' to utilize the current generated by the transistor M1' and flowing into the input terminal of the first current mirror CM1, thereby controlling the first current mirror CM1 to determine the magnitude of the first sub-current I_sub1.

[0035] Therefore, in an embodiment where the first current control circuit 110 is replaced with the first current control circuit 400, the steps S320 performed during the tracking period include: generating, by the monitoring circuit 120, a control signal Seao based on the voltage of the first node N1 and the reference voltage Vref; receiving the control signal Seao through the control terminal of the transistor M1' of the first current control circuit 400; and determining the magnitude of the first sub-current I_sub1 by using the first current mirror CM1 of the first current control circuit 400. In the embodiment regarding the first current control circuit 400, the steps S310, S330, and S340 are similar to the steps S310, S330, and S340 described for the first current control circuit 110, and thus the detailed description thereof is omitted here.

[0036] The following details step S340. Please refer to Figure 5 , wherein Figure 5 is a schematic diagram of a reading circuit 500 according to an embodiment of the present disclosure. Figure 5 The reading circuit 500 of Figure 1The read circuit 130. The read circuit 500 includes a first switch circuit 510, a second switch circuit 520, and a storage array 530. The first switch circuit 510 includes first switches S1[1]-S1[n] and is coupled between the second node N2 and the storage array 530, where n is a positive integer. The second switch circuit 520 includes second switches S2[1]-S2[n] and is coupled between the third node N3 and the storage array 530. The storage array 530 includes resistors R[1]-R[n] connected in parallel between the first switch circuit 510 and the second switch circuit 520. Specifically, the first ends of the resistors R[1]-R[n] are respectively coupled to the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S1[1]-S1[n]. The second ends of the resistors R[1]-R[n] are respectively coupled to the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[1]-S2[n]. That is, the storage array 530 is coupled to the second input terminal of the amplifier 122 through the first switch circuit 510 and is coupled to the output terminal of the amplifier 122 through the second switch circuit 520.

[0037] The first switches S1[1]-S1[n] and the second switches S2[1]-S2[n] are turned off during the tracking period and turned on during the sensing period. During the sensing period, when the second sub-current I_sub2 flows through the resistors R[1]-R[n] from the second node N2 to the third node N3, an output voltage Vout is generated at the third node N3 (i.e., the output terminal of the amplifier 122). In some embodiments, the read circuit 500 further includes a reset circuit 540, where the reset circuit 540 can short the second node N2 to the third node N3 to reset the output voltage Vout.

[0038] In some embodiments, one or more of the resistors R[1]-R[n] can be respectively replaced by one or more capacitors to implement an integrator. In some embodiments, the first switches S1[1]-S1[n] or the second switches S2[1]-S2[n] can be omitted, that is, the read circuit 130 can include at least one switch circuit and a storage array 530, where the at least one switch circuit and the storage array 530 are coupled between the second input terminal of the amplifier 122 and the output terminal of the amplifier 122, and the at least one switch circuit is turned off during the tracking period and operates during the sensing period. Therefore, in Figure 5 the embodiments, step S340 is performed during the sensing period and includes: receiving the second sub-current I_sub2 through the storage array 530 of the read circuit 500; and generating an output voltage Vout at the output terminal of the amplifier 122 in response to the second sub-current I_sub2 flowing through the storage array 530 and the at least one switch circuit.

[0039] Please refer to Figure 6 , where Figure 6 is a schematic diagram of a read circuit 600 according to an embodiment of the present disclosure. The read circuit 600 includes a first switch circuit 610, a second switch circuit 620, and a storage array 630. The first switch circuit 610 includes first switches S1[1]-S1[4] and is coupled between a second node N2 and the storage array 630. The second switch circuit 620 includes second switches S2[1]-S2[4] and is coupled between a third node N3 and the storage array 630. The storage array 630 includes a first capacitor C[1] and a second capacitor C[2]. Two ends of the first capacitor C[1] are respectively coupled to the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S1[1] and S1[2], and two ends of the first capacitor C[1] are respectively coupled to the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[1] and S2[2]. Two ends of the second capacitor C[2] are respectively coupled to the second node N2 (i.e., the second input terminal of the amplifier 122) through the first switches S1[3] and S1[4], and two ends of the second capacitor C[2] are respectively coupled to the third node N3 (i.e., the output terminal of the amplifier 122) through the second switches S2[3] and S2[4]. In some embodiments, the read circuit 600 further includes a reset circuit 640, where the reset circuit 640 can short-circuit the second node N2 to the third node N3 to reset the output voltage Vout.

[0040] Please refer to Figure 6 、 Figure 7 and Figure 8 , where Figure 7 and Figure 8 are waveform schematic diagrams of the read circuit 600 according to an embodiment of the present disclosure. In Figure 7 and Figure 8 , the high level of the waveform represents that the corresponding component is turned on or enabled, and the low level of the waveform represents that the corresponding component is turned off or disabled. First, describe the embodiment of Figure 7 . In Figure 7During the sensing period, the PPG light source is enabled, and the first switch circuit 610 and the second switch circuit 620 form a first circuit topology to transmit the second sub-current I_sub2 to the first capacitor C[1] and the second capacitor C[2]. In addition, the first circuit topology is used to connect the first capacitor C[1] and the second capacitor C[2] in parallel between the second node N2 (i.e., the second input of the amplifier 122) and the third node N3 (i.e., the output of the amplifier 122). In one embodiment, the first circuit topology can be implemented by turning on the first switches S1[1] and S1[4] and the second switches S2[2] and S2[3] and turning off the other switches. Thus, both the environmental AC component Iac_amb and the reflected AC component Iac_rfl are stored in the first capacitor C[1] and the second capacitor C[2].

[0041] After Figure 7 the sensing period (i.e., after forming the first circuit topology), during the holding period, the PPG light source is disabled, and the first switch circuit 610 and the second switch circuit 620 form a second circuit topology to transmit the second sub-current I_sub2 to the second capacitor C[2]. In one embodiment, the second circuit topology can be implemented by turning on the first switch S1[4] and the second switch S2[3] and turning off the other switches. In some embodiments, the second switch S2[2] may remain on during the holding period. Thus, the information stored in the second capacitor C[2] is updated to include only the environmental AC component Iac_amb.

[0042] After Figure 7After the holding period (i.e., after forming the second circuit topology), in the output period, the first switching circuit 610 and the second switching circuit 620 form a third circuit topology to perform charge sharing between the first capacitor C[1] and the second capacitor C[2], thereby canceling the environmental AC component Iac_amb stored in the first capacitor C[1]. Specifically, the positive terminal (e.g., the first terminal) and the negative terminal (e.g., the second terminal) of the first capacitor C[1] are respectively coupled to the negative terminal (e.g., the first terminal) and the positive terminal (e.g., the second terminal) of the second capacitor C[2]. In some embodiments, the third circuit topology can be implemented by turning on the first switches S1[1] and S1[3] and the second switches S2[2] and S2[4] and turning off other switches. Therefore, the output voltage Vout is generated in the output period and only includes the reflected AC component Iac_rfl representing heart rate, blood oxygen saturation, etc. It should be understood that the number of capacitors in the storage array 630 is not intended to limit the scope of the present disclosure, but is provided as an exemplary embodiment, where the storage array 630 can include more than two capacitors for performing charge sharing to cancel the environmental AC component Iac_amb.

[0043] Referring to Figure 8 , in Figure 8 the sensing period, the first switching circuit 610 and the second switching circuit 620 form a different first circuit topology to transfer the second sub-current I_sub2 to the first capacitor C[1] instead of the second capacitor C[2]. Figure 8 The other operation periods of Figure 7 are respectively similar to the corresponding periods described in

[0044] Therefore, Figure 6 and Figure 7 Steps S340 of the embodiments are performed from the transmission period to the output period, and step S340 includes: in the sensing period, controlling the first switching circuit 610 and the second switching circuit 620 of the reading circuit 600 to form a first circuit topology to transfer the second sub-current I_sub2 to the first capacitor C[1] and the second capacitor C[2] of the reading circuit 600 and for connecting the first capacitor C[1] and the second capacitor C[2] in parallel between the second input terminal of the amplifier 122 and the output terminal of the amplifier 122; after forming the first circuit topology, controlling the first switching circuit 610 and the second switching circuit 620 to form a second circuit topology to transfer the second sub-current I_sub2 to the second capacitor C[2]; and after forming the second circuit topology, controlling the first switching circuit 610 and the second switching circuit 620 to form a third circuit topology to perform charge sharing between the first capacitor C[1] and the second capacitor C[2].

[0045] In addition, Figure 6 and Figure 8 step S340 of the embodiment is performed during the transmission period to the output period, and step S340 includes: during the sensing period, controlling the first switching circuit 610 and the second switching circuit 620 of the reading circuit 600 to form a first circuit topology to transmit the second sub-current I_sub2 to the first capacitor C[1] of the reading circuit 600; after forming the first circuit topology, controlling the first switching circuit 610 and the second switching circuit 620 to form a second circuit topology to transmit the second sub-current I_sub2 to the second capacitor C[2]; and after forming the second circuit topology, controlling the first switching circuit 610 and the second switching circuit 620 to form a third circuit topology to perform charge sharing between the first capacitor C[1] and the second capacitor C[2].

[0046] Step S350 will be described in detail below. Refer to Figure 9 , wherein Figure 9 is a schematic diagram of a second current control circuit 900 according to an embodiment of the present disclosure. The second current control circuit 900 is coupled to the first node N1 and can be used to implement Figure 1 the second current control circuit 140. The second current control circuit 900 includes a second current mirror 910, a switch array 920, and an enablement switch 930. The second current mirror 910 includes an input terminal and at least one output terminal, wherein the input terminal of the second current mirror 910 is used to receive a reference current I_ref. The enablement switch 930 includes a first terminal and a second terminal, wherein the first terminal of the enablement switch 930 is coupled to the first node N1 to receive a third sub-current I_sub3. The enablement switch 930 is used to conduct during the sensing period.

[0047] The switch array 920 is coupled between the second terminal of the enablement switch 930 and at least one output terminal of the second current mirror 910. Specifically, the switch array 920 includes at least one switch (e.g., switches 922[1]-922[k], where k is a positive integer), which are respectively coupled to at least one output terminal of the second current mirror 910. The switches 922[1]-922[k] are respectively controlled by the bits Sca[1]-Sca[k] of the calibration signal. In some embodiments, the calibration signal is generated and adjusted by Figure 1 the digital signal processor 103 based on the magnitude of the second sub-current I_sub2 in the previous sensing period during the current sensing period.

[0048] Specifically, when the third sub-current I_sub3 is different from the reflected DC component Idc_rfl, the second sub-current I_sub2 in the previous sensing period includes a part of the reflected DC component Idc_rfl that is not filtered by the third sub-current I_sub3 (hereinafter referred to as the redundant DC component). The digital signal processor 103 is used to detect the magnitude of the redundant DC component output from the analog-to-digital converter 101, and is used to adjust the bits Sca[1]-Sca[k] of the calibration signal based on the magnitude of the redundant DC component, so as to approximate the third sub-current I_sub3 generated by the second current control circuit 900 to the reflected DC component Idc_rfl.

[0049] Therefore, step S350 includes: in the sensing period, through the second current control circuit 900 (or Figure 1 the second current control circuit 140), determine the magnitude of the third sub-current I_sub3 based on the magnitude of the second sub-current I_sub2 in the previous sensing period, where the third sub-current I_sub3 is a part of the input current I_in.

[0050] It should be understood that the above signal filtering method 300 may include more or fewer operations than those shown in the Figure 3 flowchart, and these operations can be executed in any appropriate order. For example, steps S310 and S320 can be executed simultaneously. In another example, steps S330, S340, and S350 can be executed simultaneously.

[0051] In some embodiments, Figure 1 、 Figure 4 and Figure 9 the N-type and P-type transistors in can be replaced with P-type and N-type transistors respectively. In addition, Figure 1 the first operating voltage represented by the ground symbol in can be replaced with a high voltage, and Figure 1 the second operating voltage represented by the high voltage in can be replaced with a low voltage. In this case, the directions of the input current I_in, the first sub-current I_sub1, the second sub-current I_sub2, and the third sub-current I_sub3 are respectively opposite to the directions shown in Figure 1

[0052] ​Certain terms are used in the specification and claims to refer to particular elements. However, one of ordinary skill in the art should understand that the same element may be referred to by different terms. The specification and claims do not use the differences in terms as a way to distinguish elements, but rather use the differences in the functions of the elements as the basis for distinction. In addition, it should be understood that the term "comprising" used in the specification and claims is open-ended, that is, including but not limited to. In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described that a first element is coupled to a second element, it means that the first component can be directly connected to the second element through an electrical connection or have a signal connection such as wireless transmission, optical transmission, etc., or the first element is indirectly electrically connected or signal-connected to the second element through other elements or connection means.

[0053] It should be understood that, throughout the discussion herein and in the claims that follow, the phrase "and / or" includes any and all combinations of one or more of the associated listed items. Unless the context clearly dictates otherwise, a single term used herein includes a plurality of referents.

[0054] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of this disclosure provided they fall within the scope of the appended claims and their equivalents.

[0055] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure document. Those skilled in the art should understand that they can readily use the present disclosure document as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure document, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure document.

[0056] Symbolic Explanation

[0057] 100: Analog Front-End Circuit

[0058] 101: Analog-to-Digital Converter

[0059] 103: Digital Signal Processor

[0060] 110, 400: First Current Control Circuit

[0061] 120: Monitoring Circuit

[0062] 122: Amplifier

[0063] 124: Sample and Hold Circuit

[0064] 126,920: Switch Array

[0065] 130,500,600: Reading Circuit

[0066] 140,900: Second Current Control Circuit

[0067] 300: Signal Filtering Method

[0068] 510,610: First Switch Circuit

[0069] 520,620: Second Switch Circuit

[0070] 530,630: Storage Array

[0071] 540,640: Reset Circuit

[0072] 910: Second Current Mirror

[0073] 922[1]-922[k]: Switch

[0074] Sca[1]-Sca[k]: Bit

[0075] 930: Enable Switch

[0076] I_in: Input Current

[0077] I_sub1: First Sub-Current

[0078] I_sub2: Second Sub-Current

[0079] I_sub3: Third Sub-Current

[0080] Vref: Reference Voltage

[0081] N1: First Node

[0082] N2: Second Node

[0083] N3: Third Node

[0084] Vout: Output Voltage

[0085] Seao: Control Signal

[0086] SW: Sampling Switch

[0087] SC: Sampling Capacitor

[0088] M1,M1': Transistor

[0089] PI: Physiological Information

[0090] Iac_amb: Ambient Alternating Current Component

[0091] Idc_amb: Ambient Direct Current Component

[0092] Iac_rfl: Reflected Alternating Current Component

[0093] Idc_rfl: Reflected Direct Current Component

[0094] VDD: High Voltage

[0095] CM1: First Current Mirror

[0096] S1[1]-S1[n]: First Switch

[0097] S2[1]-S2[n]: Second Switch

[0098] R[1]-R[n]: Resistor

[0099] C[1]: First Capacitor

[0100] C[2]: Second Capacitor

[0101] I_ref: Reference Current

[0102] S310, S320, S330, S340, S350: Steps

Claims

1. An analog front-end circuit for photoplethysmography, comprising: A first current control circuit, coupled to a first node and configured to generate a first sub-current, wherein the first sub-current is a part of an input current flowing into the first node; A monitoring circuit, coupled to the first node and configured to receive a reference voltage, wherein during a tracking period, the monitoring circuit is configured to control the first current control circuit to determine the magnitude of the first sub-current so as to control the voltage of the first node to track the reference voltage; And A reading circuit, coupled to the first node through the monitoring circuit; Wherein during a sensing period after the tracking period, the monitoring circuit is configured to control the first current control circuit to maintain the first sub-current at the magnitude of the first sub-current determined during the tracking period; Wherein after maintaining the first sub-current, the monitoring circuit is configured to transfer a second sub-current from the first node to the reading circuit, such that the reading circuit is configured to convert the second sub-current into an output voltage, wherein the second sub-current is a part of the input current.

2. The analog front-end circuit according to claim 1, wherein the monitoring circuit comprises: An amplifier, comprising a first input terminal, a second input terminal and an output terminal, wherein the second input terminal of the amplifier is coupled to the reading circuit; A sample-and-hold circuit, coupled to the output terminal of the amplifier and the first current control circuit and configured to sample the output of the amplifier, wherein the sample-and-hold circuit is configured to output the sampled output of the amplifier to control the first current control circuit to determine the magnitude of the first sub-current; And A switch array, coupled to the first node, the first input terminal and the second input terminal of the amplifier and configured to receive the reference voltage, wherein during the tracking period, the switch array is configured to respectively provide the second sub-current and the reference voltage to the first input terminal and the second input terminal of the amplifier, and wherein during the sensing period, the switch array is configured to respectively provide the second sub-current and the reference voltage to the second input terminal and the first input terminal of the amplifier.

3. The analog front-end circuit according to claim 2, wherein the sample-and-hold circuit comprises: A sampling capacitor, comprising a first end and a second end, wherein the first end of the sampling capacitor is coupled to the first current control circuit, and the second end of the sampling capacitor is configured to receive a first operating voltage; And A sampling switch, coupled between the output terminal of the amplifier and the first end of the sampling capacitor, wherein the sampling switch is turned on during the tracking period and turned off during the sensing period.

4. The analog front-end circuit according to claim 2, wherein the reading circuit comprises: At least one switch circuit, configured to be turned off during the tracking period and turned on during the sensing period; And A storage array, comprising at least one resistor connected in parallel and coupled to the at least one switch circuit; Wherein the at least one switch circuit and the storage array are coupled between the second input terminal of the amplifier and the output terminal of the amplifier.

5. The analog front-end circuit according to claim 2, wherein the reading circuit comprises: A first switch circuit; A second switch circuit; A first capacitor; And A second capacitor; Wherein two ends of the first capacitor and two ends of the second capacitor are coupled to a second input end of the amplifier through the first switch circuit, and two ends of the first capacitor and two ends of the second capacitor are coupled to an output end of the amplifier through the second switch circuit; Wherein during the sensing period, the first switch circuit and the second switch circuit form a first circuit topology to transmit the second sub-current to the first capacitor and the second capacitor, and to connect the first capacitor and the second capacitor in parallel between the second input end of the amplifier and the output end of the amplifier; Wherein after forming the first circuit topology, the first switch circuit and the second switch circuit form a second circuit topology to transmit the second sub-current to the second capacitor; Wherein after forming the second circuit topology, the first switch circuit and the second switch circuit form a third circuit topology to perform charge sharing between the first capacitor and the second capacitor.

6. The analog front-end circuit according to claim 2, wherein the reading circuit comprises: A first switch circuit; A second switch circuit; A first capacitor; And A second capacitor; Wherein two ends of the first capacitor and two ends of the second capacitor are coupled to a second input end of the amplifier through the first switch circuit, and two ends of the first capacitor and two ends of the second capacitor are coupled to an output end of the amplifier through the second switch circuit; Wherein during the sensing period, the first switch circuit and the second switch circuit form a first circuit topology to transmit the second sub-current to the first capacitor; Wherein after forming the first circuit topology, the first switch circuit and the second switch circuit form a second circuit topology to transmit the second sub-current to the second capacitor; Wherein after forming the second circuit topology, the first switch circuit and the second switch circuit form a third circuit topology to perform charge sharing between the first capacitor and the second capacitor.

7. The analog front-end circuit according to claim 1, wherein the first current control circuit comprises: A transistor, comprising a first end, a second end and a control end, wherein the first sub-current flows through the transistor, wherein the first end of the transistor is coupled to the first node, the second end of the transistor is configured to receive a first operating voltage, and the control end of the transistor is coupled to the monitoring circuit to receive a control signal generated by the monitoring circuit based on the voltage at the first node and the reference voltage.

8. The analog front-end circuit according to claim 1, wherein the first current control circuit comprises: A transistor, comprising a first end, a second end and a control end, wherein the first end of the transistor is configured to receive a second operating voltage, and the control end of the transistor is coupled to the monitoring circuit to receive a control signal generated by the monitoring circuit based on the voltage at the first node and the reference voltage; And A first current mirror, including an input terminal and an output terminal, wherein the input terminal of the first current mirror is coupled to the second terminal of the transistor, and the output terminal of the first current mirror is coupled to the first node, and a first sub-current flows through the output terminal of the first current mirror.

9. The analog front-end circuit according to claim 1, further comprising: A second current control circuit, coupled to the first node and configured to generate a third sub-current during the sensing period, wherein the third sub-current is a part of the input current; wherein the second current control circuit is configured to determine the magnitude of the third sub-current according to the magnitude of the second sub-current in the previous sensing period.

10. A signal filtering method for photoplethysmography, comprising: During a tracking period, monitoring, by a monitoring circuit, a voltage of a first node and a reference voltage, wherein an input current flows into the first node; During the tracking period, controlling, by the monitoring circuit, a first current control circuit coupled to the first node to determine a magnitude of a first sub-current, wherein the first sub-current is a part of the input current and is generated by the first current control circuit; During a sensing period after the tracking period, controlling, by the monitoring circuit, the first current control circuit to maintain the first sub-current having the magnitude of the first sub-current determined during the tracking period; and after maintaining the first sub-current, converting, by a reading circuit coupled to the first node via the monitoring circuit, a second sub-current transmitted from the first node to the reading circuit by the monitoring circuit into an output voltage, wherein the second sub-current is a part of the input current.

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