Analog-to-digital converter and image sensor including same

Abstract

An analog-to-digital converter and an image sensor including the same are provided. The image sensor includes: a pixel array including a plurality of active pixels; and an analog-to-digital converter (ADC) that converts pixel signals of the plurality of active pixels into digital signals. The ADC includes: an input circuit outputting a first signal in which a ramp signal is applied to a pixel signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply node and a ground node, and outputting, to an output node, a second signal obtained by inverting a first signal input through the input node; and a code generation circuit outputting a digital signal based on the second signal. The inverter includes at least one bias transistor connected in series with the pull-down transistor between the pull-down transistor and a ground node and controlled by a bias voltage.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2024-0010838, filed with the Korean Intellectual Property Office on January 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The exemplary embodiments disclosed herein relate to a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and more particularly, to an analog-to-digital converter that converts a pixel signal of an image sensor into a digital signal and an image sensor including the analog-to-digital converter. Background Art

[0003] An image sensor is a device that converts an optical signal into an electrical signal and includes a charge-coupled device (CCD) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor.

[0004] Although power consumption increases due to an increase in the number of pixels in an image sensor, the importance of low-power driving capabilities in a mobile environment is also increasing.

[0005] Related art image sensors mainly use an OTA (Operational Transconductance Amplifier) analog-to-digital converter based on 5 transistors (5T) (hereinafter, referred to as ADC) to convert a pixel signal into a digital signal. However, the 5T-based OTA ADC has a problem in ensuring full well capacity (FWC) in a low-power environment using a low driving voltage due to a narrow signal input range. Summary of the Invention

[0006] The disclosed exemplary embodiments provide an image sensor that operates stably in a low-power environment.

[0007] The disclosed embodiments provide an image sensor that can be implemented with a relatively small area.

[0008] According to one or more exemplary embodiments disclosed, an image sensor includes: a pixel array including a plurality of active pixels; and an analog-to-digital converter (ADC) configured to convert pixel signals of the plurality of active pixels into digital signals, wherein the ADC includes: an input circuit configured to receive a ramp signal and a pixel signal and output a first signal in which the ramp signal is applied to the pixel signal; an inverter including a pull-up transistor and a pull-down transistor serially connected between a power node and a ground node, the inverter being configured to output a second signal obtained by inverting the first signal input through an input node to an output node; and a code generation circuit configured to output a digital signal based on the second signal, and wherein the inverter includes at least one bias transistor that is serially connected to the pull-down transistor between the pull-down transistor and the ground node and is configured to be controlled by a bias voltage.

[0009] According to one or more exemplary embodiments disclosed, an image sensor includes a plurality of pixels, and each of the plurality of pixels includes: a photodetector including a photoelectric conversion element; an input circuit configured to receive a ramp signal and a pixel signal of the plurality of pixels and output a first signal in which the pixel signal is applied to the ramp signal; an inverter including a pull-up transistor and a pull-down transistor serially connected between a power terminal and a ground terminal, the inverter being configured to output a second signal obtained by inverting the first signal input through an input node to an output node; and a code generation circuit configured to output a digital signal based on the second signal, and wherein the inverter includes at least one bias transistor that is serially connected to the pull-down transistor between the pull-down transistor and the ground terminal and is configured to be controlled by a bias voltage.

[0010] According to one or more exemplary embodiments disclosed, an image sensor includes: a pixel array including a plurality of active pixels; and an analog-to-digital converter (ADC) configured to convert pixel signals of the plurality of active pixels into digital signals, wherein the ADC includes: an input circuit configured to receive a ramp signal and a pixel signal and configured to output a first signal in which the ramp signal is applied to the pixel signal; an inverter including a pull-up transistor and a pull-down transistor serially connected between a power node and a ground node, the inverter being configured to output a second signal obtained by inverting the first signal input through an input node to an output node; and a code generation circuit configured to output a digital signal based on the second signal, and wherein the inverter includes at least one starvation transistor configured to limit a magnitude of a current flowing through at least one of the pull-up transistor and the pull-down transistor during a transition operation of the inverter.

[0011] According to one or more disclosed example embodiments, an analog-to-digital converter (ADC) includes: an inverter including a P-type pull-up transistor and an N-type pull-down transistor, the P-type pull-up transistor and the N-type pull-down transistor being serially connected to each other between a power supply node and a ground node through an output node and having gate electrodes connected to an input node, the inverter being configured to output a second signal obtained by inverting a first signal input through the input node to the output node; and a code generation circuit configured to output a digital signal based on the second signal, wherein the inverter includes at least one bias transistor, the at least one bias transistor being serially connected to the N-type pull-down transistor between the N-type pull-down transistor and the ground node and being configured to be controlled by a bias voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the disclosure will become apparent by describing the disclosed embodiments in detail with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating an example of an image device according to one or more disclosed example embodiments.

[0014] Figure 2 is a view illustrating an image sensor according to one or more disclosed example embodiments.

[0015] Figure 3A and Figure 3B is a view illustrating a pixel of an image sensor according to a disclosed example embodiment.

[0016] Figure 4 is a view illustrating an analog-to-digital converter (ADC) according to one or more disclosed example embodiments.

[0017] Figure 5 is a view illustrating a bias circuit of an image sensor according to one or more disclosed example embodiments.

[0018] Figure 6 is illustrated according to Figure 4 a view of an operation timing of an ADC according to an example embodiment.

[0019] Figure 7A is conceptually described according to Figure 4 a view of a signal swing of an ADC according to an example embodiment.

[0020] Figure 7B is illustrated according to Figure 4 a view of a result of a pixel swing of an image sensor including an ADC according to an example embodiment.

[0021] Figure 8is a diagram showing an ADC according to one or more other exemplary embodiments disclosed.

[0022] Figure 9 is a block diagram of an image sensor according to one or more exemplary embodiments disclosed.

[0023] Figure 10 is a block diagram of an image sensor according to one or more other exemplary embodiments disclosed.

[0024] Figure 11 is a block diagram of an image sensor according to one or more other exemplary embodiments disclosed.

[0025] Figure 12 is a block diagram of an image sensor according to one or more other exemplary embodiments disclosed.

[0026] Figure 13 is a block diagram of an electronic device according to one or more exemplary embodiments disclosed.

[0027] Figure 14 is a block diagram of an application processor according to one or more exemplary embodiments disclosed. Detailed Description

[0028] Hereinafter, the disclosed exemplary embodiments may be described in detail and clearly to such an extent that an ordinary person skilled in the art can easily implement the disclosure.

[0029] Figure 1 is a block diagram showing an example of an image device 1000 according to one or more exemplary embodiments disclosed.

[0030] According to one or more exemplary embodiments disclosed, the image device 1000 may perform analog-to-digital conversion on a pixel signal PXS by using an inverter-based analog-to-digital converter (ADC) 150 including a bias transistor.

[0031] Referring to Figure 1 , the image device 1000 may include an image sensor 100 and an image signal processor 200.

[0032] The image device 1000 may be an electronic device (such as, a digital camera, a smart phone, a wearable device, the Internet of Things (IoT), a tablet computer, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, etc.). In addition, the image device 1000 may be an electronic device provided as an accessory included in a vehicle, a manufacturing facility, a door, various measurement devices, etc.

[0033] The image sensor 100 can be implemented to generate image data as visual information of an object captured through a lens, and the image signal processor 200 can be implemented to process the image data generated by the image sensor 100 for output to a display device or for storage in a storage device.

[0034] The image signal processor 200 can perform demosaic on the image signal according to a pixel pattern by interpolation, can perform color correction, can adjust the dynamic range, or can reduce noise by filtering or the like. The image signal processor 200 can additionally perform other methods for improving image quality.

[0035] In Figure 1 , the image signal processor 200 is shown to be placed outside the image sensor 100. However, in some embodiments, the image signal processor 200 can be placed inside the image sensor 100. Optionally, according to an embodiment, part of the logic of the image signal processor 200 can be placed in the image sensor 100, and other logic can be placed in an application processor (AP) outside the image sensor 100.

[0036] The image sensor 100 can include a pixel array 110, a row driver 120, a timing controller 130, a ramp signal generator (Ramp Gen.) 140, an ADC 150, and a buffer 160.

[0037] The pixel array 110 can include a plurality of pixels (e.g., active pixels). For example, the plurality of pixels can be arranged in a matrix form. The pixel array 110 can receive a plurality of pixel drive signals CSn (such as a selection signal for controlling a selection transistor, a reset signal for controlling a reset transistor, and a transfer transistor control signal for controlling a transfer transistor) from the row driver 120. Each of the plurality of pixels in the pixel array 110 can operate under the control of the received pixel drive signal CSn.

[0038] The row driver 120 can drive one row of the pixel array 110 under the control of the timing controller 130. The row driver 120 can generate a selection signal for driving one row among the plurality of rows. The row driver 120 can activate the pixels corresponding to the selected row. The pixel signals PXS of the pixels of the selected row can be transmitted to the ADC 150 through a plurality of column lines CLm.

[0039] The pixel signal PXS can include a reset voltage signal and a pixel voltage signal. The pixel voltage signal can be the voltage of a floating diffusion region that "embodies the charge generated in the photodiode PD included in each of the plurality of pixels". The reset voltage signal can be the voltage of a floating diffusion region that "does not embody the charge generated in the photodiode PD".

[0040] The timing controller 130 can control the pixel array 110, the row driver 120, the ramp signal generator 140, and the ADC 150. The timing controller 130 can provide a timing control signal TC to the row driver 120. The timing controller 130 can control the ramp signal generator 140 through a ramp control signal CS_RP and can control the ADC 150 through an ADC control signal CS_ADC. The ramp control signal CS_RP can include a ramp enable signal, a mode signal, and the like.

[0041] The ramp signal generator 140 can generate a ramp signal RAMP in response to the ramp enable signal. The ramp signal generator 140 can generate a ramp signal RAMP having a preset slope. The ramp signal generator 140 can provide the generated ramp signal RAMP to the ADC 150. In one embodiment, the slope of the ramp signal RAMP can be set differently based on the mode signal. The mode signal can be a signal based on a capture mode selected by a user. For example, the capture mode can be a wide-angle mode, a low-light mode, or the like.

[0042] The ADC 150 can convert a reset voltage signal and a pixel voltage signal of the pixel signal PXS into pixel data PXD as a digital signal based on the ramp signal RAMP for output. For example, the ADC 150 can use a correlated double sampling (CDS) method to convert the reset voltage signal and the pixel voltage signal into digital signals respectively based on the ramp signal RAMP, and can output the difference between the reset voltage signal and the pixel voltage signal as the pixel data PXD, and the pixel data PXD is a digital signal.

[0043] According to one or more exemplary embodiments disclosed, the ADC 150 may convert a pixel signal PXS using an inverter 152_1 including a bias transistor and may output pixel data PXD. The ADC 150 based on the inverter 152_1 may output pixel data PXD as a digital signal converted from the pixel signal PXS, where the pixel signal PXS is an analog signal. The ADC 150 may perform analog-to-digital conversion based on the inverter 152_1, and the inverter 152_1 includes a smaller number of transistors compared to a related art 5-transistor (5T) operational transconductance amplifier (OTA) ADC. Accordingly, the ADC 150 has a headroom for an operating voltage such that the ADC 150 may operate within a wide pixel swing range even in a low-power environment provided with a low driving voltage. In addition, at least one bias transistor serially connected to the inverter 152_1 of the ADC 150 may operate as a current-dependent source. As a result, the influence of the power supply voltage on the inverter 152_1 of the ADC 150 may be reduced, thereby allowing the ADC 150 to operate stably. In some embodiments, the operating voltage range of the inverter 152_1 may be set to be greater than 50% of the driving voltage provided from a power supply node (or referred to as a power supply terminal). In one example, the power supply node may supply power of 1V or less.

[0044] The buffer 160 may be implemented to temporarily store the pixel data PXD output from the ADC 150 and then amplify and output the stored pixel data PXD.

[0045] Figure 2 is a diagram showing in detail an image sensor according to one or more exemplary embodiments disclosed. Figure 2 The image sensor 100 of may correspond to Figure 1 The image sensor 100 of. Referring to Figure 2 , the image sensor 100 according to one or more exemplary embodiments disclosed includes a pixel array 110, a row driver 120, a timing controller 130, a ramp signal generator 140, an ADC 150, and a buffer 160. The embodiments described with reference to Figure 2 will be described on the assumption that the ADC 150 is arranged for each column line and the ADCs 150 for the respective column lines operate in parallel. However, the embodiments described with reference to Figure 2 do not limit the arrangement of the ADC 150 for each column line. Specifically, as in the embodiments described below with reference to Figures 10 to 12 , the ADC 150 may be arranged for each pixel or for each pixel group. In this case, the ADC 150 may operate in parallel for each pixel or for each pixel group.

[0046] The pixel array 110 may include a plurality of pixels PX. Each pixel PX may be electrically connected to one row line and one column line among a plurality of row lines and a plurality of column lines. In one embodiment, each pixel PX may include a plurality of transistors controlled by the row driver 120. Optionally, in another embodiment, two or more adjacent pixels PX may form a pixel group, and two or more pixels PX included in the pixel group may share at least some of the transfer transistor, the driving transistor, the selection transistor, and the reset transistor.

[0047] Each of the plurality of pixels PX may include a photodetector, and the photodetector may include a photoelectric conversion element that converts an incident optical signal into an electrical signal. Each pixel PX may include at least one photoelectric conversion element.

[0048] The photoelectric conversion element may be a photodiode PD. The photoelectric conversion element may be any one of a photodiode (PD), a photoelectric capacitor, a photogate, a pinned photodiode (PPD), a partially pinned photodiode, an organic photodiode (OPD), and a quantum dot (QD), or a combination thereof. Embodiments of this specification are described on the premise that the photoelectric conversion element is a photodiode PD, but the embodiments of this specification are not limited to the photodiode PD, and the above other photoelectric conversion elements may be used.

[0049] The pixel signal PXS generated from each pixel of the row selected by the selection signal of the row driver 120 may be transmitted to the ADC 150 through the column line corresponding to each pixel.

[0050] The ADC 150 may include an input circuit (INCT) 151, a comparator 152, and a code generation circuit 153.

[0051] There are a plurality of input circuits (INCT) 151 according to one or more example embodiments disclosed, and the plurality of input circuits 151 may correspond to a plurality of column lines. Each of the input circuits 151 may receive the pixel signal PXS from the column line and the ramp signal RAMP from the ramp signal generator 140. The input circuit 151 may generate a first output signal obtained by applying the ramp signal RAMP to the pixel signal PXS. The first output signal may be provided to the comparator 152. Specifically, the input signal input to the comparator 152 may be a signal obtained by applying the ramp signal RAMP to the pixel signal PXS.

[0052] Comparator 152 according to one or more disclosed example embodiments may generate a comparison result signal by comparing a first output signal "obtained by applying a ramp signal RAMP to a pixel signal PXS" with a reference level. Comparator 152 may generate the comparison result signal based on a correlated double sampling method. Comparator 152 may generate the comparison result signal by comparing the reference level with each first output signal obtained by applying the ramp signal RAMP to each of a reset voltage signal and a pixel voltage signal. Comparator 152 may compare each first output signal "obtained by applying the ramp signal RAMP to each of the reset voltage signal and the pixel voltage signal" with a reference level of the same voltage level. Specifically, a decision point for each comparison operation for the reset voltage signal and the pixel voltage signal may be maintained at the same voltage level. The generated comparison result signal may be provided to a code generation circuit 153.

[0053] Comparator 152 may include a plurality of stages. The first stage of the plurality of stages may include an inverter INV, and the second stage of the plurality of stages may include an amplifier AMP. The inverter INV may receive the first output signal and may provide a second output signal obtained by inverting the first output signal to the amplifier AMP. The inverter INV may include at least one bias transistor controlled by a bias voltage. The amplifier AMP may generate the comparison result signal by amplifying the second output signal and may provide the comparison result signal to the code generation circuit 153.

[0054] The code generation circuit 153 may include a counter CNT. The counter CNT may count a clock signal corresponding to the level of the reset voltage signal and the level of the pixel voltage signal based on the comparison result signal obtained by applying the ramp signal RAMP to each of the reset voltage signal and the pixel voltage signal. The counter CNT may generate pixel data PXD as a digital signal based on the difference between the level of the reset voltage signal and the level of the pixel voltage signal.

[0055] The buffer 160 may include a plurality of column memory blocks (MEM) 161 corresponding to a plurality of columns for storing the pixel data PXD. The buffer 160 may include a sense amplifier (SA) 162 for amplifying the pixel data PXD stored in the column memory block 161. The sense amplifier (SA) 162 may output the amplified pixel data PXD as image data IDT.

[0056] Figure 3A and Figure 3B is a diagram showing pixels of an image sensor according to a disclosed example embodiment. Figure 3A of the pixel PXa and Figure 3B of the pixel PXb each may be associated with Figure 2corresponds to the pixel PX of the image sensor 100.

[0057] Referring to Figure 3A , the pixel PXa may include a photoelectric conversion element PD, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX.

[0058] The photoelectric conversion element PD may generate photocharge corresponding to incident light.

[0059] The transfer transistor TX may electrically connect the photoelectric conversion element PD to the floating diffusion node FD based on a transfer transistor control signal TG. When the transfer transistor TX is turned on, the photocharge of the photoelectric conversion element PD electrically connected to the floating diffusion node FD may move to the floating diffusion node FD.

[0060] The reset transistor RX may electrically connect the floating diffusion node FD to a reset voltage. The reset transistor RX may reset the floating diffusion node FD to the voltage level of the power supply node VDD through a reset control signal RS provided from the Figure 1 and Figure 2 row driver 120. Figure 3A It is shown that the reset voltage is provided from the power supply node VDD, but according to an embodiment, the reset voltage may be provided from a voltage node having a voltage level other than the voltage level of the power supply node VDD.

[0061] The driving transistor DX may be driven by a driving voltage provided from the power supply node VDD. The driving transistor DX may output an output voltage Vout corresponding to the charge accumulated in the floating diffusion node FD. The driving transistor DX may output the output voltage Vout to the column line CLi through a selection transistor SX (e.g., turned on based on a selection control signal SEL).

[0062] The reset voltage signal output after the floating diffusion node FD and the reset voltage are electrically connected through the reset transistor RX and the pixel voltage signal output after the photocharge of the photoelectric conversion element PD moves to the floating diffusion node FD may be output to the column line CLi as the output voltage Vout, respectively.

[0063] Figure 1 and Figure 2 The ADC 150 of

[0064] Referring to Figure 3B, the pixel PXb may include a plurality of photoelectric conversion elements PD, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX. Specifically, the plurality of photoelectric conversion elements PD may share the transfer transistor TX, the floating diffusion node FD, the reset transistor RX, the driving transistor DX, and the selection transistor SX.

[0065] The reset voltage signal output after electrically connecting the floating diffusion node FD to the reset voltage through the reset transistor RX and the pixel voltage signal output after the optical charges of the plurality of photoelectric conversion elements PD move to the floating diffusion node FD in the same time period may be respectively output as the output voltage Vout to the column line CLi.

[0066] Figure 3B It is shown that one transfer transistor TX shared by the plurality of photoelectric conversion elements PD may be controlled by the same transfer transistor control signal TG, but the disclosure is not limited thereto, and the plurality of photoelectric conversion elements PD may be electrically connected to the floating diffusion node FD through different transfer transistors. In this case, the different transfer transistors may be controlled by different transfer transistor control signals.

[0067] The pixels in the disclosed exemplary embodiments are not limited to Figure 3A the pixel PXa and Figure 3B the pixel PXb. Various pixel forms and operations may be used (such as, for example, a form in which one microlens is shared by the plurality of photoelectric conversion elements PD of one pixel, a form in which one microlens is shared by the plurality of photoelectric conversion elements PD of a plurality of pixels, and a form in which one pixel or a group of pixels outputs a plurality of pixel signals based on different conversion gains).

[0068] Figure 4 is a diagram showing in detail an ADC according to one or more exemplary embodiments of the disclosure. Figure 4 The ADC 150 of Figure 1 and Figure 2 corresponds to the ADC 150 of Figure 4 The embodiments described with reference to Figure 4 will be described on the assumption that the ADC 150 is arranged for each column line and operates in parallel for each column line. However, the embodiments described with reference to Figures 10 to 12 do not limit the arrangement of the ADC 150 for each column line. Specifically, as in the embodiments described below with reference to

[0069] Referring to Figure 4, the ADC 150 may include an input circuit 151, an inverter 152_1, an amplifier (AMP) 152_2, and a counter (CNT) 153_1. Figure 4 The input circuit 151, the inverter 152_1, the amplifier 152_2, and the counter 153_1 shown in Figure 4 may correspond to a column line CLi. Accordingly, the ADC 150 of the image sensor may include an input circuit, an inverter, an amplifier, and a counter corresponding to each column line.

[0070] In one embodiment, Figure 4 the ADC 150 may be a single-slope ADC.

[0071] The input circuit 151 according to one or more example embodiments disclosed may include a plurality of capacitors C1 and C2.

[0072] The first capacitor C1 may be connected to the column line CLi and the input node IN. The pixel signal PXS output from the pixel PX through the column line CLi may be sampled by the first capacitor C1 and transmitted to the input node IN. Specifically, the first capacitor C1 may sample each of the reset voltage signal and the pixel voltage signal of the analog signal component output from the pixel PX.

[0073] The second capacitor C2 may be connected to the ramp signal generator and the input node IN. The second capacitor C2 may receive the ramp signal RAMP generated by the ramp signal generator. According to an embodiment, the ramp signal RAMP may be a single-slope upward slope ramp signal increasing at a consistent slope, or a single-slope downward slope ramp signal decreasing at a consistent slope. The second capacitor C2 may perform a function of attenuating the direct current (DC) component of the ramp signal RAMP and transmitting the voltage change of the ramp signal RAMP to the input node IN.

[0074] The voltage change (e.g., voltage change amount) of the ramp signal RAMP at the input node IN may be applied to the pixel signal PXS and input to the inverter 152_1 as the input signal Vf.

[0075] The inverter 152_1 may include a pull-up transistor PUT, a pull-down transistor PDT, an auto-zero transistor AZT, and a bias transistor BT.

[0076] The pull-up transistor PUT and the pull-down transistor PDT are different types of transistors and can be connected in series between a power supply node VDD and a ground node (or ground terminal) GND. For example, the pull-up transistor PUT can be a P-type metal oxide semiconductor field effect transistor (MOSFET), and the pull-down transistor PDT can be an N-type MOSFET. The source terminal of the pull-up transistor PUT can be connected to the power supply node VDD, and the drain terminal of the pull-up transistor PUT can be connected to the drain terminal of the pull-down transistor PDT and the output node OUT. The source terminal of the pull-down transistor PDT can be connected to the ground node GND through a bias transistor BT. The gate terminals of the pull-up transistor PUT and the pull-down transistor PDT can be commonly connected to the input node IN. The inverter 152_1 can receive an input signal Vf from the input node IN and can output an output signal OUT1 obtained by inverting the input signal Vf to the output node OUT.

[0077] The input node IN and the output node OUT of the inverter 152_1 can be connected through an auto-zeroing transistor AZT. The source terminal of the auto-zeroing transistor AZT can be connected to the input node IN of the inverter 152_1, and the drain terminal of the auto-zeroing transistor AZT can be connected to the output node OUT. The auto-zeroing transistor AZT can be controlled by an auto-zeroing signal AZS and can operate like a switch. The auto-zeroing signal AZS can be an initialization signal for determining an initial operating level when the ADC 150 starts operating and can be provided from Figure 1 and Figure 2 the timing controller 130.

[0078] The output signal OUT1 output from the output node OUT of the inverter 152_1 can be input to an amplifier (AMP) 152_2, and the CDS signal OUT2 amplified by the amplifier 152_2 can be input to a counter (CNT) 153_1. The amplifier 152_2 can include a common-source amplifier. Optionally, the amplifier 152_2 can include an operational amplifier (OP-AMP).

[0079] The counter 153_1 can count the level of the input signal Vf based on the CDS signal OUT2. The counter 153_1 can count the level of the input signal Vf by considering the difference between the level of the reset voltage signal and the level of the pixel voltage signal. Information about counting the level of the input signal Vf can be output as pixel data PXD, which is a digital signal. The counter 153_1 can include an up / down counter or a bit-by-bit counter.

[0080] The inverter 152_1 according to one or more disclosed example embodiments may include at least one bias transistor BT connected in series with the pull-down transistor PDT between the pull-down transistor PDT and the ground node GND. Figure 4 It is shown that there is one bias transistor BT, but according to an embodiment, the bias transistors BT may be connected in series with each other.

[0081] When the bias transistor BT is implemented as an N-type MOSFET, the drain terminal of the bias transistor BT may be connected to the source terminal of the pull-down transistor PDT, and the source terminal of the bias transistor BT may be connected to the ground node GND. The gate terminal of the bias transistor BT may be connected to a bias circuit and may be controlled by a bias voltage BN. The magnitude of the bias current IB may be adjusted by the magnitude of the bias voltage BN.

[0082] Therefore, the bias transistor BT may operate as a current-dependent source due to the bias voltage BN, and the bias current IB as a controlled current may flow through the bias transistor BT. As a result, when the on state (or off state) of the pull-up transistor PUT and the off state (or on state) of the pull-down transistor PDT change, it is feasible to prevent the output signal OUT1 from changing significantly due to the power supply node VDD being affected by the current path instantaneously occurring in the inverter 152_1. Specifically, the output signal OUT1 of the inverter 152_1 may be stably output through the bias transistor BT. The bias transistor BT may be a starving transistor, which is configured to limit the amount of current flowing through the pull-up transistor PUT or the pull-down transistor PDT (or at least one of the pull-up transistor PUT and the pull-down transistor PDT) during the transition operation of the inverter 152_1.

[0083] According to an embodiment, a cascode transistor (not shown) connected in series to each of the bias transistor BT and the pull-down transistor PDT may be additionally provided between the bias transistor BT and the pull-down transistor PDT. The cascode transistor may include a gate electrode receiving a cascode voltage. The cascode transistor may be used as a buffer between the power supply node VDD and the bias transistor BT. When the cascode transistor is implemented as an N-type MOSFET and the cascode voltage remains at a high level, the magnitude of the bias current IB may be adjusted by the magnitude of the bias voltage BN.

[0084] Compared with the related art ADC, the ADC 150 described with reference to Figure 4 can be implemented with a smaller number of transistors. Therefore, the ADC 150 according to one or more disclosed example embodiments may have a wider swing range of the input signal. Although in Figure 4In the embodiments, the ADC 150 is described as being arranged for each column line. However, due to the small area of the image sensor, in an alternative embodiment, the ADC 150 may be arranged for each pixel and the ADC 150 may operate in parallel for each pixel.

[0085] Figure 5 is a diagram showing a bias circuit of an image sensor according to one or more exemplary embodiments. As Figure 5 The bias voltage BN, which is the output of the bias circuit 170, may correspond to the bias voltage BN supplied to the bias transistor BT described with reference to Figure 4

[0086] The bias circuit 170 may include a constant current source IS, a first mirror circuit 171, a second mirror circuit 172, and an output circuit 173. In addition to Figure 5 the bias circuit 170 shown in

[0087] In the bias circuit 170, the current supplied from the constant current source IS may be mirrored by the first mirror circuit 171, the second mirror circuit 172, and the output circuit 173, and the gate voltage of the output circuit 173 may be output as the bias voltage BN. The bias voltage BN may be provided to Figure 4 the gate terminal of the bias transistor BT in

[0088] According to an embodiment, when a cascode transistor (not shown) connected in series with the bias transistor BT of Figure 4 is additionally provided, the cascode voltage supplied to the gate terminal of the cascode transistor may be the bias voltage BN that is the output of the bias circuit 170. Alternatively, the cascode voltage may be a voltage of a different magnitude output from a circuit having a structure similar to the bias circuit 170 shown in Figure 5 Figure 5 In

[0089] Figure 6 is a diagram showing the operation timing of an ADC according to one or more exemplary embodiments. Figure 6 The operation timing of Figure 4 may correspond to the operation of the ADC 150 according to the embodiment of Figure 4 and Figure 6 Figure 6 The operation timing of Figure 4The ramp signal RAMP of the input circuit 151 of the ADC 150 in the embodiment is an upward slope ramp signal in the form of a single slope that increases at a consistent slope. However, a downward slope ramp signal in the form of a single slope that decreases at a consistent slope can also be applied in a similar manner.

[0090] After selecting a row of the pixel array, the auto-zero transistor AZT can be turned on by the auto-zero signal AZS at time t0. The auto-zero transistor AZT can remain in the on state during the section (or time period) between time t0 and time t1. The section between time t0 and time t1 can be referred to as the auto-zero section before the operation of the inverter 152_1 is performed.

[0091] The inverter 152_1 can be initialized in response to the auto-zero signal AZS during the auto-zero section. When the auto-zero transistor AZT is turned on, the input node IN through which the input signal Vf is input and the output node OUT through which the output signal OUT1 of the inverter 152_1 is output can be electrically connected to each other. As a result, during the auto-zero section, the voltage levels of the input node IN and the output node OUT of the inverter 152_1 can become the same level as the common level voltage VCM (e.g., the reference level). At time t1, the auto-zero transistor AZT can be turned off, and the auto-zero transistor AZT can remain off during the operation section of the inverter 152_1.

[0092] After subtracting the offset from the ramp signal RAMP at time t2, the ramp signal RAMP that starts to increase from time t3 can be reflected in the reset voltage signal of the pixel signal PXS, and as a result, the input signal Vf can be increased. The CDS signal OUT2 of the amplifier 152_2 can remain high until time t4 when the input signal Vf is at the same level as the level of the first decision point DP1, and the CDS signal OUT2 of the amplifier 152_2 changes to low at time t4.

[0093] The counter 153_1 can count the counting clock signal CNT_CLK from time t3 until time t4. At time t4, the polarity of the CDS signal OUT2 of the amplifier 152_2 is inverted to low. When the counter 153_1 is an up / down counter, the counter 153_1 can count down the counting clock signal CNT_CLK from time t3 to time t4. The counter 153_1 can stop counting the counting clock signal CNT_CLK at time t4 when the CDS signal OUT2 is inverted to low, and can latch the count value from time t3 to time t4 as data in response to the turn-on (or activation) of the hold signal HOLD. As a result, the count value corresponding to the voltage magnitude of the reset voltage signal can be stored. The hold signal HOLD can be generated byFigure 2 is provided by the timing controller 130.

[0094] Figure 6 shows the switching of activating the count clock signal CNT_CLK from time t3 to time t4. However, according to an embodiment, the switching of the count clock signal CNT_CLK can be activated before this and can be held until time t5. In this case, the counting operation of the count clock signal CNT_CLK for the counter 153_1 can be performed only from time t3 to time t4.

[0095] The first determination point DP1 at which the counting operation of the counter 153_1 for the voltage magnitude of the reset voltage signal of the pixel signal PXS stops can correspond to the time when the input signal Vf becomes the same level as the common level voltage VCM.

[0096] In order to count the voltage magnitude of the pixel voltage signal of the pixel signal PXS between time t5 and time t6, when the counter 153_1 is an up / down counter, the count reverse signal RVS_CNT can be inverted and provided to the counter 153_1 to perform an up counting.

[0097] The input signal Vf whose offset is reflected by subtracting the ramp signal RAMP from the pixel voltage signal at time t5 can reflect the increase of the ramp signal RAMP from time t6. The CDS signal OUT2 of the amplifier 152_2 can remain high until time t7 when the input signal Vf becomes the same level as the level of the second determination point DP2, and is inverted to low level at time t7.

[0098] The counter 153_1 can count the count clock signal CNT_CLK from time t6 until time t7. At time t7, the polarity of the CDS signal OUT2 of the amplifier 152_2 is inverted to low level. When the counter 153_1 is an up / down counter, the counter 153_1 can perform an up counting of the count clock signal CNT_CLK from time t6 to time t7. The counter 153_1 can stop counting the count clock signal CNT_CLK at time t7 when the CDS signal OUT2 is inverted to low level and can latch the count value up to that time as data. As a result, the count value corresponding to the voltage magnitude of the pixel voltage signal can be stored.

[0099] The counter 153_1 can output the result of calculating the count value corresponding to the voltage magnitude of the reset voltage signal and the count value corresponding to the voltage magnitude of the pixel voltage signal as pixel data PXD, and the pixel data PXD is a digital signal.

[0100] The second determination point DP2 at which the counting operation of the counter 153_1 for the voltage magnitude of the pixel voltage signal of the pixel signal PXS is stopped can correspond to the time when the input signal Vf becomes the same level as the common level voltage VCM. Specifically, the voltage magnitudes of both the pixel voltage signal and the reset voltage signal can be determined by comparing the magnitude of the input signal Vf with the magnitude of the common level voltage VCM. In short, the determination points DP1 and DP2 of each of the reset voltage signal and the pixel voltage signal of the pixel signal PXS can be maintained at the same voltage level that can be used as the common level voltage VCM. Therefore, since the voltage magnitudes of both the reset voltage signal and the pixel voltage signal can be counted by comparing with the same voltage level, the structure and operation of the counter 153_1 can be simplified.

[0101] Figure 7A conceptually describes the signal swing of an ADC according to Figure 4 the embodiment of Figure 7A The input signal Vf of Figure 4 can correspond to the input signal Vf of the ADC 150 according to Figure 7B shows the result of simulating the pixel swing of an image sensor applying the ADC 150 according to Figure 4 the embodiment of Figure 7B shows the simulation result assuming that the capacitors C1 and C2 have the same capacitance. Referring to Figure 4 , Figure 7A and Figure 7B , the pixel swing of the ADC 150 will be described. Figure 7A and Figure 7B are diagrams of an upward slope ramp signal in the form of a single slope where the ramp signal RAMP input to the input circuit 151 of the ADC 150 according to Figure 4 the embodiment of

[0102] Figure 7A shows the first input signal DARK based on the optical signal input to the image sensor in a dark environment and the second input signal BRIGHT based on the optical signal input to the image sensor in a bright environment.

[0103] The reset voltage signals of the first input signal DARK and the second input signal BRIGHT can be counted between time t1 and time t2. The pixel voltage signal of the first input signal DARK can be counted between time t3 and time t4, and the pixel voltage signal of the second input signal BRIGHT can be counted between time t3 and time t5.

[0104] Refer to Figure 7A , a signal swing SWING is shown, where the signal swing SWING is a voltage level difference between an input signal Vf corresponding to pixel voltage signals of a first input signal DARK and a second input signal BRIGHT.

[0105] Compared with load transistors between a power supply node and an output terminal and load transistors between the output terminal and a ground node of the ADC 150 according to the disclosed embodiments, the related-art 5T-based OTA ADC has a much larger number of load transistors between the power supply node and the output terminal and load transistors between the output terminal and the ground node. Thus, when a power supply voltage of 1V is used at the power supply node, the operable pixel swing of the related-art 5T-based OTA ADC is experimentally confirmed to be about 250mV. As a result, in the related-art 5T-based OTA ADC, the range of the signal swing within the range of the pixel swing can be smaller. Therefore, when a low power supply voltage as a driving voltage is used in a low-power environment, there is a problem that the range of the pixel swing of the first input signal DARK and the second input signal BRIGHT in the related-art 5T-based OTA ADC may not be able to achieve high-bit resolution of an image signal.

[0106] In contrast, since the number of load transistors between the output terminal and the power supply node is reduced and the number of load transistors between the output terminal and the ground node is reduced, the ADC 150 according to one or more example embodiments disclosed can ensure a large margin. Thus, even when a low power supply voltage is used as a driving voltage in a low-power environment, the ADC 150 according to one or more example embodiments disclosed also has a larger range of pixel swing of the first input signal DARK and the second input signal BRIGHT. As a result, the range of the signal swing is widened, and as a result, high-bit resolution of an image signal can be ensured.

[0107] Figure 7B Shows the results of the ADC 150 according to one or more example embodiments disclosed at various levels (e.g., 0.85V, 1.05V, or 1.25V) of the power supply voltage with respect to each of various process corners at a very low temperature (e.g., -55 degrees Celsius ( C)), room temperature (e.g., 25 degrees Celsius), and high temperature (e.g., 105 degrees Celsius). Refer to Figure 7B, It is confirmed that, in the simulation for each environment, even when a power supply voltage of 0.85 V is received, the narrowest range of the pixel swing of the ADC 150 according to one or more disclosed exemplary embodiments is greater than 500 mV. Therefore, even when a low power supply voltage is used as a driving voltage in a low-power environment, the ADC 150 according to one or more disclosed exemplary embodiments has a high ratio of pixel swing to the low power supply voltage, and thus high-bit resolution of the image signal can be ensured.

[0108] Figure 8 is a view showing an ADC according to another disclosed exemplary embodiment. Figure 8 The ADC 150b can be associated with Figure 1 and Figure 2 The ADC 150 corresponds. Referring to Figure 8 , an ADC 150b according to another disclosed exemplary embodiment will be described. Additional descriptions of portions overlapping with the description with reference to Figure 4 will be omitted to avoid redundancy. The embodiment described with reference to Figure 8 is described on the assumption that the ADC 150b is arranged for each column line and operates in parallel for each column line. However, the embodiment described with reference to Figure 8 is not limited to arranging the ADC 150b for each column line. For example, as in the exemplary embodiment described below with reference to Figures 10 to 12 , the ADC 150b can be arranged for each pixel or for each pixel group. In this case, the ADC 150b can operate in parallel for each pixel or for each pixel group.

[0109] Referring to Figure 8 , the ADC 150b can include an input circuit 151, an inverter 152_1b, an amplifier (AMP) 152_2, and a counter (CNT) 153_1. The input circuit 151, the inverter 152_1b, the amplifier 152_2, and the counter 153_1 shown in Figure 8 can be arranged for each column line.

[0110] The input circuit 151 can include a first capacitor C1 and a second capacitor C2. The first capacitor C1 samples each of a reset voltage signal and a pixel voltage signal of an analog signal component output from the pixel PX, and the second capacitor C2 receives a ramp signal RAMP.

[0111] The voltage change amount of the ramp signal RAMP at the input node IN can be reflected in the pixel signal PXS and can be input as an input signal Vf to the inverter 152_1b.

[0112] The inverter 152_1b according to one or more exemplary embodiments disclosed may include a pull-up transistor PUT, a pull-down transistor PDT, an auto-zeroing transistor AZT, a bias transistor BT, and a plurality of path transistors PT1 and PT2.

[0113] The pull-up transistor PUT and the pull-down transistor PDT may be different types of transistors connected in series between a power supply node VDD and a ground node GND, and the gate terminals of the pull-up transistor PUT and the pull-down transistor PDT may be commonly connected to an input node IN. The inverter 152_1b may receive an input signal Vf from the input node IN, and may output an output signal OUT1 obtained by inverting the input signal Vf to an output node OUT. The input node IN and the output node OUT of the inverter 152_1b may be connected to each other through the auto-zeroing transistor AZT.

[0114] The output signal OUT1 of the inverter 152_1b may be input to an amplifier 152_2, and the amplifier 152_2 may amplify the output signal OUT1 and may output a CDS signal OUT2. A counter 153_1 may count the level of the input signal Vf based on the CDS signal OUT2, and may output information about the counting of the level of the input signal Vf as pixel data PXD, where the pixel data PXD is a digital signal.

[0115] Unlike the embodiment described with reference to Figure 4 the inverter 152_1b of the ADC 150b according to one or more exemplary embodiments disclosed may include a plurality of path transistors PT1 and PT2.

[0116] The path transistors PT1 and PT2 may be implemented as different types of transistors, and may be connected in parallel between the power supply node VDD and the bias transistor BT. Specifically, one terminal of each of the path transistors PT1 and PT2 may be connected to the power supply node VDD, and the other terminal may be connected to the drain terminal of the bias transistor BT. In one example, the path transistors PT1 and PT2 may be controlled by the same control signal. For example, the gate terminals of the path transistors PT1 and PT2 may be connected to the input node IN, and may be controlled by the input signal Vf input to the inverter 152_1b.

[0117] When the level of the input signal Vf changes to another level, the pull-up transistor PUT and the pull-down transistor PDT can change from the conducting state to the non-conducting state or can change from the non-conducting state to the conducting state simultaneously. Similarly, through the same input signal Vf, the first path transistor PT1 can change to the same state as the pull-up transistor PUT, and the second path transistor PT2 can change to the same state as the pull-down transistor PDT. That is to say, the first path transistor PT1 and the second path transistor PT2 can conduct in different time periods. Therefore, when the states of the pull-up transistor PUT and the pull-down transistor PDT are changed by the input signal Vf, at the same time, one of the first path transistor PT1 and the second path transistor PT2 can change to the conducting state. Specifically, a current path can always exist between the power supply node VDD and the bias transistor BT. As a result, the current path through the first path transistor PT1 or the second path transistor PT2 can prevent power fluctuations caused by the simultaneous state change of the pull-up transistor PUT and the pull-down transistor PDT. Therefore, the current path through the first path transistor PT1 or the second path transistor PT2 can prevent the magnitude of the bias current IB flowing through the bias transistor BT from instantaneously changing due to power fluctuations. The current path formed by the first path transistor PT1 or the second path transistor PT2 can stably maintain the magnitude of the bias current IB flowing through the bias transistor BT. In addition, the power supply node VDD affected by the ADC 150b can be reduced due to the bias current IB of the bias transistor BT. The bias current IB can remain substantially consistent in the first section and the second section of the input signal Vf. The first section is from the time when the input signal Vf of the inverter 152_1b starts to change to the time when the input signal Vf reaches the level of the decision point. The second section is from the time when the input signal Vf reaches the level of the decision point until the input signal Vf is inverted after reaching the level of the decision point. In addition, due to the smaller number of load transistors of the ADC 150b, a stable operating voltage range for the pixel swing can be ensured.

[0118] While being implemented with a smaller number of transistors than the ADCs of the related art, the ADC 150b described with reference to Figure 8 can operate stably. Therefore, due to the small area, in an embodiment different from the embodiment described as being arranged for each column line Figure 8 , the ADC 150b can be arranged for each pixel and can operate in parallel for each pixel.

[0119] Figure 9 is a block diagram of the image sensor 100a according to one or more exemplary embodiments disclosed. Additional descriptions of the overlapping parts will be omitted to avoid redundancy.

[0120] The image sensor 100a may include a stacked first chip (or first die) 10a and a second chip (or second die) 20a.

[0121] For example, the first chip 10a may be stacked on the second chip 20a in a direction D3 perpendicular to the plane of the substrate. The first chip 10a may be electrically connected to the second chip 20a. For example, the first chip 10a and the second chip 20a may send pixel signals or control signals through through-silicon vias (TSVs, or through-silicon vias) between pads located in the peripheral area of the chips. The first chip 10a may also be electrically connected to the second chip 20a through an intra-pixel contact IN_CT inside the pixel PXc. The intra-pixel contact may be, for example, a Cu-to-Cu (C2C) bonding contact. The pixel signals (or pixel data) of the first chip 10a may be sent to the readout circuit (or image signal processing logic) of the second chip 20a.

[0122] There may be a plurality of pixels PXc in the pixel array, and the plurality of pixels PXc may be arranged in a matrix form in the pixel array. The pixel circuit of the pixel PXc according to one or more exemplary embodiments disclosed may be driven in a low-power environment. For example, the pixel circuit may be driven by a power supply voltage of about 1V. The pixels PXc of the pixel array may output pixel signals including a reset voltage signal or a pixel voltage signal for the CDS method.

[0123] The second chip 20a may include a readout circuit, a timing controller, logic (such as image signal processing logic), and an interface circuit. The readout circuit may include an ADC.

[0124] The second chip 20a according to one or more exemplary embodiments disclosed may include any one of the above ADC 150 and / or ADC150b. Optionally, according to an embodiment, a part of the circuit of the ADC 150 and / or ADC 150b may be provided on the first chip 10a, and other circuits may be provided on the second chip 20a. When part or all of the circuits of the ADC 150 and / or ADC 150b are provided on the first chip 10a, part or all of the circuits of the ADC 150 and / or ADC 150b may be provided inside the pixel PXc. In this case, the pixel PXc may send pixel data to the second chip 20a.

[0125] Figure 10 It is a block diagram of an image sensor 100b according to another exemplary embodiment disclosed. Additional descriptions of parts overlapping with the above will be omitted to avoid redundancy.

[0126] The image sensor 100b may include a stacked first chip 10b and second chip 20b. The first chip 10b and the second chip 20b may be connected to each other through a wafer bonding process using Cu-to-Cu (C2C) interconnections at the pixel level. The first chip 10b and the second chip 20b may be electrically connected not only through intra-pixel contacts inside the pixel PXd, but also through a Cu-to-Cu (C2C) array located in the peripheral region of the chip. Control signals for controlling the pixel circuits may be sent through the C2C array. Pixel signals (or pixel data) of the first chip 10b may be sent to the readout circuit (or image signal processing logic) of the second chip 20b through the intra-pixel contacts.

[0127] The second chip 20b according to one or more of the disclosed example embodiments may include any one of the above-described ADC 150 and / or ADC150b.

[0128] In one embodiment, the ADC 150 and / or ADC 150b may be disposed on the second chip 20b. In this case, the ADC 150 and / or ADC 150b may operate for each column line, or according to an embodiment, the ADC 150 and / or ADC150b may be C2C interconnected with the pixel PXd at the pixel level, and the ADC 150 and / or ADC 150b may operate in parallel for each pixel.

[0129] In another embodiment, a part of the ADC 150 and / or ADC 150b may be disposed on the first chip 10b, and another part (or the remaining part) may be disposed on the second chip 20b. Optionally, all of the ADC 150 and / or ADC 150b may be disposed on the first chip 10b. When part or all of the ADC 150 and / or ADC 150b are disposed on the first chip 10b, according to an embodiment, part or all of the ADC 150 and / or ADC 150b may be disposed inside the pixel PXd. The partial circuits of the ADC 150 and / or ADC 150b disposed inside the pixel PXd may be electrically connected to the other circuits of the ADC 150 and / or ADC 150b disposed on the second chip 20b through C2C interconnections at the pixel level. In addition, the ADC 150 and / or ADC 150b may operate in parallel for each pixel.

[0130] In one embodiment, the ADC 150 and / or ADC 150b may be Figure 2 disposed for each column line as in the

[0131] In another embodiment, the ADC 150 and / or the ADC 150b may not operate for each column line, but for each pixel. Specifically, the ADC 150 and / or the ADC 150b may be specifically provided for each pixel or pixel group and may operate in parallel with each other. Therefore, parallel digital conversion can be performed on the output of each pixel PXd. In this case, some or all of the ADC 150 and / or the ADC 150b may be provided on the first chip 10b, or some or all of the ADC 150 and / or the ADC 150b may be provided on the second chip 20b.

[0132] Figure 11 is a block diagram of an image sensor 100c according to another embodiment disclosed. Additional descriptions of parts overlapping with the above will be omitted to avoid redundancy.

[0133] Referring to Figure 11 , in addition to the first chip 10c and the second chip 20c, the image sensor 100c may further include a third chip 30c. The third chip 30c, the second chip 20c, and the first chip 10c may be sequentially stacked in a direction D3 perpendicular to the plane of the substrate. The third chip 30c may include a memory device. For example, the third chip 30c may include a volatile memory device (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)). The third chip 30c may receive signals from the first chip 10c and the second chip 20c and may process the signals through the memory device.

[0134] In one embodiment, the ADC 150 and / or the ADC 150b may be provided on the second chip 20c. In this case, the ADC 150 and / or the ADC 150b may operate for each column line, or according to an embodiment, the ADC 150 and / or the ADC 150b may be C2C interconnected with the pixel PXe at the pixel level and may operate in parallel for each pixel.

[0135] In another embodiment, some or all of ADC 150 and / or ADC 150b may be disposed on the first chip 10c. When a part of ADC 150 and / or ADC 150b is disposed on the first chip 10c, another part may be disposed on the second chip 20c. When some or all of ADC 150 and / or ADC 150b are disposed on the first chip 10c, according to an embodiment, some or all of ADC 150 and / or ADC 150b may be disposed inside the pixel PXe. When a partial circuit of ADC 150 and / or ADC 150b is disposed inside the pixel PXe of the first chip 10c, the partial circuit of ADC 150 and / or ADC 150b disposed inside the pixel PXe may be electrically connected to other circuits of ADC 150 and / or ADC 150b disposed on the second chip 20c by pixel-level C2C interconnection. In addition, ADC 150 and / or ADC 150b may operate in parallel for each pixel.

[0136] In one embodiment, ADC 150 and / or ADC 150b may be disposed for each column line as in the Figure 2 embodiment, and may perform parallel digital conversion on the outputs of the column lines.

[0137] In another embodiment, ADC 150 and / or ADC 150b may not operate for each column line, but for each pixel. Specifically, ADC 150 and / or ADC 150b may be specifically disposed for each pixel or pixel group, and may operate in parallel with each other. Therefore, parallel digital conversion may be performed on the output of each pixel PXe.

[0138] In addition, ADC 150 and / or ADC 150b may be set to be partially separated on multiple chips and electrically connected to each other. The number of multiple chips is not specifically limited. For example, in two chips according to the Figure 10 embodiment and three chips according to the Figure 11 embodiment and more than that number of multiple chips, ADC 150 and / or ADC 150b may be separately disposed on multiple chips and may be set to be electrically connected. The mutually separated partial circuits in ADC 150 and / or ADC 150b may be electrically connected to each other not only through the in-pixel C2C interconnection within the pixel, but also through the C2C array located in the peripheral area of the chip.

[0139] According to an embodiment, the nodes separating ADC 150 and / or ADC150b may be determined in various ways. For example, the input circuit 151 of the above-mentioned ADC 150 and / or ADC 150b may be disposed on the Figure 9 first chip 10a of Figure 10the first chip 10b, and / or Figure 11 on the first chip 10c. The inverters 152_1 and 152_1b, the amplifier 152_2, and the counter 153_1 of the ADC 150 and / or ADC 150b can be provided on Figure 9 the second chip 20a of Figure 10 the second chip 20b, and / or Figure 11 on the second chip 20c. Optionally, the input circuit 151 and one of the pull-up transistor PUT and the pull-down transistor PDT of the inverters 152_1 and 152_1b can be provided on Figure 9 the first chip 10a of Figure 10 the first chip 10b, and / or Figure 11 on the first chip 10c, and the remaining circuits of the inverters 152_1 and 152_1b and the counter 153_1 can be provided on Figure 9 the second chip 20a of Figure 10 the second chip 20b, and / or Figure 11 on the second chip 20c. Figure 12 is a block diagram of an image sensor 100d according to one or more disclosed example embodiments. Additional descriptions of parts overlapping with the above will be omitted to avoid redundancy.

[0140] Referring to Figure 12 , the image sensor 100d can include a first chip 10d and a second chip 20d. The first chip 10d and the second chip 20d can be sequentially stacked in a direction perpendicular to the plane of the substrate. For example, the second chip 20d can include a logic and input / output (IO) block.

[0141] The first chip 10d and the second chip 20d can be connected to each other through a wafer bonding process using pixel-level C2C interconnections. The first chip 10d and the second chip 20d can be electrically connected not only through the in-pixel contacts inside the pixel PXf, but also through a Cu-to-Cu (C2C) array located in the peripheral area of the chip.

[0142] Each pixel PXf of the first chip 10d according to one or more disclosed example embodiments may include any one of the above-described ADC150 and / or ADC 150b. Optionally, each pixel PXf may include a partial circuit of the ADC 150 and / or ADC 150b. For example, the input circuit 151 of the above-described ADC 150 and / or ADC 150b may be disposed inside each pixel PXe of the first chip 10d, and the inverter, amplifier, and counter of the ADC 150 and / or ADC 150b may be disposed on the second chip 20d. Optionally, the input circuit 151 and one of the pull-up transistor PUT and the pull-down transistor PDT of the inverter may be disposed inside each pixel PXe of the first chip 10d. Specifically, one of the ADC 150 and / or ADC 150b may be provided specifically for each pixel PXf or for each pixel group including adjacent pixels. Thus, according to an embodiment, the ADC 150 and / or ADC 150b of each pixel PXf or each pixel group may perform analog-to-digital conversion in parallel for each pixel or each pixel group.

[0143] Figure 13 is a block diagram of an electronic device according to one or more disclosed example embodiments. Additional descriptions of portions overlapping with the above will be omitted to avoid redundancy.

[0144] The electronic device 1000b may include an imaging unit 1100, an image sensor 1200, and a processor 1300. The electronic device 1000b may perform autofocus based on phase data provided from the image sensor 1200 to the processor 1300.

[0145] The processor 1300 may control the overall operation of the electronic device 1000b. The processor 1300 may control the position of the lens 1110 by providing a control signal to the actuator 1120. As a result, the focal length may be controlled.

[0146] The imaging unit 1100 may be a component that receives light, and may include a lens 1110 and an actuator 1120. The lens 1110 may include a plurality of lenses.

[0147] The actuator 1120 may move the lens 1110 in a direction in which the distance from the object “S” increases or decreases based on a control signal from the processor 1300.

[0148] The image sensor 1200 may generate image data and phase data based on incident light. The image sensor 1200 may include a pixel array 1210, a timing controller 1220, an ADC 1230, and an image signal processor (ISP-FE) 1240.

[0149] The pixels of the pixel array 1210 may include at least one photoelectric conversion element.

[0150] The ADC 1230 according to one or more exemplary embodiments disclosed may be an inverter-based ADC. For example, the ADC 1230 may be any one of the above-mentioned ADC 150 and / or ADC 150b. Thus, even in a low-power environment, the electronic device 1000b according to one or more exemplary embodiments disclosed can stably convert a pixel signal into pixel data as a digital signal.

[0151] The processor 1300 may perform parallax calculation using the phase data. The processor 1300 may provide a control signal based on the parallax calculation result to the actuator 1120 to move the position of the lens 1110.

[0152] The processor 1300 may provide an operation mode control signal INFO_MD to the timing controller 1220. The timing controller 1220 may control the operation of the pixel array 1210 based on the operation mode control signal INFO_MD.

[0153] Figure 14 is a block diagram of an application processor 1300b according to one or more exemplary embodiments disclosed. Additional descriptions of parts overlapping with the above will be omitted to avoid redundancy.

[0154] The application processor 1300b may include an image signal processing device 1310. The image signal processing device 1310 may include a plurality of image signal processing units 1311 to 1313 (ISP1, ISP2, and ISP3), a camera module control unit 1314, and a camera interface 1315.

[0155] The camera module control unit 1314 may send control signals CSa, CSb, and CSc to a plurality of camera modules based on a mode signal. Figure 14 It is shown that the control signals CSa, CSb, and CSc are sent to three camera modules, but the embodiment is not limited thereto. According to an embodiment, the camera module control unit 1314 may send control signals to two camera modules, or may send control signals to four or more camera modules.

[0156] The image signals ISa, ISb, and ISc according to one or more exemplary embodiments disclosed may be based on signals digitally converted by the ADCs of a plurality of cameras. The ADCs of the plurality of cameras may be inverter-based ADCs. In an inverter-based ADC, a bias transistor may be connected in series between the pull-down transistor PDT and the ground node.

[0157] The image signals ISa, ISb, and ISc can be stored in the external memory 1400 from multiple cameras through the camera interface 1315. The image signal processing units ISP1 and ISP2 can process the image signals ISa, ISb, and ISc stored in the external memory 1400, and can display the processed image signals ISa, ISb, and ISc on a display, or can perform autofocus. The image signals ISa, ISb, and ISc can include image data and phase data. The image signals ISa, ISb, and ISc stored in the external memory 1400 can be encoded image signals. The image signal processing units ISP1 and ISP2 can read the encoded image signals from the external memory 1400 and decode the encoded image signals, and can display the image data generated based on the decoded image signals. In one example, the image signal processing unit ISP3 can be connected to the image generator 1500.

[0158] According to one or more example embodiments disclosed, an image sensor can operate stably in a low-power environment.

[0159] According to one or more example embodiments disclosed, an image sensor can be implemented in a relatively small area.

[0160] The above description is provided to describe examples for implementing the disclosed embodiments. Embodiments with simple design changes or easily changeable designs should be included in the disclosure and the above embodiments. In addition, techniques that can be easily changed and implemented using the above embodiments should be included in the disclosure. Although the disclosure has been described with reference to the disclosed embodiments, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims and their equivalents.

Claims

1. An image sensor, comprising: a pixel array including a plurality of active pixels; and an analog-to-digital converter configured to: convert pixel signals of the plurality of active pixels into digital signals, and wherein the analog-to-digital converter includes: an input circuit configured to receive a ramp signal and a pixel signal and configured to output a first signal obtained by applying the ramp signal to the pixel signal; an inverter including a pull-up transistor and a pull-down transistor connected in series between a power supply node and a ground node, the inverter being configured to output a second signal obtained by inverting a first signal input through an input node of the inverter to an output node of the inverter; and a code generation circuit configured to: output a digital signal based on the second signal, and wherein the inverter includes at least one bias transistor, the at least one bias transistor being connected in series with the pull-down transistor between the pull-down transistor and the ground node and configured to be controlled by a bias voltage.

2. The image sensor according to claim 1, wherein, A drain terminal of the at least one bias transistor is electrically connected to a source terminal of the pull-down transistor, and a source terminal of the at least one bias transistor is electrically connected to the ground node.

3. The image sensor according to claim 1, wherein, The power supply node is set to supply power of 1V or less.

4. The image sensor according to claim 1, Among them, the magnitude of a reset voltage signal of the pixel signal is determined based on a comparison between a first signal obtained by applying a ramp signal to the reset voltage signal and a reference voltage level, and wherein the magnitude of a pixel voltage signal of the pixel signal is determined based on a comparison between a first signal obtained by applying a ramp signal to the pixel voltage signal and a reference voltage level.

5. The image sensor according to claim 1, wherein, The input circuit includes: a first capacitor configured to: sample the pixel signal and be electrically connected to an input node of the inverter; and a second capacitor configured to: transfer a voltage change of the ramp signal to the input node of the inverter.

6. The image sensor according to claim 1, wherein, The inverter includes an auto-zeroing transistor having a source terminal and a drain terminal electrically connected to the input node and the output node, respectively, and the auto-zeroing transistor is configured to be controlled by an auto-zeroing signal input to a gate terminal of the auto-zeroing transistor.

7. The image sensor according to claim 1, further comprising: a first transistor and a second transistor connected in parallel between the power supply node and a drain terminal of the at least one bias transistor, and wherein the first transistor and the second transistor are set to be turned on in different time periods.

8. The image sensor according to claim 7, wherein, The first transistor and the second transistor are different types of transistors and are set to be controlled by the same control signal.

9. The image sensor according to claim 8, wherein, The first transistor and the second transistor are set to be controlled by a first signal.

10. The image sensor according to claim 7, wherein, The first signal includes a first section and a second section, the first section from the time when the first signal starts to change to the time when the first signal reaches the reference voltage level, the second section from the time when the first signal reaches the reference voltage level to the time when the first signal is inverted, and wherein the first transistor and the second transistor are set such that magnitudes of currents flowing through the at least one bias transistor in a time period corresponding to the first section and a time period corresponding to the second section are consistent.

11. The image sensor according to any one of claims 1 to 10, wherein, The operating voltage range of the inverter is set to be greater than 50% of the driving voltage supplied from the power supply node.

12. The image sensor according to any one of claims 1 to 10, wherein, The pixel array is provided on the first die, and wherein at least a part of the analog-to-digital converter is provided on the first die, and the remaining part of the analog-to-digital converter is provided on the second die, and the second die is electrically connected to the first die and vertically stacked.

13. The image sensor according to claim 12, wherein, The input circuit is provided on the first die, and the inverter and the code generation circuit are provided on the second die.

14. The image sensor according to claim 12, wherein, One of the pull-up transistor and the pull-down transistor of the inverter and the input circuit are provided on the first die, and the remaining circuit of the inverter and the code generation circuit are provided on the second die.

15. An image sensor, the image sensor including a plurality of pixels, wherein, Each of the plurality of pixels includes: A photodetector including a photoelectric conversion element; An input circuit configured to receive a ramp signal and a pixel signal of the plurality of pixels, and configured to output a first signal obtained by applying the ramp signal to the pixel signal; An inverter including a pull-up transistor and a pull-down transistor connected in series between a power terminal and a ground terminal, and configured to output a second signal obtained by inverting the first signal input through the input node of the inverter to the output node of the inverter; and A code generation circuit configured to: output a digital signal based on the second signal, and wherein the inverter includes at least one bias transistor, and the at least one bias transistor is connected in series with the pull-down transistor between the pull-down transistor and the ground terminal and is configured to be controlled by a bias voltage.

16. An image sensor, comprising: A pixel array including a plurality of active pixels; And An analog-to-digital converter configured to convert pixel signals of the plurality of active pixels into digital signals, wherein the analog-to-digital converter includes: An input circuit configured to receive a ramp signal and a pixel signal, and configured to output a first signal obtained by applying the ramp signal to the pixel signal; An inverter including a pull-up transistor and a pull-down transistor connected in series between a power node and a ground node, and the inverter is configured to output a second signal obtained by inverting the first signal input through the input node of the inverter to the output node of the inverter; and A code generation circuit configured to: output a digital signal based on the second signal, and wherein the inverter includes at least one starvation transistor, and the at least one starvation transistor is configured to limit the magnitude of the current flowing through at least one of the pull-up transistor and the pull-down transistor during the transition operation of the inverter.

17. An analog-to-digital converter, comprising: An inverter including a P-type pull-up transistor and an N-type pull-down transistor, and the P-type pull-up transistor and the N-type pull-down transistor are connected in series with each other between a power node and a ground node through the output node of the inverter and have gate electrodes connected to the input node of the inverter, and the inverter is configured to output a second signal obtained by inverting the first signal input through the input node to the output node; And A code generation circuit configured to: output a digital signal based on the second signal, Among them, the inverter includes at least one bias transistor, and the at least one bias transistor is connected in series with the N-type pull-down transistor between the N-type pull-down transistor and the ground node and is configured to be controlled by a bias voltage.

18. The analog-to-digital converter according to claim 17, further comprising: A first transistor and a second transistor, connected in parallel between the power supply node and the drain terminal of the at least one bias transistor, wherein the first transistor and the second transistor are arranged to be turned on in different time periods by the same control signal.

19. The analog-to-digital converter according to claim 17, wherein, The at least one bias transistor is configured to operate as a current-dependent current source.

20. The analog-to-digital converter according to claim 17, further comprising: An auto-zeroing transistor, configured to: connect the input node to the output node.

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