Static and dynamic switching preamplifier and working method thereof
By designing a statically and dynamically switchable preamplifier in a successive approximation analog-to-digital converter, the problems of high power consumption and low gain are solved, and the effect of low power consumption and high gain is achieved, reducing the design difficulty and area of the comparator.
Patent Information
- Application Number
- CN202510331263.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-25
AI Technical Summary
In existing successive approximation analog-to-digital converters, the preamplifier has high power consumption and low gain, or requires additional bias voltage circuits or external terminals, increasing chip area and complexity.
Design a preamplifier that can be switched statically and dynamically, and generates bias voltage and offset voltage by switching to static amplifier mode during the sampling phase, and switches to dynamic amplifier mode during the comparison phase, combining energy storage capacitors and casubic tube structure to achieve low power consumption and high gain.
During the sampling and comparison stage of the analog-to-digital converter, the gain of the preamplifier is greatly improved, the automatic zeroing effect is improved, the power consumption is reduced by 63%, the comparator design difficulty is reduced and the area is reduced.
Smart Images
Figure CN120377916A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog-to-digital converters, and particularly to a preamplifier capable of static and dynamic switching and its working method. Background Art
[0002] The successive approximation analog-to-digital converter has the characteristics of low power consumption and is easy to scale with the feature size of the CMOS process. It has become the mainstream choice for medium-precision analog-to-digital converters. It generally has two working states: sampling and comparison, and mainly includes modules such as a switched-capacitor circuit, a digital-to-analog converter, a preamplifier, a comparator, and a successive approximation register. Among them, the preamplifier can generate the bias voltage for the switched-capacitor circuit and the comparator during the sampling of the analog-to-digital converter, and can automatically zero the offset with the switched-capacitor circuit. During the comparison, it is responsible for pre-amplifying the signal provided by the switched-capacitor circuit for use by the comparator. As one of the few analog circuits in the successive approximation analog-to-digital converter, the power consumption and gain of the preamplifier have a great impact on the power consumption and accuracy of the analog-to-digital converter. With the increasing demand for low-power applications and the continuous reduction of the feature size of the CMOS process, low power consumption and high gain have become the main issues for the preamplifier. Currently, the common preamplifier structures mainly have two types: static amplifiers and dynamic amplifiers.
[0003] For a successive approximation analog-to-digital converter using a static amplifier, during the sampling of the analog-to-digital converter, the preamplifier generates the bias voltage for the switched-capacitor circuit and the comparator, as well as the offset voltage for automatic zeroing of the offset of the preamplifier itself. During the comparison of the analog-to-digital converter, the preamplifier is responsible for amplifying the input signal and providing it for use by the comparator. After the comparator finishes the comparison, the preamplifier remains in the working state and waits to amplify the next signal. This amplification-comparison-waiting action will be repeated several times, and the number of repetitions is determined by the resolution of the analog-to-digital converter. For example, for a 12-bit successive approximation analog-to-digital converter, this action is repeated at least 12 times. The advantage of the preamplifier with this structure is that it can provide the bias voltage and achieve automatic zeroing, making the structure and use of the analog-to-digital converter relatively simple. However, since the preamplifier is still working during the waiting period, its disadvantages are high power consumption and low gain.
[0004] For a successive approximation analog-to-digital converter (ADC) employing a dynamic amplifier, when the ADC samples, the preamplifier does not operate, and the bias voltages of the switched-capacitor circuit and the comparator are provided by a dedicated circuit or externally. When the ADC compares, the preamplifier amplifies the signal for use by the comparator and automatically enters the standby mode to reduce power consumption by recognizing the VALID signal indicating the end of the comparator comparison. The advantages of this preamplifier structure are low power consumption and high gain. However, the disadvantages are that an additional bias voltage circuit or external terminals are required. The bias voltage circuit generates additional power consumption, and the external terminals increase the chip area. At the same time, since there is no auto-zero function, an ADC using this type of preamplifier often needs to introduce digital compensation circuits and processes to reduce offset, which also increases the complexity of the ADC structure and usage. Summary of the Invention
[0005] In view of the above, the present invention provides a preamplifier capable of static and dynamic switching and its working method to solve at least one of the above-mentioned problems.
[0006] To achieve the above object, the present invention adopts the following solutions:
[0007] According to a first aspect of the present invention, there is provided a preamplifier capable of static and dynamic switching, the preamplifier comprising: a first control resistor, a second control resistor, a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, and a storage capacitor, wherein:
[0008] The first control resistor and the first switch are connected between the power supply line and the VSP node;
[0009] The second control resistor and the second switch are connected between the ground line and the VSN node;
[0010] The gate of the first input transistor is connected to the first input terminal, the source is connected to the VSP node, and the drain is connected to the first node;
[0011] The gate of the second input transistor is connected to the second input terminal, the source is connected to the VSP node, and the drain is connected to the second node;
[0012] The gate of the third input transistor is connected to the first input terminal, the source is connected to the VSN node, and the drain is connected to the first node;
[0013] The gate of the fourth input transistor is connected to the second input terminal, the source is connected to the VSN node, and the drain is connected to the second node;
[0014] One end of the energy storage capacitor is connected to the power supply line through a third switch and to the VSP node through a fourth switch, and the other end is connected to the ground line through a fifth switch and to the VSN node through a sixth switch;
[0015] The first input terminal and the first node are connected through a seventh switch, the second input terminal and the second node are connected through an eighth switch, the first node is further connected to a first output terminal, the second node is further connected to a second output terminal, the first node is connected to a third node through a ninth switch, the second node is connected to the third node through a tenth switch, and the third node is connected to the output terminal of the bias voltage generating circuit.
[0016] As an embodiment of the present invention, the above preamplifier further includes a first cascode transistor, a second cascode transistor, a third cascode transistor, and a fourth cascode transistor;
[0017] The gates of the first cascode transistor and the second cascode transistor are both connected to the VSN node;
[0018] The gates of the third cascode transistor and the fourth cascode transistor are both connected to the VSP node;
[0019] The sources and drains of the first cascode transistor and the third cascode transistor are connected in series between the drain of the first input transistor and the drain of the third input transistor, and the first node is located between the first cascode transistor and the third cascode transistor;
[0020] The sources and drains of the second cascode transistor and the fourth cascode transistor are connected in series between the drain of the second input transistor and the drain of the fourth input transistor, and the second node is located between the second cascode transistor and the fourth cascode transistor.
[0021] As an embodiment of the present invention, the first input transistor and the second input transistor are PMOS transistors, and the third input transistor and the fourth input transistor are NMOS transistors.
[0022] According to a second aspect of the present invention, there is provided a working method of a preamplifier capable of static and dynamic switching. The preamplifier is applied to a successive approximation analog-to-digital converter or a hybrid analog-to-digital converter having a successive approximation analog-to-digital converter. The preamplifier is respectively connected to a bias voltage generating circuit, a switched capacitor circuit, and a comparator. The preamplifier adopts the structure of the preamplifier as described in claim 1. The working method includes:
[0023] When the successive approximation analog-to-digital converter is in the sampling stage, the preamplifier switches to the static amplifier mode, generating a bias voltage for use by the switched-capacitor circuit and generating an offset voltage for auto-zeroing;
[0024] When the successive approximation analog-to-digital converter is in the stage after sampling and before comparison starts, the preamplifier switches to the standby mode, and the output of the preamplifier is set to the common-mode voltage by the bias voltage generation circuit to serve as the bias voltage of the comparator;
[0025] When the successive approximation analog-to-digital converter is in the comparison stage, the preamplifier switches to the dynamic amplifier mode, amplifies the input signal and provides it for use by the comparator. After the comparator completes the comparison, the preamplifier switches to the standby mode to wait for the next enable signal until the successive approximation analog-to-digital converter completes the conversion.
[0026] As an embodiment of the present invention, the preamplifier switching to the static amplifier mode in the above method includes: closing the first switch, the second switch, the seventh switch, and the eighth switch, opening the ninth switch and the tenth switch, while ensuring that the third switch and the fourth switch are not closed simultaneously, and the fifth switch and the sixth switch are not closed simultaneously, so that the preamplifier switches to the static amplifier mode.
[0027] As an embodiment of the present invention, the preamplifier switching to the standby mode in the above method includes: closing the third switch, the fifth switch, the ninth switch, and the tenth switch, while opening the first switch, the second switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch, so that the preamplifier switches to the standby mode.
[0028] As an embodiment of the present invention, the preamplifier switching to the dynamic amplifier mode in the above method includes: closing the fourth switch and the sixth switch, while opening the first switch, the second switch, the third switch, the fifth switch, the seventh switch, the eighth switch, the ninth switch, and the tenth switch, so that the preamplifier switches to the dynamic amplifier mode.
[0029] As an embodiment of the present invention, after the preamplifier switches to the static amplifier mode in the above method, the method further includes: the preamplifier controls the static current in the static amplifier mode by adjusting the first control resistor and the second control resistor to match the sampling time.
[0030] As an embodiment of the present invention, when the successive approximation analog-to-digital converter is in the stage after sampling and before comparison starts, the method further includes: charging the energy storage capacitor using the power supply.
[0031] As an embodiment of the present invention, in the above method, the preamplifier is switched to the dynamic amplifier mode, and after amplifying the input signal, it is provided for use by the comparator. After the comparator completes the comparison, the preamplifier is switched to the standby mode to wait for the next enable signal until the successive approximation analog-to-digital converter completes the conversion, including:
[0032] The preamplifier receives the enable signal sent by the logic control circuit and is switched to the dynamic amplifier mode;
[0033] The preamplifier powers the preamplifier through the energy storage capacitor to amplify the input signal, and supplies the amplified input signal for use by the comparator;
[0034] After the comparator completes the comparison, it sends a VALID signal to the logic control circuit, and the logic control circuit then sends a standby signal to the preamplifier. The preamplifier receives the standby signal and enters the standby mode to wait for the next enable signal;
[0035] The preamplifier repeats the cycle between the dynamic amplifier mode and the standby mode multiple times until the successive approximation analog-to-digital converter completes the conversion.
[0036] It can be seen from the above technical solutions that the preamplifier capable of static and dynamic switching and its working method provided by the present invention can be switched between the static amplifier mode, the standby mode, and the dynamic amplifier mode during the sampling and comparison operations of the successive approximation analog-to-digital converter. During the sampling of the successive approximation analog-to-digital converter, the preamplifier operates in the static amplifier mode, which greatly improves the gain of the preamplifier and also significantly enhances the effect of automatic zero adjustment; when the successive approximation analog-to-digital converter performs comparison, the preamplifier repeats the cycle between the dynamic amplifier mode and the standby mode several times. On the one hand, the gain is also greatly improved, so the performance requirements for the comparator are reduced, the design difficulty of the comparator can be reduced, and the area of the comparator can be reduced; on the other hand, due to the existence of the standby mode, the power consumption of the preamplifier is greatly reduced during the entire conversion cycle of the successive approximation analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:
[0038] Figure 1 is a schematic structural diagram of a preamplifier capable of static and dynamic switching provided by an embodiment of the present application;
[0039] Figure 2 is a schematic structural diagram of a preamplifier with static and dynamic switching provided by another embodiment of the present application;
[0040] Figure 3 is a schematic flowchart of a working method of a preamplifier with static and dynamic switching provided by an embodiment of the present application;
[0041] Figure 4 are simulation result diagrams of various working states of a preamplifier with static and dynamic switching provided by an embodiment of the present application;
[0042] Figure 5 is a circuit structure diagram of a preamplifier in the prior art. Detailed implementation manners
[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer and more understandable, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.
[0044] Since the current preamplifier only adopts the structure of a static amplifier or a dynamic amplifier alone, and both of these structures have their own defects. Therefore, the purpose of this application is to switch the preamplifier between a static amplifier and a dynamic amplifier for the two different states of sampling and comparison of a successive approximation analog-to-digital converter, and on the premise of retaining the bias voltage generation and auto-zeroing functions, utilize the advantages of a new type of low-power high-gain dynamic amplifier to improve the power consumption and gain of the preamplifier.
[0045] As Figure 1 shown is a schematic structural diagram of a preamplifier with static and dynamic switching provided by an embodiment of the present application, which is applied to a successive approximation analog-to-digital converter or a hybrid analog-to-digital converter with a successive approximation analog-to-digital converter. As Figure 1 can be seen, the preamplifier includes: a first control resistor RS1, a second control resistor RS2, a first input transistor MPINP1, a second input transistor MPINN1, a third input transistor MNINP2, a fourth input transistor MNINN2, and a storage capacitor CRES.
[0046] The first control resistor RS1 and the first switch SW1 are connected between the power supply line VCC and the VSP node.
[0047] The second control resistor RS2 and the second switch SW2 are connected between the ground line VSS and the VSN node.
[0048] The gate of the first input transistor MPINP1 is connected to the first input terminal INP, the source is connected to the VSP node, and the drain is connected to the first node N1.
[0049] The gate of the second input transistor MPINN1 is connected to the second input terminal INN, the source is connected to the VSP node, and the drain is connected to the second node N2.
[0050] The gate of the third input transistor MNINP2 is connected to the first input terminal INP, the source is connected to the VSN node, and the drain is connected to the first node N1.
[0051] The gate of the fourth input transistor MNINN2 is connected to the second input terminal INN, the source is connected to the VSN node, and the drain is connected to the second node N2.
[0052] One end of the energy storage capacitor CRES is connected to the power supply line VCC through the third switch SW3 and to the VSP node through the fourth switch SW4, and the other end is connected to the ground line VSS through the fifth switch SW5 and to the VSN node through the sixth switch SW6.
[0053] The preamplifier of this embodiment includes two input terminals and two output terminals. Among them, the first input terminal INP and the first node N1 are connected through the seventh switch SW7, the second input terminal INN and the second node N2 are connected through the eighth switch SW8, the first node N1 is also connected to the first output terminal OUTN, the second node N2 is also connected to the second output terminal OUTP, the first node N1 is connected to the third node N3 through the ninth switch SW9, the second node N2 is connected to the third node N3 through the tenth switch SW10, and the third node N3 is connected to the output terminal of the bias voltage generation circuit.
[0054] With the above structure, the present application can make the preamplifier work in different modes by closing and disconnecting each switch unit, so as to realize the switching between the static amplifier and the dynamic amplifier. The specific working process will be described in the subsequent method embodiments.
[0055] Preferably, the first control resistor RS1 and the second control resistor RS2 in this embodiment are adjustable resistors. When the successive approximation analog-to-digital converter samples, they can control the static current of the preamplifier. By adjusting the resistance value, the static current matching the sampling time can be set. The static current refers to the current flowing through the preamplifier when there is no input signal, and the sampling time refers to the time when the analog-to-digital converter samples the input signal. In the sampling stage, the preamplifier requires a certain setup time to reach a stable state. If the static current is too small, the setup time may be too long, resulting in a decrease in sampling accuracy; while if the static current is too large, although the setup time can be shortened, the power consumption will increase. Therefore, in this embodiment, by adjusting the first control resistor RS1 and the second control resistor RS2, an optimal compromise point can be found between the setup time and the power consumption, thereby optimizing the performance of the preamplifier.
[0056] Preferably, the above-mentioned first input transistor MPINP1 and second input transistor MPINN1 are PMOS transistors, and the third input transistor MNINP2 and fourth input transistor MNINN2 are NMOS transistors. Therefore, the two input pairs of transistors, namely the first input transistor MPINP1 and the third input transistor MNINP2, and the second input transistor MPINN1 and the fourth input transistor MNINN2, both form a CMOS input, and the output resistance is much higher than that of the existing structure. The gain of the preamplifier is proportional to the output resistance. Therefore, at the same static current, the gain of the preamplifier of the present invention is greatly improved, thereby improving the effect of auto-zeroing.
[0057] Preferably, in order to further improve the gain and anti-kickback ability of the overall circuit, as Figure 2 shown, the preamplifier of this embodiment may further include: a first cascode transistor MPCASP1, a second cascode transistor MPCASN1, a third cascode transistor MNCASP2, and a fourth cascode transistor MNCASN2.
[0058] It can be seen from Figure 2 that the gates of the first cascode transistor MPCASP1 and the second cascode transistor MPCASN1 are both connected to the VSN node, and the gates of the third cascode transistor MNCASP2 and the fourth cascode transistor MNCASN2 are both connected to the VSP node.
[0059] In addition, the sources and drains of the first cascode transistor MPCASP1 and the third cascode transistor MNCASP2 are connected in series between the drain of the first input transistor MPINP1 and the drain of the third input transistor MNINP2, and the sources and drains of the second cascode transistor MPCASN1 and the fourth cascode transistor MNCASN2 are connected in series between the drain of the second input transistor MPINN1 and the drain of the fourth input transistor MNINN2.
[0060] Specifically, the drain of the first input transistor MPINP1 and the source of the first cascode transistor MPCASP1 are connected to the fourth node N4, the drain of the first cascode transistor MPCASP1 and the drain of the third cascode transistor MNCASP2 are connected to the first node N1, and the source of the third cascode transistor MNCASP2 and the drain of the third input transistor MNINP2 are connected to the sixth node N6. The drain of the second input transistor MPINN1 and the source of the second cascode transistor MPCASN1 are connected to the fifth node N5, the drain of the second cascode transistor MPCASN1 and the drain of the fourth cascode transistor MNCASN2 are connected to the second node N2, and the source of the fourth cascode transistor MNCASN2 and the drain of the fourth input transistor MNINN2 are connected to the seventh node N7.
[0061] The above-mentioned fourth node N4 and fifth node N5 are connected by an eleventh switch SW11, and the sixth node N6 and seventh node N7 are connected by a twelfth switch SW12.
[0062] Further preferably, the above-mentioned first cascode transistor MPCASP1 and second cascode transistor MPCASN1 are PMOS transistors, and the third cascode transistor MNCASP2 and fourth cascode transistor MNCASN2 are NMOS transistors. During the comparison of the analog-to-digital converter, in addition to improving the gain, the cascode transistors can also reduce the kickback of the comparator to the input of the preamplifier. During the comparison stage of the analog-to-digital converter, a transient voltage or current change will be generated at the input terminal of the comparator, and this change will propagate backward to the input terminal through the preamplifier, which is the kickback noise. The kickback noise will affect the accuracy of the analog-to-digital converter, and the above-mentioned cascode structure of the present application can effectively isolate the input terminals of the comparator and the preamplifier, thereby reducing the kickback noise.
[0063] It should be noted that generally, the sources and drains of the above-mentioned input transistors and cascode transistors are exactly the same in physical structure, so they can be interchanged. For the convenience of distinction, when drawing the circuit diagram, the source terminal of the PMOS is closer to the power supply, and the source terminal of the NMOS is closer to the ground.
[0064] Next, based on the above Figure 1 and Figure 2 structure of the preamplifier, its working method will be further described. As mentioned above, the preamplifier is applied to a successive approximation analog-to-digital converter or a hybrid analog-to-digital converter with a successive approximation analog-to-digital converter. Specifically, it is respectively connected to a bias voltage generation circuit, a switched-capacitor circuit, and a comparator. As Figure 3The figure shows a schematic flowchart of a working method of a preamplifier capable of static and dynamic switching provided by an embodiment of the present application, which includes the following steps:
[0065] Step S301: When the successive approximation analog-to-digital converter is in the sampling stage, the preamplifier switches to the static amplifier mode, generates a bias voltage for use by the switched capacitor circuit, and generates an offset voltage for auto-zeroing.
[0066] In this embodiment, if based on the preamplifier structure of Figure 1 , to switch the preamplifier to the static amplifier mode, the first switch SW1, the second switch SW2, the seventh switch SW7, and the eighth switch SW8 need to be closed, and the ninth switch SW9 and the tenth switch SW10 need to be opened. At the same time, it is ensured that the third switch SW3 and the fourth switch SW4 are not closed simultaneously, and the fifth switch SW5 and the sixth switch SW6 are not closed simultaneously. Additionally, when the successive approximation analog-to-digital converter is in the sampling stage, the bias voltage generation circuit connected to the preamplifier does not need to work. Therefore, to further reduce power consumption, Figure 1 the thirteenth switch SW13 in
[0067] In another embodiment of the present application, if based on the preamplifier structure of Figure 2 , to switch the preamplifier to the static amplifier mode, the first switch SW1, the second switch SW2, the seventh switch SW7, and the eighth switch SW8 need to be closed, and the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 need to be opened. At the same time, it is ensured that the third switch SW3 and the fourth switch SW4 are not closed simultaneously, and the fifth switch SW5 and the sixth switch SW6 are not closed simultaneously.
[0068] In this static amplifier mode, since the seventh switch SW7 and the eighth switch SW8 are closed, the first input terminal INP and the first output terminal OUTN are short-circuited, and the second input terminal INN and the second output terminal OUTP are short-circuited, thereby generating a bias voltage for use by the switched capacitor circuit and generating an offset voltage for auto-zeroing at the same time.
[0069] Preferably, after the preamplifier switches to the static amplifier mode, the method of this embodiment further includes: the preamplifier controls the static current in the static amplifier mode by adjusting the first control resistor RS1 and the second control resistor RS2 to match the sampling time.
[0070] In addition, in this static amplifier mode, due to the presence of the first cascode transistor MPCASP1, the second cascode transistor MPCASN1, the third cascode transistor MNCASP2, and the fourth cascode transistor MNCASN2, the gain of the preamplifier during sampling can be increased. To reduce power consumption, in this embodiment, a dedicated bias voltage generation circuit is not used during the sampling phase. Instead, the gates of the cascode transistors are respectively connected to the VSN node and the VSP node. Although the gain is reduced compared to using a dedicated bias voltage generation circuit, it is still higher than the structure without cascode transistors, and the power consumption does not increase.
[0071] Finally, during the sampling phase, compared with the prior art, since the input pair transistors of this application are CMOS inputs and the output resistance is much higher than that of the existing structure, the gain of the preamplifier of this application has been greatly improved under the same static current, enhancing the effect of auto-zeroing.
[0072] Step S302: When the successive approximation analog-to-digital converter is in the stage after sampling ends and before comparison starts, the preamplifier switches to the standby mode, and the output of the preamplifier is set to the common-mode voltage by the bias voltage generation circuit to serve as the bias voltage of the comparator.
[0073] In this embodiment, if based on the preamplifier structure of Figure 1 To switch the preamplifier to the standby mode, the third switch SW3, the fifth switch SW5, the ninth switch SW9, and the tenth switch SW10 need to be closed, and at the same time, the first switch SW1, the second switch SW2, the fourth switch SW4, the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8 need to be opened.
[0074] In another embodiment of this application, if based on the preamplifier structure of Figure 2 To switch the preamplifier to the standby mode, the third switch SW3, the fifth switch SW5, the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 need to be closed, and at the same time, the first switch SW1, the second switch SW2, the fourth switch SW4, the sixth switch SW6, the seventh switch SW7, and the eighth switch SW8 need to be opened.
[0075] After the analog-to-digital converter finishes sampling, due to the closing of the third switch SW3 and the fifth switch SW5, the power supply starts to charge the energy storage capacitor CRES, preparing for powering the preamplifier in the dynamic amplifier mode later. Additionally, after the analog-to-digital converter finishes sampling, the bias voltage generation circuit starts to work, so the thirteenth switch SW13 also closes. The bias voltage generation circuit sets the output of the preamplifier to the VCM voltage, which is the bias voltage of the comparator. As can be seen from the above, this bias voltage circuit only works after the analog-to-digital converter finishes sampling and only consumes very little power.
[0076] Step S303: When the successive approximation analog-to-digital converter is in the comparison stage, the preamplifier switches to the dynamic amplifier mode, amplifies the input signal and provides it for use by the comparator. After the comparator finishes the comparison, the preamplifier switches to the standby mode and waits for the next enable signal until the successive approximation analog-to-digital converter completes the conversion.
[0077] In this embodiment, if based on the Figure 1 preamplifier structure, to switch the preamplifier to the dynamic amplifier mode, the fourth switch SW4 and the sixth switch SW6 need to be closed, and at the same time, the first switch SW1, the second switch SW2, the third switch SW3, the fifth switch SW5, the seventh switch SW7, the eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 need to be opened.
[0078] In another embodiment of this application, if based on the Figure 2 preamplifier structure, to switch the preamplifier to the dynamic amplifier mode, the fourth switch SW4 and the sixth switch SW6 need to be closed, and at the same time, the first switch SW1, the second switch SW2, the third switch SW3, the fifth switch SW5, the seventh switch SW7, the eighth switch SW8, the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 need to be opened.
[0079] When the preamplifier is amplifying, since the third switch SW3 and the fifth switch SW5 are opened, while the fourth switch SW4 and the sixth switch SW6 are closed, the energy storage capacitor CRES stops charging and instead supplies power to the preamplifier to amplify the input signal. As the amplification progresses, the voltage difference across the energy storage capacitor CRES continuously decreases, and the preamplifier will automatically turn off, no longer consuming power, and save the amplified signal on the two outputs for use by the comparator.
[0080] After the comparator finishes the comparison, it will send a VALID signal to the logic control circuit. The logic control circuit then sends a standby signal to the preamplifier. At this time, the preamplifier will enter the standby mode, waiting for the next enable signal. The states of each switch in the standby mode can be referred to the foregoing description. At this time, the power supply can charge the energy storage capacitor CRES again.
[0081] The above-mentioned operations of amplification - comparison - standby will be repeated several times, and the number of repetitions is determined by the resolution of the successive approximation analog - to - digital converter. Compared with the prior art, since the preamplifier of the present invention will automatically turn off during the amplification process and enter the standby mode when waiting for the next enable signal, the power consumption is greatly reduced. At the same time, since the input pair transistors are CMOS inputs, and as the amplification progresses, the VSN node rises and the VSP node drops, and the input pair transistors approach the sub - threshold region, the gain of the preamplifier can also be improved.
[0082] As Figure 4 shown in the simulation result diagram of each working state of the preamplifier that can be switched between static and dynamic states in this application, the simulation is based on the preamplifier structure of Figure 2 . Since the relevant switches are synchronously closed or opened when the preamplifier in this application switches between different modes, for the convenience of understanding, the switches that operate synchronously are represented by SWA, SWB, SWC, and SWD. Among them, SWA represents Figure 1 the first switch SW1, the second switch SW2, the seventh switch SW7, and the eighth switch SW8 in Figure 1 ; SWB represents Figure 1 the third switch SW3, the fifth switch SW5, the ninth switch SW9, the tenth switch SW10, the eleventh switch SW11, and the twelfth switch SW12 in Figure 1 ; SWC represents Figure 1 the fourth switch SW4 and the sixth switch SW6 in Figure 1 ; SWD represents Figure 1 the thirteenth switch SW13 in
[0083] Among them, the "a" state means that when the successive approximation analog - to - digital converter samples, the preamplifier is a static amplifier, SWA is high, and SWB, SWC, and SWD are low. The high potential represents that the switch is in the closed state, and the low potential represents that the switch is in the open state.
[0084] The "b" state means that between the end of the sampling of the successive approximation analog - to - digital converter and the start of the comparison of the analog - to - digital converter, the preamplifier is in the standby mode, SWA and SWC are low, and SWB and SWD are high.
[0085] When the successive approximation analog - to - digital converter compares, the preamplifier is a dynamic amplifier, and there are the following two working states:
[0086] The "d" state means that the preamplifier amplifies the input signal, SWA and SWB are low, and SWC and SWD are high.
[0087] The "e" state indicates that the preamplifier enters the standby mode, where SWA and SWC are low, and SWB and SWD are high.
[0088] To better compare the beneficial effects of this application with the prior art, the following presents the circuit structure diagram of a preamplifier in the prior art, as shown in Figure 5 shown.
[0089] The preamplifier circuit of the existing structure is as shown in Figure 5 shown. This structure belongs to a static amplifier. MNTAILP and MNTAILN are tail current tubes, MNINP and MNINN are input pair tubes, MNCASP and MNCASN are cascode tubes, and MPLOADP, MPLOADN, and RCM form a load circuit and provide common-mode feedback.
[0090] After the circuit is enabled, the SBYT signal is low, and the bias current and bias voltage generation circuit operates to generate the bias current and voltage for the preamplifier.
[0091] When the analog-to-digital converter samples, the SW1 signal is high, the input and output of the preamplifier are short-circuited, and the preamplifier operates in the unity-gain feedback mode. MPLOADP, MPLOADN, and the resistor RCM form a load circuit and provide a local common-mode feedback loop (Local Common Mode Feedback, LCMFB), such that INP = OUTN ≈ INN = OUTP. The differential voltage between INP and INN is the offset voltage of the preamplifier itself. INP and INN are the bias voltages of the switched-capacitor circuit and the comparator, and the differential voltage between INP and INN is stored in the switched-capacitor circuit for the automatic zeroing of the offset of the preamplifier itself. The offset voltages before and after automatic zeroing are shown in Equation (1):
[0092]
[0093] where V OS_original is the offset voltage before automatic zeroing, V OS_autozero is the offset voltage after automatic zeroing, and Gain samp is the gain of the preamplifier during sampling. Since a stable reference voltage (INP, INN) and offset voltage (INP - INN) need to be generated, the preamplifier must be a static amplifier during sampling.
[0094] When the analog-to-digital converter is in comparison, SW1 is low, the input and output are disconnected, and the preamplifier operates in an open-loop mode, responsible for amplifying the input signal and providing it to the comparator for use. After the comparator finishes the comparison, the preamplifier remains in the working state and waits to amplify the next signal. This amplification-comparison-waiting action will repeat several times, and the number of repetitions is determined by the resolution of the analog-to-digital converter. For a 12-bit successive approximation analog-to-digital converter, this action repeats at least 12 times. Because the preamplifier is still working during the waiting period, Figure 5 the preamplifier generates a lot of power consumption.
[0095] Compared with the above Figure 5 existing technology, the effect comparison between this application and it is shown in Table 1. When the analog-to-digital converter of this application samples, the gain of the preamplifier is greatly improved, so the effect of auto-zeroing is improved by 7 times. When the analog-to-digital converter compares, the gain is increased by 89%, so the performance requirements for the comparator are reduced, and then the design difficulty of the comparator can be reduced and the area of the comparator can be reduced. During the conversion cycle of the entire analog-to-digital converter, the power consumption of the preamplifier is reduced by 63%.
[0096] Table 1
[0097]
[0098]
[0099] As can be seen from the above, the preamplifier capable of static and dynamic switching and its working method provided by the present invention can be switched between a static amplifier mode, a standby mode, and a dynamic amplifier mode during the sampling and comparison operations of a successive approximation analog-to-digital converter. When the successive approximation analog-to-digital converter samples, the preamplifier operates in the static amplifier mode, so that the gain of the preamplifier is greatly improved and the effect of auto-zeroing is also greatly enhanced; when the successive approximation analog-to-digital converter compares, the preamplifier operates in the dynamic amplifier mode, and the gain is also greatly increased, so the performance requirements for the comparator are reduced, and the design difficulty of the comparator can be reduced and the area of the comparator can be reduced; in addition, due to the existence of the standby mode, the power consumption of the preamplifier is greatly reduced during the entire conversion cycle of the successive approximation analog-to-digital converter.
[0100] Specific embodiments are applied in the present invention to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.
Claims
1. A preamplifier capable of static and dynamic switching, characterized in that The preamplifier includes: a first control resistor, a second control resistor, a first input transistor, a second input transistor, a third input transistor, a fourth input transistor, and a storage capacitor, where: The first control resistor and the first switch are connected between the power supply line and the VSP node; The second control resistor and the second switch are connected between the ground line and the VSN node; The gate of the first input transistor is connected to the first input terminal, the source is connected to the VSP node, and the drain is connected to the first node; The gate of the second input transistor is connected to the second input terminal, the source is connected to the VSP node, and the drain is connected to the second node; The gate of the third input transistor is connected to the first input terminal, the source is connected to the VSN node, and the drain is connected to the first node; The gate of the fourth input transistor is connected to the second input terminal, the source is connected to the VSN node, and the drain is connected to the second node; One end of the storage capacitor is connected to the power supply line through the third switch and to the VSP node through the fourth switch, and the other end is connected to the ground line through the fifth switch and to the VSN node through the sixth switch; The first input terminal and the first node are connected through the seventh switch, the second input terminal and the second node are connected through the eighth switch, the first node is also connected to the first output terminal, the second node is also connected to the second output terminal, the first node is connected to the third node through the ninth switch, the second node is connected to the third node through the tenth switch, and the third node is connected to the output terminal of the bias voltage generation circuit.
2. The preamplifier capable of static and dynamic switching according to claim 1, wherein, The preamplifier further includes a first cascode transistor, a second cascode transistor, a third cascode transistor, and a fourth cascode transistor; The gates of the first cascode transistor and the second cascode transistor are both connected to the VSN node; The gates of the third cascode transistor and the fourth cascode transistor are both connected to the VSP node; The sources and drains of the first cascode transistor and the third cascode transistor are connected in series between the drain of the first input transistor and the drain of the third input transistor, and the first node is located between the first cascode transistor and the third cascode transistor; The sources and drains of the second cascode transistor and the fourth cascode transistor are connected in series between the drain of the second input transistor and the drain of the fourth input transistor, and the second node is located between the second cascode transistor and the fourth cascode transistor.
3. The preamplifier capable of static and dynamic switching as described in claim 1, wherein The first input transistor and the second input transistor are PMOS transistors, and the third input transistor and the fourth input transistor are NMOS transistors.
4. A working method of a preamplifier capable of static and dynamic switching, characterized in that, The preamplifier is applied to a successive approximation analog-to-digital converter or a hybrid analog-to-digital converter having a successive approximation analog-to-digital converter. The preamplifier is respectively connected to a bias voltage generation circuit, a switched-capacitor circuit, and a comparator. The preamplifier adopts the structure of the preamplifier as described in claim 1. The working method includes: When the successive approximation analog-to-digital converter is in the sampling stage, the preamplifier switches to the static amplifier mode, generating a bias voltage for use by the switched-capacitor circuit and generating an offset voltage for auto-zeroing. When the successive approximation analog-to-digital converter is in the stage after sampling and before comparison starts, the preamplifier switches to the standby mode, and the output of the preamplifier is set to the common-mode voltage by the bias voltage generation circuit to serve as the bias voltage for the comparator. When the successive approximation analog-to-digital converter is in the comparison stage, the preamplifier switches to the dynamic amplifier mode, amplifies the input signal and provides it for use by the comparator. After the comparator completes the comparison, the preamplifier switches to the standby mode to wait for the next enable signal until the successive approximation analog-to-digital converter completes the conversion.
5. The working method of the preamplifier capable of static and dynamic switching as described in claim 4, characterized in that, The preamplifier switching to the static amplifier mode includes: closing the first switch, the second switch, the seventh switch, and the eighth switch, opening the ninth switch and the tenth switch, and at the same time ensuring that the third switch and the fourth switch are not closed simultaneously, and the fifth switch and the sixth switch are not closed simultaneously, so that the preamplifier switches to the static amplifier mode.
6. The working method of the preamplifier capable of static and dynamic switching as described in claim 4, characterized in that, The preamplifier switching to the standby mode includes: closing the third switch, the fifth switch, the ninth switch, and the tenth switch, and at the same time opening the first switch, the second switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch, so that the preamplifier switches to the standby mode.
7. The working method of the preamplifier capable of static and dynamic switching as described in claim 4, characterized in that, The preamplifier switching to the dynamic amplifier mode includes: closing the fourth switch and the sixth switch, and at the same time opening the first switch, the second switch, the third switch, the fifth switch, the seventh switch, the eighth switch, the ninth switch, and the tenth switch, so that the preamplifier switches to the dynamic amplifier mode.
8. The working method of the preamplifier capable of static and dynamic switching according to claim 4, characterized in that, After the preamplifier switches to the static amplifier mode, the method further includes: the preamplifier controls the static current in the static amplifier mode by adjusting the first control resistor and the second control resistor to match the sampling time.
9. The working method of the preamplifier capable of static and dynamic switching according to claim 4, characterized in that When the successive approximation analog-to-digital converter is in the stage after sampling and before comparison starts, the method further includes: charging the energy storage capacitor using the power supply.
10. The working method of the preamplifier capable of static and dynamic switching as described in claim 9, characterized in that, The preamplifier switches to the dynamic amplifier mode, amplifies the input signal and provides it for use by the comparator. After the comparator completes the comparison, the preamplifier switches to the standby mode to wait for the next enable signal until the successive approximation analog-to-digital converter completes the conversion includes: The preamplifier receives the enable signal sent by the logic control circuit and switches to the dynamic amplifier mode; The preamplifier supplies power to itself through the energy storage capacitor to amplify the input signal and provides the amplified input signal for use by the comparator; After the comparator completes the comparison, it sends a VALID signal to the logic control circuit, and the logic control circuit then sends a standby signal to the preamplifier. The preamplifier receives the standby signal and enters the standby mode to wait for the next enable signal; The preamplifier repeats the cycle between the dynamic amplifier mode and the standby mode multiple times until the successive approximation analog-to-digital converter completes the conversion.