Digital-to-analog converter, analog-to-digital converter, touch chip and electronic equipment

Abstract

The invention provides a digital-to-analog converter, an analog-to-digital converter, a touch chip and an electronic device, the digital-to-analog converter omits a mode that an upper polar plate of each capacitor of a capacitor array is connected with a common reference voltage VCOM, and a second switch array coupled with the upper polar plate of the capacitor is added; meanwhile, a control logic circuit for further processing a first digital code and a first digital inverse code into a second digital code, a second digital inverse code, a third digital code and a third digital inverse code is added, so that the DAC can store the electric charge quantity in a reset stage, and the electric charge quantity output by the DAC in an output stage is larger than that of an existing digital-to-analog converter; and the capacitance area of the capacitor array can be reduced when the same quantity of electric charges is output as that of the existing DAC (Digital-to-Analog Converter). According to the analog-to-digital converter, the touch control chip and the electronic equipment, due to the adoption of the digital-to-analog converter, the circuit area can be reduced, and the reliability is also improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a digital-to-analog converter, an analog-to-digital converter, a touch chip and an electronic device. Background Art

[0002] A digital-to-analog converter (DAC) circuit is a bridge for converting between digital signals and analog signals. It can be used as a separate module or as a part of an analog-to-digital converter (ADC), and is widely used in fields such as communication, sensing, and multimedia.

[0003] Currently, a conventional digital-to-analog converter generally has a binary-weighted capacitor array, and the lower plates of each capacitor in the capacitor array are allowed to switch between three voltages: a first reference voltage Vrp (such as the power supply voltage of the system), a second reference voltage Vrn (such as the ground voltage of the system), and a common reference voltage VCOM. This digital-to-analog converter has defects such as a large area and a small amount of charge output in the output stage, thus limiting the improvement of the performance of the digital-to-analog converter, the analog-to-digital converter having this digital-to-analog converter, the touch chip, and the electronic device. Summary of the Invention

[0004] The purpose of the present invention is to provide a digital-to-analog converter, an analog-to-digital converter, a touch chip and an electronic device, which can help reduce the area of the digital-to-analog converter and increase the amount of charge output by the digital-to-analog converter.

[0005] To achieve the above purpose, the present invention provides a digital-to-analog converter, which includes:

[0006] A control logic circuit, the input end of which is coupled to a reset signal, an output control signal, a multi-bit first digital code, and a multi-bit first digital inverse code, and is used to generate a multi-bit second digital code, a multi-bit second digital inverse code, a multi-bit third digital code, and a multi-bit third digital inverse code according to the reset signal, the output control signal, the first digital code, and the first digital inverse code, wherein the first digital inverse code is the inverse code of the first digital code, the second digital inverse code is the inverse code of the second digital code, and the third digital inverse code is the inverse code of the third digital code;

[0007] A capacitor array, including a plurality of capacitors;

[0008] A first switch array, coupled to the lower plates of each capacitor in the capacitor array and controlled by at least one of the second digital code, the second digital inverse code, and the reset signal, for connecting the lower plates of each capacitor in the capacitor array to corresponding voltages respectively;

[0009] A second switch array, coupled to the upper plates of the respective capacitors in the capacitor array, and controlled by the third digital code, the third digital complement code, and the output control signal, for causing the lower plates of the respective capacitors in the capacitor array to be connected to a first reference voltage or a second reference voltage respectively during the reset phase and the output phase of the digital-to-analog converter;

[0010] Wherein, during the reset phase of the digital-to-analog converter, the voltages connected to the lower plate and the upper plate of at least one capacitor in the capacitor array are different, so that the electric charge stored in the capacitor array during the reset phase is greater than 0.

[0011] Optionally, the first switch array includes a plurality of first switches and a plurality of second switches. One end of each of the first switches is coupled to the first reference voltage, one end of each of the second switches is coupled to the second reference voltage, and the other end of each of the first switches and the other end of each of the second switches are respectively and correspondingly coupled to the lower plates of the respective capacitors in the capacitor array. The control terminal of each of the first switches is coupled to the corresponding second digital code, and each of the second switches is coupled to the corresponding second digital complement code.

[0012] Optionally, the first switch array further includes a plurality of third switches. One end of each of the third switches is coupled to a common reference voltage, the other end of each of the third switches is respectively and correspondingly coupled to the lower plates of the respective capacitors in the capacitor array, and the control terminal of each of the third switches is coupled to the reset signal;

[0013] Wherein, the reset signal and the output control signal are two non-overlapping control signals, and each of the third switches is closed during the reset phase of the digital-to-analog converter and is opened during the output phase.

[0014] Optionally, the second switch array includes a plurality of fourth switches, a plurality of fifth switches, and a plurality of sixth switches. One end of each of the fourth switches is coupled to the first reference voltage, one end of each of the fifth switches is coupled to the second reference voltage, and the other end of each of the fourth switches and the other end of each of the fifth switches are respectively and correspondingly coupled to the upper plates of the respective capacitors in the capacitor array and one end of each of the sixth switches. The other end of each of the sixth switches is coupled to the output terminal of the digital-to-analog converter. The control terminal of each of the fourth switches is coupled to the corresponding third digital code, the control terminal of each of the fifth switches is coupled to the corresponding third digital complement code, and the control terminal of each of the sixth switches is coupled to the output control signal;

[0015] Wherein, each of the sixth switches is closed during the output phase of the digital-to-analog converter and is opened during the reset phase.

[0016] Optionally, the first digital code and the first digital complement code received by the control logic circuit within the current cycle are generated by corresponding circuits external to the digital-to-analog converter in the previous cycle.

[0017] Optionally, the capacitance values of the capacitors in the capacitor array are arranged in a binary weighted manner; and / or, the digital-to-analog converter further includes a unit capacitor, the first switch array has a first switch and a second switch provided corresponding to the unit capacitor, the second switch array has a fourth switch, a fifth switch and a sixth switch provided corresponding to the unit capacitor, and the capacitance values of the capacitors in the capacitor array are all binary multiples of the capacitance value of the unit capacitor.

[0018] Optionally, the capacitor array has N capacitors, and the control logic circuit includes N groups of first logic circuits and N groups of second logic circuits provided in one-to-one correspondence with the N capacitors in the capacitor array;

[0019] Wherein, each group of the second logic circuits is used to perform a logic operation on the reset signal, the output control signal, the first digital code and the first digital complement code to generate corresponding second digital codes and second digital complement codes that are complementary to each other;

[0020] Each group of second logic circuits is used to perform a logic operation on the reset signal and the first digital code to generate corresponding third digital codes and fourth digital complement codes that are complementary to each other.

[0021] Optionally, the first logic circuit includes:

[0022] A first AND logic circuit, one input terminal is coupled to the output control signal, and the other input terminal is coupled to the corresponding first digital code;

[0023] A second AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital complement code;

[0024] An OR logic circuit, one input terminal is coupled to the output terminal of the first AND logic circuit, and the other input terminal is coupled to the output terminal of the second AND logic circuit, and outputs the corresponding second digital code;

[0025] A first inverter, the input terminal is coupled to the output terminal of the OR logic circuit, and the output terminal of the first inverter outputs the corresponding second digital complement code;

[0026] And / or, the second logic circuit includes:

[0027] A third AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital code, and outputs the corresponding third digital code;

[0028] A second inverter, with its input terminal coupled to the output terminal of the third AND logic circuit, and the output terminal of the second inverter outputs the corresponding third digital complement.

[0029] Based on the same inventive concept, the present invention further provides an analog-to-digital converter, which includes: an integrator, an analog-to-digital conversion circuit, and the digital-to-analog converter as described in the present invention. Among them, the negative input terminal of the integrator is coupled to the output terminal of the digital-to-analog converter, the positive input terminal of the integrator receives an analog input charge amount, the output terminal of the integrator is coupled to the input terminal of the analog-to-digital conversion circuit, and the output terminal of the analog-to-digital conversion circuit is coupled to the input terminal of the digital-to-analog converter; the integrator is used to subtract a reference from the analog input charge amount according to the charge amount output by the digital-to-analog converter to output a corresponding analog signal, and the analog-to-digital conversion circuit is used to quantize and convert the analog signal output by the integrator into a corresponding digital code signal, and the digital code signal includes a first digital code and a first digital complement, so as to provide it to the digital-to-analog converter.

[0030] Optionally, the analog-to-digital converter further includes a digital filter, with its input terminal coupled to the output terminal of the analog-to-digital conversion circuit, and the digital filter is used to filter out high-frequency components in the digital code signal.

[0031] Optionally, the integrator includes an adder, an operational amplifier, an integration capacitor, and an integration switch. One end of the integration capacitor and one end of the integration switch are both coupled to the negative input terminal of the operational amplifier and the output terminal of the adder, and the other end of the integration capacitor and the other end of the integration switch are both coupled to the output terminal of the operational amplifier and the input terminal of the analog-to-digital conversion circuit. The negative input terminal of the adder is coupled to the output terminal of the digital-to-analog converter, and the positive input terminal of the adder is coupled to the analog input charge amount.

[0032] Based on the same inventive concept, the present invention further provides a touch chip, which includes the analog-to-digital conversion circuit as described in the present invention.

[0033] Optionally, the touch chip further includes an analog front-end circuit coupled to the front end of the analog-to-digital converter. The analog front-end circuit includes a charge and discharge circuit, with its input terminal coupled to a corresponding sensing channel and its output terminal coupled to the positive input terminal of the integrator of the analog-to-digital converter. The charge and discharge circuit is used to convert the analog input signal generated on the sensing channel into an analog input charge amount to provide it to the integrator.

[0034] Based on the same inventive concept, the present invention further provides an electronic device, which further includes a touch panel and the touch chip as described in the present invention. The touch panel has a plurality of sensing channels, and the touch chip is coupled to each of the sensing channels.

[0035] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0036] 1. For the digital-to-analog converter of the present invention, on the basis of keeping the structure of the capacitor array of the existing digital-to-analog converter unchanged, the mode in which the upper plate of each capacitor of the capacitor array is connected to the common reference voltage VCOM is omitted, and at the same time, a control logic circuit for further processing the first digital code and the first digital complement code into a second digital code, a second digital complement code, a third digital code, and a third digital complement code is added. Thus, in the reset stage, the upper plate of each capacitor of the capacitor array is connected to the first reference voltage or the second reference voltage under the control of the third digital code or the third digital complement code, so that the DAC also stores the charge amount in the reset stage. Therefore, in the output stage, under the control of the second digital complement code or the second digital code, the change in the charge amount stored by the DAC can be made relatively larger than before, and thus the charge amount output by the DAC in the output stage increases.

[0037] 2. When outputting the same amount of charge as the existing DAC, the capacitor area of the capacitor array of the DAC of the present invention can be reduced (for example, when the charge amount fed back by the DAC is doubled, the capacitor area can be reduced by 1 time), greatly reducing the circuit area of the DAC. Moreover, a switch is omitted at each capacitor of the capacitor array, so the circuit area of the DAC can be further reduced.

[0038] 3. Since the analog-to-digital converter, the touch control chip, and the electronic device of the present invention adopt the digital-to-analog converter of the present invention, the circuit area can be reduced and the reliability is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0040] Figure 1 is a schematic circuit structure diagram of a conventional digital-to-analog converter.

[0041] Figure 2A and Figure 2B are two schematic circuit structure diagrams of the digital-to-analog converter according to the first embodiment of the present invention.

[0042] Figure 3 is a simplified circuit structure diagram of the first logic sub-circuit in the digital-to-analog converter according to the first embodiment of the present invention.

[0043] Figure 4 is a simplified circuit structure diagram of the second logic sub-circuit in the digital-to-analog converter according to the first embodiment of the present invention.

[0044] Figure 5It is a timing schematic diagram of partial signals of the digital-to-analog converter according to the first embodiment of the present invention.

[0045] Figure 6 It is a schematic diagram of an exemplary circuit structure of the digital-to-analog converter according to the second embodiment of the present invention.

[0046] Figure 7 It is a schematic diagram of the structure of the analog-to-digital converter according to an embodiment of the present invention.

[0047] Figure 8 It is a schematic diagram of the structure of the touch chip according to an embodiment of the present invention. Detailed implementation manners

[0048] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other instances, to avoid confusion with the present invention, some well-known technical features are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals represent the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to determine the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0049] Please refer to Figure 1 , a conventional N-bit digital-to-analog converter (N-bit DAC) has a reset switch Ka, an output switch Kb, a capacitor array formed by parallel connection of N capacitors C1 to C N and a switch array corresponding to the capacitor array, and the capacitors C1 to C NThe capacitance values are arranged in a binary weighted manner. The lower plates of each capacitor in the capacitor array are switched between three voltages, namely the reference voltage AVDD (e.g., the system operating power supply voltage), the reference voltage AVSS (e.g., the ground voltage), and the common reference voltage VCOM, through corresponding switches. For example, the lower plate of capacitor C1 is respectively coupled to one ends of voltage switching switches K1_1, K2_1, and K3_1. The other end of voltage switching switch K1_1 is connected to the reference voltage AVSS, the other end of voltage switching switch K2_1 is connected to the reference voltage AVDD, the other end of voltage switching switch K3_1 is connected to the common reference voltage VCOM, and the control end of voltage switching switch K1_1 is connected to the digital code The control end of voltage switching switch K2_1 is connected to the digital code D1, and the control end of voltage switching switch K3_1 is connected to the reset signal The lower plate of capacitor C2 is respectively coupled to one ends of voltage switching switches K1_2, K2_2, and K3_2. The other end of voltage switching switch K1_2 is connected to the reference voltage AVSS, the other end of voltage switching switch K2_2 is connected to the reference voltage AVDD, the other end of voltage switching switch K3_2 is connected to the common reference voltage VCOM, and the control end of voltage switching switch K1_2 is connected to the digital code The control end of voltage switching switch K2_2 is connected to the digital code D2, and the control end of voltage switching switch K3_2 is connected to the reset signal Capacitor C N The lower plate is respectively coupled to one ends of voltage switching switches K1_N, K2_N, and K3_N. The other end of voltage switching switch K1_N is connected to the reference voltage AVSS, the other end of voltage switching switch K2_N is connected to the reference voltage AVDD, the other end of voltage switching switch K3_N is connected to the common reference voltage VCOM, and the control end of voltage switching switch K1_N is connected to the digital code The control end of voltage switching switch K2_N is connected to the digital code D N and the control end of voltage switching switch K3_N is connected to the reset signal Wherein, is the digital code for Nbit quantization (which can also be called the Nbit quantized digital control signal), and is the inverse code of D1, and so on, is the inverse code of D N .

[0050] When RST is set high and S0 is set low, the upper and lower plates of capacitors C1 to C N are both connected to VCOM, the entire capacitor array is reset, and the total charge Qadc provided by the capacitor array is 0,

[0051] When RST is set low and S0 is set high, the upper plates of capacitors C1 to C N are disconnected from VCOM, and the digital code Control capacitors C1 to C N The lower plates of capacitors C1 to C are connected to AVSS or AVDD. For example, when D1 is high, the lower plate of C1 is connected to AVDD. In this case, the total charge Qadc output by the entire capacitor array of the DAC is as follows:

[0052]

[0053] Obviously, the main function of the above DAC is to re-convert the digital code it receives into an analog quantity (i.e., charge Qadc) for output. Obviously, when this DAC is applied in circuits such as charge integrators or comparators (e.g., analog-to-digital converter ADC), and the charge Qadc output by this DAC is used as the input signal of these circuits, when the processing capabilities of these circuits are fixed, the magnitude of the charge Qadc output by this DAC will directly affect the reliability of the processing results of these circuits for the input signal.

[0054] Based on this, the present invention provides a digital-to-analog converter (Nbit DAC), an analog-to-digital converter (ADC), a touch chip, and an electronic device, which at least eliminate the mode of connecting the upper plates of each capacitor in the capacitor array to VCOM, and make each capacitor in the capacitor array connect to different potentials in the reset state and the feedback state respectively. Thus, without changing the capacitor array, it is possible to increase the charge Qadc output by the DAC in the output stage, and when the same amount of charge is output as the existing DAC, the area of the capacitor array of the DAC can be reduced.

[0055] The following further details the technical solutions proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0056] First Embodiment

[0057] Please refer to Figure 2A and Figure 2B , an embodiment of the present invention provides a digital-to-analog converter (DAC), which is an Nbit (i.e., N-bit, where N is an integer greater than 1) digital-to-analog converter (i.e., Nbit DAC), and includes a capacitor array 10, a first switch array 11, a second switch array 12, and a control logic circuit 13.

[0058] The capacitor array 10 includes N capacitors C1 to C N , in one example, as Figure 2A shown, the N capacitors C1 to C N can be arranged in a binary weighted manner according to the capacitance value (i.e., the capacitance size). For example, C1 = 20 C0, C2 = 2 1 C0, ……, C N = 2 N-1 C0, thus reducing the impact of capacitor mismatch on the overall accuracy of the digital-to-analog converter.

[0059] It should be understood that in other embodiments of the present invention, according to actual requirements, the capacitors in the capacitor array 10 may also not be arranged in a binary weighted manner.

[0060] The first switch array 11 includes N first switches K1_1 to K1_N and N second switches K2_1 to K2_N. One end of each of the first switches is coupled to the first reference voltage Vrp, one end of each of the second switches is coupled to the second reference voltage Vrn, and the other end of each of the first switches and the other end of each of the second switches are respectively coupled to the lower plates of the capacitors in the capacitor array in a one-to-one correspondence. The control end of each of the first switches is coupled to the corresponding second digital code <BO1:BO N >>, and the control end of each of the second switches is coupled to the corresponding second digital complement code <BI1:BI N >>. Thus, the ranking of each capacitor (i.e., each bit capacitor) corresponds to the bits of the second digital code <BO1:BO N >> and the second digital complement code <BI1:BI N >>.

[0061] For example, the lower plate of capacitor C1 is coupled to one end (i.e., the output end) of the first switch K1_1 and one end (i.e., the output end) of the second switch K2_1. The other end (i.e., the input end) of the first switch K1_1 is coupled to the first reference voltage Vrp, and the other end (i.e., the input end) of the second switch K2_1 is coupled to the second reference voltage Vrn. The control end of the first switch K1_1 is coupled to the second digital code BO1, and the control end of the second switch K2_1 is coupled to the second digital complement code BI1, and BO1 is the complement code of BI1. The lower plate of capacitor C2 is coupled to one end (i.e., the output end) of the first switch K1_2 and one end (i.e., the output end) of the second switch K2_2. The other end (i.e., the input end) of the first switch K1_2 is coupled to the first reference voltage Vrp, and the other end (i.e., the input end) of the second switch K2_2 is coupled to the second reference voltage Vrn. The control end of the first switch K1_2 is coupled to the second digital code BO2, and the control end of the second switch K2_2 is coupled to the second digital complement code BI2, and BO2 is the complement code of BI2. And so on, capacitor C N-1The lower plate of the capacitor is coupled to one end (i.e., the output end) of the first switch K1_N-1 and one end (i.e., the output end) of the second switch K2_N-1. The other end (i.e., the input end) of the first switch K1_N-1 is coupled to the first reference voltage Vrp, and the other end (i.e., the input end) of the second switch K2_N-1 is coupled to the second reference voltage Vrn. The control end of the first switch K1_N-1 is coupled to the second digital code BO N-1 The control end of the second switch K2_N-1 is coupled to the second digital inverse code BI N-1 and BO N-1 is the inverse code of BI N-1 The lower plate of the capacitor C N is coupled to one end (i.e., the output end) of the first switch K1_N and one end (i.e., the output end) of the second switch K2_N. The other end (i.e., the input end) of the first switch K1_N is coupled to the first reference voltage Vrp, and the other end (i.e., the input end) of the second switch K2_N is coupled to the second reference voltage Vrn. The control end of the first switch K1_N is coupled to the second digital code BO N The control end of the second switch K2_N is coupled to the second digital inverse code BI N and BO N is the inverse code of BI N That is to say, the second digital inverse code <BI N :BI1> is the inverse code of the second digital code <BO N :BO1>.

[0062] The second switch array 12 includes N fourth switches K4_1 to K4_N, N fifth switches K5_1 to K5_N, and N sixth switches K6_1 to K6_N. One end of each of the fourth switches is coupled to the first reference voltage Vrp, one end of each of the fifth switches is coupled to the second reference voltage Vrn, and the other end of each of the fourth switches and the other end of each of the fifth switches are respectively coupled to the upper plates of the capacitors in the capacitor array and one end of the sixth switches in a one-to-one correspondence. The other end of each of the sixth switches is coupled to the output end of the DAC. The control end of each of the fourth switches is coupled to the corresponding third digital code <AO1:AO N >, the control end of each of the fifth switches is coupled to the corresponding third digital inverse code <AI1:AI N >, and the control end of each of the fifth and sixth switches is coupled to the output control signal S0. Thus, the ranking of each capacitor (i.e., each bit capacitor) corresponds to the bits of the third digital code <AO1:AO N > and the third digital inverse code <AI1:AI N >.

[0063] For example, the upper plate of capacitor C1 is coupled to one end of the fourth switch K4_1 (i.e., the output end of the fourth switch K4_1), one end of the fifth switch K5_1 (i.e., the output end of the fifth switch K5_1), and one end of the sixth switch K6_1 (i.e., the input end of the sixth switch K6_1). The other end of the fourth switch K4_1 (i.e., the input end of the fourth switch K4_1) is coupled to the first reference voltage Vrp. The other end of the fifth switch K5_1 (i.e., the input end of the fifth switch K5_1) is coupled to the second reference voltage Vrn. The other end of the sixth switch K6_1 (i.e., the output end of the fifth switch K6_1) is coupled to the output end of the DAC. The control end of the fourth switch K4_1 is coupled to the third digital code AO1. The control end of the fifth switch K5_1 is coupled to the third digital complement AI1, and AO1 is the complement of AI1. The control end of the sixth switch K6_1 is coupled to the output control signal S0. The upper plate of capacitor C2 is coupled to one end of the fourth switch K4_2 (i.e., the output end of the fourth switch K4_2), (i.e., the output end of the fifth switch K5_1), and one end of the sixth switch K6_2 (i.e., the input end of the sixth switch K6_2). The other end of the fourth switch K4_2 (i.e., the input end of the fourth switch K4_2) is coupled to the first reference voltage Vrp. The other end of the fifth switch K5_2 (i.e., the input end of the fifth switch K5_2) is coupled to the second reference voltage Vrn. The other end of the sixth switch K6_2 (i.e., the output end of the sixth switch K6_2) is coupled to the output end of the DAC. The control end of the fourth switch K4_2 is coupled to the second digital code AO2. The control end of the fifth switch K5_2 is coupled to the second digital complement AI2, and AO2 is the complement of AI2. The control end of the sixth switch K6_2 is coupled to the output control signal S0. And so on, the upper plate of capacitor C N-1 is coupled to one end of the fourth switch K4_N-1 (i.e., the output end of the fourth switch K4_N-1), (i.e., the output end of the fifth switch K5_N-1), and one end of the sixth switch K6_N-1 (i.e., the input end of the sixth switch K6_N-1). The other end of the fourth switch K4_N-1 (i.e., the input end of the fourth switch K4_N-1) is coupled to the first reference voltage Vrp. The other end of the fifth switch K5_N-1 (i.e., the input end of the fifth switch K5_N) is coupled to the second reference voltage Vrn. The other end of the sixth switch K6_N-1 (i.e., the output end of the sixth switch K6_N-1) is coupled to the output end of the DAC. The control end of the fourth switch K4_N-1 is coupled to the second digital code AO N-1 , the control end of the fifth switch K5_N-1 is coupled to the second digital complement AI N-1 , and AO N-1 is the complement of AI N-1 , and the control end of the sixth switch K6_N-1 is coupled to the output control signal S0. Capacitor C NThe upper electrode plate thereof is coupled to one end (i.e., the output end) of the fourth switch K4_N, (i.e., the output end) of the fifth switch K5_N, and one end (i.e., the input end) of the sixth switch K6_N. The other end (i.e., the input end) of the fourth switch K4_N is coupled to the first reference voltage Vrp. The other end (i.e., the input end) of the fifth switch K5_N is coupled to the second reference voltage Vrn. The other end (i.e., the output end) of the sixth switch K6_N is coupled to the output end of the DAC. The control end of the fourth switch K4_N is coupled to the second digital code AO N The control end of the fifth switch K5_N is coupled to the second digital complement AI N and AO N is the complement of AI N . The control end of the sixth switch K6_N is coupled to the output control signal S0. That is to say, the second digital complement <AI N :AI1> is the complement of the second digital code <AO N :AO1>.

[0064] It should be understood that each switch in the first switch array 11 and each switch in the second switch array 12 can respectively adopt any suitable three-terminal switch element, such as MOS transistor, triode, etc. The present invention does not make specific limitations thereto.

[0065] Please refer to Figure 3 and Figure 4 . The control logic circuit 13 includes N groups of first logic circuits <131N:1311> and N groups of second logic circuits <132N:1321> which are respectively arranged in one-to-one correspondence with the N capacitors C1 to C N in the capacitor array 10.

[0066] Please refer to Figure 3 . The corresponding input ends of the N groups of first logic circuits <131N:1311> are respectively coupled to the N-bit first digital code <D N :D1>, the N-bit first digital complement reset signal and the output control signal S0, and are used to generate an N-bit second digital code <BO1:BO N > and an N-bit second digital complement <BI reset signal and the output control signal S0 according to the first digital code <D1:D N >, the first digital complement N :BI1>, and the second digital complement <BI N :BI1> is the complement of the second digital code <BO1:BO NThe one's complement of >. The circuit structures of the N groups of first logic circuits <131N:1311> are basically the same and can be implemented using any suitable circuit design.

[0067] Exemplarily, the N groups of first logic circuits <131N:1311> include N first AND logic circuits <and1n:and11>, N second AND logic circuits <and2n:and21>, N OR logic circuits <orn:or1>and N first inverters <inv1n:inv11>. Among them, N first AND logic circuits <and1n:and11>The input ends are respectively coupled to output a control signal S0 and an N-bit first digital code <D N : D1>, and N second AND logic circuits <and2n:and21>The input ends are respectively coupled to a reset signal and the first digital complement of N bits N OR logic circuits <orn:or1>The output terminals (i.e., N first inverters) <inv1n:inv11>At the input end), N second digital codes of N bits <BO N :BO1> are provided, and the first inverter <inv1n:inv11>Provide the second one's complement of N bits <BI at the output end N : BI1>.

[0068] Among them, N first AND logic circuits <and1n:and11>and N second AND logic circuits <and2n:and21>It can be implemented by using corresponding AND gates or corresponding multiplexers and other circuit structures respectively. N OR logic circuits <orn:or1>It can be implemented by using corresponding circuit structures such as OR gates or flip-flops, etc. The present invention does not make specific limitations thereon.

[0069] Please refer to Figure 2A (or Figure 2B ) and Figure 3 , taking the i-th group of the first logic circuits 131i in the control logic circuit 13 as an example. The i-th group of logic circuits 131i corresponds to the i-th capacitor C in the capacitor array 10 i configured to generate a second digital code BO for controlling the first switch K1_i and a second digital inverse code BI for controlling the second switch K2_i according to the first digital code D i , the first digital inverse code reset signal and the output control signal S0 i and i .

[0070] The i-th group of logic circuits 11i includes a first AND logic circuit AND1i, a second AND logic circuit AND2i, an OR logic circuit ORi, and a first inverter INV1i. Among them, one input terminal of the first AND logic circuit AND1i is coupled to the output control signal S0, and the other input terminal is coupled to the corresponding first digital code D i , and the first AND logic circuit AND1i performs an AND operation on the output control signal S0 and the first digital code D i . One input terminal of the second AND logic circuit AND2i is coupled to the reset signal , and the other input terminal is coupled to the corresponding first digital inverse code . The second AND logic circuit AND2i performs an AND operation on the reset signal and the first digital inverse code . One input terminal of the OR logic circuit ORi is coupled to the output terminal of the first AND logic circuit AND1i, and the other input terminal is coupled to the output terminal of the second AND logic circuit AND2i. The output terminal of the OR logic circuit ORi is coupled to the input terminal of the first inverter INV1i, and the output terminal of the OR logic circuit ORi outputs the second digital code BO i . The output terminal of the first inverter INV1i outputs a second digital inverse code BI that is inverse to the second digital code BO i i .

[0071] Please refer to Figure 4 , the corresponding input terminals of the N groups of second logic circuits <132N:1321> are respectively coupled to the N-bit first digital code <D N :D1>, and the reset signal and are configured to generate according to the first digital code <D1:D N > and the reset signal ​Generate a third digital code <AO1:AO of N bits N > and a third digital complementary code <AI of N bits N :AI1>, and the third digital complementary code <AI N :AI1> is the complementary code of the third digital code <AO1:AO N . The circuit structures of N groups of second logic circuits <132N:1321> are basically the same and can be implemented by any suitable circuit design.

[0072] Exemplarily, N groups of second logic circuits <132N:1321> include N third AND logic circuits <and3n:and31>and N second inverters <inv2n:inv21>Among them, N third AND logic circuits <and3n:and31>The input ends are respectively coupled to a reset signal and the first digital code <D N :D1> of N bits, and N third AND logic circuits <and3n:and31>The output terminal is coupled to N second inverters <inv2n:inv21>at the input end and provide a third digital code <AO of N bits N :AO1>, N second inverters <inv2n:inv21>Provide the third digital one's complement of N bits <AI at the output end N : AI1>.

[0073] Among them, N third AND logic circuits <and3n:and31>It can be implemented by using corresponding AND gates or corresponding multiplexers and other circuit structures, and the present invention does not make specific limitations thereto.

[0074] Please combine Figure 2A (or Figure 2B ) and Figure 4 , taking the i-th group of second logic circuits 132i in the control logic circuit 13 as an example. The i-th group of logic circuits 132i corresponds to the i-th capacitor C in the capacitor array 10 i configured to generate a third digital code AO for controlling the fourth switch K4_i according to the first digital code D i and the reset signal and a third digital complement AI for controlling the fifth switch K5_i i . i .

[0075] The i-th group of logic circuits 11i includes a third AND logic circuit AND3i and a second inverter INV2i. Among them, one input terminal of the third AND logic circuit AND3i is coupled to the reset signal and the other input terminal is coupled to the corresponding first digital code D i . The third AND logic circuit AND3i performs an AND operation on the reset signal and the first digital code D i and outputs the third digital code AO i . The output terminal of the second inverter INV2i outputs a third digital complement AI that is inverted with respect to the third digital code AO i . i .

[0076] In the Nbit DAC of this embodiment, the first reference voltage Vrp and the second reference voltage Vrn are two potential voltages with different magnitudes, and any suitable voltage magnitude can be selected, and it can be provided by a constant voltage source or various reference voltage generation circuits. The present invention does not make specific limitations thereto. For example, the first reference voltage Vrp is greater than 0 (for example, the system operating power supply voltage AVDD), and the second reference voltage Vrn is equal to 0.

[0077] In this embodiment, the output control signal S0 and the reset signal are two non-overlapping control signals, and these two signals will not be simultaneously high or simultaneously low at any moment during the working cycle of the digital-to-analog converter. As an example, the reset signal is inverted with respect to the output control signal S0. When the reset signal is high, the output control signal S0 is low, and each of the sixth switches K6_1 to K6_N is turned off, and the digital-to-analog converter is in the reset stage; when the reset signal When it is low, the output control signal S0 is high, and each of the sixth switches K6_1 to K6_N is closed, and the digital-to-analog converter is in the output stage.

[0078] In addition, when the Nbit DAC of the present invention is integrated into a circuit such as an ADC (not shown) as a circuit module and is used to feedback the digital signals output by these circuits (i.e., the first digital code and the first digital complement), the first digital code <D1:D N > and the first digital complement received by its control logic circuit 13 in the current cycle are actually generated by the pre-stage circuit of the Nbit DAC in the previous cycle. For example, when the corresponding circuit with the Nbit DAC is working, the analog signal is input for the first time into the corresponding circuit with the Nbit DAC. The pre-stage circuit of the Nbit DAC processes and quantifies the first input analog signal and then outputs the first digital code and the first digital complement for the first time; when the analog signal is input for the second time, the Nbit DAC outputs the first charge amount based on the first digital code and the first digital complement for the first time and feeds it back to the corresponding circuit with the Nbit DAC again. Obviously, the first charge amount feeds back the analog signal input for the first time.

[0079] As an example, as shown in Figure 5 At the falling edge of S0, the pre-stage circuit of the Nbit DAC quantifies the analog signal at the current moment, and the corresponding first digital code is D1, D2,..., D corresponding to the arrow N (in fact, the first digital complement that is inverted with it will also be generated synchronously). Therefore, in the (q - 1)T period (representing a period of time in a discrete system, where q is an integer greater than 1), the first digital code and the first digital complement feedback by the Nbit DAC (i.e., coupled to the Nbit DAC) are the first digital code and the first digital complement corresponding to the analog signal input into the corresponding circuit with the Nbit DAC in the (q - 2)T period, simply referred to as the first digital code and the first digital complement in the (q - 2)T period, and the first digital code and the first digital complement feedback by the Nbit DAC in the qT period (i.e., coupled to the Nbit DAC) are the first digital code and the first digital complement corresponding to the analog signal input into the corresponding circuit with the Nbit DAC in the (q - 1)T period, simply referred to as the first digital code and the first digital complement in the (q - 1)T period.

[0080] In the Nbit DAC of this embodiment, the output control signal S0 controls the closing or opening of each of the sixth switches K6_1 to K6_N, thereby respectively controlling the reset of the capacitor array 10 of the DAC and the output of the charge amount Qadc at the output end of the DAC. The second digital code <BO1:BO N > and the second digital complement <BI1:BI N >Control the lower plates of the capacitors in the capacitor array 10 to connect to the first reference voltage Vrp or the second reference voltage Vrn respectively and successively.

[0081] As an example, see Figure 2A (or Figure 2B )to Figure 5 The working timing of the N-bit DAC of this embodiment within a (q-1)T period (where q is an integer greater than 1) is as follows:

[0082] At the beginning, the output control signal S0 is low level, and the reset signal is high, at this time, the sixth switches K6_1 to K6_N are disconnected, the N-bit DAC is in the reset stage, and the control logic circuit 13 can generate the N-bit first digital code according to the time (q-2)T. <D N :D1>(which may correspond to Figure 7 The N-bit ADC quantized output codeword MSB to LSB) and the N-bit first digital inverse codeword and S0 and Generate N bits of the second digital code <BO1:BO N >、Nbit second digital inverse code <BI N :BI1>, Nbit third digit code <AO1:AO N >、Nbit third digit inverse code <AI N :AI1>, thus each capacitor C1~C in the capacitor array of Nbit DAC N The upper plate consists of the third digital code of N bits <AO1:AO N >、Nbit third digit inverse code <AI N :AI1> determines whether to connect to Vrp or Vrn, and the lower plate is determined by the second digital code of Nbit <BO1:BO N >、Nbit second digital inverse code <BI N :BI1> decides to connect Vrp or Vrn, and the potentials of the upper and lower plates of at least one capacitor in the capacitor array are different, thereby precharging the capacitor array 10 through Vrp and Vrn, so that the charge Q0 stored in the capacitor array 10 is greater than 0, and since each sixth switch is disconnected at this time, the Nbit DAC will not output the charge Qadc. As an example, Figure 7 The N-bit ADC quantization output codeword is used as the N-bit first digital codeword. <D N :D1>, taking its most significant bit MSB as an example, if the MSB of the codeword output by the Nbit ADC is high, the upper plate of the capacitor in the capacitor array corresponding to the MSB is connected to Vrp and the lower plate is connected to Vrn, otherwise the upper plate is connected to Vrn and the lower plate is connected to Vrp.

[0083] When the output control signal S0 jumps to a high level, the reset signal is at a low level. At this time, the sixth switches K6_1 to K6_N are closed and conducting, and the N-bit DAC is in the output stage. The control logic circuit 13 still generates an N-bit second digital code <BO1:BO N :D1> according to the N-bit first digital code <D Figure 7 :D1> generated at the (q - 2)T moment (which can correspond to the MSB to LSB of the codeword quantized and output by the N-bit ADC in ), the N-bit first digital complement code and S0 and N generate an N-bit second digital complement code <BI N :BI1>. Thus, the lower plates of the respective capacitors C1 to C N in the capacitor array of the N-bit DAC are determined by the N-bit second digital code <BO1:BO N :D1> and the N-bit second digital complement code <BI N :BI1> to be connected to Vrp or Vrn. Since the sixth switches K6_1 to K6_N are closed and conducting, the upper plates of the respective capacitors C1 to C N in the capacitor array of the N-bit DAC are connected to the output terminal of the DAC (i.e., Figure 7 the inverting input terminal of the integrator in Figure 7 ), causing the amount of charge Q1 stored in the capacitor array 10 to change relative to Q0 in the reset stage. And since the sixth switches K6_1 to K6_N are closed at this time, the N-bit DAC will output an amount of charge Qadc (for example, providing an amount of charge to the inverting input terminal of the integrator in

[0084] ). For example, please refer to Figure 2A (or Figure 2B ), Figure 4 and Figure 5 . For the i-th capacitor C i in the capacitor array 10, if the first digital code D i generated within the (q - 2)T period is 0, then within the (q - 1)T period, during the stage when S0 is at a low level and the reset signal is at a high level (i.e., the reset stage of the N-bit DAC), the upper plate of C i is connected to Vrp, the lower plate is connected to Vrn, and the amount of charge stored between the upper and lower plates of C i is (Vrp - Vrn)*C i , and during the phase when the reset signal is at a low level and S0 is at a high level (i.e., the output phase of the Nbit DAC), C i 's lower plate is connected to Vrp, and C i 's upper plate is connected to the output of the DAC (i.e., Figure 7 the inverting input terminal of the integrator in), and the potential becomes VCOM. The electric charge stored between the upper and lower plates of C i is (VCOM - Vrp)*C i , C i The change value Qadc_C of the electric charge stored during the output phase relative to the electric charge stored during the previous reset phase i is (2*Vrp - Vrn - VCOM)*C i .

[0085] And Figure 1 In the Nbit DAC shown, for C i , during the reset phase, C i Since both the upper and lower plates are connected to VCOM, the electric charge stored in it is 0. And during the output phase, the electric charge stored in C i is even (VCOM - AVDD)*C i , and the change value of its electric charge is 0 - (VCOM - AVDD)*C i .

[0086] Obviously, when Vrp = AVDD = 2*VCOM and Vrn = AVSS = 0, for the capacitor C i at the same position in the capacitor array, in the scheme of this embodiment, Qadc_C i = (2*Vrp - Vrn - VCOM)*C i = 3*VCOM*C i , and Figure 1 in the scheme shown, Qadc_C i = 0 - (VCOM - AVDD)*C i = VCOM*C i . The change value of the electric charge of C i in this embodiment is larger than that of C Figure 1 in the Nbit DAC shown i The change value of the charge quantity is 3 times larger. This shows that in the Nbit DAC solution of the present invention, compared with the traditional Nbit DAC, with the same capacitance array, the charge quantity that can be provided in the output stage can be greatly increased. Moreover, since the charge quantity that can be provided by the Nbit DAC of the present invention in the output stage can be greatly increased compared with the traditional solution, the capacitance array in the Nbit DAC of the present invention can have a smaller area than the capacitance array in the traditional solution when the same charge quantity is output. Of course, in other embodiments of the present invention, Vrp, Vrn, and VCOM can also take other values to make the Nbit DAC output a higher charge quantity than the traditional solution, and the present invention does not make specific limitations on this.

[0087] It should be understood that Figure 2A 、 Figure 3 and Figure 4 The circuit structure shown is only a specific example of the digital-to-analog converter in this embodiment, and does not indicate that the digital-to-analog converter in this embodiment only has these structures. Those skilled in the art can adaptively add, delete, and replace the corresponding circuit structures in the digital-to-analog converter in this embodiment according to the requirements of the actual product. For example, in another example of this embodiment, as Figure 2B shown, the digital-to-analog converter further includes a unit capacitor C0. In the first switch array 11, there are also a first switch K1_0 and a second switch K2_0 that are respectively coupled to the lower plates of the unit capacitor C0 in one-to-one correspondence. In the second switch array 12, there are also a fourth switch K4_0, a fifth switch K5_0, and a sixth switch K6_0 that are respectively coupled to the upper plates of the unit capacitor C0 in one-to-one correspondence. In the control logic circuit 13, there are also a first logic circuit 1310 and a second logic circuit 1320 corresponding to the unit capacitor C0. The first logic circuit 1310 is used to generate the second digital code BO0 required for the control end of the first switch K1_0 and the second digital inverse code BI0 required for the control end of the second switch K2_0. The second logic circuit 1320 is used to generate the third digital code AO0 required for the control end of the fourth switch K4_0 and the third digital inverse code AI0 required for the control end of the fifth switch K5_0. In addition, the capacitance values of the capacitors C1 to C N are all binary multiples of the unit capacitor C0 and are arranged in a binary weighted manner, thereby reducing the influence of capacitor mismatch on the overall accuracy of the digital-to-analog converter.

[0088] Second Embodiment

[0089] Please refer to Figure 6 The present embodiment provides a digital-to-analog converter (DAC), which is an N-bit (i.e., N is an integer greater than 1) digital-to-analog converter (i.e., N-bit DAC), and includes a capacitor array 10, a first switch array 11, a second switch array 12, and a control logic circuit 13. The capacitor array 10 includes N capacitors C1 to C N The first switch array 11 includes not only N capacitors C1 to C N The lower electrode plate of the second switch array 12 includes N first switches K1_1-K1_N and N second switches K2_1-K2_N coupled one by one to the lower electrode plate of the second switch array 12. The second switch array 12 includes N capacitors C1-C N The control logic circuit 13 includes N fourth switches K4_1-K4_N, N fifth switches K5_1-K5_N and N sixth switches K6_1-K6_N coupled to the upper plate of the capacitor array 10 in a one-to-one manner. N The N groups of first logic circuits <131N:1311> and the N groups of second logic circuits <132N:1321> are arranged in a one-to-one correspondence, and the N groups of first logic circuits <131N:1311> are used to generate a first digital code according to the first digital code. <D1:D N >、First digit inverse code Reset signal and output control signal S0 to generate Nbit second digital code <BO1:BO N > and N bits of the second digital complement <BI N :BI1>, N groups of second logic circuits <132N:1321> are used to generate a first digital code according to the first digital code. <D1:D N > and reset signal Generate N bits of the third digital code <AO1:AO N > and the third digit of N bits in 1's complement <AI N The N first switches K1_1-K1_N and the N fourth switches K4_1-K4_N are all coupled to the first reference voltage Vrp, the N second switches K2_1-K2_N and the N fifth switches K5_1-K5_N are all coupled to the second reference voltage Vrn, and the N sixth switches K6_1-K6_N are all coupled to the output end of the DAC.

[0090] The connection relationship among the capacitor array 10 , the first switch array 11 , the second switch array 12 and the control logic circuit 13 in this embodiment is the same as that in the first embodiment, and can be referred to above, which will not be repeated here.

[0091] The difference between the digital-to-analog converter (DAC) of this embodiment and the first embodiment is that the first switch array 11 further includes one end connected to N capacitors C1 to C N N third switches K3_1 to K3_N respectively coupled to the lower plates, with the other ends of the N third switches K3_1 to K3_N all coupled to a common reference voltage VCOM, and the control ends of the N third switches K3_1 to K3_N all coupled to a reset signal

[0092] For example, the lower plate of capacitor C1 is coupled to one end (i.e., the output end) of the third switch K3_1, the other end (i.e., the input end) of the third switch K3_1 is coupled to the common reference voltage VCOM, and the control end of the third switch K3_1 is coupled to the reset signal The lower plate of capacitor C2 is coupled to one end (i.e., the output end) of the third switch K3_2, the other end (i.e., the input end) of the third switch K3_2 is coupled to the common reference voltage VCOM, and the control end of the third switch K3_2 is coupled to the reset signal And so on, the lower plate of capacitor C N-1 is coupled to one end (i.e., the output end) of the third switch K3_N - 1, the other end (i.e., the input end) of the third switch K3_N - 1 is coupled to the common reference voltage VCOM, and the control end of the third switch K3_N - 1 is coupled to the reset signal The lower plate of capacitor C N is coupled to one end (i.e., the output end) of the third switch K3_N, the other end (i.e., the input end) of the third switch K3_N is coupled to the common reference voltage VCOM, and the control end of the third switch K3_N is coupled to the reset signal.

[0093] As an example, please refer to Figures 5 to 6 , the working timing of the N - bit DAC in this embodiment within the (q - 1)T period (where q is an integer greater than 1) is as follows:

[0094] At the beginning, the output control signal S0 is at a low level, and the reset signal is at a high level. At this time, the sixth switches K6_1 to K6_N are disconnected, and the third switches K3_1 to K3_N are closed and conducting. The N - bit DAC is in the reset stage. The control logic circuit 13 can generate an N - bit third digital code <AO1:AO N > and an N - bit third digital complement code <AI Figure 7 :AI1> according to the N - bit first digital code <D N :D1> generated at the (q - 2)T moment (which can correspond to the MSB to LSB of the codeword quantized and output by the N - bit ADC in N ), and the S0. Thus, each capacitor C1 to C in the capacitor array of the N - bit DAC N The upper plate of the capacitor is determined by the third digital code <AO1:AO of N bits N > and the third digital inverse code <AI of N bits N :AI1> to connect to Vrp or Vrn. The lower plate is connected to VCOM because the third switches K3_1 to K3_N are closed and conducting. At this time, the potentials of the upper and lower plates of each capacitor in the capacitor array are different, thereby pre-charging the capacitor array 10 so that the charge quantity Q0 stored in the capacitor array 10 is greater than 0. And because each of the sixth switches is open at this time, the N-bit DAC does not output the charge quantity Qadc to the outside. As an example, Figure 7 The codeword quantized and output by the N-bit ADC in N is used as the first digital code <D of N bits

[0095] Taking its most significant bit MSB as an example, if the MSB of the codeword output by the N-bit ADC is high, the upper plate of the capacitor in the capacitor array corresponding to this MSB is connected to Vrp, otherwise the upper plate is connected to Vrn. When the output control signal S0 jumps to a high level, the reset signal N is at a low level. At this time, the sixth switches K6_1 to K6_N are closed and conducting, and the third switches K3_1 to K3_N are open. The N-bit DAC is in the output stage. The control logic circuit 13 generates the second digital code <BO1:BO of N bits Figure 7 in and the second digital inverse code as well as S0 and N > and the second digital inverse code <BI of N bits N :BI1> according to the first digital code <D of N bits N generated at the (q - 2)T moment (which can correspond to N the MSB to LSB of the codeword quantized and output by the N-bit ADC in N ). Thus, the lower plates of the capacitors C1 to C in the capacitor array of the N-bit DAC N are determined by the second digital code <BO1:BO of N bits Figure 7 in Figure 7 > and the second digital inverse code <BI of N bits N :BI1> to connect to Vrp or Vrn. And because the sixth switches K6_1 to K6_N are closed and conducting, the upper plates of the capacitors C1 to C in the capacitor array of the N-bit DAC are connected to the output terminal of the DAC (i.e., Figure 7 the inverting input terminal of the integrator in Figure 7 ), so that the charge quantity Q1 stored in the capacitor array 10 changes relative to Q0 in the reset stage. And because the sixth switches K6_1 to K6_N are closed at this time, the N-bit DAC will output the charge quantity Qadc to the outside (for example, to Figure 7 The reverse input terminal of the integrator provides the amount of charge). At this time, the Qadc output by the Nbit DAC is Qadc = Q0 - Q1, which is the difference between the amount of charge Q0 stored by the capacitor array 10 during the reset phase and the amount of charge Q0 stored during the output phase (i.e., the change value of the stored charge).

[0096] For example, please combine Figure 5 and Figure 6 to the capacitor C in the capacitor array 10 a the capacitor C b the capacitor C c the capacitor C d For, if the first digital code D a generated during the (q - 2)T period is 0, the first digital code D b is 0, the first digital code D c is 1, the first digital code D d is 1, then during the (q - 1)T period, in the stage where S0 is at a low level and the reset signal is at a high level (i.e., the reset stage of the Nbit DAC), the upper plate of C a is connected to Vrp, the upper plate of C b is connected to Vrp, the upper plate of C c is connected to Vrn, the upper plate of C d is connected to Vrn, and the lower plates of the capacitors C a the capacitor C b the capacitor C c the capacitor C d are all connected to VCOM. The amount of charge stored between the upper and lower plates of C a is (Vrp - VCOM)*C a , the amount of charge stored between the upper and lower plates of C b are all (Vrp - VCOM)*C b , the amount of charge stored between the upper and lower plates of C c is (Vrn - VCOM)*C c , the amount of charge stored between the upper and lower plates of C d is (Vrn - VCOM)*C d .

[0097] And in the stage where the reset signal is at a low level and S0 is at a high level (i.e., the output stage of the Nbit DAC), the lower plate of C a is connected to Vrp, the lower plate of C b is connected to Vrn, the lower plate of C c is connected to Vrp, the lower plate of C d is connected to Vrn, and for the capacitors C a the capacitor C b the capacitor C c and the upper plates of the capacitors C d are all connected to the output terminal of the DAC (i.e., the inverting input terminal of the integrator in Figure 7 ), and the potential becomes VCOM. At this time, the electric charge stored between the upper and lower plates of C a is (VCOM - Vrp) * C a , and the change value Qadc_C of the electric charge stored by C a during the output stage relative to the electric charge stored during the previous reset stage is a (2 * Vrp - 2 * VCOM) * C a ; the electric charge stored between the upper and lower plates of C b is (VCOM - Vrn) * C b , and the change value Qadc_C of the electric charge stored by C b during the output stage relative to the electric charge stored during the previous reset stage is b (Vrp + Vrn - 2 * VCOM) * C b ; the electric charge stored between the upper and lower plates of C c is (VCOM - Vrp) * C c , and the change value Qadc_C of the electric charge stored by C a during the output stage relative to the electric charge stored during the previous reset stage is c (Vrn + Vrp - 2 * VCOM) * C c ; the electric charge stored between the upper and lower plates of C d is (VCOM - Vrn) * C d , and the change value Qadc_C of the electric charge stored by C d during the output stage relative to the electric charge stored during the previous reset stage is d (2 * VCOM - 2 * Vrn) * C d .

[0098] And Figure 1 in the Nbit DAC shown, during the reset stage, for the capacitors C a , capacitor C b , capacitor C c , capacitor C d , since both the upper and lower plates are connected to VCOM, the electric charge stored in them is 0. During the output stage, the electric charge stored in capacitor C a is (VCOM - AVDD) * C a , and the change value of its electric charge is 0 - (VCOM - AVDD) * C a ; the electric charge stored in capacitor C b is (VCOM - AVSS) * C b , and the change value of its electric charge is (VCOM - AVSS) * C b ; Capacitor C c The stored charge amount is (VCOM - AVDD) * C c , and the change value of the charge amount is 0 - (VCOM - AVDD) * C c ; Capacitor C d The stored charge amount is (VCOM - AVSS) * C d , and the change value of the charge amount is (VCOM - AVSS) * C d .

[0099] When Vrp = AVDD = 2 * VCOM and Vrn = AVSS = 0, for the capacitor C in the capacitor array a , Capacitor C b , Capacitor C c , Capacitor C d , in the solution of this embodiment, there are:

[0100] Qadc_C a = (2 * Vrp - 2 * VCOM) * C a = 2 * VCOM * C a ;

[0101] Qadc_C b = (Vrp + Vrn - 2 * VCOM) * C b = 0;

[0102] Qadc_C c = (Vrn + Vrp - 2 * VCOM) * C c = 0;

[0103] Qadc_C d = (2 * VCOM - 2 * Vrn) * C d = 2 * VCOM * C d ;

[0104] Qadc_C a + Qadc_C b + Qadc_C c + Qadc_C d＝ 2 * VCOM * C a + 2 * VCOM * C d .

[0105] And Figure 1 in the solution shown, there are:

[0106] Qadc_C a = 0 - (VCOM - AVDD) * C a = VCOM * C a ;

[0107] Qadc_C b = (VCOM - AVSS) * C b = VCOM * C b ,

[0108] Qadc_C c = 0 - (VCOM - AVDD) * C c = VCOM * C c ,

[0109] Qadc_C d = (VCOM - AVSS) * C d = VCOM * C d ;

[0110] Qadc_C a + Qadc_C b + Qadc_C c + Qadc_C d＝ VCOM * (C a + C b + C c + C d ).

[0111] Obviously, when 2 * C a + 2 * C d > C a + C b + C c + C d in this embodiment, the total charge change value of the capacitor C a , capacitor C b , capacitor C c , capacitor C d is larger than the total charge change value of the capacitor C Figure 1 shown in the scheme, capacitor C a , capacitor C b , capacitor C c , capacitor C d .

[0112] This shows that the Nbit DAC scheme of this embodiment, compared with the traditional Nbit DAC, can increase the charge that can be provided in the output stage under the condition of the same capacitor array structure, and can reduce the area of the capacitor array when outputting the same amount of charge. Of course, in other embodiments of the present invention, Vrp, Vrn, and VCOM can also take other values, and / or the capacitors in the capacitor array can be arranged in a way other than binary weighting. For example, making the above 2 * C a + 2 * C d much larger than C a + C b + C c + C d , thereby increasing as much as possible the amount of electric charge that can be provided during the output stage, so that the Nbit DAC output of this embodiment outputs a higher amount of electric charge compared to the conventional solution. The present invention does not make specific limitations in this regard.

[0113] Third Embodiment

[0114] The digital-to-analog converter of the present invention can be applied to analog-to-digital converters, touch chips, and related electronic devices, and its application range can be wider compared to the conventional solution.

[0115] Please refer to Figure 7 , this embodiment provides an analog-to-digital converter 21 (Analog-to-Digital Converter), which has the digital-to-analog converter Nbit DAC of the present invention. Therefore, this analog-to-digital converter 21 can be a first-order Nbit deltasigma ADC (i.e., a first-order Nbit ⊿-∑ADC).

[0116] In this embodiment, the analog-to-digital converter 21 further includes an integrator INT, an analog-to-digital conversion circuit Nbit ADC, and a digital filter DF (Digital Filter). The negative input terminal of the integrator INT (i.e., Figure 6 the negative input terminal "-" of the adder U0 in Figure 6 ) is coupled to the output terminal of the Nbit DAC. The positive input terminal of the integrator INT (i.e., N the positive input terminal "+" of the adder U0 in ) receives the analog input electric charge Qsig (which can also be referred to as an analog input signal). The output terminal of the integrator INT is coupled to the input terminal of the analog-to-digital conversion circuit Nbit ADC, and the output terminal of the analog-to-digital conversion circuit Nbit ADC is coupled to the input terminal of the Nbit DAC. The integrator INT is used to subtract the reference from the analog input electric charge Qsig according to the electric charge Qadc output by the Nbit DAC to output an analog signal (i.e., the input electric charge after subtracting the reference) Qin after subtracting the reference. The analog-to-digital conversion circuit Nbit ADC is used to quantize and convert the analog signal Qin output by the integrator INT into a corresponding digital code signal. The digital code signal includes a first digital code <D1:D N > and a first digital complement to be provided to the digital-to-analog converter Nbit DAC and the digital filter DF.

[0117] The input terminal of the digital filter DF is coupled to the output terminal of the analog-to-digital conversion circuit Nbit ADC. The digital filter DF is used to filter out the high-frequency components in the first digital code <D1:D N > and the first digital complement .

[0118] It should be understood that the integrator INT, the analog-to-digital conversion circuit Nbit ADC, and the digital filter DF in the analog-to-digital converter 21 can be implemented using any suitable circuit design, and the present invention does not make specific limitations thereto.

[0119] As an example, the digital filter DF can be a Finite Impulse Response (FIR) filter or an Infinite Impulse Response (IIR) filter, and the present invention does not make specific limitations thereto. The digital filter DF outputs a digital signal DOUT <j:0>, where J + 1 > N. For example, J + 1 = 12 and N = 6 - 8.

[0120] As an example, please refer to Figure 7 , the integrator INT includes an adder U0, an operational amplifier Int_OP, an integration capacitor Cfb, and an integration switch Int_RST. One end of the integration capacitor Cfb and one end of the integration switch Int_RST are both coupled to the negative input "-" of the operational amplifier Int_OP and the output of the adder U0. The other end of the integration capacitor Cfb and the other end of the integration switch Int_RST are both coupled to the output of the operational amplifier Int_OP and the input of the analog-to-digital conversion circuit Nbit ADC. The negative input "-" of the adder U0 is coupled to the output of the digital-to-analog converter Nbit DAC, and the positive input "+" of the adder U0 is coupled to the analog input charge amount Qsig.

[0121] The analog-to-digital conversion circuit Nbit ADC quantizes the output Vout of the integrator INT, that is, converts the analog signal Qin into a first digital code <D1:D N > and a first digital complement in a process. Here, D represents the quantized digital signal, corresponding to the least significant bit (LSB) to the most significant bit (MSB) respectively. If the quantization range of the analog-to-digital conversion circuit Nbit ADC is Vref and there are a total of N bits, that is, 2 N values, corresponding to <00…0> (corresponding to the least significant bit) to <11…1> (corresponding to the most significant bit) respectively, then LSB = Vref / 2 N , MSB = Vref * (2 N - 1) / 2 N .

[0122] The function of the N-bit ADC in the analog-to-digital conversion circuit can be simply understood as converting the analog signal vout output by the integrator INT into a digital code, while the function of the N-bit DAC in the digital-to-analog converter can be simply understood as converting the digital code output by the N-bit ADC in the analog-to-digital conversion circuit back into an analog signal output. That is, the Qadc output by the N-bit DAC is the feedback of the previous input of the N-bit ADC (i.e., the analog signal vout), and it is also the feedback of the Qsig of the previous input of the integrator INT. Suppose that at the first operation, the N-bit DAC has not generated feedback yet. After the first input analog input charge amount (i.e., the first analog signal) Qsig is processed by the integrator INT and then quantized by the N-bit ADC in the analog-to-digital conversion circuit, the first set of digital codes is output. When Qsig is input to the integrator INT for the second time, the N-bit DAC receives the first set of digital codes and converts them into the Qadc of the first feedback (which is approximately equal to the first input Qsig). The integrator INT makes a difference between the second input Qsig and the Qadc of the first feedback. This difference is very small and almost equal to zero. That is, the analog signal vout output by the integrator INT is superimposed with a very small difference. After the second quantization by the N-bit ADC, the second set of digital codes is output, and so on, realizing the function that the output of the N-bit ADC tracks the input of the integrator INT. At this time, the output switch Ks in the N-bit DAC is a feedback switch, and when it is closed, it can feedback Qadc to the negative input terminal of the integrator INT.

[0123] The analog-to-digital converter 21 can perform oversampling on the analog input charge amount Qsig, and the oversampling rate is M. In this way, when the target accuracy is (J + 1)-bit accuracy, the number of bits N of the N-bit ADC in this analog-to-digital converter 21 does not have to be equal to (J + 1), and it can be less than (J + 1). The output of the analog-to-digital converter 21 after sampling and digital filtering can easily reach 12-bit accuracy. In this way, the design difficulty and area of the N-bit ADC in the analog-to-digital converter 21 can be greatly reduced, and the linearity requirements for the N-bit DAC are the same as those for the DAC in the analog-to-digital converter under the traditional structure. For example, when J = 11, the target accuracy is 12-bit, and N is equal to 6 to 8.

[0124] Please refer to Figure 5 and Figure 7 , the working principle of the analog-to-digital converter 21 in this embodiment is as follows: At the falling edge of S0, the N-bit ADC in the analog-to-digital conversion circuit quantizes the output Vout of the integrator INT at the current moment, and then generates the first digital code used to reflect the analog input charge amount Qsig received by the integrator INT at the current moment (i.e., Figure 5 In, the D1, D2,..., D corresponding to the arrow N ) and the one's complement of the first digital code, so that the N-bit DAC receives and feeds back the first digital code and the one's complement of the first digital code obtained by quantizing the analog input charge amount Qsig at the current moment by the N-bit ADC in the next cycle. That is to say, in the (q-1)T cycle, the N-bit DAC receives and feeds back the first digital code and the one's complement of the first digital code obtained by quantizing the Vout output by the integrator INT by the N-bit ADC in the (q-2)T cycle, while in the (A)T cycle, the N-bit DAC receives and feeds back the first digital code and the one's complement of the first digital code obtained by quantizing the Vout output by the integrator INT by the N-bit ADC in the (q-1)T cycle.

[0125] Please refer to Figure 7 and Figure 8 , based on the same inventive concept, this embodiment further provides a touch chip, which includes the analog-to-digital converter 21 as described in the present invention, and an analog front-end circuit AFE (Analog Front-end) coupled to the front end of the analog-to-digital converter 21. The analog front-end circuit AFE includes a charge and discharge circuit 20. The input end of the charge and discharge circuit 20 is coupled to a corresponding sensing channel (not marked), and the output end of the charge and discharge circuit 20 is coupled to the positive input end of the integrator INT of the analog-to-digital converter 21 (i.e., the positive input end of the adder U0). The charge and discharge circuit 20 is configured to convert an analog input signal (such as a self-capacitance or mutual capacitance or sensing voltage) generated on the sensing channel RX into an analog input charge amount Qsig to be provided to the integrator INT.

[0126] The charge and discharge circuit 20 can be implemented by any suitable circuit design. As an example, the charge and discharge circuit 20 includes switches P1 to P3 and a current source I0. Among them, the switches P1 to P3 can be any suitable three-terminal switch elements, such as MOS transistors, bipolar transistors, etc. The control end of the switch P1 (such as the gate of the PMOS transistor) receives a control signal S1, the control end of the switch P2 (such as the gate of the PMOS transistor) receives a control signal S2, the control end of the switch P3 (such as the gate of the PMOS transistor) receives an output control signal S0. One end of the current source I0 is connected to a reference voltage AVSS (the AVSS can be an internal ground voltage or the above-mentioned Vrn, where the internal ground voltage is, for example, different from the external ground voltage ground or 0V voltage), and the other end is coupled to one end of the switch P2 (such as the source of the PMOS transistor). The other end of the switch P2 (such as the drain of the PMOS transistor) is coupled to one end of the switch P1 and one end of the switch P3. The other end of the switch P3 serves as the output end of the charge and discharge circuit 20 to output the analog input charge amount Qsig, and the other end of the switch P1 is coupled to a common reference voltage VCOM.

[0127] After the integrator INT reset phase, switch P1 closes, switches P2 and P3 both open, and the analog input signal (such as a sensed voltage) on the sensing channel RX is strongly pulled to VCOM. After the integrator INNT reset ends, switch P1 opens, switches P2 and P3 close, and at the same time the transmit channel TX jumps high. The current source I0 can charge or discharge the sensing channel RX, thereby converting the analog input signal on the sensing channel RX into an analog input charge quantity Qsig output. This Qsig is input to the integrator INNT and subtracted from the Qadc fed back by the DAC (i.e., subtracting the reference). The resulting Qin after subtracting the reference is converted by the integrator INT into Vout (which contains Qsig information), and the Nbit ADC quantizes Vout into a first digital code and a first digital complement code.

[0128] Based on the same inventive concept, please refer to Figure 8 , an embodiment of the present invention further provides an electronic device, which further includes a touch panel 30 and a touch chip 31 as described in the present invention. The touch panel 30 has a plurality of sensing channels, and the touch chip 31 is coupled to each of the sensing channels and is used to detect capacitance changes on the touch panel 30. The detection result of the touch chip 31 can be used to identify the position of a touch event on the touch panel 30 and to determine the user's touch operation.

[0129] Among them, the touch panel 30 can be any touch panel such as an OLED touch screen, which has m longitudinally extending transmit channels TX<1> to TX <m>and n laterally extending sensing channels RX<1> to RX <n>, the intersection of each transmission channel TX and each sensing channel RX is a sensing node, and the values of m and n both depend on the size and shape of the touch panel 30.

[0130] Since the human body is a conductor and is connected to the ground, both the self-capacitance and mutual capacitance of the sensing channel RX touched or approached by a finger will change. Therefore, the touch chip 31 can adopt these two capacitance detection methods, self-capacitance and mutual capacitance, to detect the change in self-capacitance or mutual capacitance on the touch panel 30, and then calculate the touch position of the finger based on the change in the self-capacitance or mutual capacitance, so as to realize touch recognition on the touch panel 30.

[0131] Exemplarily, when performing self-capacitance detection, the touch chip 31 scans the change in the self-capacitance of each transmission channel TX and sensing channel RX to the ground. When a finger approaches or touches, the self-capacitance on the transmission channel TX and sensing channel RX near the finger will increase. When performing mutual-capacitance detection, the touch chip detects the change in the mutual capacitance between the transmission channel TX and the sensing channel RX. Among them, Figure 7 where Cm is the parasitic capacitance between the transmission channel TX and the sensing channel RX, and Cb is the parasitic capacitance between the cathode (Cathode) of the touch panel 30 and the sensing channel RX. Figure 6 The figure shows a mutual-capacitance detection method, where Csig represents the capacitance generated between the finger and the sensing channel RX when the finger touches the touch panel 30 (that is, the capacitance component generated between the finger and the touch panel 30)

[0132] The working principle of the touch chip 31 is to generate Csig when a finger touches the touch screen and Csig disappears when the finger leaves the screen. By scanning the change in self-capacitance or mutual capacitance (that is, whether there is Csig) at each sensing node on the touch panel 30, it is determined whether the touch panel 30 is touched and the touch position. In this embodiment, the touch chip 32 has an analog front-end circuit AFE and an analog-to-digital converter ADC set in one-to-one correspondence with the sensing channel RX, that is, the number of sensing channels RX is equal to the number of analog front-end circuits AFE and analog-to-digital converters ADC. However, in other embodiments of the present invention, the number of analog front-end circuits AFE can also be less than the number of sensing channels RX, and it is realized that multiple sensing channels RX share one analog front-end circuit AFE. And please refer to Figure 6 As shown, the change in self-capacitance or mutual capacitance at each sensing node on the touch panel 30 can be converted into an analog input charge quantity Qsig by the charge and discharge circuit 20, and the analog input charge quantity Qsig when there is or is not a finger touch at each sensing node is different. Thus, the analog input charge quantity Qsig output by the charge and discharge circuit 20 contains finger information. This Qsig containing finger information is sent to the analog-to-digital converter of the present invention for quantization. Thus, by quantifying the "difference" of Qsig, the magnitude of Csig can be judged, and thus it can be judged whether there is a touch.

[0133] For the analog-to-digital converter, touch chip and electronic device of this embodiment, since the analog-to-digital converter of this embodiment is adopted, the area can be made smaller and the reliability can be higher.

[0134] The above description is only a description of the preferred embodiments of the present invention and does not impose any limitation on the scope of the present invention. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure belong to the protection scope of the technical solution of the present invention.< / n> < / m>

Claims

1. A digital-to-analog converter, characterized in that, Comprising: A control logic circuit, the input end of which is coupled to a reset signal, an output control signal, a multi-bit first digital code, and a multi-bit first digital complement code, and is configured to generate a multi-bit second digital code, a multi-bit second digital complement code, a multi-bit third digital code, and a multi-bit third digital complement code according to the reset signal, the output control signal, the first digital code, and the first digital complement code. Wherein, the first digital complement code is the complement code of the first digital code, the second digital complement code is the complement code of the second digital code, and the third digital complement code is the complement code of the third digital code; A capacitor array including a plurality of capacitors; A first switch array, coupled to the lower plates of the respective capacitors in the capacitor array, and controlled by at least one of the second digital code, the second digital complement code, and the reset signal, for connecting the lower plates of the respective capacitors in the capacitor array to corresponding voltages respectively; A second switch array, coupled to the upper plates of the respective capacitors in the capacitor array, and controlled by the third digital code, the third digital complement code, and the output control signal, for connecting the lower plates of the respective capacitors in the capacitor array to a first reference voltage or a second reference voltage respectively during the reset stage and the output stage of the digital-to-analog converter; Wherein, during the reset stage of the digital-to-analog converter, the voltages connected to the lower plate and the upper plate of at least one capacitor in the capacitor array are different, so that the electric charge stored in the capacitor array during the reset stage is greater than 0.

2. The digital-to-analog converter according to claim 1, wherein The first switch array includes a plurality of first switches and a plurality of second switches. One end of each of the first switches is coupled to the first reference voltage, one end of each of the second switches is coupled to the second reference voltage, and the other ends of each of the first switches and the other ends of each of the second switches are respectively and correspondingly coupled to the lower plates of the respective capacitors in the capacitor array. The control end of each of the first switches is coupled to the corresponding second digital code, and each of the second switches is coupled to the corresponding second digital complement code.

3. The digital-to-analog converter according to claim 2, wherein, The first switch array further includes a plurality of third switches. One end of each of the third switches is coupled to a common reference voltage, the other ends of each of the third switches are respectively and correspondingly coupled to the lower plates of the respective capacitors in the capacitor array, and the control end of each of the third switches is coupled to the reset signal; Wherein, the reset signal and the output control signal are two non-overlapping control signals, and each of the third switches is closed during the reset stage of the digital-to-analog converter and is opened during the output stage.

4. The digital-to-analog converter according to claim 1, wherein The second switch array includes a plurality of fourth switches, a plurality of fifth switches, and a plurality of sixth switches. One end of each of the fourth switches is coupled to the first reference voltage, one end of each of the fifth switches is coupled to the second reference voltage, and the other end of each of the fourth switches and the other end of each of the fifth switches are respectively coupled to the upper plates of the capacitors in the capacitor array and one end of each of the sixth switches. The other end of each of the sixth switches is coupled to the output end of the digital-to-analog converter. The control end of each of the fourth switches is coupled to the corresponding third digital code, the control end of each of the fifth switches is coupled to the corresponding third digital complement code, and the control end of each of the sixth switches is coupled to the output control signal; Among them, each of the sixth switches is closed during the output stage of the digital-to-analog converter and opened during the reset stage.

5. The digital-to-analog converter according to claim 1, wherein The first digital code and the first digital complement code received by the control logic circuit in the current cycle are generated by the corresponding external circuit of the digital-to-analog converter in the previous cycle.

6. The digital-to-analog converter according to claim 1, characterized in that, The capacitance values of the capacitors in the capacitor array are arranged in a binary weighted manner; and / or, the digital-to-analog converter further includes a unit capacitor. The first switch array has a first switch and a second switch provided corresponding to the unit capacitor, and the second switch array has a fourth switch, a fifth switch, and a sixth switch provided corresponding to the unit capacitor. The capacitance values of the capacitors in the capacitor array are all binary multiples of the capacitance value of the unit capacitor.

7. The digital-to-analog converter according to any one of claims 1-6, characterized in that, The capacitor array has N capacitors, and the control logic circuit includes N groups of first logic circuits and N groups of second logic circuits provided corresponding to the N capacitors in the capacitor array; Among them, each group of the second logic circuits is used to perform a logical operation on the reset signal, the output control signal, the first digital code, and the first digital complement code to generate corresponding second digital codes and second digital complement codes that are complementary to each other; Each group of the second logic circuits is used to perform a logical operation on the reset signal and the first digital code to generate corresponding third digital codes and fourth digital complement codes that are complementary to each other.

8. The digital-to-analog converter according to claim 7, characterized in that, The first logic circuit includes: A first AND logic circuit, one input terminal is coupled to the output control signal, and the other input terminal is coupled to the corresponding first digital code; A second AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital complement code; An OR logic circuit, one input terminal is coupled to the output terminal of the first AND logic circuit, and the other input terminal is coupled to the output terminal of the second AND logic circuit, and outputs the corresponding second digital code; A first inverter, the input terminal is coupled to the output terminal of the OR logic circuit, and the output terminal of the first inverter outputs the corresponding second digital complement code; and / or, the second logic sub-circuit includes: A third AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital code, and outputs the corresponding third digital code; A second inverter, the input terminal is coupled to the output terminal of the third AND logic circuit, and the output terminal of the second inverter outputs the corresponding third digital complement code.

9. An analog-to-digital converter, characterized in that, Comprising: An integrator, an analog-to-digital conversion circuit, and a digital-to-analog converter as described in any one of claims 1-8, wherein a negative input terminal of the integrator is coupled to an output terminal of the digital-to-analog converter, a positive input terminal of the integrator receives an analog input charge amount, an output terminal of the integrator is coupled to an input terminal of the analog-to-digital conversion circuit, and an output terminal of the analog-to-digital conversion circuit is coupled to an input terminal of the digital-to-analog converter; The integrator is configured to subtract a reference from the analog input charge amount according to the charge amount output by the digital-to-analog converter to output a corresponding analog signal, and the analog-to-digital conversion circuit is configured to quantize and convert the analog signal output by the integrator into a corresponding digital code signal, where the digital code signal includes a first digital code and a first digital complementary code, and is provided to the digital-to-analog converter.

10. The analog-to-digital converter according to claim 9, wherein It further includes a digital filter, an input terminal of which is coupled to an output terminal of the analog-to-digital conversion circuit, and the digital filter is configured to filter out high-frequency components in the digital code signal.

11. The analog-to-digital converter according to claim 9, characterized in that, The integrator includes an adder, an operational amplifier, an integration capacitor, and an integration switch. One end of the integration capacitor and one end of the integration switch are both coupled to a negative input terminal of the operational amplifier and an output terminal of the adder. The other end of the integration capacitor and the other end of the integration switch are both coupled to an output terminal of the operational amplifier and an input terminal of the analog-to-digital conversion circuit. A negative input terminal of the adder is coupled to an output terminal of the digital-to-analog converter, and a positive input terminal of the adder is coupled to the analog input charge amount.

12. A touch chip, characterized in that, Comprising an analog-to-digital converter as described in any one of claims 9-11.

13. The touch control chip according to claim 12, wherein, It further includes an analog front-end circuit coupled to the front end of the analog-to-digital converter. The analog front-end circuit includes a charge and discharge circuit, an input terminal of which is coupled to a corresponding sensing channel, and an output terminal of which is coupled to a positive input terminal of the integrator of the analog-to-digital converter. The charge and discharge circuit is configured to convert an analog input signal generated on the sensing channel into an analog input charge amount and provide it to the integrator.

14. An electronic device, characterized in that, Comprising a touch panel and a touch chip as described in claim 12 or 13. The touch panel has a plurality of sensing channels, and the touch chip is coupled to each of the sensing channels.

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