Digital-to-analog converter, analog-to-digital converter, touch chip and electronic equipment

Abstract

According to the digital-to-analog converter, the analog-to-digital converter, the touch control chip and the electronic equipment provided by the invention, on the basis of keeping structures of a capacitor array, a reset switch, an output switch and the like of an existing digital-to-analog converter unchanged, a switch for connecting a lower polar plate of each capacitor of the capacitor array with a common reference voltage VCOM is omitted; meanwhile, a control logic circuit for further processing a first digital code and a second digital code into a third digital code and a fourth digital code is added, so that the DAC can store the electric charge quantity in the reset stage, the electric charge quantity output by the DAC in the output stage is larger than that output by an existing digital-to-analog converter, and when the electric charge quantity output by the DAC is the same as that output by the existing DAC, the electric charge quantity output by the DAC is larger than that output by the existing DAC. The capacitance area of the capacitor array can be reduced. According to the analog-to-digital converter, the touch control chip and the electronic equipment, due to the adoption of the digital-to-analog converter, the circuit area can be reduced, and the reliability is also improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and particularly to a digital-to-analog converter, an analog-to-digital converter, a touch chip, and an electronic device. Background Art

[0002] A digital-to-analog converter (DAC) circuit is a bridge for converting between digital signals and analog signals. It can be used as a separate module or as part of an analog-to-digital converter (ADC), and is widely applied in fields such as communication, sensing, and multimedia.

[0003] Currently, a conventional digital-to-analog converter generally has a binary-weighted capacitor array, and the lower plates of each capacitor in the capacitor array are allowed to switch between three voltages: a first reference voltage AVDD (such as the power supply voltage of the system), a second reference voltage AVSS (such as the ground voltage of the system), and a common reference voltage VCOM. This digital-to-analog converter has defects such as a large area and a small amount of charge output in the output stage, thus limiting the performance improvement of the digital-to-analog converter, the analog-to-digital converter having this digital-to-analog converter, the touch chip, and the electronic device. Summary of the Invention

[0004] The purpose of the present invention is to provide a digital-to-analog converter, an analog-to-digital converter, a touch chip, and an electronic device, which can help reduce the area of the digital-to-analog converter and increase the amount of charge output by the digital-to-analog converter.

[0005] To achieve the above purpose, the present invention provides a digital-to-analog converter, which includes:

[0006] A control logic circuit, whose input end is coupled to a reset signal, an output control signal, a multi-bit first digital code, and a multi-bit second digital code, and is configured to generate a multi-bit third digital code and a multi-bit fourth digital code according to the reset signal, the output control signal, the first digital code, and the second digital code, wherein the second digital code is the inverse code of the first digital code, and the fourth digital code is the inverse code of the third digital code;

[0007] A capacitor array, including a plurality of capacitors, and the upper plates of each capacitor are coupled to each other;

[0008] A switch array, including a plurality of first switches and a plurality of second switches. One end of each of the first switches is coupled to a first reference voltage, one end of each of the second switches is coupled to a second reference voltage, and the other ends of each of the first switches and the other ends of each of the second switches are respectively coupled to the lower plates of each capacitor in the capacitor array in a one-to-one correspondence. The control end of each of the first switches is coupled to the corresponding third digital code, and the control end of each of the second switches is coupled to the corresponding fourth digital code;

[0009] Wherein, the third digital code or the fourth digital code is used to control the lower plates of the capacitors in the capacitor array to connect to the first reference voltage or the second reference voltage during the reset stage of the digital-to-analog converter, so that the electric charge stored in the capacitor array is greater than 0.

[0010] Optionally, the fourth digital code or the third digital code is used to control the lower plates of the capacitors in the capacitor array to connect to the second reference voltage or the first reference voltage during the output stage of the digital-to-analog converter. And when the first reference voltage is greater than 0 and the second reference voltage is equal to 0, the change value of the corresponding capacitor in the capacitor array relative to the electric charge stored in it during the reset stage during the output stage is the product of the capacitance value of the capacitor and the first reference voltage.

[0011] Optionally, the upper plates of all the capacitors are coupled to a common reference voltage during the reset stage, and the common reference voltage is half of the difference between the first reference voltage and the second reference voltage.

[0012] Optionally, the digital-to-analog converter further includes a reset switch and an output switch. The output end of the reset switch and the input end of the output switch are both coupled to the upper plates of the capacitors in the capacitor array. The input end of the reset switch is coupled to the common reference voltage, the control end of the reset switch is coupled to the reset signal, the control end of the output switch is coupled to the output control signal, the output end of the output switch is directly used as or coupled to the output end of the digital-to-analog converter, and the reset signal and the output control signal are two non-overlapping control signals;

[0013] Wherein, during the reset stage of the digital-to-analog converter, the reset signal controls the reset switch to close, and the output control signal controls the output switch to open. During the output stage of the digital-to-analog converter, the reset signal controls the reset switch to open, and the output control signal controls the output switch to close.

[0014] Optionally, the first digital code and the second digital code received by the control logic circuit in the current cycle are generated by the corresponding circuit outside the digital-to-analog converter in the previous cycle.

[0015] Optionally, the capacitance values of the capacitors in the capacitor array are arranged in a binary weighted manner; and / or, the digital-to-analog converter further includes a unit capacitor. The lower plate of the unit capacitor is coupled to the common reference voltage, the upper plate of the unit capacitor is coupled to the upper plates of the capacitors in the capacitor array, and the capacitance values of the capacitors in the capacitor array are all binary multiples of the capacitance value of the unit capacitor.

[0016] Optionally, the capacitor array has N capacitors, and the control logic circuit includes N groups of logic circuits respectively arranged corresponding to the N capacitors in the capacitor array. Each group of logic circuits includes:

[0017] A first AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital code;

[0018] A second AND logic circuit, one input terminal is coupled to the output control signal, and the other input terminal is coupled to the corresponding second digital code;

[0019] An OR logic circuit, one input terminal is coupled to the output terminal of the first AND logic circuit, and the other input terminal is coupled to the output terminal of the second AND logic circuit, and outputs the corresponding third digital code;

[0020] An inverter, the input terminal is coupled to the output terminal of the OR logic circuit, and the output terminal of the inverter outputs the corresponding fourth digital code.

[0021] Based on the same inventive concept, the present invention further provides an analog-to-digital converter, which includes: an integrator, an analog-to-digital conversion circuit, and the digital-to-analog converter as described in the present invention. Wherein, the negative input terminal of the integrator is coupled to the output terminal of the digital-to-analog converter, the positive input terminal of the integrator receives an analog input charge amount, the output terminal of the integrator is coupled to the input terminal of the analog-to-digital conversion circuit, and the output terminal of the analog-to-digital conversion circuit is coupled to the input terminal of the digital-to-analog converter; the integrator is used to subtract the reference from the analog input charge amount according to the charge amount output by the digital-to-analog converter to output a corresponding analog signal, and the analog-to-digital conversion circuit is used to quantize and convert the analog signal output by the integrator into a corresponding digital code signal, and the digital code signal includes a first digital code and a second digital code, and is provided to the digital-to-analog converter.

[0022] Optionally, the analog-to-digital converter further includes a digital filter, the input terminal is coupled to the output terminal of the analog-to-digital conversion circuit, and the digital filter is used to filter out high-frequency components in the digital code signal.

[0023] Optionally, the integrator includes an adder, an operational amplifier, an integration capacitor, and an integration switch. One end of the integration capacitor and one end of the integration switch are both coupled to the negative input terminal of the operational amplifier and the output terminal of the adder, and the other end of the integration capacitor and the other end of the integration switch are both coupled to the output terminal of the operational amplifier and the input terminal of the analog-to-digital conversion circuit. The negative input terminal of the adder is coupled to the output terminal of the digital-to-analog converter, and the positive input terminal of the adder is coupled to the analog input charge amount.

[0024] Based on the same inventive concept, the present invention further provides a touch chip, which includes the analog-to-digital conversion circuit as described in the present invention.

[0025] Optionally, the touch chip further includes an analog front-end circuit coupled to the front end of the analog-to-digital converter. The analog front-end circuit includes a charge and discharge circuit. The input end of the charge and discharge circuit is coupled to a corresponding sensing channel, and the output end thereof is coupled to the positive input end of the integrator of the analog-to-digital converter. The charge and discharge circuit is configured to convert an analog input signal generated on the sensing channel into an analog input charge quantity for providing to the integrator.

[0026] Based on the same inventive concept, the present invention further provides an electronic device, which further includes a touch panel and the touch chip as described in the present invention. The touch panel has a plurality of sensing channels, and the touch chip is coupled to each of the sensing channels.

[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0028] 1. For the digital-to-analog converter of the present invention, on the basis of keeping the structures of the existing digital-to-analog converter such as the capacitor array, the reset switch, and the output switch unchanged, the switch for connecting the lower electrode plate of each capacitor of the capacitor array to the common reference voltage VCOM is omitted, and at the same time, a control logic circuit for further processing the first digital code and the second digital code into a third digital code and a fourth digital code is added. Thus, in the reset stage, the lower electrode plate of each capacitor of the capacitor array is connected to the first reference voltage or the second reference voltage through the control of the third digital code or the fourth digital code, so that the DAC also stores a charge quantity. Therefore, in the output stage, through the control of the fourth digital code or the third digital code, the change in the charge quantity stored in the DAC can be made relatively larger than before, thereby increasing the charge quantity output by the DAC in the output stage.

[0029] 2. When outputting the same amount of charge quantity as the existing DAC, the capacitance area of the capacitor array of the DAC of the present invention can be reduced (for example, when the charge quantity fed back by the DAC is doubled, the capacitance area can be reduced by 1 time), greatly reducing the circuit area of the DAC. Moreover, a switch is omitted at each capacitor of the capacitor array, so the circuit area of the DAC can be further reduced.

[0030] 3. Since the analog-to-digital converter, the touch chip, and the electronic device of the present invention adopt the digital-to-analog converter of the present invention, the circuit area can be reduced and the reliability is also improved. Description of the Drawings

[0031] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0032] Figure 1 is a schematic circuit structure diagram of a conventional digital-to-analog converter.

[0033] Figure 2A and Figure 2B are schematic diagrams of two example circuit structures of a digital - to - analog converter according to an embodiment of the present invention.

[0034] Figure 3 is a schematic diagram of a simplified circuit structure of a control logic circuit in a digital - to - analog converter according to an embodiment of the present invention.

[0035] Figure 4 is a schematic diagram of the circuit structure of the i - th group of control logic circuits in a digital - to - analog converter according to an embodiment of the present invention.

[0036] Figure 5 is a timing diagram of partial signals of a digital - to - analog converter according to an embodiment of the present invention.

[0037] Figure 6 is a schematic diagram of the structure of an analog - to - digital converter according to an embodiment of the present invention.

[0038] Figure 7 is a schematic diagram of the structure of a touch chip according to an embodiment of the present invention. Detailed implementation manners

[0039] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, in order to avoid obscuring the present invention, some well - known technical features are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to determine the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0040] Please refer to Figure 1 , a conventional N - bit digital - to - analog converter (N - bit DAC) has a reset switch K0, an output switch Ks, and consists of N capacitors C1 to C NA capacitor array formed in parallel and a switch array corresponding to the capacitor array, where the capacitance values of capacitors C1 to C N are arranged in a binary weighted manner. The lower plate of each capacitor in the capacitor array can be switched among three voltages: a first reference voltage AVDD (such as the power supply voltage), a second reference voltage AVSS (such as the ground voltage), and a common reference voltage VCOM through corresponding switches. For example, the lower plate of capacitor C1 is respectively coupled to one ends of voltage switching switches K1_1, K2_1, and K3_1. The other end of voltage switching switch K1_1 is connected to the second reference voltage AVSS, the other end of voltage switching switch K2_1 is connected to the common reference voltage VCOM, the other end of voltage switching switch K3_1 is connected to the first reference voltage AVDD, and the control end of voltage switching switch K1_1 is connected to the digital code The control end of voltage switching switch K2_1 is connected to the reset signal RST, and the control end of voltage switching switch K3_1 is connected to the digital code D1; the lower plate of capacitor C2 is respectively coupled to one ends of voltage switching switches K1_2, K2_2, and K3_2. The other end of voltage switching switch K1_2 is connected to the second reference voltage AVSS, the other end of voltage switching switch K2_2 is connected to the common reference voltage VCOM, the other end of voltage switching switch K3_2 is connected to the first reference voltage AVDD, and the control end of voltage switching switch K1_2 is connected to the digital code The control end of voltage switching switch K2_2 is connected to the reset signal RST, and the control end of voltage switching switch K3_2 is connected to the digital code D2; the lower plate of capacitor C N is respectively coupled to one ends of voltage switching switches K1_N, K2_N, and K3_N. The other end of voltage switching switch K1_N is connected to the second reference voltage AVSS, the other end of voltage switching switch K2_N is connected to the common reference voltage VCOM, the other end of voltage switching switch K3_N is connected to the first reference voltage AVDD, and the control end of voltage switching switch K1_N is connected to the digital code The control end of voltage switching switch K2_N is connected to the reset signal RST, and the control end of voltage switching switch K3_N is connected to the digital code D N , where is an N-bit quantized digital code (which can also be called an N-bit quantized digital control signal), and is the inverse code of D1, and so on, is the inverse code of D N .

[0041] When RST is set high and S0 is set low, the upper and lower plates of capacitors C1 to C N are both connected to VCOM, the entire capacitor array is reset, and the total charge Qadc provided by the capacitor array is 0,

[0042] When RST is set low and S0 is set high, capacitors C1 to CN The upper electrode plate of is disconnected from VCOM, and the digital code controls capacitors C1 to C N The lower electrode plate of is connected to AVSS or AVDD. For example, when D1 is high, the lower electrode plate of C1 is connected to AVDD. In this case, the total charge Qadc output by the entire capacitor array of the DAC is:

[0043]

[0044] The above DAC has the following defects:

[0045] 1. The main function of the above DAC is to re-convert the received digital code into an analog quantity (i.e., charge quantity Qadc) and output it. Obviously, when this DAC is applied in circuits such as charge integrators or comparators (such as analog-to-digital converters ADC), and the charge quantity Qadc output by this DAC is used as the input signal of these circuits, when the processing capabilities of these circuits are certain, the magnitude of the charge quantity Qadc output by this DAC will directly affect the reliability of the processing results of these circuits for the input signal.

[0046] 2. Each capacitor in the capacitor array of the above DAC requires three switches to switch three reference voltages, and the capacitance size and area of the capacitor array are relatively large. Therefore, the area of the DAC is large, which limits the application range of this DAC.

[0047] Based on this, the present invention provides a digital-to-analog converter (Nbit DAC), an analog-to-digital converter (ADC), a touch control chip, and an electronic device. On the basis of keeping the existing capacitor array, reset switch, and output switch of the DAC unchanged, the switch that connects the lower electrode plate of each capacitor in the capacitor array to the common reference voltage VCOM in the original switch array is omitted. At the same time, a control logic circuit for further processing the digital code into a third digital code <DI N :DI1> and a fourth digital code <DO N :DO1> is added, which is used to control the lower electrode plate of each capacitor in the capacitor array to be connected to the first reference voltage AVDD or the second reference voltage AVSS, thereby increasing the charge quantity output by the DAC. When the same amount of charge quantity as the existing DAC is output, the capacitance area of the capacitor array of the DAC of the present invention can be reduced (for example, when the charge quantity fed back by the DAC doubles compared with the prior art, its capacitance area can be reduced by 1 time compared with the prior art), greatly reducing the circuit area of the DAC. Moreover, one switch is omitted at each capacitor in the capacitor array, so the circuit area of the DAC can be further reduced.

[0048] The technical solution proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0049] Please refer to Figure 2A and Figure 2B , an embodiment of the present invention provides a digital-to-analog converter (DAC), which is an N-bit (i.e., N bits, where N is an integer greater than 1) digital-to-analog converter (i.e., N-bit DAC), and includes a capacitor array 10, a switch array 11, a control logic circuit 12, a reset switch K0, and an output switch Ks.

[0050] Among them, in one example, as Figure 2A shown, the digital-to-analog converter of this embodiment further includes a unit capacitor C0. The lower plate of the unit capacitor C0 and the input end of the reset switch K0 are both coupled to the common reference voltage VCOM. The upper plate of the unit capacitor C0 is coupled to the output end of the reset switch K0 and the input end of the output switch Ks. The output end of the output switch Ks is directly used as the output end of the digital-to-analog converter or is coupled to the output end of the digital-to-analog converter. Among them, the capacitance value of the unit capacitor C0 is expressed as 2 0 C u . That is, C0 = 2 0 C u .

[0051] The control end of the reset switch K0 is also coupled to the reset signal RST to be closed and opened under the control of the reset signal RST. The control end of the output switch Ks is also coupled to the output control signal S0 to be closed and opened under the control of the output control signal S0. Among them, the reset signal RST and the output control signal S0 are two non-overlapping control signals, and these two signals will not be both high level or both low level at any moment during the working cycle of the digital-to-analog converter. Thus, at any moment during the working cycle of the digital-to-analog converter, the control reset switch K0 and the output switch Ks will not be closed at the same time, nor will they be opened at the same time, thereby avoiding the occurrence of a short circuit. Among them, when the reset signal RST controls the reset switch K0 to be closed and the output control signal S0 controls the output switch Ks to be opened, the digital-to-analog converter is in the reset stage; when the reset signal RST controls the reset switch K0 to be opened and the output control signal S0 controls the output switch Ks to be closed, the digital-to-analog converter is in the output stage.

[0052] The capacitor array 10 includes N capacitors C1 to C N , and the upper plates of each of the capacitors C1 to C N are all coupled to the upper plate of the unit capacitor C0. It can also be said that the N capacitors C1 to C NConnected in parallel. In an example of this first embodiment, as Figure 2A shown, N capacitors C1 to C N can be arranged in a binary weighted manner according to the capacitance value (i.e., the capacitance size), and the capacitance values of C1 to C N are all binary multiples of the unit capacitance C0. For example, C1 = 2 0 C u , C2 = 2 1 C u , ……, C N = 2 N-1 C u , thereby reducing the influence of capacitor mismatch on the overall accuracy of the digital-to-analog converter.

[0053] In another example, as Figure 2B shown, when the overall accuracy requirement of the digital-to-analog converter permits, the digital-to-analog converter in this embodiment can also omit the setting of the unit capacitance C0 to further simplify the circuit.

[0054] In addition, it should be understood that in other embodiments of the present invention, according to actual needs, the capacitors in the capacitor array 10 may not be arranged in a binary weighted manner.

[0055] The switch array 11 includes N first switches K4_1 to K4_N and N second switches K5_1 to K5_N. One end of each of the first switches is coupled to the first reference voltage AVDD, one end of each of the second switches is coupled to the second reference voltage AVSS, and the other end of each of the first switches and the other end of each of the second switches are respectively coupled to the lower plates of the capacitors in the capacitor array in a one-to-one correspondence. The control end of each of the first switches is coupled to the corresponding third digital code <DI N :DI1>, and the control end of each of the second switches is coupled to the corresponding fourth digital code <DO N :DO1>. Thus, the ranking of each capacitor (i.e., each bit capacitor) is related to the third digital code <DI N :DI1> and the fourth digital code <DO N:DO1>. For example, the lower plate of capacitor C1 is coupled to one end (i.e., the output end) of the first switch K4_1 and one end (i.e., the output end) of the second switch K5_1. The other end (i.e., the input end) of the first switch K4_1 is coupled to the first reference voltage AVDD, and the other end (i.e., the input end) of the second switch K5_1 is coupled to the second reference voltage AVSS. The control end of the first switch K4_1 is coupled to the third digital code DI1, and the control end of the second switch K5_1 is coupled to the fourth digital code DO1, and DO1 is the inverse code of DI1. The lower plate of capacitor C2 is coupled to one end (i.e., the output end) of the first switch K4_2 and one end (i.e., the output end) of the second switch K5_2. The other end (i.e., the input end) of the first switch K4_2 is coupled to the first reference voltage AVDD, and the other end (i.e., the input end) of the second switch K5_2 is coupled to the second reference voltage AVSS. The control end of the first switch K4_2 is coupled to the third digital code DI2, and the control end of the second switch K5_2 is coupled to the fourth digital code DO2, and DO2 is the inverse code of DI2. And so on, the lower plate of capacitor C N is coupled to one end (i.e., the output end) of the first switch K4_N and one end (i.e., the output end) of the second switch K5_N. The other end (i.e., the input end) of the first switch K4_N is coupled to the first reference voltage AVDD, and the other end (i.e., the input end) of the second switch K5_N is coupled to the second reference voltage AVSS. The control end of the first switch K4_N is coupled to the third digital code DI N , and the control end of the second switch K5_N is coupled to the fourth digital code DO N , and DO N is the inverse code of DI N . That is to say, the fourth digital code <DO N :DO1> is the inverse code of the third digital code <DI N :DI1>.

[0056] Among them, each switch in the switch array 11, as well as the reset switch K0 and the output switch Ks, can respectively adopt any suitable three-terminal switch element, such as MOS transistors, bipolar transistors, etc., and the present invention does not make specific limitations on this.

[0057] The control logic circuit 12 can be implemented by adopting any suitable circuit design, and its corresponding input ends are respectively coupled to the Nbit first digital code <D N :D1>, the Nbit second digital code the reset signal RST and the output control signal S0, and is used for according to the first digital code <D N: D1>, The reset signal RST and the output control signal S0 generate an N-bit third digital code <DI N : DI1> and an N-bit fourth digital code <DO N : DO1>. Among them, the second digital code is the inverse code of the first digital code <D N : D1>.

[0058] As an example, please refer to Figure 3 , the control logic circuit 12 includes N groups of logic circuits set in one-to-one correspondence with N capacitors C1 to C in the capacitor array 10 N One by one, each group of logic circuits includes a first AND logic circuit, a second AND logic circuit, an OR logic circuit, and an inverter. Thus, the control logic circuit 12 includes N first AND logic circuits <and1n:and11>, N second AND logic circuits <and2n:and21>, N OR logic circuits <orn:or1>and N inverters <invn:inv1>Among them, N first AND logic circuits <and1n:and11>The input ends are respectively coupled to a reset signal RST and an N-bit first digital code <D N :D1>, and N second AND logic circuits <and21:and2n>The input ends thereof are respectively coupled to an output control signal S0 and an N-bit second digital code N OR logic circuits <orn:or1>The output terminals (i.e., N inverters) <inv1:invn>Provide the third digital code <DI of N bits at the input end) N DI1>, N inverters <inv1:invn>The output terminal provides an N-bit fourth digital code <DO N :DO1>.

[0059] Among them, N first AND logic circuits <and1n:and11>and N second AND logic circuits <and2n:and21>It can be implemented by using corresponding AND gates or corresponding multiplexers and other circuit structures respectively. The N OR logic circuits can be implemented by using corresponding OR gates or flip - flops and other circuit structures respectively. The present invention does not make specific limitations in this regard.

[0060] Please combine Figure 2A (OR Figure 2B ) and Figure 4 , taking the i - th group of logic circuits 11i in the control logic circuit 12 as an example. The i - th group of logic circuits 11i corresponds to the i - th capacitor C i in the capacitor array 10. It is configured to generate a third digital code DI i for controlling the first switch K4_i and a fourth digital code DO for controlling the second switch K5_i according to the first digital code D i , the second digital code i , the reset signal RST and the output control signal S0.

[0061] The i - th group of logic circuits 11i includes a first AND logic circuit AND1i, a second AND logic circuit AND2i, an OR logic circuit ORi and an inverter INVi. Among them, one input terminal of the first AND logic circuit AND1i is coupled to the reset signal RST, and the other input terminal is coupled to the corresponding first digital code D i . The first AND logic circuit AND1i performs an AND operation on the reset signal RST and the first digital code D i . One input terminal of the second AND logic circuit AND2i is coupled to the output control signal S0, and the other input terminal is coupled to the corresponding second digital code . The second AND logic circuit AND2i performs an AND operation on the output control signal S0 and the second digital code . One input terminal of the OR logic circuit ORi is coupled to the output terminal of the first AND logic circuit AND1i, and the other input terminal is coupled to the output terminal of the second AND logic circuit AND2i. The output terminal of the OR logic circuit ORi is coupled to the input terminal of the inverter INVi. The output terminal of the OR logic circuit ORi outputs the third digital code DI i . The output terminal of the inverter INVi outputs a fourth digital code DO i that is inverted with respect to the third digital code DI i .

[0062] It should be understood that in the N - bit DAC of this embodiment, the common reference voltage VCOM, the first reference voltage AVDD and the second reference voltage AVSS can be selected as voltages of any appropriate magnitude, and they can be provided by a constant voltage source or various reference voltage generation circuits. The present invention does not make specific limitations in this regard. For example, the first reference voltage AVDD is greater than 0 (for example, it is the system operating power supply voltage), and the second reference voltage AVSS is equal to 0.

[0063] In addition, when the N-bit DAC of the present invention is integrated into a circuit such as an ADC (not shown) as a circuit module and is used to feedback the digital signals (i.e., the first digital code and the second digital code) output by these circuits, the first digital code <D N :D1> and the second digital code received by its control logic circuit 12 in the current cycle are actually generated by the pre-stage circuit of the N-bit DAC in the previous cycle. For example, when the corresponding circuit with the N-bit DAC is working, the analog signal is input into the corresponding circuit with the N-bit DAC for the first time. The pre-stage circuit of the N-bit DAC processes and quantifies the first input analog signal and outputs the first digital code and the second digital code for the first time. When the analog signal is input for the second time, the N-bit DAC outputs the first charge amount based on the first digital code and the second digital code for the first time and feeds it back to the corresponding circuit with the N-bit DAC again. Obviously, the first charge amount feeds back the first input analog signal. As an example, as shown in

[0064] Combined with Figure 5 shown, at the falling edge of S0, the pre-stage circuit of the N-bit DAC quantifies the analog signal at the current moment. The corresponding first digital code is D1, D2,..., D corresponding to the arrow N (in fact, the second digital code that is actually inverted will also be generated synchronously). Therefore, within the (A-1)T period (representing a period of time in a discrete system, where A is an integer greater than 1), the N-bit DAC feeds back (i.e., the N-bit DAC is coupled to) the first digital code and the second digital code corresponding to the analog signal input into the corresponding circuit with the N-bit DAC within the (A-2)T period, simply referred to as the first digital code and the second digital code within the (A-2)T period. And within the (A)T period, the N-bit DAC feeds back (i.e., the N-bit DAC is coupled to) the first digital code and the second digital code corresponding to the analog signal input into the corresponding circuit with the N-bit DAC within the (A-1)T period, simply referred to as the first digital code and the second digital code within the (A-1)T period.

[0065] In the N-bit DAC of this embodiment, the reset signal RST and the output control signal S0 control the closing or opening of the reset switch K0 and the output switch S0 in a non-overlapping manner, so as to respectively control the reset of the capacitor array 10 of the DAC and the output of the charge amount Qadc at the output end of the DAC. The third digital code <DI N :DI1> and the fourth digital code <DO N :DO1> respectively control the lower plates of the respective capacitors in the capacitor array 10 to be connected to the first reference voltage AVDD or the second reference voltage AVSS successively.

[0066] As an example, please refer to Figure 2A (or Figure 2B ) to Figure 5 , the working timing of the Nbit DAC of this embodiment within (A - 1)T cycles (where A is an integer greater than 1) is as follows:

[0067] At the beginning, RST is at a high level and S0 is at a low level, K0 is closed, Ks is open, the Nbit DAC is in the reset stage, and the upper plates of the capacitors C1 - C N in the capacitor array of the Nbit DAC are all connected to VCOM, and the upper and lower plates of the unit capacitor C0 are both connected to VCOM. At the same time, the control logic circuit 12 generates a third digital code <DI N :DI1> and a fourth digital code <DO N :DO1> according to the first digital code and the second digital code generated by the previous stage circuit of the Nbit DAC within (A - 2)T cycles, so as to control the lower plates of the capacitors C1 - C N in the capacitor array 10 to be connected to the first reference voltage AVDD or the second reference voltage AVSS through the third digital code <DI N :DI1> or the fourth digital code <DO N :DO1>, thereby pre - charging the capacitor array 10, making the electric charge stored in the capacitor array 10 greater than 0, and since Ks is open at this time, the Nbit DAC does not output the electric charge Qadc to the outside. At this time, the total electric charge Q0 stored in the capacitor array 10 of the Nbit DAC is:

[0068]

[0069] When RST jumps to a low level and S0 jumps to a high level, K0 is open, Ks is closed, the Nbit DAC is in the output stage, and the upper plate of the unit capacitor C0 and the upper plates of the capacitors C1 - C N in the capacitor array of the Nbit DAC are all disconnected from VCOM. At the same time, the control logic circuit 12 still generates a third digital code <DI N :DI1> and a fourth digital code <DO N :DO1> according to the first digital code and the second digital code generated by the previous stage circuit of the Nbit DAC within (A - 2)T cycles, so as to control the lower plates of the capacitors C1 - C N in the capacitor array 10 through the fourth digital code <DO N :DO1> or the third digital code <DI N The lower plate of the capacitor is connected to the first reference voltage AVDD or the second reference voltage AVSS. Among them, for the capacitor whose lower plate is connected to AVDD during the reset stage, its lower plate is changed to be connected to AVSS during the output stage, and for the capacitor whose lower plate is connected to AVSS during the reset stage, its lower plate is changed to be connected to AVDD during the output stage, so that the amount of charge stored in the capacitor array 10 changes relative to the reset stage. And since Ks is closed at this time, the Nbit DAC will output an amount of charge Qadc to the outside. At this time, the total amount of charge Q1 stored in the capacitor array 10 of the Nbit DAC is:

[0070]

[0071] At this time, the Qadc output by the Nbit DAC = Q0 - Q1, that is, the difference between the amount of charge Q1 stored in the capacitor array 10 during the output stage and the amount of charge Q0 stored in the capacitor array 10 during the reset stage (that is, the change value of the stored charge amount).

[0072] When VCOM = (AVDD - AVSS) / 2 (that is, the common reference voltage VCOM is half of the difference between the first reference voltage AVDD and the second reference voltage AVSS), for example, when AVDD = 2*VCOM and AVSS = 0V, the amount of charge Qadc output by the Nbit DAC in this embodiment is Figure 1 twice that of the amount of charge Qadc output by the traditional Nbit DAC shown.

[0073] For example, please refer to Figure 2A (or Figure 2B ), Figure 4 and Figure 5 , for the i-th capacitor C i in the capacitor array 10, if the first digital code D i generated within the period of (A - 2)T is 0, VCOM = AVDD / 2 > 0V, AVSS = 0V, then within the period of (A - 1)T, during the stage when RST is at a high level and S0 is at a low level (that is, the reset stage of the Nbit DAC), the upper plate of C i is connected to VCOM, and the lower plate is connected to AVSS. The amount of charge stored between the upper and lower plates of C i is (VCOM - AVSS)*C i = VCOM*C i . And during the stage when RST is at a low level and S0 is at a high level (that is, the output stage of the Nbit DAC), the lower plate of C i is connected to AVDD. The amount of charge stored between the upper and lower plates of C i is (VCOM - AVDD)*C i . The change value of the amount of charge stored in C i relative to the amount of charge stored during the previous reset stage is VCOM*C i -(VCOM - AVDD)*C i = AVDD*C i = 2*VCOM*C i That is to say, when AVDD > 0 and AVSS = 0, for any capacitor C in the capacitor array 10 i the change value of the stored charge amount in the output stage relative to the stored charge amount in the reset stage is the capacitance value C i of this capacitor C i multiplied by the first reference voltage AVDD.

[0074] And Figure 1 in the Nbit DAC shown, for C i in the reset stage, since the lower plate is connected to VCOM, the stored charge amount is 0, while in the output stage C i even if the stored charge amount is (VCOM - AVDD)*C i the change value of its charge amount is 0 - (VCOM - AVDD)*C i = VCOM*C i i .

[0075] Obviously, the change value of the charge amount of C i in this embodiment is 1 time larger than Figure 1 the change value of the charge amount of C i in the Nbit DAC shown. This shows that the Nbit DAC solution of the present invention can greatly increase the charge amount that can be provided in the output stage compared with the traditional Nbit DAC. And because the charge amount that the Nbit DAC of the present invention can provide in the output stage can be greatly increased compared with the traditional solution, the capacitor array in the Nbit DAC of the present invention can have a smaller area than the capacitor array in the traditional solution under the same signal conditions. Of course, in other embodiments of the present invention, AVDD, VCOM, and AVSS can also take other values to make the Nbit DAC output a higher charge amount relative to the traditional solution, and the present invention does not make specific limitations on this.

[0076] The digital - to - analog converter of the present invention can be applied to analog - to - digital converters, touch chips, and related electronic devices, and its application range can be wider than that of traditional solutions.

[0077] Please refer to Figure 6 ​Based on the same inventive concept, an embodiment of the present invention further provides an analog-to-digital converter 21 (Analog-to-Digital Converter), which has the digital-to-analog converter Nbit DAC described in the present invention, so the analog-to-digital converter 21 can be a first-order Nbit delta sigma ADC (i.e., a first-order Nbit⊿-∑ADC).

[0078] In this embodiment, the analog-to-digital converter 21 further includes an integrator INT, an analog-to-digital conversion circuit Nbit ADC and a digital filter DF (Digital Filter). The negative input terminal of the integrator INT (i.e. Figure 6 The negative input terminal "-" of the adder U0 in the embodiment is coupled to the output terminal of the N-bit DAC, and the positive input terminal of the integrator INT (i.e. Figure 6 The positive input terminal "+" of the adder U0 in the integrator receives the analog input charge Qsig (also referred to as the analog input signal), the output terminal of the integrator INT is coupled to the input terminal of the analog-to-digital conversion circuit Nbit ADC, and the output terminal of the analog-to-digital conversion circuit Nbit ADC is coupled to the input terminal of the Nbit DAC. The integrator INT is used to subtract a reference from the analog input charge Qsig according to the charge Qadc output by the Nbit DAC to output an analog signal after subtracting the reference (i.e., the input charge after subtracting the reference) Qin, and the analog-to-digital conversion circuit Nbit ADC is used to quantize and convert the analog signal Qin output by the integrator INT into a corresponding digital code signal, and the digital code signal includes a first digital code <D N :D1> and the second digit code To provide it to the digital-to-analog converter Nbit DAC and the digital filter DF.

[0079] The input end of the digital filter DF is coupled to the output end of the analog-to-digital conversion circuit Nbit ADC, and the digital filter DF is used to filter out the first digital code <D N :D1> and the second digit code The high frequency components in .

[0080] It should be understood that the integrator INT, the analog-to-digital conversion circuit Nbit ADC and the digital filter DF in the analog-to-digital converter 21 can be implemented by any suitable circuit design, and the present invention does not make any specific limitation to this.

[0081] As an example, the digital filter DF may be a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter, which is not specifically limited in the present invention. The digital filter DF outputs a digital signal DOUT <j:0>, where J + 1 > N. For example, J + 1 = 12 and N = 6 - 8.

[0082] As an example, please refer to Figure 6 , the integrator INT includes an adder U0, an operational amplifier Int_OP, an integration capacitor Cfb, and an integration switch Int_RST. One end of the integration capacitor Cfb and one end of the integration switch Int_RST are both coupled to the negative input terminal "-" of the operational amplifier Int_OP and the output terminal of the adder U0. The other end of the integration capacitor Cfb and the other end of the integration switch Int_RST are both coupled to the output terminal of the operational amplifier Int_OP and the input terminal of the analog-to-digital conversion circuit Nbit ADC. The negative input terminal "-" of the adder U0 is coupled to the output terminal of the digital-to-analog converter Nbit DAC, and the positive input terminal "+" of the adder U0 is coupled to the analog input charge amount Qsig.

[0083] The analog-to-digital conversion circuit Nbit ADC quantizes the output Vout of the integrator INT, that is, converts the analog signal Qin into a first digital code <D N :D1> and a second digital code . The D here represents the quantized digital signal, corresponding to the least significant bit (LSB) to the most significant bit (MSB) respectively. If the quantization range of the analog-to-digital conversion circuit Nbit ADC is Vref and there are a total of N bits, that is, 2 N values, corresponding to <00…0> (corresponding to the least significant bit) to <11…1> (corresponding to the most significant bit) respectively, then LSB = Vref / 2 N , MSB = Vref * (2 N - 1) / 2 N .

[0084] The function of the N-bit ADC in the analog-to-digital conversion circuit can be simply understood as converting the analog signal vout output by the integrator INT into a digital code, while the function of the N-bit DAC in the digital-to-analog converter can be simply understood as converting the digital code output by the N-bit ADC in the analog-to-digital conversion circuit back into an analog signal output. That is, the Qadc output by the N-bit DAC is the feedback of the previous input of the N-bit ADC (i.e., the analog signal vout), and it is also the feedback of the Qsig of the previous input of the integrator INT. Suppose that at the first operation, the N-bit DAC has not generated feedback yet. After the first input analog input charge amount (i.e., the first analog signal) Qsig is processed by the integrator INT and then quantized by the N-bit ADC in the analog-to-digital conversion circuit, the first set of digital codes is output. When the Qsig is input to the integrator INT for the second time, the N-bit DAC receives the first set of digital codes and converts them into the Qadc of the first feedback (which is approximately equal to the first input Qsig). The integrator INT subtracts the Qadc of the first feedback from the Qsig input for the second time. This difference is very small and almost equal to zero, that is, the analog signal vout output by the integrator INT is superimposed with a very small difference. After the second quantization by the N-bit ADC, the second set of digital codes is output, and so on, realizing the function that the output of the N-bit ADC tracks the input of the integrator INT. At this time, the output switch Ks in the N-bit DAC is a feedback switch, and when it is closed, it can feedback the Qadc to the negative input terminal of the integrator INT.

[0085] The analog-to-digital converter 21 can perform oversampling on the analog input charge amount Qsig, and the oversampling rate is M. In this way, when the target accuracy is (J + 1)-bit accuracy, the number of bits N of the N-bit ADC in this analog-to-digital converter 21 does not have to be equal to (J + 1), and it can be less than (J + 1). The output of the analog-to-digital converter 21 after sampling and digital filtering can easily reach 12-bit accuracy. In this way, the design difficulty and area of the N-bit ADC in the analog-to-digital converter 21 can be greatly reduced, and the linearity requirements for the N-bit DAC are the same as those for the DAC in the analog-to-digital converter under the traditional structure. For example, when J = 11, the target accuracy is 12-bit, and N is equal to 6 to 8.

[0086] Please refer to Figure 5 and Figure 6 , the working principle of the analog-to-digital converter 21 in this embodiment is as follows: At the falling edge of S0, the N-bit ADC in the analog-to-digital conversion circuit quantizes the output Vout of the integrator INT at the current moment, and then generates the first digital code for reflecting the analog input charge amount Qsig received by the integrator INT at the current moment (i.e., Figure 5 In, the D1, D2,..., D corresponding to the arrow N ) and the second digital code, such that the N-bit DAC receives and feeds back in the next period the first digital code and the second digital code obtained by the N-bit ADC quantizing the analog input charge amount Qsig at the current moment. That is to say, in the (A-1)T period, the N-bit DAC receives and feeds back the first digital code and the second digital code obtained by the N-bit ADC quantizing Vout output by the integrator INT in the (A-2)T period, while in the (A)T period, the N-bit DAC receives and feeds back the first digital code and the second digital code obtained by the N-bit ADC quantizing Vout output by the integrator INT in the (A-1)T period.

[0087] Please refer to Figure 6 and Figure 7 , based on the same inventive concept, an embodiment of the present invention further provides a touch chip, which includes the analog-to-digital converter 21 as described in the present invention, and an analog front-end circuit AFE (Analog Front-end) coupled to the front end of the analog-to-digital converter 21. The analog front-end circuit AFE includes a charge and discharge circuit 20. The input end of the charge and discharge circuit 20 is coupled to a corresponding sensing channel (not marked), and the output end of the charge and discharge circuit 20 is coupled to the positive input end of the integrator INT of the analog-to-digital converter 21 (i.e., the positive input end of the adder U0). The charge and discharge circuit 20 is configured to convert an analog input signal (such as a self-capacitance or a mutual capacitance or a sensing voltage) generated on the sensing channel RX into an analog input charge amount Qsig for providing to the integrator INT.

[0088] The charge and discharge circuit 20 can be implemented by any suitable circuit design. As an example, the charge and discharge circuit 20 includes switches P1 to P3 and a current source I0. Among them, the switches P1 to P3 can be any suitable three-terminal switch elements, such as MOS transistors, bipolar transistors, etc. The control end of the switch P1 (such as the gate of the PMOS transistor) receives a control signal S1, the control end of the switch P2 (such as the gate of the PMOS transistor) receives a control signal S2, the control end of the switch P3 (such as the gate of the PMOS transistor) receives an output control signal S0. One end of the current source I0 is connected to a first power supply voltage AVSS (this voltage AVSS is an internal ground voltage, which can be different from the external ground voltage ground or 0V voltage), and the other end is coupled to one end of the switch P2 (such as the source of the PMOS transistor). The other end of the switch P2 (such as the drain of the PMOS transistor) is coupled to one end of the switch P1 and one end of the switch P3. The other end of the switch P3 serves as the output end of the charge and discharge circuit 20 to output the analog input charge amount Qsig, and the other end of the switch P1 is coupled to a common reference voltage VCOM.

[0089] After the integrator INT reset phase, switch P1 closes, switches P2 and P3 both open, and the analog input signal (such as a sensed voltage) on the sensing channel RX is strongly pulled to VCOM. After the integrator INNT reset ends, switch P1 opens, switches P2 and P3 close, and at the same time the transmit channel TX jumps high. The current source I0 can charge or discharge the sensing channel RX, thereby converting the analog input signal on the sensing channel RX into an analog input charge quantity Qsig for output. This Qsig is input to the integrator INNT and subtracted from the Qadc fed back by the DAC (i.e., subtracting the reference). The resulting Qin after subtracting the reference is converted by the integrator INT into Vout (which contains Qsig information), and the Nbit ADC quantizes Vout into a first digital code and a second digital code.

[0090] Based on the same inventive concept, please refer to Figure 7 , an embodiment of the present invention further provides an electronic device, which further includes a touch panel 30 and a touch chip 31 as described in the present invention. The touch panel 30 has a plurality of sensing channels, and the touch chip 31 is coupled to each of the sensing channels and is used to detect capacitance changes on the touch panel 30. The detection result of the touch chip 31 can be used to identify the position of a touch event on the touch panel 30 and determine the user's touch operation.

[0091] Among them, the touch panel 30 can be any touch panel such as an OLED touch screen, which has m longitudinally extending transmit channels TX<1> to TX <m>and n laterally extending sensing channels RX<1> to RX <n>, each intersection point of each transmission channel TX and each sensing channel RX is a sensing node, and the values of m and n both depend on the size and shape of the touch panel 30.

[0092] Since the human body is a conductor and is connected to the ground, both the self-capacitance and mutual capacitance of the sensing channel RX touched or approached by a finger will change. Therefore, the touch chip 31 can adopt these two capacitance detection methods of self-capacitance and mutual capacitance to detect the change of self-capacitance or mutual capacitance on the touch panel 30, and then calculate the touch position of the finger according to the change of the self-capacitance or mutual capacitance, so as to realize touch recognition on the touch panel 30.

[0093] Exemplarily, when performing self-capacitance detection, the touch chip 31 scans the change of the self-capacitance of each transmission channel TX and sensing channel RX to the ground. When a finger approaches or touches, the self-capacitance on the transmission channel TX and sensing channel RX near the finger will increase. When performing mutual-capacitance detection, the touch chip detects the change of the mutual capacitance between the transmission channel TX and the sensing channel RX. Among them, Figure 7 where Cm is the parasitic capacitance between the transmission channel TX and the sensing channel RX, and Cb is the parasitic capacitance between the cathode (Cathode) of the touch panel 30 and the sensing channel RX. Figure 6 The figure shows a mutual-capacitance detection method, where Csig represents the capacitance generated between the finger when touching the touch panel 30 and the sensing channel RX (that is, the capacitance component generated between the finger and the touch panel 30)

[0094] The working principle of the touch chip 31 is to judge whether the touch panel 30 is touched and the touch position by generating Csig when a finger touches the touch screen and Csig disappearing when the finger leaves the screen, and by scanning the change of the self-capacitance or mutual capacitance (that is, whether there is Csig) at each sensing node on the touch panel 30. In this embodiment, the touch chip 32 has an analog front-end circuit AFE and an analog-to-digital converter ADC arranged in one-to-one correspondence with the sensing channel RX, that is, the number of sensing channels RX is equal to the number of analog front-end circuits AFE and analog-to-digital converters ADC. However, in other embodiments of the present invention, the number of analog front-end circuits AFE can also be less than the number of sensing channels RX, and it is realized that multiple sensing channels RX share one analog front-end circuit AFE. And please refer to Figure 6 As shown, the change in self - capacitance or mutual - capacitance at each sensing node on the touch panel 30 can be converted into an analog input charge quantity Qsig by the charge - discharge circuit 20. Moreover, the analog input charge quantity Qsig when there is or is not a finger touch at each sensing node is different. Thus, the analog input charge quantity Qsig output by the charge - discharge circuit 20 contains finger information. This Qsig containing finger information is sent to the analog - to - digital converter of the present invention for quantization. Therefore, by quantifying the "difference" of Qsig, the magnitude of Csig can be judged, and thus it can be determined whether there is a touch.

[0095] For the analog - to - digital converter, touch chip, and electronic device of this embodiment, since the analog - to - digital converter of this embodiment is adopted, the area can be made smaller and the reliability can be higher.

[0096] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure fall within the protection scope of the technical solution of the present invention.< / n> < / m>

Claims

1. A digital-to-analog converter, characterized in that, Comprising: A control logic circuit, whose input end is coupled to a reset signal, an output control signal, a multi-bit first digital code, and a multi-bit second digital code, and is configured to generate a multi-bit third digital code and a multi-bit fourth digital code according to the reset signal, the output control signal, the first digital code, and the second digital code. Wherein, the second digital code is the inverse code of the first digital code, and the fourth digital code is the inverse code of the third digital code; A capacitor array, including a plurality of capacitors, and the upper plates of each capacitor are coupled to each other; A switch array, including a plurality of first switches and a plurality of second switches. One end of each of the first switches is coupled to a first reference voltage, one end of each of the second switches is coupled to a second reference voltage, and the other ends of each of the first switches and the other ends of each of the second switches are respectively coupled to the lower plates of each capacitor in the capacitor array. The control end of each of the first switches is coupled to the corresponding third digital code, and the control end of each of the second switches is coupled to the corresponding fourth digital code; Wherein, the third digital code or the fourth digital code is used to control the lower plates of the capacitors in the capacitor array to connect to the first reference voltage or the second reference voltage during the reset stage of the digital-to-analog converter, so that the electric charge stored in the capacitor array during the reset stage is greater than 0.

2. The digital-to-analog converter according to claim 1, wherein The fourth digital code or the third digital code is used to control the lower plates of each capacitor in the capacitor array to connect to the second reference voltage or the first reference voltage during the output stage of the digital-to-analog converter. And when the first reference voltage is greater than 0 and the second reference voltage is equal to 0, the change value of the corresponding capacitor in the capacitor array during the output stage relative to the electric charge stored during the reset stage is the product of the capacitance value of the capacitor and the first reference voltage.

3. The digital-to-analog converter according to claim 2, wherein The upper plates of each capacitor are coupled to a common reference voltage during the reset stage, and the common reference voltage is half of the difference between the first reference voltage and the second reference voltage.

4. The digital-to-analog converter according to claim 1 or 2, characterized in that, It further includes a reset switch and an output switch. The output end of the reset switch and the input end of the output switch are both coupled to the upper plates of each capacitor in the capacitor array. The input end of the reset switch is coupled to the common reference voltage, the control end of the reset switch is coupled to the reset signal, the control end of the output switch is coupled to the output control signal, and the output end of the output switch is directly used as or coupled to the output end of the digital-to-analog converter. The reset signal and the output control signal are two non-overlapping control signals; Wherein, during the reset stage of the digital-to-analog converter, the reset signal controls the reset switch to close, and the output control signal controls the output switch to open. During the output stage of the digital-to-analog converter, the reset signal controls the reset switch to open, and the output control signal controls the output switch to close.

5. The digital-to-analog converter according to claim 1, wherein The first digital code and the second digital code received by the control logic circuit in the current cycle are generated by the corresponding external circuit of the digital-to-analog converter in the previous cycle.

6. The digital-to-analog converter according to claim 1, wherein The capacitance values of the capacitors in the capacitor array are arranged in a binary weighted manner; and / or, the digital-to-analog converter further includes a unit capacitor, the lower plate of the unit capacitor is coupled to a common reference voltage, the upper plate of the unit capacitor is coupled to the upper plates of the capacitors in the capacitor array, and the capacitance values of the capacitors in the capacitor array are all binary multiples of the capacitance value of the unit capacitor.

7. The digital-to-analog converter according to any one of claims 1-3 or 5-6, characterized in that The capacitor array has N capacitors, and the control logic circuit includes N groups of logic circuits respectively corresponding to the N capacitors in the capacitor array. Each group of logic circuits includes: A first AND logic circuit, one input terminal is coupled to the reset signal, and the other input terminal is coupled to the corresponding first digital code; A second AND logic circuit, one input terminal is coupled to the output control signal, and the other input terminal is coupled to the corresponding second digital code; An OR logic circuit, one input terminal is coupled to the output terminal of the first AND logic circuit, and the other input terminal is coupled to the output terminal of the second AND logic circuit, and outputs the corresponding third digital code; An inverter, the input terminal is coupled to the output terminal of the OR logic circuit, and the output terminal of the inverter outputs the corresponding fourth digital code.

8. An analog-to-digital converter, characterized in that, Including: An integrator, an analog-to-digital conversion circuit, and a digital-to-analog converter according to any one of claims 1-7, wherein the negative input terminal of the integrator is coupled to the output terminal of the digital-to-analog converter, the positive input terminal of the integrator receives an analog input charge amount, the output terminal of the integrator is coupled to the input terminal of the analog-to-digital conversion circuit, and the output terminal of the analog-to-digital conversion circuit is coupled to the input terminal of the digital-to-analog converter; The integrator is configured to subtract a reference from the analog input charge amount according to the charge amount output by the digital-to-analog converter to output a corresponding analog signal, and the analog-to-digital conversion circuit is configured to quantize and convert the analog signal output by the integrator into a corresponding digital code signal, and the digital code signal includes a first digital code and a second digital code, and is provided to the digital-to-analog converter.

9. The analog-to-digital converter according to claim 8, wherein It further includes a digital filter, the input terminal is coupled to the output terminal of the analog-to-digital conversion circuit, and the digital filter is configured to filter out high-frequency components in the digital code signal.

10. The analog-to-digital converter according to claim 8, wherein, The integrator includes an adder, an operational amplifier, an integration capacitor, and an integration switch. One end of the integration capacitor and one end of the integration switch are both coupled to the negative input terminal of the operational amplifier and the output terminal of the adder, and the other end of the integration capacitor and the other end of the integration switch are both coupled to the output terminal of the operational amplifier and the input terminal of the analog-to-digital conversion circuit. The negative input terminal of the adder is coupled to the output terminal of the digital-to-analog converter, and the positive input terminal of the adder is coupled to the analog input charge amount.

11. A touch chip, characterized in that, Including an analog-to-digital converter according to any one of claims 8-10.

12. The touch control chip according to claim 11, wherein It further includes an analog front-end circuit coupled to the front end of the analog-to-digital converter. The analog front-end circuit includes a charge and discharge circuit, its input terminal is coupled to a corresponding sensing channel, and its output terminal is coupled to the positive input terminal of the integrator of the analog-to-digital converter. The charge and discharge circuit is configured to convert the analog input signal generated on the sensing channel into an analog input charge amount and provide it to the integrator.

13. An electronic device, characterized in that, Comprising a touch panel and a touch chip as described in claim 11 or 12, the touch panel having a plurality of sensing channels, and the touch chip being coupled to each of the sensing channels.

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