VDMOS power chip preparation method

Abstract

The invention discloses a VDMOS power chip preparation method, and belongs to the field of power semiconductor devices. Manufacturing a groove on the epitaxial layer of the silicon substrate; depositing a field oxygen medium and a source polycrystal in the groove; performing P-well general injection on the surface; carrying out photoetching corrosion on the source polycrystal in the groove and growing a gate oxide medium and a gate polycrystal; performing source region injection on the device; depositing a dielectric layer to completely cover as an isolation layer, manufacturing a contact hole, performing body region injection in the contact hole, and completing metal contact lead-out; manufacturing a front metal and a passivation layer medium on the whole surface; and a cooling fin and drain terminal metal are manufactured on the back surface, and manufacturing of the whole VDMOS power chip applied to the high computing power is completed. The power consumption efficiency of the chip is effectively improved, and the working heat consumption is reduced; meanwhile, the radiating fin further increases the metal contact area of the drain terminal, reduces the contact resistance of the drain terminal, eliminates the stress of the high chip, improves the high reliability of the chip, and facilitates the miniaturization, low cost and large scale of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and particularly to a method for fabricating a VDMOS power chip. Background Art

[0002] In recent years, with the rapid advancement of data center construction, the demand for power semiconductors has been continuously increasing. The surging power demand of data centers has driven continuous technological upgrades. At the same time, the popularization of AI servers has caused the power demand per single rack to soar from 30 kW to over 100 kW, posing higher requirements for the efficiency and stability of the power supply system.

[0003] Since silicon power devices are widely used in power supply systems and continuously challenge extreme working conditions. There are bottlenecks in terms of working frequency, power, heat resistance temperature, energy efficiency, resistance to harsh environments, and miniaturization. The third-generation semiconductors represented by gallium nitride and silicon carbide exhibit superior physical properties in terms of thermal conductivity, frequency conversion, high-temperature working characteristics, etc. However, whether it is silicon-based power devices or broadband compound semiconductor power devices, thermal design is essential in the process of power device design. Especially in the thermal design of the internal structure of the chip, excellent chip thermal design can fundamentally solve the thermal power consumption of the power chip, thereby getting rid of the constraints and restrictions on package thermal design and case thermal design, and greatly improving the thermal efficiency and application scenarios of the power chip.

[0004] Therefore, data centers are urgently in need of power chips that can efficiently convert electrical energy to reduce costs and emissions. At the same time, higher power conversion efficiency also means less heat generation, thereby reducing the cooling cost. Advanced power semiconductor technologies play a key role in the power conversion and distribution of data centers, making it possible to meet these requirements.

[0005] The current shield-gate VDMOS power chip device is one of the newest device types applied in power supplies, but there are still certain restrictions in terms of heat dissipation performance, especially in the case of high-power small-area chips. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for fabricating a VDMOS power chip to solve the problems in the background art.

[0007] To solve the above technical problems, the present invention provides a method for fabricating a VDMOS power chip, including the following steps:

[0008] Step S11, fabricating a trench on the epitaxial layer of a silicon substrate;

[0009] Step S12, depositing field oxide dielectric and source polycrystal in the trench;

[0010] Step S13, performing P-well general implantation on the surface;

[0011] Step S14: Perform photolithography etching on the source polycrystal in the trench and grow gate oxide dielectric and gate polycrystal.

[0012] Step S15: Inject into the source region of the device.

[0013] Step S16: Deposit a dielectric layer to fully cover it as an isolation layer, fabricate contact holes, perform body region injection in the contact holes, and complete metal contact lead-out.

[0014] Step S17: Fabricate front-side metal and passivation layer dielectric on the entire surface.

[0015] Step S18: Fabricate a heat sink and drain-end metal on the back side to complete the fabrication of the entire high-computing-power VDMOS power chip.

[0016] In one embodiment, the depth of the trench is 1 μm to 5 μm, the width is 0.1 μm to 0.5 μm, and the inclination angle and bottom topography of the trench are well controlled.

[0017] In one embodiment, depositing field oxide dielectric and source polycrystal in the trench includes: growing SiO2 dielectric field oxide on the sidewalls and bottom of the trench, depositing source polycrystal to fill the trench, and removing the excess source polycrystal on the surface.

[0018] In one embodiment, the thickness of the field oxide dielectric is 100 nm to 600 nm, and the thickness of the source polycrystal is 0.5 μm to 1.0 μm.

[0019] In one embodiment, performing P-well general injection on the surface includes: performing P-well injection fabrication in the cell region and terminals of the chip, the implanted impurity being one or more combinations of B / BF2 / BF3, the implantation energy being 50 keV to 100 keV, and the implantation dose being 1E12 to 5E13.

[0020] In one embodiment, the thickness of the gate oxide dielectric is 30 nm to 60 nm, and the thickness of the gate polycrystal is 0.5 μm to 1.0 μm to form the gate control terminal of the chip.

[0021] In one embodiment, injecting into the source region of the device includes: injecting N-type impurities as one or more combinations of As / P, the implantation energy being 40 keV to 80 keV, and the implantation dose being 1E15 - 1E16.

[0022] In one embodiment, in step S16, the dielectric layer is grown by chemical deposition, and the thickness of the dielectric layer is 0.6 μm to 0.8 μm; the designed size of the contact hole is 150 nm to 300 nm, and the P-type impurity for body region implantation is one or a combination of B / BF2 / BF3, the implantation energy is 20 keV to 60 keV, and the implantation dose is 1E15 - 5E15.

[0023] In one embodiment, the thickness of the front metal is 4 μm to 6 μm, and the gate control terminal, source control terminal, and body control terminal of the chip are respectively led out from the contact hole for subsequent bonding; the thickness of the passivation layer dielectric is 0.5 μm to 1.0 μm, which completes device isolation and protection, where the passivation layer dielectric is SiO2, or SiO2 + Si3N4.

[0024] In one embodiment, the heat sink is a groove-type heat sink, with a width of 0.1 μm to 0.5 μm and a depth of 0.5 μm to 10 μm; the drain metal is TiNiAg evaporation plating, with a thickness of 0.1 μm to 2 μm.

[0025] The present invention provides a method for manufacturing a VDMOS power chip, which has the following beneficial effects:

[0026] (1) An innovative design of integrating a heat sink for a high-computing-power VDMOS power chip is proposed. Compared with ordinary high-power VDMOS power chips, the heat dissipation capacity of the high-computing-power VDMOS power chip is greatly improved; the contact area of the bottom drain terminal control end is increased, effectively reducing the contact resistance; at the same time, the stress of the high-computing-power VDMOS power chip is eliminated, improving the high-reliability performance of the high-computing-power VDMOS power chip;

[0027] (2) No new process manufacturing procedures are introduced, and the manufacturing adopts conventional methods, which are simple, effective, and operable. Description of the Drawings

[0028] Figure 1 is a schematic flow chart of a method for manufacturing a VDMOS power chip provided by the present invention;

[0029] Figure 2 is a schematic diagram of fabricating a trench on the epitaxy of a substrate;

[0030] Figure 3 is a schematic diagram of depositing field oxide dielectric and source polycrystal in the trench;

[0031] Figure 4 is a schematic diagram of fabricating a general P-well;

[0032] Figure 5 is a schematic diagram of photolithography and etching of source polycrystal, growth of gate oxide dielectric, and gate polycrystal;

[0033] Figure 6 It is a schematic diagram of fabricating the source region N+ lithography and implantation;

[0034] Figure 7 It is a schematic diagram of fabricating the contact holes and the body region P+ implantation;

[0035] Figure 8 It is a schematic diagram of fabricating the metal and the passivation layer dielectric;

[0036] Figure 9 It is a schematic diagram of fabricating the back integrated heat sink and the drain terminal metal. Detailed implementation manners

[0037] The following further elaborates in detail on a method for fabricating a VDMOS power chip proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0038] The present invention provides a method for fabricating a VDMOS power chip, and its process is as Figure 1 shown, including the following steps:

[0039] Step S11: Fabricate trenches on the epitaxial layer of the silicon substrate;

[0040] Step S12: Deposit field oxide dielectric and source polycrystal in the trenches;

[0041] Step S13: Perform P-well general implantation on the surface;

[0042] Step S14: Perform photolithography etching on the source polycrystal in the trenches and grow gate oxide dielectric and gate polycrystal;

[0043] Step S15: Perform source region implantation on the device;

[0044] Step S16: Deposit a dielectric layer as an isolation layer, fabricate contact holes, perform body region implantation in the contact holes, and complete metal contact leads;

[0045] Step S17: Fabricate front metal and passivation layer dielectric on the entire surface;

[0046] Step S18: Fabricate a heat sink and a drain terminal metal on the back to complete the fabrication of the entire VDMOS power chip applied to high computing power.

[0047] The specific process steps are as follows:

[0048] First, provide a Si substrate 1 (N+SUB), prepare an epitaxial layer 2 (N-EPI) on its surface, fabricate a trench 3 (Trench) on the epitaxial layer 2 (N-EPI), the depth of the trench 3 is in the range of 1 μm to 5 μm, and the width is in the range of 0.1 μm to 0.5 μm. Control the tilt angle and bottom topography of the trench 3, such as Figure 2 shown is a cross-sectional schematic diagram of the completion of this step;

[0049] Complete the field oxide SiO2 dielectric 4 (Field Oxide) on the side and bottom of the trench 3, with a thickness of 100 nm to 600 nm; deposit source polycrystal 5 (S-Poly) in the trench 3, with a deposition thickness in the range of 0.5 μm to 1.0 μm, fill the trench 3, and remove the excess source polycrystal 5, such as Figure 3 shown is a cross-sectional schematic diagram after the completion of this step;

[0050] Conduct a general implantation design of a P well 6 (Pwell) on the surface. The implanted impurities of the P well 6 are one or more combinations of P-type impurities such as B / BF2 / BF3, etc. The implantation energy of the P well 6 is 50 keV to 100 keV, and the implantation dose is 1E12 to 5E13, forming the cell area Cell and the terminal Terminal at one time, such as Figure 4 shown is a cross-sectional schematic diagram after the completion of this step;

[0051] Perform photolithography and etching on the source polycrystal 5 in the trench 3 in the cell area Cell to form the cell area Cell and the terminal Terminal of the high-computing power VDMOS power chip. Grow a gate oxide SiO2 dielectric 7 (GateOxide) in the trench 3 that has undergone photolithography and etching, and deposit and etch the control area of the gate polycrystal 8 (G-Poly) to form the device gate control terminal, which plays a switching control role for the high-computing power VDMOS power chip; the thickness of the gate oxide SiO2 dielectric 7 is 30 nm to 60 nm; the thickness of the gate polycrystal 8 is 0.5 μm to 1.0 μm. The gate oxide SiO2 dielectric 7 and the field oxide SiO2 dielectric 4 are made of the same material, and the gate polycrystal 8 and the source polycrystal 5 are made of the same material; such as Figure 5 shown is a cross-sectional schematic diagram after the completion of this step;

[0052] Perform source region 9 (N+) implantation on the device, with impurities being As / P, an implantation energy of 40 keV to 80 keV, and an implantation dose of 1E15 - 1E16, such as Figure 6 shown is a cross-sectional schematic diagram after the completion of this step;

[0053] The deposited SiO2 dielectric layer 10 serves as an isolation layer, and the thickness of the SiO2 dielectric layer 10 is 0.6 μm to 0.8 μm. Contact holes are fabricated with a designed size of 150 nm to 300 nm. Impurities B / BF2 / BF3 of the body region 11 (P+) are implanted into the contact holes to form the contact function of the body control terminal of the high-computing power VDMOS power chip. The implantation energy is 20 keV to 60 keV, and the implantation dose is 1E15 - 5E15. Then, tungsten plugs 12 (W) are formed to make metal contacts and lead-outs. The contact holes formed by the tungsten plugs 12 are used to contact the source control terminal and the body control terminal through the metal layer; among them, the body region 11 is in contact with the source region 9, as Figure 7 shown in the cross-sectional schematic diagram after completing this step;

[0054] Metal 13 (Metal) is fabricated on the entire surface with a thickness of 4 μm to 6 μm. The gate control terminal, source control terminal, and body control terminal of the high-computing power VDMOS power chip are respectively led out from the contact holes for subsequent bonding; at the same time, a passivation dielectric 14 (Passivation) is deposited with a thickness of 0.5 μm to 1.0 μm to complete device isolation and protection, as Figure 8 shown in the cross-sectional schematic diagram;

[0055] After completing the fabrication of the front-side high-computing power chip, a grooved heatspreader 15 is fabricated on the back side with a width of 0.1 μm to 0.5 μm and a depth of 0.5 μm to 10 μm. On the one hand, this grooved heatspreader can effectively discharge a large amount of heat generated during the operation of the high-computing power VDMOS power chip, thereby improving the performance and reliability of the high-computing power VDMOS power chip; on the other hand, the integrated grooved heatspreader can effectively release the stress caused by the ultra-thick metal of the power chip. Especially in the P-type VDMOS power chip, it eliminates the chips of the VDMOS power chip;

[0056] Finally, a drain metal 16 (TiNiAg) is evaporated on the back side of the wafer with a thickness of 0.1 μm to 2 μm to complete the fabrication of the entire high-computing power VDMOS power chip.

[0057] The design method of the present invention realizes the monolithic integration of the heat sink for the high-computing power VDMOS chip, effectively improves the power consumption efficiency of the high-computing power VDMOS power chip, and reduces the working heat dissipation; at the same time, the heat sink design further increases the metal contact area at the drain end, reduces the drain end contact resistance, eliminates the chip stress, improves the chip reliability, and is conducive to the miniaturization, low-cost, and large-scale production of the chip. The present invention can achieve the monolithic integration of the high-computing power VDMOS power chip without adding any new process steps.

[0058] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A method for preparing a VDMOS power chip, characterized in that, It includes the following steps: Step S11: Fabricate trenches on the epitaxial layer of the silicon substrate; Step S12: Deposit field oxide dielectric and source polycrystal in the trenches; Step S13: Perform P-well general implantation on the surface; Step S14: Lithographically etch the source polycrystal in the trenches and grow gate oxide dielectric and gate polycrystal; Step S15: Perform source region implantation on the device; Step S16: Deposit a dielectric layer to completely cover it as an isolation layer, fabricate contact holes, perform body region implantation in the contact holes, and complete metal contact lead-out; Step S17: Fabricate front-side metal and passivation layer dielectric on the entire surface; Step S18: Fabricate a heat sink and drain-end metal on the back side to complete the fabrication of the entire high-computing-power VDMOS power chip.

2. The method for manufacturing a VDMOS power chip according to claim 1, wherein, The depth of the trenches is 1μm - 5μm, the width is 0.1μm - 0.5μm, and the tilt angle and bottom topography of the trenches are well controlled.

3. The manufacturing method of the VDMOS power chip according to claim 1, wherein The depositing field oxide dielectric and source polycrystal in the trenches includes: growing SiO2 dielectric field oxide on the sidewalls and bottom of the trenches, depositing source polycrystal to fill the trenches, and removing the excess source polycrystal on the surface.

4. The method for fabricating a VDMOS power chip according to claim 3, wherein The thickness of the field oxide dielectric is 100nm - 600nm, and the thickness of the source polycrystal is 0.5μm - 1.0μm.

5. The preparation method of the VDMOS power chip according to claim 1, wherein The performing P-well general implantation on the surface includes: performing P-well implantation fabrication in the cell region and terminal of the chip, the implanted impurity being one or a combination of B / BF2 / BF3, the implantation energy being 50keV - 100keV, and the implantation dose being 1E12 - 5E13.

6. The method for manufacturing a VDMOS power chip according to claim 1, wherein, The thickness of the gate oxide dielectric is 30nm - 60nm, and the thickness of the gate polycrystal is 0.5μm - 1.0μm, forming the gate control terminal of the chip.

7. The method for manufacturing a VDMOS power chip as described in claim 1, wherein The performing source region implantation on the device includes: implanting N-type impurities as one or a combination of As / P, the implantation energy being 40keV - 80keV, and the implantation dose being 1E15 - 1E16.

8. The method for preparing a VDMOS power chip according to claim 1, wherein, In Step S16, the dielectric layer is grown by chemical deposition, the thickness of the dielectric layer is 0.6μm - 0.8μm; the designed size of the contact holes is 150nm - 300nm, the P-type impurity for body region implantation is one or a combination of B / BF2 / BF3, the implantation energy is 20keV - 60keV, and the implantation dose is 1E15 - 5E15.

9. The method for preparing a VDMOS power chip according to claim 1, wherein, The thickness of the front-side metal is 4μm - 6μm, leading out the gate control terminal, source control terminal, and body control terminal of the chip from the contact holes respectively for subsequent bonding; the thickness of the passivation layer dielectric is 0.5μm - 1.0μm, completing device isolation and protection, where the passivation layer dielectric is SiO2, or SiO2 + Si3N4.

10. The manufacturing method of the VDMOS power chip according to claim 1, characterized in that, The heat sink is a grooved heat sink, the width is 0.1μm - 0.5μm, and the depth is 0.5μm - 10μm; the drain metal is TiNiAg evaporation plating, and the thickness is 0.1μm - 2μm.

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