Semiconductor power device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor power device and a preparation method thereof, and the method comprises the steps: providing an N + substrate, forming a first epitaxial layer on the N + substrate, and forming a first P-type diffusion region on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, and forming a second P-type diffusion region on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, and forming a third P-type diffusion region on the third epitaxial layer; forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region into a whole; and forming a double-layer shield gate structure on the gate trench of the fourth epitaxial layer. On the premise of the same withstand voltage, the unit area conduction resistance of the semiconductor power device is reduced, and the conduction loss is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a semiconductor power device and a manufacturing method thereof. Background Art

[0002] In semiconductor manufacturing processes, the performance optimization of power semiconductor devices has become the core focus of technology research and development. Among them, the Shielded Gate Trench MOSFET (SGT-MOSFET for short) occupies an important position in medium and high voltage power conversion scenarios due to its low on-state loss, high switching speed, and excellent breakdown voltage characteristics. As a switching device, it is applied to motor drive systems, inverter systems, and power management systems in new energy electric vehicles, new photovoltaic power generation, energy-saving household appliances, etc., and is a core power control component. However, with the continuous improvement of the device efficiency requirements in application scenarios, how to reduce its on-state loss on the premise of maintaining the breakdown voltage (BV) unchanged has become the key to the performance upgrade of SGT-MOSFET. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor power device and a manufacturing method thereof to reduce the on-state resistance per unit area of the semiconductor power device and the on-state loss on the premise of the same breakdown voltage.

[0004] In a first aspect, an embodiment of the present application discloses a manufacturing method of a semiconductor power device, including: Providing an N+ substrate; Forming a first epitaxial layer of the same doping type on the N+ substrate, after ion implantation of the first epitaxial layer, forming a first P-type diffusion region on the first epitaxial layer; Forming at least one second epitaxial layer on the first epitaxial layer, after ion implantation of the second epitaxial layer, forming a second P-type diffusion region on the second epitaxial layer; Forming at least one third epitaxial layer on the second epitaxial layer, after ion implantation of the third epitaxial layer, forming a third P-type diffusion region on the third epitaxial layer; Forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region into one body by high-temperature diffusion to form a functional diffusion region; Forming a plurality of gate trenches on the fourth epitaxial layer, and forming a double-layer shield gate structure on the gate trenches; Performing self-aligned ion implantation between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region; A contact hole region connected to the P-type body region is formed on the fourth epitaxial layer, and a source metal layer covering the contact hole region is formed, and a drain region is formed by forming a back metal on the N+ substrate.

[0005] In a possible example: when the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region are respectively formed, the ion implantation concentrations of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are the same.

[0006] In a possible example: the formation area of the first P-type diffusion region on the first epitaxial layer is S1, the formation area of the second P-type diffusion region on the second epitaxial layer is S2, and the formation area of the third P-type diffusion region on the third epitaxial layer is S3. Then, the vertical projections of S1, S2, and S3 in the direction from the fourth epitaxial layer to the N+ substrate are concentrically arranged and coincide with each other.

[0007] In a possible example: when the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region are respectively formed, the ion implantation doses of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are distributed in a stepped manner.

[0008] In a possible example: in the direction from the fourth epitaxial layer to the N+ substrate, the curve profiles of the side connections on the same side of the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region are normally distributed.

[0009] In a possible example: a double-layer shield gate structure is formed on the gate trench, including: A first trench oxide layer is formed on the bottom and side walls of the gate trench; A first polysilicon layer is deposited in the gate trench. The first polysilicon layer covers the first trench oxide layer. After etching back the first polysilicon layer from the top to the bottom of the gate trench to a first etching depth, the first trench oxide layer is continuously etched back to the first etching depth. Wherein, the etched-back first trench oxide layer is formed into a second trench oxide layer; A second polysilicon layer is deposited in the gate trench. The second polysilicon layer covers the first polysilicon layer and the second trench oxide layer, and the second polysilicon layer and the second trench oxide layer are etched back to a second etching depth; A gate structure is formed in the gate trench.

[0010] In a possible example: forming a gate structure in the gate trench includes: A gate oxide layer is formed in the gate trench. The gate oxide layer covers the second polysilicon layer and the side walls of the gate trench; Deposit a gate polysilicon layer in the gate trench; After etching back the gate polysilicon layer to below the top surface of the fourth epitaxial layer, continue to form the gate oxide layer flush with the top surface of the fourth epitaxial layer on the gate polysilicon layer.

[0011] In a possible example: The functional diffusion region is formed in part of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer.

[0012] In a possible example: Forming a contact hole region connected to the P-type body region on the fourth epitaxial layer includes: Form a field oxide layer on the fourth epitaxial layer; Etch a contact hole through a contact hole mask on the field oxide layer, and the contact hole penetrates from the top surface of the fourth epitaxial layer into the P-type body region; Perform P++ ion implantation on the contact hole to form the contact hole region.

[0013] In a second aspect, an embodiment of the present application discloses a semiconductor power device prepared by the semiconductor power device preparation method described in any of the above embodiments, including: An N+ substrate, a functional diffusion region, a double-layer shield gate structure, a P-type body region, an N+ source region, a contact hole region, a source metal layer, and a drain region; A first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer are sequentially stacked on the N+ substrate; the functional diffusion region is connected in part of the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer, and a plurality of gate trenches are provided on the fourth epitaxial layer, and the double-layer shield gate structure is disposed in the gate trenches; The P-type body region is connected between adjacent gate trenches in the fourth epitaxial layer; The N+ source region is connected above the P-type body region in the fourth epitaxial layer; The contact hole region is disposed between adjacent gate trenches on the fourth epitaxial layer and is connected to the P-type body region; The source metal layer is disposed on the top surface of the fourth epitaxial layer and covers the contact hole region; The drain region is disposed on the bottom surface of the N+ substrate.

[0014] In summary, compared with the prior art, the present application discloses a semiconductor power device and a manufacturing method thereof, including: forming a first epitaxial layer of the same doping type on an N+ substrate, after ion implantation on the first epitaxial layer, forming a first P-type diffusion region on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, after ion implantation on the second epitaxial layer, forming a second P-type diffusion region on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, after ion implantation on the third epitaxial layer, forming a third P-type diffusion region on the third epitaxial layer; forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region into one body through high-temperature diffusion to form a functional diffusion region; forming a plurality of gate trenches on the fourth epitaxial layer, and forming a double-layer shield gate structure on the gate trenches; performing self-aligned ion implantation between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region; forming a contact hole region connected to the P-type body region and a source metal layer covering the contact hole region on the fourth epitaxial layer, and forming a drain region by back metallization of the N+ substrate. That is, through the above settings, the power device uses an N-type epitaxial layer with a higher concentration, reducing the on-resistance per unit area and the conduction loss of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 is a flowchart of the manufacturing method of the semiconductor power device according to the embodiment of the present application; Figure 2 is a schematic structural diagram of the first semiconductor power device according to the embodiment of the present application; Figure 3 is a schematic structural diagram of the second semiconductor power device according to the embodiment of the present application; Figure 4 is a schematic structural diagram of the third semiconductor power device according to the embodiment of the present application; Figure 5 is a schematic structural diagram of the fourth semiconductor power device according to the embodiment of the present application; Figure 6 is a schematic structural diagram of the fifth semiconductor power device according to the embodiment of the present application; Figure 7 is a schematic structural diagram of the sixth semiconductor power device according to the embodiment of the present application; Figure 8 is a schematic structural diagram of the seventh semiconductor power device according to the embodiment of the present application; Figure 9 It is a schematic structural diagram of the 8th semiconductor power device according to an embodiment of the present application; Figure 10 It is a sub - flow chart of the method for manufacturing a semiconductor power device according to an embodiment of the present application. Detailed implementation manners

[0017] Here, exemplary embodiments will be described in detail, and examples are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element. In addition, components, features, elements with the same name in different embodiments of the present application may have the same meaning or may have different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0019] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] In subsequent descriptions, suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of explaining the present application, and they have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0021] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0022] The technical solution shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0023] Please refer to Figure 1 and in combination with Figures 2 to 9 The method for manufacturing a semiconductor power device according to an embodiment of the present application includes: S101, providing an N+ substrate 1.

[0024] In a possible implementation manner of the present application, referring to Figure 2 , the material for forming the N+ substrate 1 can be single-crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, etc. The material of the N+ substrate 1 can also be a SiGe substrate, a group III-V element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates well-known to those skilled in the art. For example, P atoms can be implanted into single-crystalline silicon to form an N-type conductive semiconductor substrate, so as to improve the material selectivity and adaptability to the actual production environment.

[0025] In one example, several cell regions can be defined on the N+ substrate 1 to include a large number of repeated basic units of the semiconductor power device. Then, the gate trenches on the N+ substrate 1 can be regarded as cell trenches.

[0026] S102, forming a first epitaxial layer 21 of the same doping type on the N+ substrate 1. After ion implantation of the first epitaxial layer 21, a first P-type diffusion region 31 is formed on the first epitaxial layer 21.

[0027] In a possible implementation manner of the present application, referring to Figures 2 to 4 , through an epitaxial growth process, a first epitaxial layer 21 is formed on the N+ substrate 1. The first epitaxial layer 21 has the same N-type doping as the N+ substrate 1. After the formation of the first epitaxial layer 21, a P-type ion implantation process is performed on it to form a first P-type diffusion region 31.

[0028] S103, forming at least one second epitaxial layer 22 on the first epitaxial layer 21. After ion implantation of the second epitaxial layer 22, a second P-type diffusion region 32 is formed on the second epitaxial layer 22.

[0029] In a possible implementation manner of the present application, referring to Figure 3 and Figure 4 , through an epitaxial growth process, at least one second epitaxial layer 22 is formed on the first epitaxial layer 21. The second epitaxial layer 22 has the same N-type doping as the first epitaxial layer 21. After the formation of the second epitaxial layer 22, a P-type ion implantation process is performed on it to form a second P-type diffusion region 32.

[0030] It can be understood that according to the device design requirements or specific application environment needs, the second epitaxial layer 22 can be set to one layer or multiple layers.

[0031] S104, form at least one third epitaxial layer 23 on the second epitaxial layer 22. After ion implantation on the third epitaxial layer 23, form a third P-type diffusion region 33 on the third epitaxial layer 23.

[0032] In a possible implementation manner of this application, refer to Figure 3 and Figure 4 , through the epitaxial growth process, form at least one third epitaxial layer 23 on the second epitaxial layer 22. The third epitaxial layer 23 has the same N-type doping as the second epitaxial layer 22. After the formation of the third epitaxial layer 23, perform a P-type ion implantation process on it to form a third P-type diffusion region 33.

[0033] It can be understood that according to the device design requirements or specific application environment needs, the third epitaxial layer 23 can be set to one layer or multiple layers.

[0034] S105, form a fourth epitaxial layer 24 on the third epitaxial layer 23, and connect the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 into one body through high-temperature diffusion to form a functional diffusion region 3.

[0035] In a possible implementation manner of this application, refer to Figure 3 and Figure 4 , through the epitaxial growth process, form a fourth epitaxial layer 24 on the third epitaxial layer 23. The fourth epitaxial layer 24 has the same N-type doping as the third epitaxial layer 23, that is, the doping types of the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24 are the same, and they are sequentially stacked on the N+ substrate 1 through the epitaxial growth process, thereby ensuring crystal continuity and material interface quality.

[0036] And, after the formation of the fourth epitaxial layer 24, adopt the high-temperature diffusion process to diffusely connect the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 previously formed in the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 respectively to form an integrated functional diffusion region 3. Then the functional diffusion region 3 is formed in part of the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24, that is, the functional diffusion region 3 penetrates the second epitaxial layer 22 and the third epitaxial layer 23 in the vertical direction from the fourth epitaxial layer 24 to the N+ substrate 1 in the power device structure, and extends to the upper part of the first epitaxial layer 21 and the lower part of the fourth epitaxial layer 24.

[0037] In one example, the functional diffusion regions 3 may be spherically distributed in the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24.

[0038] Thus, through the functional diffusion regions 3 in the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24, the electric field distribution of each epitaxial layer can be effectively adjusted to endow the power device with higher breakdown voltage and optimized breakdown characteristics. That is, the functional diffusion regions 3 enable each epitaxial layer to have a higher concentration of ion doping, equivalently increasing the breakdown voltage and reducing the on-resistance per unit area of the power device, thereby reducing its conduction loss.

[0039] In one example, the high-temperature diffusion process includes a thermal annealing furnace or a rapid thermal processing process, which is carried out in an inert atmosphere (such as nitrogen or argon) or an oxidizing atmosphere. The high-temperature conditions include 1000 °C to 1150 °C, and the high-temperature diffusion time includes 30 min to 90 min to form continuous functional diffusion regions 3 in each epitaxial layer.

[0040] In one example, when forming the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 respectively, the ion implantation concentrations for the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 are the same.

[0041] That is, in order to form continuous and electrically consistent functional diffusion regions 3, during the processes of forming the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 respectively, the same ion implantation process parameters are adopted to ensure that each diffusion region in each epitaxial layer has the same doping concentration and electrical characteristics.

[0042] Specifically, when performing ion implantation on the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 respectively, the same P-type doping ions are selected, such as boron ions B + , and the implantation energy and implantation dose are set to be consistent. For example, the implantation energy can be set to 60 keV, the implantation dose is set to 3×10¹³ ions / cm², and the implantation method can adopt a vertical implantation process to ensure good consistency of the doping distribution among the layers.

[0043] Thus, in the high-temperature diffusion step, the diffusion regions with consistent concentration are more likely to achieve continuous fusion in the vertical direction, avoiding the formation of high-resistance junctions or potential steps, thereby improving the structural integrity and conductive continuity of the functional diffusion regions 3. Moreover, the consistent charge concentration of the three-layer diffusion regions enables the overall functional diffusion regions 3 to establish a stable and uniform electric field regulation region longitudinally in the epitaxial layer, which helps to increase the breakdown voltage of the power device and relieve the electric field concentration under the trench.

[0044] Among them, the formation area of the first P-type diffusion region 31 on the first epitaxial layer 21 is S1, the formation area of the second P-type diffusion region 32 on the second epitaxial layer 22 is S2, and the formation area of the third P-type diffusion region 33 on the third epitaxial layer 23 is S3. Then, the vertical projections of S1, S2, and S3 in the direction from the fourth epitaxial layer 24 to the N+ substrate 1 are concentrically arranged and coincide with each other.

[0045] Thus, the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 form a vertically stacked and longitudinally corresponding structure, arranged vertically within the depth range from the fourth epitaxial layer 24 to the N+ substrate 1. This helps to achieve effective vertical fusion of the three diffusion regions during the high-temperature diffusion process, avoid the formation of lateral deviations or diffusion dead zones, ensure the integrity and symmetry of the functional diffusion region 3, and the symmetric distribution along the depth direction of the power device can establish a uniform electric field gradient under the gate trench 11, reduce the electric field concentration effect, and improve the breakdown voltage withstand performance of the power device.

[0046] In a possible implementation manner of the present application, when forming the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 respectively, the ion implantation doses for the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 are distributed in a stepped manner.

[0047] Specifically, when forming the first P-type diffusion region 31 in the first epitaxial layer 21, the applied ion implantation dose is set to D1. When forming the second P-type diffusion region 32 in the second epitaxial layer 22, the ion implantation dose is set to D2. When forming the third P-type diffusion region 33 in the third epitaxial layer 23, the ion implantation dose is set to D3. Then, D1 > D2 > D3, forming a doping concentration gradient that decreases layer by layer from bottom to top to constitute a P-type doping stepped distribution structure in the vertical direction.

[0048] Optionally, D1 can be set to 5×10¹³ ions / cm², D2 to 3×10¹³ ions / cm², and D3 to 1×10¹³ ions / cm² to ensure that the diffusion depths of the first P-type diffusion region 31, the second P-type diffusion region 32, and the third P-type diffusion region 33 are similar but the concentration levels are distinct.

[0049] Thus, a relatively highly doped first P-type diffusion region 31 is formed opposite to the high-voltage end of the N+ substrate 1, so as to effectively suppress the electric field peak at its bottom, while the relatively low-doped second P-type diffusion region 32 and third P-type diffusion region 33 above form a transition region, thereby gradient-adjusting the electric field strength, improving the overall breakdown voltage performance of the power device, and the P-type doping step distribution structure can avoid obvious potential mutations at the diffusion region interface, thereby improving the consistency and stability of the breakdown voltage of the power device. Moreover, due to the gradually decreasing concentration, during the high-temperature diffusion process, the doping distribution is smoother, and the functional diffusion region 3 can form an extended structure with good continuity and controllable doping gradient in the vertical direction.

[0050] In one example, in the direction from the fourth epitaxial layer 24 to the N+ substrate 1, the curve profile of the side connection lines on the same side of the first P-type diffusion region 31, second P-type diffusion region 32 and third P-type diffusion region 33 is a normal distribution, so as to facilitate the fusion of the first epitaxial layer 21, second epitaxial layer 22 and third epitaxial layer 23 in the high-temperature diffusion process, and then form a continuous functional diffusion region 3.

[0051] S106. Form a plurality of gate trenches 11 on the fourth epitaxial layer 24, and form a double-layer shield gate structure 4 on the gate trenches 11.

[0052] In a possible implementation manner of the present application, continue to combine Figure 10 , and form a double-layer shield gate structure 4 on the gate trenches 11, including: S1061. Form a first trench oxide layer 41 on the bottom and side walls of the gate trench 11.

[0053] In one example, referring to Figures 4 to 6 , the first trench oxide layer 41 can be formed on the bottom and side walls of the gate trench 11 by a thermal oxidation process.

[0054] S1062. Deposit a first polysilicon layer 42 in the gate trench 11. The first polysilicon layer 42 covers the first trench oxide layer 41. After etching back the first polysilicon layer 42 from the top to the bottom of the gate trench 11 to a first etching depth, continue to etch back the first trench oxide layer 41 to the first etching depth. Among them, the etched-back first trench oxide layer 41 is formed into a second trench oxide layer 43.

[0055] In one example, mark the first etch-back depth as H1. After the first polysilicon layer 42 is etched back to the depth of H1, continue to etch back the first trench oxide layer 41 to the depth of H1. So that after the polysilicon layer is deposited in the trench, it has an appropriate depth to form an effective shielding structure in the gate trench 11, optimize the electric field distribution at the bottom and sidewalls of the gate trench 11, help reduce the on-resistance and improve the comprehensive performance of the device. That is, the etched-back first trench oxide layer 41 and the first polysilicon layer 42 construct the first layer of shield gate structure in the gate trench 11.

[0056] S1063, deposit a second polysilicon layer 44 in the gate trench 11. The second polysilicon layer 44 covers the first polysilicon layer 42 and the second trench oxide layer 43, and etch back the second polysilicon layer 44 and the second trench oxide layer 43 to the second etch-back depth.

[0057] In one example, referring to Figures 6 to 8 , mark the second etch-back depth as H2. Then the second polysilicon layer 44 and the second trench oxide layer 43 are etched back to the depth of H2. So that the second polysilicon layer 44 has an appropriate depth on the first layer of shield gate structure to form the second layer of shield gate structure in the gate trench 11, thereby constructing the double-layer shield gate structure 4 of the semiconductor power device, so as to reduce the on-resistance of the semiconductor power device and improve the comprehensive performance of the device.

[0058] Wherein, the second etch-back depth H2 < the first etch-back depth H1.

[0059] Then for the power device of the embodiment of the present application, a double-layer shield gate structure 4 is formed in the gate trench 11, that is, two independent polysilicon shield gates are arranged in the lower part of the gate trench 11. This kind of stacked structure design can "divide the voltage" more effectively, and form two gradient electric field shielding regions below the bottom of the gate trench 11. That is, through the electric field regulation effect of the double-layer shield gate structure 4, the electric field peak under the high-voltage operation of the power device can be effectively suppressed, and the maximum electric field intensity of the PN junction of the power device can be reduced, thereby improving the high breakdown voltage characteristic of the power device. And the double-layer shield gate structure 4 can also effectively reduce the direct electric field coupling path between the gate structure 5 and the drain region 10 in the subsequent embodiment, thereby reducing the parasitic gate-drain capacitance and improving the switching performance and dv / dt immunity of the power device.

[0060] It should be noted that the double-layer shield gate structure 4 not only optimizes the electric field below the gate trench 11, but also further covers the potential difference between the upper part of the gate trench 11 and the region outside the gate trench 11 to weaken the induction intensity of the body region of the power device on the drain electric field. Based on this effect, the fourth epitaxial layer 24 can use N-type epitaxial material with a higher doping concentration, which is beneficial to reducing the on-resistance of the epitaxial layer, thereby further reducing the total on-loss of the power device.

[0061] Thus, based on the dual cooperation of the functional diffusion region 3 and the double-layer shield gate structure 4, acting on the vertical drift region and the trench control region of the power device respectively, the voltage withstand capacity of the power device is ensured, the electric field distribution of each epitaxial layer is optimized, so that the doping concentration of the multi-layer N-type epitaxial structure can be comprehensively increased, while maintaining the voltage withstand performance of the power device, reducing the on-resistance per unit area of the power device and its conduction loss.

[0062] S1064, form a gate structure 5 in the gate trench 11.

[0063] In a possible implementation manner of the present application, combined with Figure 7 and Figure 8 , form a gate structure 5 in the gate trench 11, including: I. Form a gate oxide layer 51 in the gate trench 11, and the gate oxide layer 51 covers the second polysilicon layer 44 and the sidewall of the gate trench 11.

[0064] In an example, the second trench oxide layer 43 after being etched back continues to remain on the sidewall of the gate trench 11, which can be regarded as the gate oxide layer 51, and the gate oxide layer 51 covering the second polysilicon layer 44 can also be formed in the gate trench 11 through a thermal oxidation process.

[0065] II. Deposit a gate polysilicon layer 52 in the gate trench 11.

[0066] In an example, the gate polysilicon layer 52 covers the gate oxide layer 51, that is, the gate oxide layer 51 isolates the gate polysilicon layer 52 and the second polysilicon layer 44 in the gate trench 11.

[0067] III. After etching back the gate polysilicon layer 52 to below the top surface of the fourth epitaxial layer 24, continue to form a gate oxide layer 51 flush with the top surface of the fourth epitaxial layer 24 on the gate polysilicon layer 52. Thus, a gate structure 5 is formed in the gate trench 11.

[0068] S107, perform self-aligned ion implantation between adjacent gate trenches 11 on the fourth epitaxial layer 24 to form a P-type body region 6 and an N+ source region 7 located above the P-type body region 6.

[0069] In an example, referring to Figure 9 , perform self-aligned P-ion implantation between adjacent gate trenches 11 on the fourth epitaxial layer 24 to form a P-type body region 6, perform N+ ion implantation to form an N+ source region 7, and perform annealing to push the well, wherein the push-well junction depth of the P-type body region 6 is greater than the push-well junction depth of the N+ source region 7.

[0070] S108, form a contact hole region 8 connected to the P-type body region 6 and a source metal layer 9 covering the contact hole region 8 on the fourth epitaxial layer 24, and form a drain region 10 by back-golding the N+ substrate 1.

[0071] In a possible implementation of the present application, forming a contact hole region 8 connected to the P-type body region 6 on the fourth epitaxial layer 24 includes: forming a field oxide layer 12 on the fourth epitaxial layer 24; etching a contact hole 81 through a contact hole 81 mask on the field oxide layer 12, and the contact hole 81 penetrates from the top surface of the fourth epitaxial layer 24 into the P-type body region 6; performing P++ ion implantation on the contact hole 81 to form the contact hole region 8.

[0072] Wherein, the source metal layer 9 may include an alloy layer and a surface metal layer, and the alloy layer is deposited in the contact hole 81.

[0073] In addition, injecting P++ ions of the same ion implantation type as the P-type body region 6 into the contact hole 81 and annealing to push the well to form the contact hole region 8. Then, based on the contact hole 81 penetrating from the top surface of the fourth epitaxial layer 24 into the P-type body region 6, the P++ ions diffuse out of the contact hole region 8 in the P-type body region 6, and using the design that the concentration of P++ ions is greater than the ion concentration of the P-type body region 6, a graded junction is formed in the P-type body region 6 in the contact hole region 8, reducing the Schottky barrier.

[0074] The embodiment of the present application also discloses a semiconductor power device, which is prepared by the semiconductor power device preparation method of any of the above embodiments. Refer to Figure 9 , the semiconductor power device includes: an N+ substrate 1, a functional diffusion region 3, a double-layer shield gate structure 4, a P-type body region 6, an N+ source region 7, a contact hole region 8, a source metal layer 9, and a drain region 10.

[0075] In a possible implementation of the present application, a first epitaxial layer 21, a second epitaxial layer 22, a third epitaxial layer 23, and a fourth epitaxial layer 24 are sequentially stacked on the N+ substrate 1; the functional diffusion region 3 is connected to a part of the first epitaxial layer 21, the second epitaxial layer 22, the third epitaxial layer 23, and the fourth epitaxial layer 24, and several gate trenches 11 are provided on the fourth epitaxial layer 24, and a double-layer shield gate structure 4 is disposed in the gate trenches 11; the P-type body region 6 is connected between adjacent gate trenches 11 in the fourth epitaxial layer 24; the N+ source region 7 is connected above the P-type body region 6 in the fourth epitaxial layer 24; the contact hole region 8 is disposed between adjacent gate trenches 11 on the fourth epitaxial layer 24 and is connected to the P-type body region 6; the source metal layer 9 is disposed on the top surface of the fourth epitaxial layer 24 and covers the contact hole region 8; the drain region 10 is disposed on the bottom surface of the N+ substrate 1.

[0076] For other working principles and processes of the semiconductor power device in this embodiment, refer to the description of the semiconductor power device preparation method in the foregoing embodiment of the present application, which will not be elaborated here.

[0077] The above has introduced in detail the semiconductor power device and its manufacturing method provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. It should be noted that in the present application, the descriptions of the various embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0078] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, as long as the combination of these technical features does not exist in contradiction, is equally included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor power device, characterized in that, include: Providing an N+ substrate; forming a first epitaxial layer of the same doping type on the N+ substrate, and forming a first P-type diffusion region on the first epitaxial layer after ion implantation on the first epitaxial layer; forming at least one second epitaxial layer on the first epitaxial layer, and forming a second P-type diffusion region on the second epitaxial layer after ion implantation on the second epitaxial layer; forming at least one third epitaxial layer on the second epitaxial layer, and forming a third P-type diffusion region on the third epitaxial layer after ion implantation on the third epitaxial layer; forming a fourth epitaxial layer on the third epitaxial layer, and connecting the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region into one by high-temperature diffusion to form a functional diffusion region; forming a plurality of gate trenches on the fourth epitaxial layer, and forming a double-layer shielding gate structure on the gate trenches; Performing self-aligned ion implantation between adjacent gate trenches on the fourth epitaxial layer to form a P-type body region and an N+ source region located above the P-type body region; A contact hole region connected to the P-type body region and a source metal layer covering the contact hole region are formed on the fourth epitaxial layer, and a drain region is formed by back-gold deposition on the N+ substrate.

2. The method for manufacturing a semiconductor power device according to claim 1, wherein When the first P-type diffusion region, the second P-type diffusion region, and the third P-type diffusion region are formed respectively, the ion implantation concentrations in the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are the same.

3. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, The formation area of the first P-type diffusion region on the first epitaxial layer is S1, the formation area of the second P-type diffusion region on the second epitaxial layer is S2, and the formation area of the third P-type diffusion region on the third epitaxial layer is S3. The vertical projections of S1, S2, and S3 in the direction from the fourth epitaxial layer to the N+ substrate are concentrically arranged and overlap with each other.

4. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, When the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region are formed respectively, ion implantation doses for the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are distributed in a step manner.

5. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, In the direction from the fourth epitaxial layer to the N+ substrate, the curve profile of the connecting line on the same side of the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region is normally distributed.

6. The method for manufacturing a semiconductor power device according to claim 1, wherein, The forming of a double-layer shielding gate structure on the gate trench comprises: forming a first trench oxide layer on the bottom and sidewalls of the gate trench; Depositing a first polysilicon layer in the gate trench, the first polysilicon layer covering the first trench oxide layer, etching back the first polysilicon layer from the top to the bottom of the gate trench to a first etching back depth, and then continuing to etch back the first trench oxide layer to the first etching back depth, wherein the first trench oxide layer after etching back forms a second trench oxide layer; Depositing a second polysilicon layer in the gate trench, wherein the second polysilicon layer covers the first polysilicon layer and the second trench oxide layer, and etching back the second polysilicon layer and the second trench oxide layer to a second etching back depth; A gate structure is formed in the gate trench.

7. The method for manufacturing a semiconductor power device according to claim 6, wherein, Forming a gate structure in the gate trench includes: Forming a gate oxide layer in the gate trench, the gate oxide layer covering the second polysilicon layer and the sidewalls of the gate trench; Depositing a gate polysilicon layer in the gate trench; After etching back the gate polysilicon layer to below the top surface of the fourth epitaxial layer, continue to form the gate oxide layer on the gate polysilicon layer that is flush with the top surface of the fourth epitaxial layer.

8. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, The functional diffusion region is formed in part of the first epitaxial layer, second epitaxial layer, third epitaxial layer, and fourth epitaxial layer.

9. The method for manufacturing a semiconductor power device according to claim 1, wherein, Forming a contact hole region connected to the P-type body region on the fourth epitaxial layer includes: Forming a field oxide layer on the fourth epitaxial layer; Etching a contact hole through a contact hole mask on the field oxide layer, the contact hole penetrating from the top surface of the fourth epitaxial layer into the P-type body region; Performing P++ ion implantation into the contact hole to form the contact hole region.

10. A semiconductor power device prepared by the method for preparing a semiconductor power device according to any one of claims 1 to 9, characterized in that, Includes: An N+ substrate, a functional diffusion region, a double-layer shield gate structure, a P-type body region, an N+ source region, a contact hole region, a source metal layer, and a drain region; A first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer are sequentially stacked on the N+ substrate; the functional diffusion region is connected in part of the first epitaxial layer, second epitaxial layer, third epitaxial layer, and fourth epitaxial layer, and a plurality of gate trenches are provided on the fourth epitaxial layer, and the double-layer shield gate structure is disposed in the gate trenches; The P-type body region is connected between adjacent gate trenches in the fourth epitaxial layer; The N+ source region is connected above the P-type body region in the fourth epitaxial layer; The contact hole region is disposed between adjacent gate trenches on the fourth epitaxial layer and is connected to the P-type body region; The source metal layer is disposed on the top surface of the fourth epitaxial layer and covers the contact hole region; The drain region is disposed on the bottom surface of the N+ substrate.

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