Semiconductor chip, manufacturing method and application

Abstract

The invention discloses a semiconductor chip, which comprises a semiconductor lamination layer arranged on a substrate, the semiconductor lamination layer is provided with a functional area, the semiconductor lamination layer is provided with a protection structure, and the protection structure is arranged at the periphery of the functional area from a top view; the protection structure comprises at least two metal layers; each metal layer comprises at least one metal section; the upper metal layer is partially stacked on the lower metal layer; the projection shape of the protection structure in the direction from the semiconductor lamination layer to the substrate is a first closed pattern, and the projection shape of each metal layer in the direction from the semiconductor lamination layer to the substrate is a non-closed pattern. Each metal layer of the semiconductor chip can eliminate the sudden charge transfer phenomenon generated by contact or approaching between two objects with different charges generated in the chip manufacturing process, a charge release path is formed, and semiconductor lamination damage in the chip manufacturing process is prevented; and the high-quality product output proportion of the semiconductor chip is increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to semiconductor chips applied in the radio frequency field. Background Art

[0002] With the development of semiconductor technology, the size of circuits is getting smaller and smaller, and the miniaturization degree of electronic devices is getting higher and higher, making the components on the chip very sensitive to the charges generated by the outside world. Even a small amount of charge accumulation or sudden charge transfer will cause permanent damage to the tiny structures inside the semiconductor chip.

[0003] During the manufacturing process of semiconductor chips, it usually includes processes such as cleaning wafers, film formation, etching, photoresist stripping, deposition of metal thin films, and metal stripping. There will be a phenomenon of sudden charge transfer generated by the contact or proximity between two objects with different charges, and during this process, permanent damage will be caused to the epitaxial layer of the semiconductor chip. Currently, it is usually solved by improving production equipment or machines, but still cannot avoid the impact of sudden charge transfer on the wafers during the process. For example, during the etching process, an arc discharge phenomenon occurs when the solution sprayed on the wafer surface comes into contact with the wafer surface. During the process of cleaning the wafer, the wafer rotates, and then water is sprayed on the wafer surface. Using the cross-cutting force between the wafer and the vertically sprayed water beam during the rotation of the wafer to remove impurities on the wafer surface will also generate charge accumulation. There is a possibility of damage to the semiconductor chip during the further manufacturing process due to the residual charge on the wafer.

[0004] In addition, during the cutting of wafers, the packaging of semiconductor chips, or the use of semiconductor chips, in order to solve this problem, existing semiconductor chips usually use devices such as transistors, diodes, or capacitors to form a protection circuit to form an effective charge release path. However, the protection circuit not only has a complex structure, but also its setting will occupy additional area on the semiconductor chip, invisibly increasing the manufacturing cost. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies existing in the prior art and provide an improvement in a semiconductor chip, its manufacturing method, and its application.

[0006] In order to achieve the above purposes, the technical solution of the present invention is as follows: The present invention provides a semiconductor chip, including a substrate and a semiconductor stack laminated on the substrate. The semiconductor stack is provided with a functional area, semiconductor components are formed in the functional area, the functional area includes a device area and a pad area arranged outside the device area; at least one pad is arranged in the pad area; at least one electrode is arranged in the device area; A protection structure is provided on the semiconductor stack. When viewed from a top view, the protection structure is disposed in a non-functional area outside the functional area; the protection structure includes at least two metal layers; each metal layer includes at least one metal segment; the upper metal layer is partially stacked on the lower metal layer; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure.

[0007] In an embodiment of the present invention, the protection structure includes a top metal layer. When viewed from a top view, the top metal layer is not connected to the pad.

[0008] In an embodiment of the present invention, it further includes a connecting metal segment; the protection structure includes a top metal layer; the pad area includes at least a first pad, and the connecting metal segment is used to electrically connect the first pad to the protection structure. The first pad is equipotential with the ground terminal of the semiconductor chip.

[0009] In an embodiment of the present invention, a dielectric layer is provided above the connecting metal segment. The connecting metal segment is formed on the same layer as at least one other metal layer of the protection structure except the top metal layer.

[0010] Furthermore, the top metal layer has an extending portion facing inward, one end of the connecting metal segment is connected to the extending portion, and the other end is connected to the first pad.

[0011] Furthermore, the dielectric layer above the connecting metal segment is provided with a first via hole and a second via hole. One end of the connecting metal segment is electrically connected to the top metal layer of the protection structure through the first via hole; the other end of the connecting metal segment is electrically connected to the first pad through the second via hole.

[0012] In an embodiment of the present invention, the semiconductor stack further includes a first ion implantation area, the protection structure includes a first metal layer, and the first metal layer is stacked on the first ion implantation area.

[0013] In an embodiment of the present invention, the first ion implantation area is provided with a groove, and the first metal layer is disposed on the groove of the first ion implantation area.

[0014] In an embodiment of the present invention, a second ion implantation area is provided in the device area of the functional area of the semiconductor stack; the second ion implantation area and the first ion implantation area are formed by an ion implantation process.

[0015] Further, in the present invention, the functional region includes a device region and a pad region disposed outside the device region; the pad region is provided with at least one pad; the device region is provided with at least one electrode; when viewed from a top view, the projections of the electrodes in the functional region and the pads in the pad region in the direction from the semiconductor stack to the substrate are in the shape of a second figure, and the second figure is located within a first closed figure.

[0016] In an embodiment of the present invention, the semiconductor stack is further provided with an isolation region, and the protection structure includes a first metal layer disposed on the isolation region. The isolation region is formed by an ion implantation process.

[0017] In some embodiments of the present invention, it further includes a back metal layer disposed on the back surface of the substrate; the protection structure is electrically connected to the back metal layer.

[0018] In some embodiments of the present invention, the semiconductor stack is further provided with a first isolation region and a second isolation region. When viewed from a top view, the pad region is disposed in the first isolation region; the second isolation region is located on the periphery of the protection structure.

[0019] In an embodiment of the present invention, when viewed from a top view, the perimeter of the projection pattern of the protection structure in the direction from the semiconductor stack to the substrate is L; the perimeter of the projection pattern of the i-th metal layer of the protection structure in the direction from the semiconductor stack to the substrate is L Mi , where i is a natural number greater than or equal to 1; 1 > L Mi / L ≥ 0.5. When the first metal layer is composed of at least two metal segments, the shortest distance between any two adjacent metal segments is greater than or equal to 2 µm. When the first metal layer is composed of one metal segment, the shortest distance between the head and the tail of the metal segment of the first metal layer is greater than or equal to 2 µm. The thickness of the first metal layer is d1; the shortest distance between any two adjacent metal segments of the first metal layer or the shortest distance between the head and the tail of the metal segment of the first metal layer is e1, and e1 ≥ 10 × d1.

[0020] In an embodiment of the present invention, the device region of the semiconductor chip is provided with a HEMT device. The semiconductor chip includes a back metal layer disposed on the back surface of the substrate, and the protection structure is electrically connected to the back metal layer; the protection structure includes a first metal layer and a top metal layer; the HEMT device includes a source electrode, a drain electrode, and a gate electrode; the source electrode includes a source contact layer and a source metal layer disposed on the source contact layer; the drain electrode includes a drain contact layer and a drain metal layer disposed on the drain contact layer; the first metal layer, the source contact layer, and the drain metal layer are disposed on the same layer; the top metal layer, the source metal layer, and the drain metal layer are disposed on the same layer.

[0021] In an embodiment of the present invention, the HEMT device further includes a field plate electrode; the protection structure further includes an intermediate metal layer; the intermediate metal layer is disposed between the first metal layer and the top metal layer; the intermediate metal layer and the field plate electrode are disposed in the same layer, that is, the intermediate metal layer and the field plate electrode are formed by the same metal deposition step.

[0022] Correspondingly, the present invention further provides a method for manufacturing a semiconductor chip, forming a semiconductor stack on a substrate; and dividing the semiconductor stack into functional regions; the functional regions include a device region and a pad region outside the device region; forming a protection structure on the semiconductor stack outside the functional region is formed synchronously with several metal deposition process steps for forming at least one electrode and at least one pad in the functional region; the protection structure includes at least two metal layers; each metal layer includes at least one metal segment; the upper metal layer partially overlaps the lower metal layer; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure; viewed from a top view, the projection shapes of the electrodes in the functional region and the pads in the pad region in the direction from the semiconductor stack to the substrate are a second figure, and the second figure is located within the first closed figure.

[0023] Correspondingly, the present invention further provides an electronic device including the above semiconductor chip.

[0024] Compared with the prior art, the present invention has the following beneficial effects: The protection structure of the semiconductor chip of the present invention includes at least two metal layers; each metal layer includes at least one metal segment; the upper metal layer partially overlaps the lower metal layer; forming a protection structure on the semiconductor stack outside the functional region is formed synchronously with several metal deposition process steps for forming at least one electrode and at least one pad in the functional region; each metal layer can eliminate the sudden charge transfer phenomenon generated by contact or proximity between two objects with different charges generated during the manufacturing process, form a charge release path, prevent damage to the semiconductor stack during the manufacturing process, and increase the yield rate of excellent semiconductor chips. The projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure; the electrodes of the semiconductor chip and the metal layers of the protection structure are formed by a photolithography process during the preparation process. After the wafer deposition metal layer process, wet etching is required to strip the photoresist. In order to etch the photoresist with the etching solution during wet etching and effectively strip the photoresist under the metal layer. At the same time, the protection structure of the present invention is disposed outside the functional region, does not increase the area of the semiconductor chip, and prevents damage to the epitaxial layer.

[0025] The protection structure of the present invention is electrically connected to the ground terminal of the semiconductor chip, especially connected to the back metal layer of the semiconductor chip, and can shield and release the charges generated by the outside world during the use of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of forming isolation region B in the first embodiment of the present invention.

[0027] Figure 2 Schematic diagram of forming gate G in the first embodiment of the present invention.

[0028] Figure 3 Schematic diagram of forming the first opening V1 in the first embodiment of the present invention.

[0029] Figure 4 Top view schematic diagram of forming the first metal layer of the protection structure in the first embodiment of the present invention.

[0030] Figure 5 Cross-sectional schematic diagram of forming the first metal layer of the protection structure in the first embodiment of the present invention.

[0031] Figure 6 Schematic diagram of forming the third dielectric layer 53 in the first embodiment of the present invention.

[0032] Figure 7 Cross-sectional schematic diagram of forming the top metal layer including the protection structure in the first embodiment of the present invention.

[0033] Figure 8 Cross-sectional schematic diagram of forming the fourth dielectric layer 54 in the first embodiment of the present invention.

[0034] Figure 9 Top view schematic diagram of forming the fourth dielectric layer 54 in the first embodiment of the present invention.

[0035] Figure 10 is Figure 9 Cross-sectional schematic diagram in the a-a' direction in

[0036] Figure 11 Top view schematic diagram of the semiconductor chip in the second embodiment of the present invention.

[0037] Figure 12 Cross-sectional schematic diagram of the semiconductor chip in the second embodiment of the present invention.

[0038] Figure 13 Top view schematic diagram of the semiconductor chip in the third embodiment of the present invention.

[0039] Figure 14 is Figure 13 Enlarged schematic diagram at P in

[0040] Figure 15 is Figure 14 Cross-sectional schematic diagram in the b-b' direction in

[0041] Figure 16 Schematic diagram of forming the first opening V1 and the first connection metal segment opening V1' in the third embodiment of the present invention.

[0042] Figure 17 Schematic diagram of forming the first layer of metal segment group C1 and the first connection metal segment C1' in the third embodiment of the present invention.

[0043] Figure 18 Cross-sectional schematic diagram of the semiconductor chip in the fourth embodiment of the present invention.

[0044] Figure 19 Cross-sectional schematic diagram of the semiconductor chip in the fifth embodiment of the present invention.

[0045] Figure 20 Cross-sectional schematic diagram of the semiconductor chip in the sixth embodiment of the present invention.

[0046] Figure 21 Cross-sectional schematic diagram of the semiconductor chip in the seventh embodiment of the present invention.

[0047] Figure 22 Cross-sectional schematic diagram of the semiconductor chip in the eighth embodiment of the present invention.

[0048] Figure 23 Cross-sectional schematic diagram of the semiconductor chip in the ninth embodiment of the present invention.

[0049] Figure 24 Top view schematic diagram of forming the first layer of metal segment group C1 in the ninth embodiment of the present invention.

[0050] Figure 25 Top view schematic diagram of the protection structure in the ninth embodiment of the present invention (the specific structure of the device area A is not shown).

[0051] Figure 26 Cross-sectional schematic diagram of the semiconductor chip in the tenth embodiment of the present invention.

[0052] Figure 27 Top view schematic diagram of the semiconductor chip in the tenth embodiment of the present invention.

[0053] Figure 28 It is Figure 27 Cross-sectional schematic diagram in the c-c' direction in

[0054] Figure 29 It is Figure 27 Cross-sectional schematic diagram in the d-d' direction in

[0055] Figure 30 It is Figure 27 Cross-sectional schematic diagram in the e-e' direction in

[0056] Figure 31Top view schematic of forming the first ion implantation region FC in the non-functional region Q' in the ninth embodiment of the present invention Figure One 。

[0057] Figure 32 Top view schematic of forming the first ion implantation region FC in the non-functional region Q' in the ninth embodiment of the present invention Figure Two 。

[0058] Figure 33 Top view schematic of forming the second isolation region B2 in the non-functional region Q' and the first isolation region B1 in the functional region in the ninth embodiment of the present invention.

[0059] Figure 34 Cross-sectional schematic of forming the gate G in the ninth embodiment of the present invention.

[0060] Figure 35 Cross-sectional schematic of forming the first layer of the protection structure metal segment group C1, the first source metal layer S1, and the first drain metal layer D1 in the ninth embodiment of the present invention.

[0061] Figure 36 Cross-sectional schematic of the semiconductor chip in the eleventh embodiment of the present invention. Detailed implementation manners

[0062] To enable those skilled in the art to further understand the present invention, some embodiments of the present invention are specifically listed below, and the composition and the intended effects of the present invention are described in detail in conjunction with the accompanying drawings. It should be noted that the drawings are all simplified schematic diagrams. For the convenience of description, the components shown in the various drawings of the present invention may not be drawn in an actual number, shape, and size in an equal proportion. In fact, the sizes of some features may be deliberately enlarged or reduced to facilitate discussion. The detailed situation can be adjusted according to the design requirements.

[0063] Embodiment 1 This embodiment provides a semiconductor chip, which includes a substrate and a semiconductor stack disposed on the substrate. The semiconductor stack is provided with a functional region, and the region where semiconductor elements are formed is the functional region. The functional region includes a device region and a pad region disposed around the device region. When viewed from a top view, the periphery of the device region is an isolation region, and the pad region of the semiconductor chip is disposed on the isolation region. It further includes a protection structure disposed on the isolation region of the semiconductor stack. The protection structure is disposed in a non-functional region and includes at least two metal layers. Each metal layer includes at least one metal segment. The upper metal layer partially overlaps the lower metal layer. The projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure. The projection shape of the functional region in the direction from the semiconductor stack to the substrate is a second figure, and the second figure is located within the first closed figure. For example, the number of metal layers of the protection structure is two, three, four, etc. In one embodiment, the number of metal layers of the protection structure is two, namely a bottom metal layer and a top metal layer. The projection shape of the bottom metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure, and the projection shape of the top metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure. The projection shape of the protection structure formed by the bottom metal layer and the top metal layer in the direction from the semiconductor stack to the substrate is a first closed figure.

[0064] The pad region includes a plurality of pads, and the plurality of pads are used as input / output terminals of the semiconductor chip.

[0065] In this embodiment, when viewed from a top view, each metal layer of the protection structure is composed of a plurality of metal segments, surrounding the periphery of the device region. The perimeter of the first metal layer is L M1 , and the perimeter of the projection pattern of the protection structure in the direction from the semiconductor stack to the substrate is L. Preferably, 1 > L M1 / L ≥ 0.5, that is, the first metal layer is a non-closed surrounding structure. A photoresist is disposed on the dielectric layer without the first metal layer in the region where the protection structure of the semiconductor stack is disposed, which is beneficial to improving the metal stripping effect in the non-retained region after metal deposition. In the position without the first metal layer in the region where the protection structure is disposed, an organic solvent can more easily enter and dissolve the photoresist to strip the metal. L M1 When L / L is less than 0.5, in the semiconductor chip manufacturing process, the radiation degree of the first metal layer of the protection structure surrounding the device region is insufficient, that is, the ability of the first metal layer of the protection structure to shield and release charges is insufficient.

[0066] In a specific implementation, the width W1 of the first metal layer of the protection structure is 6 to 20 μm. In order to improve the effect of the included structural result, subsequent metal layers of the protection structure will be partially stacked on the first metal layer. The width of the first metal layer needs to be greater than the minimum width of other subsequent stacked metal layers. Usually, the minimum width of the top metal layer is set to be about 3 to 4 μm. At the same time, the width setting of the first metal layer is also related to the number of metal layers of the protection structure.

[0067] The thickness of the first metal layer of the protection structure is d1; the shortest distance between any two adjacent metal segments of the first metal layer is e1, and e1 ≥ 10×d1. As the bottom layer of the protection structure, subsequent metal layers of the protection structure will be partially stacked on the first metal layer. Therefore, the distance between any two adjacent metal segments of the first metal layer is controlled to prevent the photoresist from collapsing during the yellow light process when the metal layers of other layers of the subsequent protection structure are stacked above the first metal layer, and the distance between any two adjacent metal segments (or when the first metal layer is composed of one metal segment, the shortest distance between the head and the end of the metal segment of the first metal layer) is too close.

[0068] Viewed from the top view, the perimeter of the projection pattern of the protection structure in the direction from the semiconductor stack to the substrate is L; the perimeter of the projection pattern of the i-th metal layer of the protection structure in the direction from the semiconductor stack to the substrate is L Mi , where i is a natural number greater than or equal to 1; the perimeter setting of the i-th metal layer is the same as that of the first metal layer, that is, 1 > L Mi / L ≥ 0.5. The i layer in the i-th layer is the first metal layer, …, the i-th metal layer respectively set in the direction from the substrate to the semiconductor stack.

[0069] Furthermore, the semiconductor chip includes a back metal layer provided on the back surface of the substrate, and the protection structure is electrically connected to the back metal layer. During the packaging and subsequent use of the semiconductor chip, the charges generated by the outside are shielded and released.

[0070] In one embodiment, the semiconductor stack below the protection structure is provided with a back hole, and the back metal layer is connected to the protection structure through the back hole. In another embodiment, the protection structure is connected to an electrode of a semiconductor chip, and the semiconductor stack below the electrode of the semiconductor chip is provided with a back hole, and the back metal layer is connected to the electrode of the semiconductor chip through the back hole. In other embodiments, the protection structure is connected to the pad area, and the semiconductor stack and the substrate below a pad in the pad area are provided with back holes. The back metal layer is provided on the back surface of the substrate and in the back holes, and the back metal layer is connected to a pad through the back hole.

[0071] Taking the semiconductor element as a GaN-based HEMT semiconductor device as an example. See Figures 1 to 10As shown, the functional region Q includes a device region A and a pad region H. Several electrodes in the device region A are respectively a source electrode S and a drain electrode D that are oppositely arranged, and a gate electrode G disposed between the source electrode S and the drain electrode D. The pad region H is provided with input and output terminals of the semiconductor chip. The pad region H of the semiconductor chip is provided with a source pad S0, a drain pad D0, and a gate pad G0 that are respectively connected to the source electrode S, the drain electrode D, and the gate electrode G of the device region A. Among them, the source pad S0 is the first pad.

[0072] Taking the semiconductor element as a GaN-based HEMT semiconductor device as an example, the semiconductor chip of this embodiment is fabricated as follows: Step 1: Provide a semiconductor epitaxial structure 100, which includes a semiconductor stack formed in sequence on a substrate 1, including a buffer layer 2, a channel layer 3, and a barrier layer 4. The buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0073] In other embodiments, an insertion layer is further provided between the channel layer 3 and the barrier layer 4. The insertion layer can be an AlN layer, and a cap layer can be further provided on the barrier layer 4. The cap layer can be a GaN layer.

[0074] Step 2: Form an isolation region B. The isolation region B is formed by ion implantation around the device region A of the functional region, as Figure 1 shown. The specific implementation method is as follows: Using photoresist as a mask, performing a photoresist coating, exposure, and development process to make the region to be isolated for ion implantation, and removing the photoresist to form the isolation region B. The implanted ions are nitrogen ions or helium ions.

[0075] Step 3: Deposit a first dielectric layer 51, and form a gate opening GV in the first dielectric layer 51 in the gate region of the device region A of the functional region. Then, form the gate electrode G through photolithography and metal deposition processes, as Figure 2 shown.

[0076] Step 4: Deposit a second dielectric layer 52. Using photoresist as a mask, perform a photoresist coating, exposure, and development process to form a first opening V1 (located in the non-functional region Q') in the first dielectric layer 51 and the second dielectric layer 52 of the isolation region B to expose the surface of the semiconductor stack; form a first source opening VS1 and a first drain opening VD1 in the second dielectric layer 52 of the device region A. From a top view, the projection shape of the first opening V1 on the isolation region B in the direction from the semiconductor stack to the substrate is a non-closed structure, as Figure 3 shown, where Figure 3 the first source opening VS1 and the first drain opening VD1 are not shown, and the second dielectric layer is not shown for clearer display.

[0077] Step 5, through a photolithography process, deposit the first metal layer M1, and remove the photoresist. At the first opening V1, form a plurality of metal segments, namely the first to fourth segments M11 to M14 of the first-layer metal segment group, constituting the first-layer metal segment group C1, and form the first-layer metal layer including the protection structure; at the first source opening VS1, form the first source metal layer S1; at the first drain opening VD1, form the first drain metal layer D1, as Figure 4 , 5 shown. The shortest distance between the first segment M11 and the second segment M12 of the first-layer metal segment group is d11, the shortest distance between the second segment M12 and the third segment M13 of the first-layer metal segment group is d12, the shortest distance between the third segment M13 and the fourth segment M14 of the first-layer metal segment group is d13, and the shortest distance between the first segment M11 and the fourth segment M14 of the first-layer metal segment group is d14. It should be noted that the values of d11, d12, d13, and d14 can be the same or different. Preferably, they are each greater than 2 μm. The first segment M11 of the first-layer metal segment group is composed of three segments connected in sequence, and the lengths of each segment are L11, L12, and L13 respectively; the third segment M13 of the first-layer metal segment group is composed of three segments connected in sequence, and the lengths of each segment are L31, L32, and L33 respectively; the perimeter of the first-layer metal segment group C1 is L M1 is the sum of the lengths of the first to fourth first-layer metal segments, L M1 = L1 + L2 + L3 + L4; L1 = L11 + L12 + L13; L3 = L31 + L32 + L33. A photoresist is provided on the second dielectric layer 52 at the position V adjacent to the first opening V1 (at the position where the first-layer metal layer is not provided in the protection structure setting area), and the organic solvent is more likely to enter this place to dissolve the photoresist and strip the metal.

[0078] Figure 4 The length of the first-layer metal segment group C1 is schematically shown by the dotted line in Figure 4 . Among them, the length of the first segment M11 of the first-layer metal segment group is L1, the length of the second segment M12 of the first-layer metal segment group is L2, the length of the third segment M13 of the first-layer metal segment group is L3, and the length of the fourth segment M14 of the first-layer metal segment group is L4.

[0079] The perimeter of the first metal layer of the protection structure is L1 + L2 + L3 + L4; the width of the first metal layer of the protection structure is W1, the width of the first opening V1 is W1', W1' ≤ W1, the value range of W1 is 6 - 20 μm, and the width of the top metal layer of the protection structure is 1 - 4 μm. Other metal layers need to be stacked subsequently on the first metal layer. Preferably, the width of the upper metal layer is less than that of the lower metal layer, and the width of the subsequently stacked metal layers needs to be less than the width of the first layer. Therefore, the width of the first metal layer needs to be greater than the minimum width of the subsequently stacked metal layers.

[0080] Preferably, the value range of W1 - W1' is 0.5 - 2 μm. Looking at the cross-sectional view, the cross-sectional shape of the first metal layer is T-shaped: W1' is the size of the first opening V1 of the first dielectric layer 51 / the second dielectric layer 52, and W1 is the width of the first metal layer. Preferably, the width of the first metal layer needs to cover the first opening V1 of the first dielectric layer 51 / the second dielectric layer 52. If it is not covered, it will cause the epitaxial layer to be exposed after the dielectric layer is opened, and it will be damaged in the subsequent processes of the chip, such as wet cleaning and etching, high-temperature processes, etc., thus affecting the reliability of the chip.

[0081] Step 6, deposit the third dielectric layer 53, as Figure 6 shown. Using photoresist as a mask, through the steps of spin coating, exposure, and development, form a second opening V2 in the third dielectric layer 53 at the isolation region B to expose a part of the upper surface of the first metal layer, and form a second source opening VS2 and a second drain opening VD2 in the functional region; looking from the top view, the second opening V2 in the isolation region is a non-closed figure.

[0082] Step 7, through the lithography process, deposit the second metal layer M2 and remove the photoresist, as Figure 7 shown. At the second opening V2, form several metal segments, namely the first to second segments M21, M22 of the second layer metal segment group, which constitute the second layer metal segment group C2, and form the top metal layer including the protection structure; at the second source opening VS2, form the second source metal layer S2, and at the second drain opening VD2, form the second drain metal layer D2. The second source metal layer S2 is stacked on the first source metal layer S1 to constitute the source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1 to constitute the drain D of the semiconductor device; form at least one pad (not shown) at the third dielectric layer 53 in the pad region H of the functional region. The pad region H forms at least one source pad, at least one gate pad, and at least one drain pad respectively; further, the source pad S0, the drain pad D0, and the gate pad G0 are respectively connected to the source S, the drain D, and the gate G.

[0083] Step 8, deposit the fourth dielectric layer 54, as Figure 8 、 9 shown.

[0084] Figure 9 Four source pads S0, one drain pad D0, and one gate pad G0 are respectively connected to the shown source S, drain D, and gate G. For clearer illustration, the schematic diagrams of the first to fourth dielectric layers are omitted herein. Among them, Figure 10 is Figure 9 a cross-sectional schematic diagram along a-a' of, and the shortest distance between the first metal segment M11 of the first metal layer group of the protection structure and the second metal segment M12 of the first metal layer group is d11. Among them, d11 > 2 μm.

[0085] Step 9: Through the steps of applying photoresist, exposing and developing, lithographically opening holes in the fourth dielectric layer 54, etching the openings in the fourth dielectric layer 54, and removing the photoresist, a partial area of the pads of the semiconductor chip is exposed to expose the input / output terminals of the semiconductor chip.

[0086] In this embodiment, the first metal layer is made of ohmic metal material, that is, the contact between the first metal layer and the semiconductor stack is an ohmic contact.

[0087] Embodiment Two This embodiment provides a semiconductor chip, which is similar to Embodiment One. The difference is that it further includes an extension Y1 extending inward and connected to the top metal layer of the protection structure (i.e., the second metal layer group C2). The extension Y1 is formed on the same layer as the top metal layer of the protection structure, and the extension Y1 is connected to the source pad S0 in the pad region H, as shown in the appendix Figure 11 shown, the extension Y1 is oriented inward. Specifically, the semiconductor chip includes four extensions Y1 and four source pads S0. The four extensions Y1 are respectively connected to the four source pads S0. The source pad S0 is equipotential with the ground potential of the semiconductor chip, and the extension Y1 is used to conductively connect the first pad to the protection structure.

[0088] Furthermore, a schematic diagram of the semiconductor chip provided in this embodiment is as shown in Figure 12 shown. A back hole 61 is provided at the semiconductor stack and the substrate corresponding to the source S in the device region A. A back metal layer 6 is provided on the back surface of the substrate of the semiconductor chip, and the back metal layer 6 is connected to the source S of the device. The extension Y1 connected to the top metal layer of the protection structure is electrically connected to the back metal layer 6 through the back hole 61. The protection structure is interconnected with the source through a metal wire, which is equivalent to grounding the protection structure. In this way, signal interference outside the semiconductor chip can be shielded. In addition, the charge accumulation generated during the subsequent manufacturing process of the semiconductor chip can be grounded nearby through the protection structure, reducing the damage to the device structure of the semiconductor chip caused by internal charge accumulation.

[0089] Embodiment Three This embodiment provides a semiconductor chip, which is similar to Embodiment 2, except that, as Figure 13 the protection structure further includes a connecting metal segment. The extending portion Y1 is not directly connected to the source pad S0. Instead, the extending portion Y1 electrically connects the source pad S0 to the protection structure through a first connecting metal segment C1'.

[0090] Figure 14 is Figure 13 an enlarged schematic view of the P position of Figure 15 is Figure 14 a cross-sectional view in the b-b' direction. The first connecting metal segment C1' formed on the same layer as the first metal layer of the protection structure. A top dielectric layer, i.e., the third dielectric layer 53, is provided on the first connecting metal segment C1'.

[0091] The extending portion Y1 of the top metal layer is not directly connected to the source pad S0 in the pad region. Instead, it is electrically connected through the first connecting metal segment C1'. The shortest distance between the extending portion Y1 and the source pad S0 is f1, and the value of f1 is 2 to 10 μm. f1 being greater than 2 μm can avoid the extending portion Y1 being too close to the source pad S0, ensuring an effective distance to improve the peeling effect of the subsequent metal peeling process. f1 being greater than 10 μm will cause a significant increase in the device area and an increase in chip cost.

[0092] On the one hand, the protection structure is interconnected with the source S through the first connecting metal segment C1', which is equivalent to grounding the protection structure. This can shield the signal interference outside the semiconductor chip. Additionally, during the subsequent manufacturing process of the semiconductor chip, the charge accumulation generated will be grounded nearby through the protection structure, reducing the damage to the device structure of the semiconductor chip caused by internal charge accumulation. On the other hand, the top metal layer of the protection structure is not directly connected to the source pad. The top metal layer, the source pad, and the active region form an approximately closed surrounding structure, which is beneficial to improving the peeling effect of the subsequent metal peeling process: if it is not approximately closed, the organic solvent can enter through the non-approximately closed area to dissolve the photoresist and improve the peeling effect. The source-drain spacing (the distance between the source and the drain) in the device region of the semiconductor is usually less than 5 to 8 μm. The thickness of the top metal layer is greater than 2 μm, usually set at 3 to 4 μm. If the top metal layer is directly connected to the source pad, it will directly increase the risk of incomplete metal peeling. Additionally, interconnecting with the source S through the first connecting metal segment C1' increases the flexibility of wiring, reducing the situation where when there is a bad contact between the top metal layer of the protection structure and the source pad, there is no other layer of metal layer directly interconnected with the pad, ensuring low-impedance grounding of the source pad.

[0093] The manufacturing method of the semiconductor chip of this embodiment includes the following: Steps 1 to 3 are the same as those in Embodiment 1 and will not be elaborated here.

[0094] Step 4, deposit the second dielectric layer 52. Using photoresist as a mask, through the steps of spin coating, exposure, and development, form a first opening V1 and a first connection metal segment opening V1' at the second dielectric layer 52 in the isolation region B; form a first source opening VS1 and a first drain opening VD1 at the second dielectric layer 52 in the device region A. When viewed from the top view, the projection shape of the first opening V1 on the isolation region B in the direction from the semiconductor stack to the substrate is a non-closed structure, as Figure 16 shown, Figure 16 the first source opening VS1 and the first drain opening VD1 are not shown in Figure 16 . For a clearer display, the second dielectric layer 52 is not shown.

[0095] Step 5, deposit the first metal layer M1 and remove the photoresist. At the first opening V1, form a plurality of metal segments, namely the first to fourth segments M11 - M14 of the first layer metal segment group, to form the first layer metal segment group C1 of the inclusion structure, which is the first layer metal layer of the protection structure. At the first connection metal segment opening V1', form a first connection metal segment C1', where the number of the first connection metal segments C1' is 4, as Figure 17 shown. Preferably, the first connection metal segment C1' is not connected to the first layer metal layer of the protection structure.

[0096] Step 6, deposit the third dielectric layer 53. Using photoresist as a mask, through the steps of spin coating, exposure, and development, form a second opening V2 at the third dielectric layer 53 in the isolation region B to expose a part of the upper surface of the first layer metal layer, and form a third opening V3 and a fourth opening V4 at the third dielectric layer 53 in the isolation region B to expose two parts of the upper surface of the first connection metal segment C1' respectively. Form a second source opening VS2 and a second drain opening VD2 in the functional region. When viewed from the top view, the second opening V2 in the isolation region is a non-closed figure.

[0097] Step 7: Through the photolithography process, deposit the second metal layer M2, and remove the photoresist. At the second opening V2, form a plurality of metal segments to form the second metal segment group C2 of the protection structure, including the first to second segments M21 and M22 of the second metal segment group, that is, form the top metal layer of the protection structure. At the same time, an extension Y1 is also formed. The third opening V3 is located below the extension Y1. The extension Y1 is connected to the first connection metal segment C1' through the second metal layer M2 deposited in the third opening V3. At the second source opening VS2, form the second source metal layer S2. At the second drain opening VD2, form the second drain metal layer D2. The second source metal layer S2 is stacked on the first source metal layer S1 to form the source S of the semiconductor device. The second drain metal layer D2 is stacked on the first drain metal layer D1 to form the drain D of the semiconductor device. At least one pad (not shown) is formed at the pad area H in the functional area at a plurality of pad openings. At the pad area H at the third dielectric layer 53, at least one source pad S0, at least one gate pad G0, and at least one drain pad D0 are respectively formed. Further, the source pad S0, the drain pad D0, and the gate pad G0 are respectively connected to the source S, the drain D, and the gate G. The fourth opening V4 is located below the source pad S0. The source pad S0 is connected to the first connection metal segment C1' through the second metal layer M2 deposited in the fourth opening V4, so as to realize the electrical connection between the source pad S0 and the second metal segment group C2 of the protection structure through the first connection metal segment C1' and the extension Y1. The shortest distance between the extension Y1 and the source pad S0 is f1. Preferably, 10μm ≥ f1 ≥ 2μm. On the one hand, avoid the extension Y1 being too close to the source pad S0 to ensure an effective distance, so as to improve the stripping effect of the subsequent metal stripping process. If f1 is set too large, it will cause a significant increase in the device area and an increase in chip cost.

[0098] Example 4 This example provides a semiconductor chip, as Figure 18 shown. Similar to Examples 1 to 3, the difference is that a source ion implantation area FS and / or a drain ion implantation area FD are respectively provided below the source and / or drain of the device area A to further reduce the contact resistance between the source and drain of the semiconductor chip and the semiconductor stack. The ions implanted in the source ion implantation area FS and the drain ion implantation area FD include at least one selected from silicon Si ions and germanium Ge ions. The same parts of this example and other examples are not described herein again.

[0099] Example 5 This example provides a semiconductor chip, Figure 19As shown, it includes a substrate and a semiconductor stack. The semiconductor stack is provided with a functional region Q. The region where semiconductor elements are formed is the functional region. The functional region includes a device region A and a pad region H disposed outside the device region A. In a top view, the outside of the device region A is an isolation region B, and the outside of the isolation region B is a protection structure region. The pad region H of the semiconductor chip is disposed on the isolation region B. It further includes a protection structure disposed in the protection structure region of the semiconductor stack. The protection structure is disposed in the non-functional region Q'. The protection structure includes at least two metal layers. Each metal layer includes at least one metal segment. The upper metal layer partially overlaps the lower metal layer. The projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure. The projection shape of the functional region in the direction from the semiconductor stack to the substrate is a second figure, and the second figure is located within the first closed figure. For example, the number of metal layers of the protection structure is two, three, four, etc. The difference from the foregoing embodiments is that in Embodiments 1 to 4, the protection structure is located above the isolation region B, while in this embodiment, the protection structure is located in the protection structure region outside the isolation region, as shown in the appendix Figure 19 As shown, a source ion implantation region FS and / or a drain ion implantation region FD are respectively disposed below the source S and / or the drain D of the device region A. The ions implanted into the ion implantation region include at least one selected from silicon Si ions and germanium Ge ions. This embodiment is similar to Embodiment 4. The difference is that in Embodiment 4, the protection structure is disposed on the isolation region B, while in this embodiment, the protection structure is not disposed on the isolation region B, that is, the protection structure is disposed on the semiconductor stack without isolation treatment. The same parts as those in other Embodiment 4 will not be described herein again.

[0100] Embodiment 6 This embodiment provides a semiconductor chip. This embodiment is similar to Embodiment 5. The difference is that Figure 20 As shown, no ion implantation region is disposed below the source and / or the drain of the device region A. The same parts as those in other Embodiment 5 will not be described herein again.

[0101] Embodiment 7 This embodiment provides a semiconductor chip. This embodiment is similar to Embodiment 5. The difference is that a first ion implantation region FC is disposed below the protection structure, as shown in Figure 21 As shown. The first ion implantation region FC is formed by a synchronous ion implantation process with the source ion implantation region FS and / or the drain ion implantation region FD. The ions implanted into the ion implantation region include at least one selected from silicon Si ions and germanium Ge ions. The same parts as those in other Embodiment 5 will not be described herein again.

[0102] A first ion implantation region FC is provided below the protection structure to reduce the contact resistance between the first metal layer of the protection structure and the semiconductor interface, and eliminate the charges accumulated in the semiconductor stack during the manufacturing process. It should be noted that ion implantation regions may not be provided below the source S and drain D of the devices of the semiconductor chip.

[0103] Example Eight This embodiment provides a semiconductor chip. This embodiment is similar to Embodiment Seven, except that, as Figure 22 shown, an isolation region is further provided on the periphery of the protection structure.

[0104] Example Nine This embodiment provides a semiconductor chip. Different from the first to ninth embodiments, the protection structure of this embodiment includes three metal layers. As shown in the appendix Figure 23 shown, a semiconductor chip includes a substrate and a semiconductor stack. The semiconductor stack is provided with a functional region Q and a non-functional region Q'. The region where semiconductor elements are formed is the functional region. The functional region includes a device region A and a pad region H provided on the periphery of the device region A; viewed from a top view, the periphery of the device region A is an isolation region, and the pad region of the semiconductor chip is provided on the isolation region; it further includes a protection structure provided on the non-functional region Q' of the semiconductor stack. The protection structure includes three metal layers, namely the first metal layer, the intermediate metal layer, and the top metal layer.

[0105] The projection shapes of the first metal layer, the intermediate metal layer, and the top metal layer in the direction from the semiconductor stack to the substrate are all non-closed figures; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure. Figure 24 、 25 shown, the protection structure includes a first metal segment group C1, a second metal segment group C2, and a third metal segment group C3. The first metal segment group C1 is configured to form the first metal layer of the protection structure on the semiconductor stack. As Figure 24 shown, the first metal layer is composed of the first metal segment group C1 and includes the first to fourth segments M11~M14 of the first metal segment group, forming the first metal layer of the protection structure. The intermediate metal layer is composed of the second metal segment group C2; the top metal layer is composed of the third metal segment group C3.

[0106] The material of the first metal layer is different from that of Embodiments One to Eight. In this embodiment, the metal material of the first metal layer is Schottky metal. The embodiment of the present invention can start to solve the charge accumulation process during the process of fabricating the gate of the semiconductor chip, further improving the yield rate of high-quality semiconductor chips.

[0107] Taking the semiconductor element as a GaN-based HEMT semiconductor device in this embodiment of the semiconductor chip as an example, as Figures 23 to 25As shown below. The specific manufacturing process is as follows: Step 1: Provide a semiconductor epitaxial structure 100, which includes a buffer layer 2, a channel layer 3, and a barrier layer 4 formed in sequence on a substrate 1. The buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0108] In other embodiments, an insertion layer is further provided between the channel layer 3 and the barrier layer 4. The insertion layer is an AlN layer, and a cap layer is further provided on the barrier layer 4. The cap layer is a GaN layer.

[0109] Step 2: Form an isolation region B. The isolation region B is formed around the device region A of the functional region by ion implantation. The specific implementation method is as follows: Use photoresist as a mask, and perform photoresist coating, exposure, and development steps to make the region that needs to be isolated for ion implantation, and then remove the photoresist to form the isolation region. The implanted ions are nitrogen ions or helium ions.

[0110] Step 3: Deposit a first dielectric layer 51, form a gate opening in the gate region of the device region in the functional region, form a first opening V1 at the non-functional region Q', and form a gate G and the first layer metal layer of the protection structure by photolithography and depositing a first metal layer M1. From a top view, the projection shape of the first opening V1 at the non-functional region Q' from the semiconductor stack to the substrate direction is a non-closed structure. The material for the metal deposition in this step is Schottky metal material. The first metal layer M1 is made of a multi-layer metal stack, such as Ni / Au stack, Ti / Pt / Au stack, Pt / Ni / Au stack, etc.

[0111] The first layer metal layer is composed of a first layer metal segment group C1, including the first to fourth segments M11, M12, M13, M14 of the first layer metal segment group. The projection shape from the semiconductor stack to the substrate direction is a non-closed loop graph, such as Figure 24 .

[0112] Step 4: Deposit a second dielectric layer 52. Use photoresist as a mask, and perform photoresist coating, exposure, and development steps to form a second opening V2 at the second dielectric layer 52 of the non-functional region Q'; form a first source opening VS1 and a first drain opening VD1 at the second dielectric layer 52 of the device region A. From a top view, the projection shape of the second opening V2 on the non-functional region Q' from the semiconductor stack to the substrate direction is a non-closed structure.

[0113] Step 5, deposit the second metal layer M2 and remove the photoresist. At the second opening V2, form a plurality of metal segments to constitute the second layer metal segment group C2, including the first to third segments M21 to M23 of the second layer metal segment group, that is, form an intermediate metal layer including the protection structure; at the first source opening VS1, form the first source metal layer S1; at the first drain opening VD1, form the first drain metal layer D1; the second metal layer M2 can be selected as a Ti / Pt / Au stack.

[0114] Step 6, deposit the third dielectric layer 53. Using the photoresist as a mask, adopt the steps of coating, exposure and development to form a third opening V3 in the third dielectric layer 53 at the non-functional region Q' to expose a part of the upper surface of the second layer metal segment group C2, and form a second source opening VS2, a second drain opening VD2, and a gate opening VG in the device region A of the functional region; viewed from the top view, the third opening V3 at the non-functional region Q' is a non-closed figure.

[0115] Step 7, through the photolithography process, deposit the third metal layer M3 and remove the photoresist. At the third opening V3, form a plurality of metal segments to form the third layer metal segment group C3, including the first and second metal segments M31 and M32 of the third layer metal segment group, that is, form the top metal layer of the protection structure; at the second source opening VS2, form the second source metal layer S2, and at the second drain opening VD2, form the second drain metal layer D2. The second source metal layer S2 is stacked on the first source metal layer S1 to constitute the source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1 to constitute the drain D of the semiconductor device; form at least one pad (not shown) at the third dielectric layer 53 in the pad region H of the functional region. The pad region H forms at least one source pad, at least one gate pad, and at least one drain pad respectively; further, the source pad, the drain pad, and the gate pad are respectively connected to the source S, the drain D, and the gate G. The third metal layer M3 can be selected as a Ti / Pt / Au stack.

[0116] Step 8, deposit the fourth dielectric layer 54.

[0117] Step 9, through the steps of coating photoresist, exposure and development, lithographically open the hole region of the fourth dielectric layer 54, etch the fourth dielectric layer 54 to form an opening, and remove the photoresist to expose a part of the region of the pad of the semiconductor chip to expose the input / output end of the semiconductor chip.

[0118] The protection structure is located in the non-functional region Q'. In the embodiment of the present invention, the semiconductor stack contacted by the protection structure is a non-isolated region. It should be noted that the semiconductor stack contacted by the protection structure can also be arranged on the isolation region or can be an ion implantation region.

[0119] It should be noted that the second metal layer M2 and the third metal layer M3 can also be Ti / Al / Ti, Ti / Al / Au laminates, etc.

[0120] Embodiment Ten This embodiment provides a semiconductor chip. Different from the first to eighth embodiments, the protection structure in this embodiment includes three metal layers. Different from the ninth embodiment, in the ninth embodiment, the material of the first metal layer is Schottky metal material, while the material of the first metal layer in the embodiment of the present invention is ohmic metal material. The ohmic metal material can be made of metal laminates such as Ti / Al / Ti, Ti / Al / Au, Ti / Pt / Au, etc.

[0121] As shown in the attached Figures 26 to 30 figures, a semiconductor chip includes a substrate and a semiconductor stack. The semiconductor stack is provided with a functional area Q and a non-functional area Q'. The area where semiconductor elements are formed is the functional area. The functional area includes a device area A and a pad area H provided on the periphery of the device area. When viewed from a top view, a first isolation area B1 is provided on the periphery of the device area A, and the pad area H of the semiconductor chip is provided on the first isolation area B1. It also includes a protection structure provided on the non-functional area Q' of the semiconductor stack. The protection structure includes three metal layers, namely the first metal layer, the intermediate metal layer, and the top metal layer.

[0122] Figure 26 is a cross-sectional schematic diagram of the semiconductor chip according to Embodiment Ten of the present invention. Figure 27 is a top view schematic diagram of the semiconductor chip according to Embodiment Ten of the present invention. Figure 28 is Figure 27 a cross-sectional schematic diagram in the c-c' direction. The distance between the fourth segment M24 of the second metal segment group and the first segment M21 of the second metal segment group is d24. Preferably, d24 is greater than 2 μm.

[0123] Figure 30 is Figure 27 a cross-sectional schematic diagram in the e-e' direction.

[0124] Furthermore, when viewed from a top view, the protection structure is provided on the semiconductor stack between the first isolation area B1 and the second isolation area B2.

[0125] Furthermore, a first ion implantation area FC is also provided in the semiconductor stack below the protection structure. The implanted ions include at least one selected from silicon Si ions and germanium Ge ions. When viewed from a top view, the projection shape of the first ion implantation area FC below the protection structure in the direction from the semiconductor stack to the substrate can be a closed figure, see Figure 32 , or it can be a non-closed figure, see Figure 31 .

[0126] Further, when viewed from the top view, a second isolation region B2 is further provided in the semiconductor stack on the periphery of the protection structure. The difference from Embodiments 1 to 8 is that it includes an intermediate metal layer.

[0127] The projection shapes of the first metal layer, the intermediate metal layer, and the top metal layer in the direction from the semiconductor stack to the substrate are all non-closed figures; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure. The protection structure includes a first metal layer formed by a first metal segment group C1, an intermediate metal layer formed by a second metal segment group C2, and a top metal layer formed by a third metal segment group C3. A schematic diagram of forming the first metal layer of the protection structure on the semiconductor stack. The first metal segment group C1 includes the first and second segments M11 to M12 of the first metal segment group to form the first metal layer of the protection structure. The second metal segment group C2 includes the first to fourth segments M21 to M24 of the second metal segment group to form the intermediate metal layer of the protection structure. The third metal segment group C3 includes the first and second segments M31 to M32 of the third metal segment group to form the top metal layer of the protection structure. The projection shapes of the first to third metal segments C1 to C3 in the direction from the semiconductor stack to the substrate are all non-closed figures.

[0128] In this embodiment, the semiconductor chip takes a GaN-based HEMT semiconductor device as an example of the semiconductor element. The semiconductor chip includes a source electrode S, a drain electrode D, a gate electrode G, a field plate electrode FP, as well as 4 source pads S0, 1 gate pad G0, and 1 drain pad D0. The source electrode S includes a first source metal layer S1 and a second source metal layer S2. The drain electrode D includes a first drain metal layer D1 and a second drain metal layer D2. The protection structure includes first to third metal segment groups C1 to C3. The first metal segment group C1 of the protection structure is provided on the same layer as the first source metal layer S1 and the first drain metal layer D1; the second metal segment group C2 of the protection structure is provided on the same layer as the field plate electrode FP; the third metal segment group C3 of the protection structure is provided on the same layer as the second source metal layer S2 and the second drain metal layer D2.

[0129] An inwardly extending portion Y1 connected to the top metal layer of the protection structure is further provided, and the protection structure further includes a connecting metal segment; the connecting metal segment is used to conductively connect the source pad S0 to the protection structure. The connecting metal segment is a second connecting metal segment C2' formed on the same layer as the second metal segment group C2 of the protection structure, and the second connecting metal segment C2' is provided with a top dielectric layer, that is, a fourth dielectric layer 54. Figure 29 For Figure 27Schematic cross-sectional view in the d-d' direction. The extension Y1 of the top metal layer is not directly connected to the source pad S0 in the pad region, but is electrically connected through the second connection metal segment C2'; the shortest distance between the extension Y1 and the source pad S0 is f1, preferably, 10μm ≥ f1 ≥ 2μm. This can avoid the extension Y1 being too close to the source pad S0, ensure an effective distance, so as to improve the peeling effect of the subsequent metal peeling process. When f1 is greater than 10μm, it will cause a significant increase in the device area and an increase in chip cost.

[0130] The specific fabrication is as follows: Step 1, provide a semiconductor epitaxial structure 100, which includes a buffer layer 2, a channel layer 3, and a barrier layer 4 formed in sequence on a substrate 1, where the buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0131] In other embodiments, an insertion layer is further provided between the channel layer 3 and the barrier layer 4, the insertion layer is an AlN layer, and a cap layer is further provided on the barrier layer 4, the cap layer is a GaN layer.

[0132] Step 2, as Figure 31 shown, in the non-functional region Q' and the device region A, by ion implantation, a first ion implantation region FC is formed in the non-functional region Q', and source ion implantation regions and / or drain ion implantation regions (not shown) are formed in the semiconductor stack in the source region and / or drain region of the device region A. The ions implanted in the ion implantation regions include at least one selected from silicon Si ions and germanium Ge ions; wherein the projection shape of the first ion implantation region FC from the semiconductor stack to the substrate direction is a non-closed figure. In other embodiments, it can also be a closed figure, as shown in 32.

[0133] Step 3, form a first isolation region B1 and a second isolation region B2, which are formed by ion implantation around the device region A in the functional region. The specific implementation method is: using photoresist as a mask, performing a photoresist coating, exposure, and development process to make the regions that need to be isolated for ion implantation, and removing the photoresist to form the first isolation region B1 and the second isolation region B2, where the ions implanted are nitrogen ions or helium ions, as Figure 33 shown.

[0134] Step 4, deposit a first dielectric layer 51, form a gate opening in the gate region of the device region A in the functional region, and form a gate G through photolithography and metal deposition processes. As Figure 34 shown, Step 5: Deposit a second dielectric layer 52. Using photoresist as a mask, through a photoresist coating, exposure, and development process, form a first opening V1 in the second dielectric layer 52 at the non-functional region Q'; form a first source opening VS1 and a first drain opening VD1 in the second dielectric layer 52 at the device region A. When viewed from a top view, the projection shape of the first opening V1 in the direction from the semiconductor stack to the substrate is a non-closed structure.

[0135] Step 6: As Figure 35 shown, through a photolithography process, deposit a first metal layer M1. At the first opening V1, form a number of metal segments, namely the first segment M11 and the second segment M12 of the first layer metal segment group, which constitute the first layer metal segment group C1, to form a first layer metal layer including a protection structure; at the first source opening VS1, form a first source metal layer S1; at the first drain opening VD1, form a first drain metal layer D1. As Figure 30 shown, the shortest distance d12 between the first segment M11 and the second segment M12 of the first layer metal segment group is greater than 2 μm.

[0136] Step 7: Deposit a third dielectric layer 53. Form a second opening V2 in the third dielectric layer 53 at the non-functional region Q' to expose a part of the upper surface of the first layer metal layer, and form a second source opening VS2 and a second drain opening VD2 in the device region A. When viewed from a top view, the second opening is a non-closed figure.

[0137] Step 8: Through a photolithography process, deposit a second metal layer M2. At the second opening V2 at the non-functional region Q', form a number of metal segments, namely the first to fourth segments M21 - M24 of the second layer metal segment group, which constitute the second layer metal segment group C2. At the location where the second connection metal segment is set, form a second connection metal segment C2', and at the location where the field plate structure is set, form a field plate electrode FP.

[0138] Step 9: Deposit a fourth dielectric layer 54 to form a second source opening VS2, a second drain opening VD2, a third opening V3, a number of fourth openings V4, and a number of fifth openings V5, respectively exposing parts of the first source metal layer S1, the second drain metal layer D1, the second layer metal segment group C2, one end of the second connection metal segment C2', and the other end of the second connection metal segment C2'.

[0139] Step 10: Through a photolithography process, deposit a third metal layer M3. At the third opening V3, form a number of metal segments to form a third-layer metal segment group C3, including the first to second segments M31 - M32 of the third-layer metal segment group, i.e., form the top metal layer of the protection structure. At the same time, also form an inwardly extending portion Y1. The fourth opening V4 is located below the extending portion Y1. The extending portion Y1 is connected to the second connecting metal segment C2' through the third metal layer M3 deposited in the fourth opening V4. At the second source opening VS2, form a second source metal layer S2. At the second drain opening VD2, form a second drain metal layer D2. The second source metal layer S2 is stacked on the first source metal layer S1 to constitute the source S of the semiconductor device. The second drain metal layer D2 is stacked on the first drain metal layer D1 to constitute the drain D of the semiconductor device. At least one pad (not shown) is formed at the pad area in the functional area at a number of pad openings. At the pad area H at the fourth dielectric layer 54, form at least one source pad, at least one gate pad, and at least one drain pad respectively. Further, the source pad S0, the drain pad D0, and the gate pad G0 are respectively connected to the source S, the drain D, and the gate G. The fifth opening V5 is located below the source pad S0. The source pad S0 is connected to the second connecting metal segment C2' through the third metal layer deposited in the fifth opening V5. The shortest distance between the extending portion Y1 and the source pad S0 is f1. Preferably, f1 ≥ 2 μm.

[0140] Step 11: Deposit a fifth dielectric layer 55.

[0141] Step 12: Through the steps of applying photoresist, exposure, and development, photolithograph the opening area of the fifth dielectric layer 55, etch the fifth dielectric layer 55, and remove the photoresist to expose a partial area of the pads of the semiconductor chip, so as to expose the input / output terminals of the semiconductor chip.

[0142] It also includes forming a back hole 61 and depositing a back metal layer 6 on the back of the substrate of the semiconductor chip.

[0143] Example XI The difference from Example X is that the first ion implantation region FC is provided with a groove, and the first-layer metal layer is disposed on the groove of the first ion implantation region FC. The source ion implantation region FS and / or the drain ion implantation region FD are provided with grooves, as Figure 36 shown.

[0144] Correspondingly, an electronic device provided by the present invention includes the semiconductor chip in the above embodiment. In particular, it is an electronic device applied to the radio frequency field. Such as a communication device, the communication device includes a receiving and / or transmitting module. The receiving module includes a radio frequency amplifier or the transmitting module includes a radio frequency amplifier. The radio frequency amplifier includes the semiconductor chip of the present invention.

[0145] For example, the electronic device includes a radio frequency amplifier, and the radio frequency amplifier includes the embodiments of the present invention.

[0146] It should be noted that the semiconductor chip is provided with a back metal layer, and the back metal layer is electrically connected to the source electrode of the device area through a back hole. The back hole can be provided in the device area or in the pad area.

[0147] The above embodiments are only used to further illustrate the present invention, but the present invention is not limited to the embodiments. It should be noted that in the embodiments of the present invention, the number of metal layers listed in the protection structure is two or three, but not limited thereto. Four or more layers can be provided according to the actual design requirements of the semiconductor chip. The functional areas of the semiconductor chip listed in the embodiments of the present invention include GaN HEMT devices, and can also include other devices such as pHEMT GaAs. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor chip, comprising a substrate and a semiconductor stack disposed on the substrate, the semiconductor stack having a functional region in which semiconductor elements are formed, characterized in that: A protection structure is provided on the semiconductor stack. When viewed from a top view, the protection structure is disposed in a non-functional region on the periphery of the functional region; The functional region includes a device region and a pad region disposed outside the device region; at least one pad is provided in the pad region; at least one electrode is provided in the device region; The protection structure includes at least two metal layers; each metal layer includes at least one metal segment; the upper metal layer is partially stacked on the lower metal layer; The projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure.

2. The semiconductor chip according to claim 1, characterized in that: The protection structure includes a top metal layer. When viewed from a top view, the top metal layer is not connected to the pad.

3. The semiconductor chip according to claim 1, characterized in that: It further includes a connecting metal segment; the protection structure includes a top metal layer; the pad region includes at least a first pad, and the connecting metal segment is used to electrically connect the first pad to the protection structure.

4. The semiconductor chip according to claim 3, characterized in that: A dielectric layer is provided above the connecting metal segment.

5. The semiconductor chip according to claim 4, characterized in that: The top metal layer has an inward extending portion, one end of the connecting metal segment is connected to the extending portion, and the other end is connected to the first pad.

6. The semiconductor chip according to claim 5, characterized in that: The dielectric layer above the connecting metal segment is provided with a first through hole and a second through hole. One end of the connecting metal segment is electrically connected to the top metal layer of the protection structure through the first through hole; the other end of the connecting metal segment is electrically connected to the first pad through the second through hole.

7. The semiconductor chip according to claim 1, characterized in that: The semiconductor stack further includes a first ion implantation region, the protection structure includes a first metal layer, and the first metal layer is stacked on the first ion implantation region.

8. The semiconductor chip according to claim 7, characterized in that: The first ion implantation region is provided with a groove, and the first metal layer is disposed on the groove of the first ion implantation region.

9. The semiconductor chip according to claim 1, characterized in that: When viewed from a top view, the projection shapes of the electrodes in the functional region and the pads in the pad region in the direction from the semiconductor stack to the substrate are a second figure, and the second figure is located within the first closed figure.

10. The semiconductor chip according to claim 1, characterized in that: The semiconductor stack is further provided with an isolation region, the protection structure includes a first metal layer, and the first metal layer is disposed on the isolation region.

11. The semiconductor chip according to claim 1, characterized in that: It further includes a back metal layer disposed on the back surface of the substrate; the protection structure is electrically connected to the back metal layer.

12. The semiconductor chip according to claim 1, wherein: The semiconductor stack further has a first isolation region and a second isolation region. When viewed from a top view, the pad region is disposed in the first isolation region; the second isolation region is located on the periphery of the protection structure.

13. The semiconductor chip according to claim 1, wherein: From the top view, the perimeter of the projection figure of the protection structure from the semiconductor stack to the substrate is L; the perimeter of the projection figure of the i-th metal layer of the protection structure from the semiconductor stack to the substrate is L Mi , i is a natural number greater than or equal to 1; 1>L Mi / L≥0.

5.

14. The semiconductor chip according to claim 1, wherein: When the first metal layer is composed of at least two metal segments, the shortest distance between any two adjacent metal segments is greater than or equal to 2 µm; When the first metal layer is composed of one metal segment, the shortest distance between the head end and the tail end of the metal segment of the first metal layer is greater than or equal to 2 µm.

15. The semiconductor chip according to claim 14, wherein: The thickness of the first metal layer is d1; the shortest distance between any two adjacent metal segments of the first metal layer or the shortest distance between the head end and the tail end of the metal segment of the first metal layer is e1, and e1 ≥ 10 × d1.

16. The semiconductor chip according to claim 1, wherein: The device region of the semiconductor chip is provided with HEMT devices. The semiconductor chip includes a back metal layer disposed on the back surface of the substrate, and the protection structure is electrically connected to the back metal layer; The protection structure includes a first metal layer and a top metal layer; The HEMT device includes a source electrode, a drain electrode, and a gate electrode; the source electrode includes a source contact layer and a source metal layer disposed on the source contact layer; the drain electrode includes a drain contact layer and a drain metal layer disposed on the drain contact layer; The first metal layer, the source contact layer, and the drain metal layer are disposed on the same layer; The top metal layer, the source metal layer, and the drain metal layer are disposed on the same layer.

17. The semiconductor chip according to claim 16, wherein: The HEMT device further includes a field plate electrode; the protection structure further includes an intermediate metal layer; the intermediate metal layer is disposed between the first metal layer and the top metal layer; The intermediate metal layer and the field plate electrode are disposed on the same layer.

18. A method for manufacturing a semiconductor chip, wherein: A semiconductor stack is formed on a substrate; and the semiconductor stack is divided into functional regions; the functional regions include a device region and a pad region outside the device region; A protection structure is formed on the semiconductor stack outside the functional regions by a plurality of metal deposition process steps that are synchronized with forming at least one electrode and at least one pad in the functional regions; The protection structure includes at least two metal layers; each metal layer includes at least one metal segment; the upper metal layer is partially stacked on the lower metal layer; The projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure; When viewed from a top view, the projection shapes of the electrodes in the functional regions and the pads in the pad region in the direction from the semiconductor stack to the substrate are a second figure, and the second figure is located within the first closed figure.

19. An electronic device, characterized in that, Comprising a semiconductor chip according to any one of claims 1 to 17.

Images