Transient insensitive level shifter

Abstract

In an example, a level shifter (200) includes a low side (104) having a first input (118) and a second input (120). The level shifter (200) also includes a high side (102), where the high side (102) has a latch (110) having a first terminal (248) and a second terminal (250). The high side (102) also includes a current comparator (106) that includes a first current mirror and a second current mirror. The high side (102) includes isolation circuitry (108) including a first transistor (240) having a first control terminal and a second transistor (242) having a second control terminal, the first transistor (240) being coupled between the first terminal (248) and the first current mirror, and the second transistor (242) being coupled between the second terminal (248) and the second current mirror. The second transistor (242) is coupled between the second terminal (250) and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

Description

BACKGROUND OF THE INVENTION

[0001] A level shifter interfaces between a lower voltage circuit system and a higher voltage circuit system. The level shifter safely converts signals between the higher voltage circuit system and the lower voltage circuit system. The level shifter can isolate and protect the lower voltage circuit system from the higher voltage (from the higher voltage circuit system), which could otherwise damage the lower voltage circuit system. One application of the level shifter is for a gate driver of a direct current (DC)-DC voltage converter. SUMMARY OF THE INVENTION

[0002] In at least one example described, a level shifter includes a low side having a first input and a second input. The level shifter further includes a high side, where the high side has a latch having a first terminal and a second terminal. The high side further includes a current comparator including a first current mirror and a second current mirror. The high side includes an isolation circuit system including a first transistor and a second transistor, where the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

[0003] In at least one example described, a level shifter includes a high side having a first input and a second input. The level shifter further includes a low side, where the low side has a latch having a first terminal and a second terminal. The low side includes a current comparator including a first current mirror and a second current mirror. The low side further includes an isolation circuit system including a first transistor and a second transistor, where the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

[0004] In at least one of the described examples, a level shifter includes a low side having a first input and a second input configured to receive one or more signals that switch the output of the level shifter. The level shifter further includes a high side having a latch with a first terminal and a second terminal. The high side further includes a current comparator including a first current mirror and a second current mirror, where the current comparator is configured to perform a current comparison between a first current and a second current. The high side includes an isolation circuitry including a first transistor and a second transistor, where the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror, and where the isolation circuitry is configured to isolate the current comparator from the latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. is a block diagram of a level shifter in various examples.

[0006] Figure 2 FIG. is a circuit diagram of a level shifter in various examples.

[0007] Figure 3 FIG. is a graph of a current comparator output in various examples.

[0008] Figure 4 FIG. is a graph of a level shifter output in various examples.

[0009] Figure 5 FIG. is a table of level shifter output conditions in various examples.

[0010] Figure 6 FIG. is a circuit diagram of a level shifter in various examples.

[0011] Figure 7 FIG. is a block diagram of a level shifter in various examples.

[0012] Figure 8 FIG. is a circuit diagram of a level shifter in various examples.

[0013] Figure 9 FIG. is a circuit diagram of a level shifter in various examples.

[0014] Figure 10 FIG. is a set of graphs of voltage waveforms of a level shifter in various examples.

[0015] Identical reference numerals or other reference indicators are used in the drawings to indicate (functionally and / or structurally) identical or similar features. DETAILED DESCRIPTION

[0016] DC-DC converters typically use a level shifter with a gate driver inside the DC-DC converter. The level shifter is suitable for transforming logic signals between voltage supply domains. For example, a circuit may use voltage values of 1V and 0V to represent logic values 1 and 0 in a first domain respectively. Another circuit may use voltage values of 5V and 0V to represent logic values 1 and 0 in a second domain respectively. The level shifter shifts the level of a logic signal that switches between 1V and 0V in the first domain into a logic signal that switches between 5V and 0V in the second domain, which is called a low-to-high level shifter.

[0017] The DC-DC converter may have a floating voltage supply for the high-side gate driver in the converter. The level shifter in the DC-DC converter may also have a high side and a low side. The level shifter in the DC-DC converter includes an output latch, and if the input signal information is lost due to transient switching, the output latch can hold the output signal of the level shifter. If the high-side gate driver voltage domain switches to a different voltage domain, parasitic capacitance generates a common-mode current in the level shifter. If the common-mode current (e.g., switching noise) is large enough, the noise can transform the output signal of the level shifter during the time when the output is stable.

[0018] In the examples herein, the common-mode signal coupled to the output latch of the low-to-high level shifter is canceled or rejected to maintain the state of the output latch. The level shifter architecture described herein creates an input dead zone that rejects the common-mode signal. The dead zone systematically blocks the noise provided to the output latch of the level shifter. If the difference between two input currents falls into the dead zone, a cross-coupled switch (e.g., a transistor) isolates and / or disconnects the output latch of the level shifter from the current comparator inside the level shifter. The dead zone provides hysteresis, which prevents the output latch from switching until the input signal provided to the level shifter is strong enough to overcome the hysteresis. The common-mode current is not strong enough to overcome the dead zone, and thus the level shifter only switches when an appropriate input signal is supplied to the level shifter. The size of the dead zone can be scaled to any suitable value by adjusting the ratio of the sizes of certain transistors in the level shifter.

[0019] In another example, the common-mode current can be canceled by using a common-mode current sensing branch and a current mirror. This example can help the level shifter shift faster in response to changes in the input signal supplied to the level shifter. This example can also help prevent the current comparator in the level shifter from being saturated by a large common-mode current. In another example, a high-to-low level shifter may include the architecture described herein on the low side of the level shifter. The architecture in this example operates similarly to the low-to-high level shifter described above. In some examples, the high-to-low level shifter may also include a common-mode current sensing branch and a current mirror to cancel the common-mode current.

[0020] Figure 1 This is a block diagram of the level shifter 100 in various examples in this document. In one example, the level shifter 100 is a low-to-high level shifter. The level shifter 100 includes a high side 102 coupled to a low side 104. The high side 102 includes a current comparator 106, isolation circuitry 108, a latch 110, and a buffer 112. The buffer 112 has a first output 114A and a second output 114B. The first output 114A provides an output signal SIG_OUT, and the second output 114B provides an inverted output signal In one example, the output signal can be provided to the gate driver of a DC-DC converter. In this example, the low side 104 is coupled to an optional copy branch 116. The low side 104 also has two inputs, V SET input 118 and V RESET input 120.

[0021] In the operation of the example, a pulse signal is provided to V SET input 118 and / or V RESET input 120 to transform the output of the latch 110, and then the output is provided at the first output 114A and the second output 114B. Then the signals (SIG_OUT and ) at the first output 114A and the second output 114B are provided to the gate driver to switch the DC-DC converter ( Figure 1 not shown in the figure). If the signals at both V SET input 118 and V RESET input 120 are low, the output of the latch 110 holds its value. The level shifter 100 operates by receiving signals at V SET input 118 and V RESET input 120 and performing a current comparison with the current comparator 106 in the high side 102. The circuitry within the current comparator 106 compares the currents generated by the signals provided at V SET input 118 and V RESET input 120. Based on these currents, the current comparator 106 can provide a signal to the latch 110 to switch the output of the latch 110 as guided by the V SET and V RESET signals provided to the low side 104.

[0022] In the example level shifter architecture described herein, the isolation circuitry 108 resides between the current comparator 106 and the latch 110. The isolation circuitry 108 allows only one side of the circuitry within the latch 110 to be pulled down by the current comparator 106 at a time. Additionally, if V SET or VRESET If none of the signals have been received by the low side 104 yet, the isolation circuit system 108 disconnects the current comparator 106 from the latch 110. Thus, if signals are received at the V SET input 118 and the V RESET input 120, only the output of the level shifter 100 can be transformed. Small variations in voltage or current, such as common-mode current or parasitic current and voltage within the level shifter 100, are not strong enough to overcome the hysteresis provided by the isolation circuit system 108. The amount of hysteresis (e.g., dead zone) can be set based on the ratio of the transistors within the current comparator 106, as described below.

[0023] In another example, an optional component replication branch 116 can be added to the level shifter 100. In some examples, the level shifter 100 can typically switch or have a high slew rate. This can generate a high common-mode current. If the common-mode current is high, the ratio between the currents compared by the current comparator 106 can be highly skewed in one direction based on the values of the currents being compared. In an example, the current comparator 106 can also be saturated by a large common-mode current. The replication branch 116 replicates the common-mode current and helps restore the ratio of the currents compared by the current comparator 106, so an accurate comparison can be performed. In one example, the replication branch 116 can completely subtract the common-mode current before the common-mode current reaches the current comparator 106.

[0024] The following Figure 2 and 6 are circuit diagrams of the level shifter 100 that include Figure 1 detailed circuit systems not shown in the figures. Figure 2 An example without the replication branch 116 is provided, and Figure 6 an example including the replication branch 116 is provided. Detailed example operations of the circuit systems within the level shifter 100 are provided with respect to the figures below.

[0025] Figure 2 are circuit diagrams of the level shifter 200 in various examples herein. The operation of the level shifter 200 is described below in conjunction with Figure 3 and 4 and 5. The level shifter 200 includes many of the components described above with respect to Figure 1 . The level shifter 200 includes a high side 102, a low side 104, a current comparator 106, an isolation circuit system 108, a latch 110, and a buffer 112. The level shifter 200 also includes a first output 114A and a second output 114B, a V SET input 118 and a V RESET input 120.

[0026] The level shifter 200 includes a voltage rail VSSL 202, a voltage rail VDDL 204, a voltage rail VSSH 205, and a voltage rail VDDH 206. There can be a voltage difference between VDDL 204 and VDDH 206. In one example, VSSH 205 and VDDH 206 can have voltages with approximately fixed voltages at both ends, while VSSL 202 and VDDL 204 can have voltages with approximately fixed voltages at both ends. However, in some examples, the voltage difference between VDDL 204 and VDDH 206 may fluctuate. The low side 104 includes a transistor 208 having a gate coupled to the V SET input 118. The transistor 210 has a gate coupled to the V RESET input 120. The transistor 208 has a source coupled to VSSL 202 and a drain coupled to the transistor 212. The transistor 210 has a source coupled to VSSL 202 and a drain coupled to the transistor 214. In one example, the transistors 208, 210, 212, and 214 can be n-channel transistors.

[0027] The transistor 212 includes a gate coupled to VDDL 204, a source coupled to the transistor 208, and a drain coupled to the transistor 216. The transistor 214 includes a gate coupled to VDDL 204, a source coupled to the transistor 210, and a drain coupled to the transistor 220.

[0028] In this example, the current comparator 106 resides within the high side 102. The current comparator 106 includes a first current mirror that includes transistors 216 and 218. The current comparator 106 includes a second current mirror that includes transistors 220 and 222. The current comparator 106 includes a third current mirror that includes transistors 224 and 226. The current comparator 106 includes a fourth current mirror that includes transistors 228 and 230. The current comparator 106 also includes transistors 232 and 234. The current comparator 106 includes a node V1 236 and a node V2 238.

[0029] In this example, the transistor 216 has a gate coupled to the gate of the transistor 218, a source coupled to VDDH 206, and a drain coupled to the transistor 212 and coupled to the gates of the transistors 216 and 218. The transistor 218 has a source coupled to VDDH 206 and a drain coupled to the transistor 224. In one example, the transistors 216 and 218 can be p-channel transistors.

[0030] Transistor 220 has a gate coupled to the gate of transistor 222, a source coupled to VDDH 206, and a drain coupled to transistor 214 and to the gates of transistors 220 and 222. Transistor 222 has a source coupled to VDDH 206 and a drain coupled to transistor 228. In one example, transistors 216 and 218 may be p-channel transistors.

[0031] Transistor 224 has a gate coupled to the gate of transistor 226 and to the drain of transistor 224. Transistor 224 has a source coupled to VSSH 205. Transistor 226 has a source coupled to VSSH 205 and a drain coupled to node V2238. In one example, transistors 224 and 226 have a 1:N ratio respectively. In one example, transistors 224 and 226 may be n-channel transistors.

[0032] Transistor 228 has a gate coupled to the gate of transistor 230 and to the drain of transistor 228. Transistor 228 has a source coupled to VSSH 205. Transistor 230 has a source coupled to VSSH 205 and a drain coupled to node V1236. In one example, transistors 228 and 230 have a 1:N ratio respectively. In one example, transistors 228 and 230 may be n-channel transistors.

[0033] Transistors 232 and 234 are cross-coupled. Transistor 232 has a gate coupled to the gates of transistors 220 and 222. Transistor 232 has a source coupled to VDDH 206 and a drain coupled to node V2 238. Transistor 234 has a gate coupled to the gates of transistors 216 and 218. Transistor 234 has a source coupled to VDDH 206 and a drain coupled to V1 236. In one example, transistors 232 and 234 may be p-channel transistors.

[0034] High-side 102 also includes isolation circuitry 108. In this example, isolation circuitry 108 includes cross-coupled transistors 240 and 242. Transistor 240 includes a gate coupled to the source of transistor 242, a source coupled to node V2238, and a drain coupled to latch 110. Transistor 242 includes a gate coupled to the source of transistor 240, a source coupled to node V1236, and a drain coupled to latch 110. In one example, transistors 240 and 242 may be n-channel transistors. In other examples, isolation circuitry 108 may include different circuitry and perform the functions described herein.

[0035] The high side 102 also includes a latch 110. The latch 110 includes inverters 244 and 246. The latch 110 also includes nodes 248 and 250. The input of inverter 244 is coupled to node 250 and the output of inverter 246. The output of inverter 244 is coupled to node 248 and the input of inverter 246. The input of inverter 246 is coupled to node 248 and the output of inverter 244. The output of inverter 246 is coupled to node 250 and the input of inverter 244.

[0036] Nodes 248 and 250 are coupled to a buffer 112. In this example, buffer 112 includes inverters 252 and 254, but in other examples, other circuitry may act as the buffer. Buffer 112 has a first output 114A that provides an output signal SIG_OUT, and a second output 114B that provides an inverted output signal

[0037] The level shifter 200 also includes various currents as Figure 2 shown. I CM1 256 is the common-mode current flowing to ground 260. I CM2 258 is the common-mode current flowing to ground 260. I SET 262 is the current flowing through transistors 208 and 212. I RESET is the current flowing through transistors 210 and 214. I SET′ 266 is I CM1 256 and I SET 262 combined. I RESET′ 268 is I CM2 258 and I RESET 264 combined. I SET′ 270 is the current flowing from transistor 234 to node V1 236. I RESET′ 272 is the current flowing from transistor 232 to node V2 238. NI RESET′ 274 is the current flowing from node V1236 to transistor 230. NI SET′ 276 is the current flowing from node V2 238 to transistor 226. Current 278 flows from transistor 240 in isolation circuitry 108 to node V2238 and has NI SET′ -I RESET′ (e.g., current 276 minus current 272) value. Current 280 flows from transistor 242 in isolation circuitry 108 to node V1 236 and has NI RESET′ -I SET′ (e.g., current 274 minus current 270) value.

[0038] In operation, at V SETAt input 118 or at V RESET Apply a high pulse at input 120 to set or reset the SIG_OUT signal (e.g., at the first output 114A and the second output 114B). If V SET input 118 and V RESET input 120 both have low signals, then SIG_OUT retains its current value. Voltage transform latches 110 are generated at nodes V1 236 and V2 238, and thus transform the SIG_OUT value. If the circuit components match, the common-mode currents I CM1 256 and I CM2 258 match. However, due to process variations and other variations, the common-mode currents may not match. Therefore, if the level shifter 200 does not include the isolation circuitry 108, the mismatched common-mode currents may cause the voltage transform latches 110 at node V1 236 or V2 238. The isolation circuitry 108, the N:1 ratios of transistors 226 and 224, and the N:1 ratios of transistors 230 and 228 create a comparator dead zone that disconnects nodes V1 236 and V2 238 from the latch 110 if the voltages at both nodes V1 236 and V2 238 are low. The output of the level shifter 200 changes only when the difference between I SET 262 and I RESET 264 is high enough, which occurs only when a high pulse is applied at input 118 or at V SET input 118 or at V RESET input 120. Additional description of the operation of the current comparator 106 is provided below.

[0039] The current comparator 106 is configured to compare I SET 262 with I RESET 264 to determine whether a pulse has been applied to V SET input 118 or V RESET input 120. If a pulse has been applied to either input, the current comparator 106 provides an output signal at node V1 236 or node V2 238, and this output signal is applied to the latch 110 via the isolation circuitry 108 to transform the latch 110. As an example of operation, if a high pulse is applied at V SET input 118 and the signal at V RESET input 120 is low, then I SET 262 is higher than I RESET 264. I SET′ 266 (the combination of I CM1 256 and I SET 262) is higher than I RESET′ 268 (which is I CM2 258 and IRESET (a combination of 264).

[0040] Current I SET′ 266 and I RESET′ Both 268 and I are mirrored in the current comparator 106. The first current mirror (transistors 216 and 218) mirrors I SET′ 266, and this current is again mirrored by the third current mirror (transistors 224 and 226). The third current mirror also has an N:1 ratio, so the current flowing through transistor 226 is NI SET′ 276, which is N times larger than I SET′ 266. Similarly, the second current mirror (transistors 220 and 222) mirrors I RESET′ 268, and this current is again mirrored by the fourth current mirror (transistors 228 and 230). The fourth current mirror also has an N:1 ratio, so the current flowing through transistor 230 is NI RESET′ 274, which is N times larger than I RESET′ 268.

[0041] The gate-connected transistors 232 and 234 in the current comparator 106 are coupled to the first current mirror and the second current mirror. The gate of transistor 232 is coupled to the second current mirror (transistors 220 and 222). The second current mirror mirrors the current I RESET′ 268, so I RESET′ 268 is also provided by transistor 232 to node V2 238. The gate of transistor 234 is coupled to the first current mirror (transistors 216 and 218). The first current mirror mirrors the current I SET′ 266, so I SET′ 266 is also provided by transistor 234 to node V1 236.

[0042] As shown in the level shifter 200, the current comparator 106 compares I RESET' 272 (which is the mirror image of I RESET′ 268) with NI SET′ 276. In addition, the current comparator 106 compares I SET′ 270 (which is the mirror image of I SET′ 266) with NI RESET′ 274. Nodes V1 236 and V2 238 provide the outputs of the current comparator 106. These outputs are provided to the isolation circuitry 108, which then passes appropriate signals to the latch 110 to flip the latch depending on the outputs. In this example, V SET input 118 receives a high pulse, so NI SET 276 at node V2 238 is greater than I RESET′is much larger than 272. The voltage at node V2 238 is pulled down. The voltage at node V1 236 is higher because node V1 236 supplies current I SET′ 270 and NI RESET′ are compared with 274. Since node V2 238 has a lower voltage and node V1 236 has a higher voltage, the gate-to-source voltage V of transistor 240 in isolation circuit system 108 GS is high. This high V GS turns on transistor 240, and node 248 in latch 110 is pulled down. Since node 248 is pulled down, the SIG_OUT signal at first output 114A goes high. Thus, in this example, level shifter 200 is set. In this example, transistor 240 is the first transistor, and the gate of transistor 240 is the first control terminal. Transistor 240 is coupled between the first terminal (node 248) of latch 110 and a first current mirror (e.g., a current mirror including transistors 224 and 226).

[0043] Conversely, in the opposite case, V RESET input 120 receives a high pulse, so NI at node V1 236 RESET′ is much larger than I SET′ at 236. The voltage at node V1 236 is pulled down. The voltage at node V2 238 is higher because node V2 238 supplies current I RESET′ 272 and NI SET′ are compared with 276. Since node V1 236 has a low voltage and node V2 238 has a higher voltage, the gate-to-source voltage V of transistor 242 in isolation circuit system 108 GS is high. This high V GS turns on transistor 242, and node 250 in latch 110 is pulled down. Since node 250 is pulled down, the signal at second output 114B goes high. Thus, level shifter 200 is reset. In this example, transistor 242 is the second transistor, and the gate of transistor 242 is the second control terminal. Transistor 242 is coupled between the second terminal (node 250) of latch 110 and a second current mirror (e.g., a current mirror including transistors 228 and 230).

[0044] In level shifter 200, if at V SET input 118 or at V RESETIf no pulse is received at input 120, the voltage values at nodes V1 236 and V2 238 are low. If the voltages at nodes V1 236 and V2 238 are low, the gate voltages at transistors 240 and 242 in isolation circuit system 108 are also low. These low gate voltages turn off transistors 240 and 242, which disconnects or isolates latch 110 from current comparator 106. As described below, due to the scaling factor N of transistors 224, 226 and transistors 228, 230, the current I CM1 256 and I CM2 caused by the difference between 258 is such that the small variations in current I SET′ 266 and I RESET′ 268 are not sufficient to overcome the dead zone or hysteresis in level shifter 200. Therefore, the output of level shifter 200 will not change in response to noise in the circuit system, but will only change when a large enough signal is provided at V SET input 118 or at V RESET input 120. A high signal at V SET input 118 or V RESET input 120 results in a high ratio between I SET 262 and I RESET 264, which allows the output of level shifter 200 to change.

[0045] Figure 3 Graph 300 is the output of current comparator 106 for various examples in this article. In graph 300, the x-axis represents the ratio between I SET′ 266 and I RESET′ 268. The y-axis represents the output of current comparator 106, which is represented by a high or low signal at node V1 236 or node V2 238.

[0046] As shown in graph 300, if the ratio between I SET′ 266 and I RESET′ 268 is 1:1, the output of current comparator 106 is low. If the ratio between I SET′ 266 and I RESET′ 268 becomes N or greater in response to a pulse provided at V SET input 118, the voltage at node V1 236 goes high. As described above, the high voltage at node V1 236 turns on transistor 240 in isolation circuit system 108, pulls node 248 low, and the SIG_OUT signal at first output 114A goes high.

[0047] In another example, if the ratio between I SET′ 266 and I RESET′ 268 changes in response to a pulse provided at VRESET If the pulse provided at input 120 becomes 1 / N or less, the voltage at node V2 238 goes high. As described above, the high voltage at node V2 238 turns on transistor 242 in isolation circuit system 108, pulling node 250 low, and the signal at the second output 114B goes high (causing SIG_OUT to go low).

[0048] Figure 4 Graph 400 is the output of level shifter 200 for various examples in this document. In graph 400, the x-axis represents the ratio between I SET′ 266 and I RESET′ 268. The y-axis represents the output of the level shifter, which is indicated by a high or low signal at the first output 114A. As described above with respect to Figure 3 if the ratio between I SET′ 266 and I RESET′ 268 becomes N or greater in response to a pulse provided at V SET input 118, then SIG_OUT goes high. If the ratio between I SET′ 266 and I RESET′ 268 becomes 1 / N or less in response to a pulse provided at V RESET input 120, then SIG_OUT goes low. If the ratio between I SET′ 266 and I RESET′ 268 is between 1 / N and N, then SIG_OUT will maintain its current value, which is represented by the HOLD region 402 in graph 400.

[0049] As shown in graph 400, the size of the HOLD region 402 can be increased or decreased by changing the value of N. N is the ratio between transistors 224, 226 and 228, 230 as described above. A large N provides a large hold region 402, and a stronger signal is required at V SET input 118 or at V RESET input 120 to change the level shifter 200. A large N provides a large amount of protection against accidental changes due to noise, common-mode current, etc. A smaller N value provides a smaller hold region 402, and a relatively weaker signal at V SET input 118 or V RESET input 120 can be suitable for changing the level shifter 200. Compared to a larger N, a smaller N can provide less protection against accidental changes, but can allow for changing with a weaker input signal received at V SET input 118 or at V RESET input 120.

[0050] Figure 5Table 500 for the output conditions of the level shifter 200 in various examples in this document. Table 500 has four columns 502, 504, 506, and 508. The first column 502 is the input condition of the current comparator 106. The input condition of the current comparator 106 is represented by the ratio between I SET′ 266 and I RESET′ 268 with respect to N. The second column 504 is the voltage value at node V1 236. The third column 506 is the voltage value at node V2 238. The fourth column 508 is the value of the output signal SIG_OUT.

[0051] In the first example, the ratio between I SET′ 266 and I RESET′ 268 is greater than N (e.g., I SET / I RESET > N). This occurs if a pulse is received at V SET input 118. In this example, the voltage at node V1 236 is high, the voltage at node V2 238 is low, and the output signal SIG_OUT becomes high.

[0052] In the second example, the ratio between I RESET′ 268 and I SET′ 266 is greater than N (e.g., I RESET / I SET > N). This occurs if a pulse is received at V RESET input 120. In this example, the voltage at node V1 236 is low, the voltage at node V2 238 is high, and the output signal SIG_OUT becomes low.

[0053] In the third example, the ratio between I SET′ 266 and I RESET′ 268 is between 1 / N and N (e.g., 1 / N < I SET / I RESET < N). This ratio represents the dead zone where no pulse has been received at V SET input 118 or at V RESET input 120. In this example, the voltage at node V1 236 is low (or high impedance, HiZ), the voltage at node V2 238 is low (or high impedance, HiZ), and the output signal SIG_OUT maintains its current value. In the case of this ratio between I SET′ 266 and I RESET′ 268, the output signal SIG_OUT of the level shifter does not change in response to common-mode noise or other noise. A pulse is required at V SET input 118 or V RESETInput pulses at input 120 are used to change the value of SIG_OUT. Thus, Table 500 shows the advantages of the dead time generated by isolation circuit system 108 and transistor ratio N.

[0054] Figure 6 Circuit diagram of level shifter 600 with replication branch 116 for various examples in this document. Level shifter 600 includes many components described above with respect to Figure 1 and 2 and like reference numerals represent like components. Level shifter 600 includes high side 102, low side 104, current comparator 106, isolation circuit system 108, latch 110, and buffer 112. Level shifter 600 also includes first output 114A and second output 114B, V SET input 118 and V RESET input 120.

[0055] Level shifter 600 operates similar to level shifter 200 described above with respect to Figure 2 . Thus, the detailed description of the operation of high side 102 and low side 104 within level shifter 600 is omitted herein. However, level shifter 600 also includes replication branch 116. Replication branch 116 may be applicable to level shifters that switch frequently or have a high slew rate. In those cases, high common-mode current may occur. In the case of high common-mode current, the value of I SET 262 may vary significantly from the value of I SET′ 266. Similarly, the value of I RESET 264 may vary significantly from the value of I RESET′ 268. High common-mode current may interfere with the ratio between I SET 262 and I RESET 264. In the case of replication branch 116, a current may be added to adjust the ratio between I SET 262 and I RESET 264.

[0056] The replica branch 116 includes transistors 602, 604, 606, and 608. Transistor 602 has a source coupled to a gate, and the gate is also coupled to the gate of transistor 214. The drain of transistor 602 is coupled to the drain of transistor 604. Transistor 604 has a gate coupled to the drain and a source coupled to VDDH 206. The gate of transistor 604 is also coupled to the gate of transistor 606. Transistor 606 has a gate coupled to the gates of transistors 604 and 608, a source coupled to VDDH 206, and a drain coupled to the drain of transistor 214. Transistor 608 has a gate coupled to the gate of transistor 606, a source coupled to VDDH 206, and a drain coupled to the drain of transistor 212.

[0057] In an example, transistors 606 and 608 have a size ratio of M:1 compared to transistor 604. Transistors 606 and 608 can be sized by a factor M to adjust how much common-mode current I CM is cancelled. In some examples, M is 1. In other examples, M can be set higher to compensate for process, voltage, temperature, and manufacturing variations. If M is set too high, then I SET 262 may be much higher than I SET′ 266, and in some examples, I SET′ 266 may not be high enough for proper operation of current comparator 106. Thus, in many examples, a value of M that is 1 or slightly higher than 1 is useful.

[0058] The replica branch 116 also includes currents I CM 610, I CM 612, I CMxM 614, and I CMxM 616. In an example, I CM2 258 is mirrored by transistor 602 to produce I CM 610. I CM 610 is equal to I CM 612. Transistors 604 and 606 mirror I CM 612 to produce I CMxM 614. I CMxM 614 has a value that is I CM 612 multiplied by the value of the transistor ratio M. Transistor 608 also operates as a current mirror to produce I CMxM 616. I CMxM 614 is provided by transistor 606 to the I RESET branch of the low side 104 that includes transistors 210 and 214. In one example, I CMxM 614 can fully or partially cancel I CM2258, in response to this, I RESET 264 is approximately equal to I RESET′ 268. Similarly, I CMxM 616 is provided by transistor 608 to the low side 104 including transistors 208 and 212 SET branch. In one instance, I CMxM 616 can completely or partially cancel I CM1 256, in response to this, I SET 262 is approximately equal to I SET′ 266.

[0059] In one instance, transistor 602 is a replica of transistors 212 and 214. These transistors can have similar parasitic capacitances, which provides better cancellation of common-mode current. In one instance, these three transistors can be high-voltage transistors having a relatively high capacitance at the drain terminal.

[0060] Figure 7 is a block diagram of a level shifter 700 for various examples herein. In one instance, level shifter 100 is a high-to-low level shifter. Level shifter 700 includes a high side 702 coupled to a low side 704. The low side 704 includes a current comparator 706, an isolation circuitry 708, a latch 710, and a buffer 712. The buffer 712 has a first output 714A and a second output 714B. The first output 714A provides an output signal SIG_OUT, and the second output 714B provides an inverted output signal In one instance, the output signal can be provided to the gate driver of a DC-DC converter. In this instance, the high side 702 is coupled to an optional replica branch 716. The high side 702 also has two inputs, V SET input 718 and V RESET input 720.

[0061] Level shifter 700 operates similar to level shifter 100 described above, except that level shifter 700 provides the output at the low side 704 instead of at the high side 702. The current comparator 706, the isolation circuitry 708, the latch 710, the buffer 712, and the replica branch 716 operate similar to their corresponding components described above with respect to Figure 1 , 2 and 6.

[0062] Described below Figure 8 and 9 are circuit diagrams of level shifter 700 including detailed circuitry not shown in Figure 7 . Figure 8 An instance without the replica branch 716 is provided, and Figure 9Provide an example that includes a copy branch 716.

[0063] Figure 8 FIG. is a circuit diagram of a level shifter 800 for various examples in this document. The level shifter 800 includes many components described above with respect to Figure 7 . The level shifter 800 includes a high side 702, a low side 704, a current comparator 706, an isolation circuitry 708, a latch 710, and a buffer 712. The level shifter 800 also includes a first output 714A and a second output 714B, a V SET input 718 and a V RESET input 720.

[0064] The level shifter 800 includes voltage rails VSSL 822, VDDL 824, VSSH 826, and VDDH 828. The level shifter 800 also includes transistors 830, 832, 834, and 836 in the high side 702. Transistor 830 includes a gate coupled to the V SET input 718, a source coupled to VDDH 828, and a drain coupled to the source of transistor 834. Transistor 832 includes a gate coupled to the V RESET input 720, a source coupled to VDDH 828, and a drain coupled to the source of transistor 836. Transistor 834 includes a gate coupled to VSSH 826, a source coupled to the drain of transistor 830, and a drain coupled to the drain of transistor 838 in the low side 704. Transistor 836 includes a gate coupled to VSSH 826, a source coupled to the drain of transistor 832, and a drain coupled to the drain of transistor 844 in the low side 704. In some examples, transistors 830, 832, 834, and 836 may be p-channel transistors. Transistors 830, 832, 834, and 836 operate similar to transistors 208, 210, 212, and 214 described above with respect to Figure 2 , and thus the detailed operation of these transistors is omitted herein.

[0065] The level shifter 100 includes a current comparator 706 in the low side 704. The current comparator 706 includes transistors 838 and 840 that operate as a current mirror. Transistor 838 includes a gate that is coupled to the gate of transistor 840 and to the drain of transistor 838. Transistor 838 includes a source that is coupled to VSSL 822. Transistor 840 includes a gate that is coupled to the gates of transistors 838 and 842, a source that is coupled to VSSL 822, and a drain that is coupled to the drain of transistor 850. In some instances, transistors 842 and 840 may have an N:1 ratio. Transistor 842 includes a source that is coupled to VSSL 822 and a drain that is coupled to node V2858. Transistors 838, 840, 842, and 850 are on the I SET 878 side of the current comparator 706. In one instance, transistors 838, 840, and 842 may be n-channel transistors. In one instance, transistor 850 may be a p-channel transistor.

[0066] The current comparator 706 includes transistors 844 and 846 that operate as a current mirror. Transistor 844 includes a gate that is coupled to the gate of transistor 846 and to the drain of transistor 844. Transistor 844 includes a source that is coupled to VSSL 822. Transistor 846 includes a gate that is coupled to the gates of transistors 844 and 848, a source that is coupled to VSSL 822, and a drain that is coupled to the drain of transistor 852. In some instances, transistors 848 and 846 may have an N:1 ratio. Transistor 848 includes a source that is coupled to VSSL 822 and a drain that is coupled to node V1 860. Transistors 844, 846, 848, and 852 are on the I RESET 880 side of the current comparator 706. In one instance, transistors 844, 846, and 848 may be n-channel transistors. In one instance, transistor 852 may be a p-channel transistor.

[0067] The current comparator 706 also includes transistors 850, 852, 854, and 846. In this example, the current comparator includes nodes V1 860 and V2 858. Transistor 850 has a gate coupled to the gate of transistor 856 and to the drain of transistor 850. Transistor 850 has a source coupled to VDDL 824. Transistor 852 has a gate coupled to the gate of transistor 854 and to the drain of transistor 852. Transistor 852 has a source coupled to VDDL 824. Transistor 854 has a gate coupled to the gate of transistor 852, a drain coupled to node V2 858, and a source coupled to VDDL 824. Transistor 856 has a gate coupled to the gate of transistor 850, a drain coupled to node V1 860, and a source coupled to VDDL 824. In one example, transistors 854 and 856 can be p-channel transistors.

[0068] The isolation circuitry 708 in the low side 704 includes two cross-coupled transistors 862 and 864. The gate of transistor 862 is coupled to the source of transistor 864 and to node V1 860. The source of transistor 862 is coupled to the gate of transistor 864 and to node V2 858. The drain of transistor 862 is coupled to node 870 in the latch 710. The gate of transistor 864 is coupled to the source of transistor 862 and to node V2 858. The source of transistor 864 is coupled to the gate of transistor 862 and to node V1 860. The drain of transistor 864 is coupled to node 872 in the latch 710. In the example, transistors 862 and 864 are p-channel transistors.

[0069] The latch 710 in the low side 704 includes inverters 866 and 868. The latch 710 also includes nodes 870 and 872. The input of inverter 866 is coupled to node 872 and to the output of inverter 868. The output of inverter 866 is coupled to node 870 and to the input of inverter 868. The input of inverter 868 is coupled to node 870 and to the output of inverter 866. The output of inverter 868 is coupled to node 872 and to the input of inverter 866.

[0070] Nodes 870 and 872 are coupled to the buffer 712. In this example, the buffer 712 includes inverters 874 and 876, but in other examples, other circuitry can act as the buffer. The buffer 712 has a first output 714A that provides an output signal SIG_OUT, and a second output 714B provides an inverted output signal

[0071] The level shifter 800 also includes current I SET 878, I RESET 880, I RESET882, I SET 884, NI SET 886 and NI RESET 888. Figure 8 also shows current 890 (NI SET -I RESET ) and 892 (NI RESET -I SET ) Also shows common-mode current I CM1 894 and I CM2 896. The level shifter 800 operates similarly to the level shifter 200 described above with respect to Figure 2 For example, the current comparator 706, isolation circuitry 708, latch 710, and buffer 712 operate similarly to their corresponding components, the current comparator 106, isolation circuitry 108, latch 110, and buffer 112, described above with respect to Figure 1 and 2 Therefore, a detailed description of this operation is omitted herein.

[0072] In one example, the current comparator 706 is configured to compare I SET 878 with I RESET 880 to determine whether a pulse has been applied to V SET input 718 or V RESET input 720. If a pulse has been applied to either input, the current comparator 706 provides an output signal at the V1 node 860 or V2 node 858, and this output signal is applied to the latch 710 via the isolation circuitry 708 to transform the latch 710.

[0073] Figure 9 is a circuit diagram of a level shifter 900 with a copy branch for various examples in this document. The level shifter 900 includes many of the components described above with respect to Figure 8 and like reference numerals represent like components. The level shifter 900 includes a high side 702, a low side 704, a current comparator 706, isolation circuitry 708, a latch 710, and a buffer 712. The level shifter 900 also includes a first output 714A and a second output 714B, a V SET input 718 and a V RESET input 720.

[0074] The level shifter 900 operates similarly to the level shifter 800 described above with respect to Figure 8 However, the level shifter 900 also includes a copy branch 716. The copy branch 716 operates similarly to the copy branch 116 described above with respect to Figure 6

[0075] The replica branch 716 can be applied to level shifters with frequent switching or high slew rate. In those cases, high common-mode current may occur. The high common-mode current may interfere with the ratio between I SET 878 and I RESET 880. In the case of the replica branch 716, a current can be added to adjust the ratio between I SET 878 and I RESET 880.

[0076] The replica branch 716 includes transistors 902, 904, 906, and 908. Transistor 902 has a source coupled to a gate, which is also coupled to the gate of transistor 836. The drain of transistor 902 is coupled to the drain of transistor 904. Transistor 904 has a gate coupled to the drain and a source coupled to VDDL 824. The gate of transistor 904 is also coupled to the gate of transistor 906. Transistor 906 has a gate coupled to the gates of transistors 904 and 908, a source coupled to VDDL 824, and a drain coupled to the drain of transistor 836. Transistor 908 has a gate coupled to the gate of transistor 906, a source coupled to VDDL 824, and a drain coupled to the drain of transistor 834.

[0077] In an example, transistors 906 and 908 have a size ratio of M:1 compared to transistor 904. Transistors 906 and 908 can be sized by a factor M to adjust how much common-mode current I CM is canceled. In some examples, M is 1. In other examples, M can be set higher to compensate for process, voltage, temperature, and manufacturing variations. In many examples, a value of M that is 1 or slightly higher than 1 is useful.

[0078] The replica branch 716 also includes currents I CM 910, I CM 912, I CMxM 914, and I CMxM 916. In an example, the common-mode current in the high side 702 is mirrored by transistor 602 to generate I CM 910. I CM 910 is equal to I CM 912. Transistors 904 and 906 mirror I CM 912 to generate I CMxM 914. I CMxM 914 has a value that is I CM 912 multiplied by the value of the transistor ratio M. Transistor 908 also operates as a current mirror to generate I CMxM 916. I CMxMI914 is provided by transistor 906 to high side 702 that includes transistors 832 and 836. RESET branch. In one instance, I CMxM 914 may fully or partially cancel the common mode current. Similarly, I CMxM 916 is provided by transistor 908 to high side 702 that includes transistors 830 and 834. SET branch. In one instance, I CMxM 916 may fully or partially cancel the common mode current.

[0079] In one instance, transistor 902 is a replica of transistors 834 and 836. These transistors may have similar parasitic capacitances, which provides better cancellation of the common mode current. In one instance, these three transistors may be high voltage transistors having a relatively high capacitance at the drain terminal.

[0080] Figure 10 A set of graphs 1000 of voltage waveforms of level shifters in various examples herein. In one instance, Figure 10 may include simulations of sets of voltage waveforms of level shifter 200.

[0081] Waveform 1002 represents the voltage difference (VDDH–VSSH) between VDDH 206 and VSSH 205. Waveform 1004 represents the voltage difference (V2-VSSH) between node V2 238 and VSSH 205. Waveform 1006 represents the voltage difference (V1-VSSH) between node V1 236 and VSSH 205. Thus, these voltages are shown in graph 1000 relative to VSSH.

[0082] Waveform 1008 represents the voltage difference between SIG_OUT and VSSH 205. Waveform 1010 represents VDDH 206, and waveform 1012 represents VSSH 205. Waveform 1014 represents the SET signal at V RESET input 118, while waveform 1016 represents the

[0083] In one instance, a pulse received at V SET input 118 or V RESET input 120 changes signal output SIG_OUT. Waveforms 1010 and 1012 show ringing caused by the switching converter. At approximate time t1, at V SETA pulse (waveform 1014) is received at input 118. This pulse causes the ringing shown in waveforms 1010 and 1012, which may be caused by common-mode noise. Some ringing is also seen in waveform 1002, which is the voltage difference between VDDH 206 and VSSH 205. At time t1, after the pulse is received, the voltage at node V2 238 goes low (waveform 1004), and the voltage at node V1 236 goes high. As described above, this voltage difference between node V1 236 and V2 238 causes isolation circuitry 108 to provide a signal to latch 110 to set the SIG_OUT signal. Thus, at time t1, SIG_OUT goes high, as shown in waveform 1008.

[0084] In another example, at time t2, at V RESET A pulse (waveform 1016) is received at input 120. This pulse causes additional ringing shown in waveforms 1010 and 1012, which may be caused by common-mode noise. At time t2, some ringing is also seen in waveform 1002. At time t2, after the pulse is received, the voltage at node V2 238 goes high (waveform 1004), and the voltage at node V1 236 goes low. As described above, this voltage difference between node V1 236 and V2 238 causes isolation circuitry 108 to provide a signal to latch 110 to reset the SIG_OUT signal. Thus, at time t2, SIG_OUT goes low, as shown in waveform 1008. Other example circuit architectures of the level shifters described herein behave similarly to that shown in graph 1000.

[0085] In an existing architecture, the common-mode current at the input of a current comparator can be coupled to the output latch. The examples described herein add an input dead zone to the current comparator to reject this common-mode noise. Rejecting common-mode noise as described herein can prevent the output latch from being disturbed by the noise. The output latch can be designed to be more sensitive or faster in response to actual set and reset inputs. Using cross-coupled transistors to decouple the output latch from the current comparator is a simple and effective solution. The cross-coupled transistors allow the current comparator to pull down one side of the output latch in response to the input current difference reaching a programmed threshold. This example isolates the output latch from low differential input noise caused by power switching and ringing. In some examples, a replica branch that helps the current comparator avoid saturation can be used to cancel the common-mode current.

[0086] In the examples herein, if there is no differential input current or if there is a low differential input current, the output latch is decoupled or isolated from the input of the level shifter. Accordingly, the output latch can be designed to be smaller or weaker such that its state can be quickly flipped by an expected set or reset input pulse. In some examples, the level shifter architecture described herein can be used to reduce propagation delay.

[0087] The examples herein can be implemented in various end device applications, including consumer devices such as battery chargers and display drivers. The examples can also be applicable to any DC-DC converter having a floating gate driver.

[0088] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is directly connected to device B; or (b) in a second example, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, and thus device B is controlled by device A via the control signal provided by device A.

[0089] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer to perform the function, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0090] A circuit or device described herein as including certain components can actually be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) can actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and can be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0091] Although certain components may be described herein as belonging to a particular process technology, these components may be interchanged with components of other process technologies. The circuits described herein may be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0092] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. In this description, unless otherwise stated, "about," "approximate," or "substantially" before a parameter means within + / - 10% of the stated parameter.

[0093] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. An electric level shifter, comprising: A low side having a first input and a second input; And A high side comprising: A latch having a first terminal and a second terminal; A current comparator comprising a first current mirror and a second current mirror; and An isolation circuit system comprising a first transistor and a second transistor, wherein the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

2. The electric level shifter according to claim 1, further comprising: An output buffer coupled to the latch, wherein the output buffer has a first output and a second output.

3. The electric level shifter according to claim 1, wherein the first current mirror is coupled to the first input, and wherein the second current mirror is coupled to the second input.

4. The electric level shifter according to claim 1, wherein the latch comprises a first inverter and a second inverter.

5. The electric level shifter according to claim 1, wherein the first current mirror comprises a third transistor and a fourth transistor, and the third transistor and the fourth transistor have an N:1 size ratio.

6. The electric level shifter according to claim 5, wherein the second current mirror comprises a fifth transistor and a sixth transistor, and the fifth transistor and the sixth transistor have an N:1 size ratio.

7. An electric level shifter, comprising: A high side having a first input and a second input; And A low side comprising: A latch having a first terminal and a second terminal; A current comparator comprising a first current mirror and a second current mirror; and An isolation circuit system comprising a first transistor and a second transistor, wherein the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

8. The electric level shifter according to claim 7, wherein the first current mirror is coupled to the first input, and wherein the second current mirror is coupled to the second input.

9. The electric level shifter according to claim 7, wherein the first current mirror comprises a third transistor and a fourth transistor, and the third transistor and the fourth transistor have an N:1 size ratio.

10. The electric level shifter according to claim 9, wherein the second current mirror comprises a fifth transistor and a sixth transistor, and the fifth transistor and the sixth transistor have an N:1 size ratio.

11. An electric level shifter, comprising: A low side having a first input and a second input configured to receive one or more signals for switching an output of the electric level shifter; And A high side comprising: A latch having a first terminal and a second terminal; A current comparator including a first current mirror and a second current mirror, wherein the current comparator is configured to perform a current comparison between a first current and a second current; and An isolation circuitry including a first transistor and a second transistor, wherein the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror, and wherein the isolation circuitry is configured to isolate the current comparator from the latch.

12. The level shifter according to claim 11, wherein the latch is configured to provide the output of the level shifter based at least in part on the current comparison.

13. The level shifter according to claim 11, further comprising: An output buffer coupled to the latch, wherein the output buffer has a first output and a second output.

14. The level shifter according to claim 11, wherein the first current mirror is coupled to the first input, and wherein the second current mirror is coupled to the second input.

15. The level shifter according to claim 11, wherein the first current mirror includes a third transistor and a fourth transistor having an N:1 size ratio.

16. The level shifter according to claim 15, wherein the second current mirror includes a fifth transistor and a sixth transistor having an N:1 size ratio.

17. The level shifter according to claim 16, wherein the isolation circuitry is configured to isolate the current comparator from the latch based at least in part on the current comparison and the N:1 size ratio.

18. The level shifter according to claim 17, wherein a larger N:1 ratio increases the range of the current comparison, wherein the isolation circuitry isolates the current comparator from the latch.

19. The level shifter according to claim 11, wherein the current comparator is configured to reject common-mode noise based on a ratio between the first current and the second current.

20. The level shifter according to claim 11, further comprising: A copy branch configured to copy a common-mode current and provide the copied common-mode current to the low side.

21. The level shifter according to claim 20, wherein the copy branch is configured to subtract the common-mode current from the first current and the second current.

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