Low-stress silicon-based pressure sensor chip and processing method

Abstract

The invention relates to the technical field of pressure sensor chips, in particular to a low-stress silicon-based pressure sensor chip and a processing method thereof, and the chip comprises an n-type silicon substrate, a p-type pressure sensitive resistor, a passivation layer, a metal electrode layer and a bonding piece; the p-type pressure sensitive resistor is arranged in a resistor placement groove in the top of the n-type silicon substrate; the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is arranged on the n-type silicon substrate and the p-type pressure sensitive resistor, and the silicon nitride layer is arranged on the silicon dioxide layer; the silicon dioxide layer and the silicon nitride layer are provided with an electric contact area and a stress release area. The electric contact area is arranged at the outer end of the top of the p-type pressure sensitive resistor, and the metal electrode layer is arranged on the electric contact area; a silicon cup is arranged at the bottom of the n-type silicon substrate, so that the n-type silicon substrate in an area above the silicon cup forms a pressure sensitive diaphragm, and the stress release area is arranged on the upper surface of the pressure sensitive diaphragm, so that the problem that the output and the reliability of the pressure sensor chip are influenced by introduction of a passivation layer is solved.

Description

Technical Field

[0001] The present application relates to the technical field of pressure sensor chips, and particularly to a low-stress silicon-based pressure sensor chip and a processing method thereof. Background Art

[0002] Pressure sensor chips based on microelectromechanical system (MEMS) technology have the characteristics of high sensitivity, low cost, reliable performance, and mass production, and are widely used in fields such as aerospace, process industry, and intelligent healthcare.

[0003] In the related art, MEMS pressure sensor chips are mainly made of silicon materials, and PN junction isolation technology is used to achieve electrical isolation between the pressure-sensitive resistor and the substrate. In order to enhance the anti-interference ability of the chip to the external environment, such as water vapor, mechanical scratches, particle contamination, etc., a passivation layer, including a silicon dioxide layer and a silicon nitride layer, is usually prepared on the chip surface to ensure the stable electrical performance of the chip.

[0004] However, the introduction of the passivation layer will also bring negative effects. Due to the different thermal expansion coefficients of silicon and the passivation layer, at different temperatures, variable film stress will be generated, and the film stress is transmitted to the pressure-sensitive resistor, resulting in a change in the resistance value, seriously affecting the output and reliability of the pressure sensor chip. For low-range pressure-sensitive chips, the film stress problem is more prominent. Summary of the Invention

[0005] The present application provides a low-stress silicon-based pressure sensor chip and a processing method thereof to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip.

[0006] The first aspect of the present application provides a low-stress silicon-based pressure sensor chip, including: an n-type silicon substrate, a p-type pressure-sensitive resistor, a passivation layer, a metal electrode layer, and a bonding component; The p-type pressure-sensitive resistor is disposed in a resistor placement groove at the top of the n-type silicon substrate, and the p-type pressure-sensitive resistor and the n-type silicon substrate are electrically isolated through a PN junction, and the upper surface of the p-type pressure-sensitive resistor is in the same plane as the n-type silicon substrate; The passivation layer includes a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is disposed on the n-type silicon substrate and the p-type pressure-sensitive resistor, and the silicon nitride layer is disposed on the silicon dioxide layer; An electrical contact area and a stress release area are formed on the silicon dioxide layer and the silicon nitride layer; the electrical contact area is disposed at the outer end of the top of the p-type pressure-sensitive resistor, and the metal electrode layer is disposed on the electrical contact area; A silicon cup is formed at the bottom of the n-type silicon substrate, so that the n-type silicon substrate above the silicon cup forms a pressure-sensitive diaphragm, and the stress release region is arranged on the upper surface of the pressure-sensitive diaphragm; The bonding component is bonded to the bottom of the n-type silicon substrate.

[0007] The low-stress silicon-based pressure sensor chip can reduce the influence of the passivation layer on the chip output and improve the stress distribution of the pressure-sensitive diaphragm by arranging p-type pressure-sensitive resistors in the resistor placement grooves of the n-type silicon substrate, realizing electrical isolation by using PN junctions, and making the upper surface of the p-type pressure-sensitive resistors coplanar with the n-type silicon substrate, combined with the settings of the silicon dioxide layer and the silicon nitride layer in the passivation layer and the openings in the electrical contact region and the stress release region, thereby improving the output stability and reliability of the sensor; in addition, by forming a silicon cup at the bottom of the n-type silicon substrate and bonding the bonding component, it helps to optimize the mechanical properties of the pressure-sensitive diaphragm and further enhance the overall performance of the sensor.

[0008] Optionally, the bonding component is one of bonding glass and bonding silicon wafer.

[0009] By bonding bonding glass or bonding silicon wafer at the bottom of the n-type silicon substrate, the structural stability of the chip can be enhanced, the stress introduced during the packaging process can be reduced, and the matching between the sensor chip and external devices can be improved, thereby improving the overall reliability.

[0010] Optionally, the n-type silicon substrate is a double-polished silicon wafer, and the thickness range of the n-type silicon substrate is 300 μm - 800 μm; the doping concentration range of the p-type pressure-sensitive resistor is 3E18 cm -3 or 2E20 cm -3 ; the junction depth range of the PN junction is 0.5 μm - 3 μm; the thickness range of the silicon dioxide layer is 50 nm - 300 nm; the thickness range of the silicon nitride layer is 50 nm - 300 nm; the thickness range of the metal electrode layer is 500 nm - 2 μm; the thickness range of the pressure-sensitive diaphragm is 15 μm - 300 μm.

[0011] By defining the n-type silicon substrate as a double-polished silicon wafer and controlling its thickness within the range of 300 μm - 800 μm, and simultaneously optimizing the doping concentration of the p-type pressure-sensitive resistor, the junction depth of the PN junction, the thickness of the passivation layer, the thickness of the metal electrode layer, and the thickness of the pressure-sensitive diaphragm, the mechanical strength and process consistency of the chip can be improved, the risk of stress concentration can be reduced, the electrical isolation effect and signal transmission stability can be improved, thereby optimizing the sensitivity and long-term reliability of the sensor.

[0012] Optionally, the number of the p-type pressure-sensitive resistors is four, and each p-type pressure-sensitive resistor is provided with two electrical contact areas. The metal electrode layer is electrically connected to the p-type pressure-sensitive resistor through the electrical contact area, and the four p-type pressure-sensitive resistors are connected by wiring through the metal electrode layer to form a Wheatstone bridge.

[0013] Using four p-type pressure-sensitive resistors, each with two electrical contact areas, and connecting them by wiring through a metal electrode layer to form a Wheatstone bridge structure can improve the sensitivity of pressure detection and the temperature compensation effect, and at the same time reduce the measurement error of a single resistor, thereby improving the output signal stability and measurement accuracy of the sensor.

[0014] Optionally, there are multiple stress release areas, and the stress release areas are arranged on the pressure-sensitive diaphragm away from the area of the p-type pressure-sensitive resistor; the interval between two adjacent stress release areas is 5 μm - 200 μm, and the width of each stress release area is 5 μm - 300 μm.

[0015] By arranging multiple stress release areas on the pressure-sensitive diaphragm away from the area of the p-type pressure-sensitive resistor, and controlling the interval between adjacent stress release areas to be 5 μm - 200 μm and the width of each stress release area to be 5 μm - 300 μm, the stress generated by the passivation layer on the pressure-sensitive diaphragm can be dispersed, the influence of stress concentration on the performance of the sensor can be reduced, and at the same time, the mechanical integrity of the diaphragm can be maintained, thereby improving the output stability and measurement accuracy of the sensor.

[0016] The second aspect of the present application provides a processing method for a low-stress silicon-based pressure sensor chip, which is used to process the low-stress silicon-based pressure sensor chip described in the first aspect. The method includes: Select an n-type double-polished silicon wafer as the n-type silicon substrate; Perform regional doping and annealing treatment on the n-type silicon substrate by ion implantation or diffusion to form p-type pressure-sensitive resistors; Prepare a silicon dioxide layer and a silicon nitride layer on the n-type silicon substrate and the p-type pressure-sensitive resistor by thermal oxidation, chemical vapor deposition or magnetron sputtering; Use one or a combination of inductively coupled plasma etching process, reactive ion etching process, and wet etching process to etch the silicon nitride layer and the silicon dioxide layer to form electrical contact areas and stress release areas; Form a metal electrode layer by magnetron sputtering or electron beam evaporation; Treat the metal electrode layer by annealing to form an ohmic contact; Etch the bottom of the n-type silicon substrate by wet etching or deep silicon etching process to form a silicon cup and a pressure-sensitive diaphragm; Bond the bonding component to the bottom of the n-type silicon substrate by anodic bonding or silicon-silicon bonding method.

[0017] On the basis of including all the beneficial effects of the low-stress silicon-based pressure sensor chip described in the first aspect, the above processing method selects an n-type double-polished silicon wafer as the substrate, combines regional doping and annealing treatment to form p-type piezoresistors, uses thermal oxidation or chemical vapor deposition to prepare silicon dioxide layer and silicon nitride layer, and forms electrical contact areas and stress release areas through a combination of various etching processes, cooperates with magnetron sputtering or electron beam evaporation to form a metal electrode layer and realizes ohmic contact through annealing treatment. Finally, form a silicon cup and a pressure-sensitive diaphragm by wet etching or deep silicon etching, and then complete the device packaging through a bonding process. This method can optimize the stress distribution of the device, improve the stability of p-type piezoresistors, improve the electrical contact performance, and enhance the mechanical reliability of the diaphragm structure, thereby improving the overall performance of the sensor.

[0018] Optionally, the impurity used for ion implantation is boron atoms, and the diffusion method uses a boron source wafer for doping.

[0019] Using boron atoms as ion implantation impurities and combining boron source wafer diffusion doping helps to improve the uniformity and controllability of the doping process, optimize the impurity concentration distribution, and thus improve the electrical performance and reliability of semiconductor devices.

[0020] Optionally, the process gases for the inductively coupled plasma etching process and the reactive ion etching process are one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen, and the etching solution for the wet etching process is a BOE solution, and the BOE solution is a mixed solution prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0021] Using one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen as the process gases for inductively coupled plasma etching and reactive ion etching, and cooperating with the BOE solution prepared in a volume ratio of 6:1 for wet etching can improve the selectivity and controllability of the etching process, optimize the pattern transfer accuracy, reduce the damage to non-target areas at the same time, and improve the processing quality of the device structure.

[0022] Optionally, the silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

[0023] Using potassium hydroxide solution or tetramethylammonium hydroxide solution as the silicon etchant for wet etching can control the etching rate and surface morphology of the silicon cup structure, reduce the defects generated during the etching process, improve the surface flatness and thickness uniformity of the pressure-sensitive diaphragm, and thus improve the performance consistency of the sensor.

[0024] Optionally, the process gas for the deep silicon etching process is one or more of perfluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0025] By using one or more of perfluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as the deep silicon etching process gas, the selectivity and anisotropy in the etching process can be optimized, the etching residues can be reduced, and the sidewall morphology of the silicon cup structure can be improved, thereby enhancing the processing accuracy and mechanical properties of the pressure-sensitive diaphragm.

[0026] As can be seen from the above technical solutions, the present application provides a low-stress silicon-based pressure sensor chip and a processing method. The chip includes: an n-type silicon substrate, a p-type pressure-sensitive resistor, a passivation layer, a metal electrode layer, and a bonding component; the p-type pressure-sensitive resistor is disposed in a resistor placement groove at the top of the n-type silicon substrate, and the p-type pressure-sensitive resistor and the n-type silicon substrate are electrically isolated through a PN junction, and the upper surface of the p-type pressure-sensitive resistor is in the same plane as the n-type silicon substrate; the passivation layer includes a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is disposed on the n-type silicon substrate and the p-type pressure-sensitive resistor, and the silicon nitride layer is disposed on the silicon dioxide layer; an electrical contact area and a stress release area are formed on the silicon dioxide layer and the silicon nitride layer; the electrical contact area is disposed at the outer end of the top of the p-type pressure-sensitive resistor, and the metal electrode layer is disposed on the electrical contact area; a silicon cup is formed at the bottom of the n-type silicon substrate, so that the n-type silicon substrate in the area above the silicon cup forms a pressure-sensitive diaphragm, and the stress release area is disposed on the upper surface of the pressure-sensitive diaphragm; the bonding component is bonded to the bottom of the n-type silicon substrate to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0028] Figure 1 Planar process plate in the processing method of the low-stress silicon-based pressure sensor chip provided by the embodiment of the present application Figure 1 ; Figure 2 Planar process plate in the processing method of the low-stress silicon-based pressure sensor chip provided by the embodiment of the present application Figure 2 ; Figure 3 Structural schematic diagram of the n-type silicon substrate in the processing method of the low-stress silicon-based pressure sensor chip provided by the embodiment of the present application; Figure 4Schematic diagram of forming a p-type piezoresistor in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 5 Schematic diagram of forming a passivation layer in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 6 Schematic diagram of forming an electrical contact area and a stress release area in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 7 Schematic diagram of forming an ohmic contact in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 8 Schematic diagram of forming a silicon cup and a pressure-sensitive diaphragm by a wet etching process in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 9 Schematic diagram after forming a silicon cup and a pressure-sensitive diaphragm by a deep silicon etching process in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 10 Schematic diagram after sealing a non-porous glass in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 11 Schematic diagram after sealing a through-hole glass in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 12 Schematic diagram after sealing a non-porous silicon wafer in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application; Figure 13 Schematic diagram after sealing a through-hole silicon wafer in the processing method of a low-stress silicon-based pressure sensor chip provided by an embodiment of the present application.

[0029] Illustration: Among them, 1 - n-type silicon substrate; 2 - p-type piezoresistor; 3 - silicon dioxide layer; 4 - silicon nitride layer; 5 - electrical contact area; 6 - stress release area; 7 - metal electrode layer; 8 - silicon cup; 9 - pressure-sensitive diaphragm; 10 - non-porous glass; 11 - through-hole glass; 12 - non-porous silicon wafer; 13 - through-hole silicon wafer. Detailed implementation manners

[0030] The embodiments will be described in detail below, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0031] The pressure sensor chip based on MEMS technology has the characteristics of high sensitivity, low cost, reliable performance, and mass production, and is widely used in the fields of aerospace, process industry, intelligent medical care, etc.

[0032] The MEMS pressure sensor chip in the related embodiments is mainly made of silicon material, and the PN junction isolation technology is used to realize the electrical isolation between the pressure-sensitive resistor and the substrate. In order to enhance the anti-interference ability of the chip to the external environment, such as water vapor, mechanical scratches, particle contamination, etc., a passivation layer, including a silicon dioxide layer and a silicon nitride layer, is usually prepared on the chip surface to ensure the stable electrical performance of the chip.

[0033] However, introducing the passivation layer will also bring negative impacts. Due to the different thermal expansion coefficients of silicon and the passivation layer, at different temperatures, variable film stress will be generated, and the film stress is transmitted to the pressure-sensitive resistor, resulting in a change in the resistance value, seriously affecting the output and reliability of the pressure sensor chip. For low-range pressure-sensitive chips, the film stress problem is more prominent.

[0034] To solve the problem that introducing the passivation layer affects the output and reliability of the pressure sensor chip, see Figures 1 - 13 , some embodiments of the present application provide a low-stress silicon-based pressure sensor chip, including: an n-type silicon substrate 1, a p-type pressure-sensitive resistor 2, a passivation layer, a metal electrode layer 7, and a bonding component; the p-type pressure-sensitive resistor 2 is arranged in a resistor placement groove at the top of the n-type silicon substrate 1, and the p-type pressure-sensitive resistor 2 and the n-type silicon substrate 1 are electrically isolated through a PN junction, and the upper surface of the p-type pressure-sensitive resistor 2 is on the same plane as the n-type silicon substrate 1.

[0035] It should be understood that the p-type pressure-sensitive resistor 2 is formed in a specific area of the n-type silicon substrate 1 by ion implantation or diffusion, and is electrically isolated from the n-type silicon substrate 1 through a PN junction to realize the insulation between the p-type pressure-sensitive resistor 2 and the n-type silicon substrate 1.

[0036] The passivation layer includes a silicon dioxide layer 3 and a silicon nitride layer 4. The silicon dioxide layer 3 is arranged on the n-type silicon substrate 1 and the p-type pressure-sensitive resistor 2 to realize passivation and isolation protection of the chip; the silicon nitride layer 4 is arranged on the silicon dioxide layer 3 to enhance the passivation and isolation protection of the passivation layer.

[0037] An electrical contact area 5 and a stress release area 6 are provided on the silicon dioxide layer 3 and the silicon nitride layer 4; the electrical contact area 5 is arranged at the outer end of the top of the p-type pressure-sensitive resistor 2, and the metal electrode layer 7 is arranged on the electrical contact area 5.

[0038] A silicon cup 8 is provided at the bottom of the n-type silicon substrate 1, so that the n-type silicon substrate 1 in the area above the silicon cup 8 forms a pressure-sensitive diaphragm 9, and the stress release area 6 is arranged on the upper surface of the pressure-sensitive diaphragm 9; the bonding member is bonded to the bottom of the n-type silicon substrate 1.

[0039] It should be understood that the electrical contact area 5 can be electrically connected to an external circuit through an external lead. The stress release area 6 is arranged on the upper surface of the pressure-sensitive diaphragm 9 to fully release the stress in the force-bearing area of the chip. Specifically, as Figure 1 shown, in some embodiments, the stress release area 6 extends inward from the edge of the pressure-sensitive diaphragm 9 in sequence and is distributed in a ring shape. As Figure 2 shown, in some other embodiments, the stress release area 6 extends outward from the edge of the p-type pressure-sensitive resistor 2 in sequence and is distributed in a ring shape. The metal electrode layer 7 is used to lead out the internal signal of the chip. The pressure-sensitive film is arranged on the silicon cup 8 to sense the external pressure signal. The bonding member is bonded to the bottom of the n-type silicon substrate 1 to reduce the packaging stress of the chip.

[0040] Growing silicon dioxide and silicon nitride on the surface of the n-type silicon substrate 1 as a passivation layer can not only effectively achieve physical isolation of adjacent electronic devices, prevent signal interference, and increase the breakdown voltage threshold of the chip, but also serve as a protective layer to prevent the chip from being damaged by environmental factors such as moisture, oxygen, and scratches, improve the anti-interference ability of the chip, and extend the service life of the chip. The stress release area 6 can release the film stress brought by the large-area passivation layer, significantly reduce the influence of the film stress on the pressure sensor chip, and thus improve the stability and reliability of the chip.

[0041] In some embodiments, the bonding member is one of bonding glass and bonding silicon wafer.

[0042] By bonding the bonding glass or bonding silicon wafer to the bottom of the n-type silicon substrate 1, the structural stability of the chip can be enhanced, the stress introduced during the packaging process can be reduced, and at the same time, the matching between the sensor chip and external devices can be improved, thereby improving the overall reliability.

[0043] It should be understood that the structure of the bonding member is not unique to meet different packaging requirements. Specifically, the bonding glass can be selected from non-porous glass 10 and through-hole glass 11, as Figure 10 and Figure 11 shown; the bonding silicon wafer includes non-porous silicon wafer 12 and through-hole silicon wafer 13, as Figure 12 and shown.

[0044] In some embodiments, the n-type silicon substrate 1 is a double-polished silicon wafer, and the thickness range of the n-type silicon substrate 1 is 300 μm - 800 μm; the doping concentration range of the p-type pressure-sensitive resistor 2 is 3E18 cm -3 or 2E20 cm -3 ; the junction depth range of the PN junction is 0.5 μm - 3 μm.

[0045] The p-type doping concentration of 3E18 cm -3 or 2E20 cm -3 can achieve self-compensation of the resistance and sensitivity temperature drift, reducing the complexity of the external circuit. The PN junction depth of 0.5 μm - 3 μm can ensure the uniform distribution of impurities, improve the reverse breakdown voltage of the resistor, and enhance the reliability and stability of the chip.

[0046] The thickness range of the silicon dioxide layer 3 is 50 nm - 300 nm; the thickness range of the silicon nitride layer 4 is 50 nm - 300 nm; the thickness range of the metal electrode layer 7 is 500 nm - 2 μm.

[0047] Controlling the thicknesses of the silicon dioxide layer 3 and the silicon nitride layer 4 within the range of 50 nm - 300 nm, while keeping the thickness of the metal electrode layer 7 at 500 nm - 2 μm, helps to balance the insulation performance and mechanical strength of the dielectric layer, optimize the stress matching of the multi-layer structure, and enhance the electrical conductivity and structural stability of the electrode.

[0048] In some embodiments, the number of the p-type pressure-sensitive resistors 2 is four, and each p-type pressure-sensitive resistor 2 is provided with two electrical contact areas 5. The metal electrode layer 7 is electrically connected to the p-type pressure-sensitive resistor 2 through the electrical contact area 5, and the four p-type pressure-sensitive resistors 2 are connected by wire routing through the metal electrode layer 7 to form a Wheatstone bridge.

[0049] It should be understood that the four p-type pressure-sensitive resistors 2 (R1, R2, R3, R4) are connected into a Wheatstone bridge through external leads to convert the pressure signal into an electrical signal.

[0050] Using four p-type pressure-sensitive resistors 2 and each having two electrical contact areas 5, and connecting them into a Wheatstone bridge structure by wire routing through the metal electrode layer 7 can improve the sensitivity of pressure detection and the temperature compensation effect, while reducing the measurement error of a single resistor, thereby enhancing the output signal stability and measurement accuracy of the sensor.

[0051] In some embodiments, the number of the metal electrode layers 7 is six, and the metal electrode layers 7 are disposed on the electrical contact areas 5.

[0052] Six metal electrode layers 7 are adopted and disposed on the electrical contact region 5, which helps to increase the current conduction path, disperse the current density, thereby reducing the risk of local overheating, improving the electrical connection stability between the electrode and the contact region, and at the same time enhancing the heat dissipation performance of the overall structure.

[0053] In some embodiments, the silicon cup 8 is of a vertical structure or a trapezoidal structure; the thickness of the pressure-sensitive diaphragm 9 is 15 μm - 300 μm.

[0054] It should be understood that the pressure-sensitive diaphragm 9 is fabricated by processing the silicon cup 8. When an external pressure acts on the pressure-sensitive diaphragm 9, the pressure-sensitive diaphragm 9 undergoes a slight deformation and generates an electrical signal; see Figure 13 and Figure 8 Figure 9 , the trapezoidal silicon cup 8 is prepared by a wet etching process, which has the characteristics of low cost, batch production, and good consistency; the vertical silicon cup 8 is prepared by a deep silicon etching process, which has the characteristics of high cost and batch production.

[0055] Adopting a silicon cup 8 with a vertical or trapezoidal structure and combining it with a pressure-sensitive diaphragm 9 with a thickness of 15 μm - 300 μm can balance the structure support and pressure sensing functions, improve the mechanical stability, optimize the transmission efficiency of the pressure signal, and improve the sensitivity and reliability of the sensor.

[0056] In some embodiments, there are multiple stress release regions 6, and the stress release regions 6 are disposed on the pressure-sensitive diaphragm 9 away from the p-type pressure-sensitive resistor 2 region; the interval between two adjacent stress release regions 6 is 5 μm - 200 μm, and the width of each stress release region 6 is 5 μm - 300 μm.

[0057] By disposing multiple stress release regions 6 on the pressure-sensitive diaphragm 9 away from the p-type pressure-sensitive resistor 2 region and controlling the interval between adjacent stress release regions 6 to be 5 μm - 200 μm and the width of each stress release region 6 to be 5 μm - 300 μm, the stress generated by the passivation layer on the pressure-sensitive diaphragm 9 can be dispersed, the influence of stress concentration on the sensor performance can be reduced, and the mechanical integrity of the diaphragm can be maintained, thereby improving the output stability and measurement accuracy of the sensor.

[0058] Some embodiments of the present application also provide a processing method for a low-stress silicon-based pressure sensor chip for processing the low-stress silicon-based pressure sensor chip described in the above embodiments. The method includes: Select an n-type double-polished silicon wafer as the n-type silicon substrate 1.

[0059] It should be understood that the n-type silicon substrate 1 is a double-polished wafer, and the thickness range of the n-type silicon substrate 1 is 300 μm - 800 μm.

[0060] Regional doping and annealing treatments are performed on the n-type silicon substrate 1 by ion implantation or diffusion to form the p-type pressure-sensitive resistor 2.

[0061] It should be understood that the doping concentration range of the p-type pressure-sensitive resistor 2 is 3E18 cm -3 or 2E20 cm -3 ; after high-temperature annealing treatment, the PN junction depth range is 0.5 μm - 3 μm.

[0062] In some embodiments, the impurity used for the ion implantation is boron atoms, and the diffusion method uses a boron source wafer for doping.

[0063] Using boron atoms as the ion implantation impurity and combining with boron source wafer diffusion doping helps to improve the uniformity and controllability of the doping process, optimize the impurity concentration distribution, and thus improve the electrical performance and reliability of the semiconductor device.

[0064] A silicon dioxide layer 3 and a silicon nitride layer 4 are prepared on the n-type silicon substrate 1 and the p-type pressure-sensitive resistor 2 by thermal oxidation, chemical vapor deposition, or magnetron sputtering.

[0065] Specifically, the thickness range of the silicon dioxide layer 3 prepared by thermal oxidation, chemical vapor deposition, or magnetron sputtering is 50 nm - 300 nm; the thickness range of the silicon nitride layer 4 prepared by thermal oxidation, chemical vapor deposition, or magnetron sputtering is 50 nm - 300 nm.

[0066] One or a combination of processes such as inductively coupled plasma etching process, reactive ion etching process, and wet etching process is used to etch the silicon nitride layer 4 and the silicon dioxide layer 3 to form the electrical contact region 5 and the stress release region 6.

[0067] Specifically, before etching the passivation layer, photoresist can be used for protection at the bottom of the n-type silicon substrate 1 and as an etching mask at the top for photolithography. First, the silicon nitride layer 4 is etched, then the silicon dioxide layer 3 is etched until reaching the silicon layer, and finally the photoresist is removed.

[0068] A metal electrode layer 7 is formed by magnetron sputtering or electron beam evaporation.

[0069] The metal electrode layer 7 is treated by annealing to form an ohmic contact.

[0070] Specifically, a metal electrode layer 7 is first formed on the passivation layer by magnetron sputtering or electron beam evaporation. The thickness of the metal electrode layer 7 is 500 nm - 2 μm. A photoresist is used as an etching mask on the top for photolithography. The metal electrode layer 7 is etched, and then the photoresist is removed. Finally, a high-temperature annealing treatment is performed to form an ohmic contact, thereby realizing the electrical connection between the metal electrode layer 7 and the p-type pressure-sensitive resistor 2.

[0071] The bottom of the n-type silicon substrate 1 is etched by a wet etching method or a deep silicon etching process to form a silicon cup 8 and a pressure-sensitive diaphragm 9.

[0072] Specifically, the bottom of the n-type silicon substrate 1 is processed by a wet etching method or a deep silicon etching method to form a silicon cup 8 and a pressure-sensitive diaphragm 9. The thickness range of the pressure-sensitive diaphragm 9 is 15 μm - 300 μm. The thickness of the pressure-sensitive diaphragm 9 of 15 μm - 300 μm can cover chips with a range specification of 1 kPa - 100 MPa, meeting the application requirements of different scenarios.

[0073] In some embodiments, the silicon etchant in the wet etching method is a potassium hydroxide solution or a tetramethylammonium hydroxide solution.

[0074] Using a potassium hydroxide solution or a tetramethylammonium hydroxide solution as the silicon etchant for wet etching can control the etching rate and surface morphology of the silicon cup 8 structure, reduce the defects generated during the etching process, improve the surface flatness and thickness uniformity of the pressure-sensitive diaphragm 9, thereby improving the performance consistency of the sensor.

[0075] In some embodiments, before wet etching, the top of the n-type silicon substrate 1 is also protected, and a silicon nitride is used as a mask for the bottom of the n-type silicon substrate 1. Then, the n-type silicon substrate 1 is anisotropically etched to form a silicon cup 8 and a pressure-sensitive diaphragm 9. The side of the silicon cup 8 can be a trapezoidal structure.

[0076] It should be understood that wet etching with potassium hydroxide solution or tetramethylammonium hydroxide solution can react with silicon efficiently, maintain the smoothness and integrity of the silicon surface, reduce the risk of equipment corrosion, facilitate waste liquid treatment, and the process parameters are easy to adjust. In the anisotropic etching process of silicon-based materials, the potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH) solution systems exhibit significant engineering advantages. By selectively activating specific crystal planes of the silicon lattice, precise control of sub-micron-scale topography can be achieved, and the surface roughness (Ra) after etching can be stably below 1 nm. Such alkaline solutions have a wide parameter regulation window (concentration 5 - 40 wt%, temperature 50 - 90 °C) at the etching kinetics level, which can not only ensure an efficient reaction with an etching rate of 0.5 - 2 μm / min, but also inhibit side reactions through the pH buffering mechanism, protecting the silicon substrate from excessive erosion. Compared with acidic etching systems, their corrosion by-products (silicate / silanol) are chemically inert, and the waste liquid can be rendered harmless through simple neutralization.

[0077] In some embodiments, before deep silicon etching, a photoresist can be used for protection on the top of the n-type silicon substrate 1, and a photoresist can be used as an etching mask at the bottom for photolithography. Then, the silicon layer is etched to make the thickness of the pressure-sensitive diaphragm 9 be 15 μm - 300 μm, and finally the photoresist is removed. The side of the silicon cup 8 can be a vertical structure.

[0078] It should be understood that the deep reactive ion etching (DRIE) process is a commonly used technology in microfabrication for creating deep and narrow structures. Commonly used gas combinations, such as sulfur hexafluoride for etching and octafluorocyclobutane for passivation, are used in an alternating cycle to achieve a high aspect ratio. The accuracy of the deep silicon etching process directly depends on the stability of the plasma source (such as ICP high-density plasma) and the rapid response ability of the equipment to gas pulses (millisecond-level switching). Modern equipment has achieved sub-micron-scale etching uniformity (within ±3%), promoting the development of MEMS devices towards higher integration.

[0079] The bonding part is bonded to the bottom of the n-type silicon substrate 1 by anodic bonding or silicon-silicon bonding.

[0080] Specifically, the anodic bonding method of the bonding glass is adopted, specifically: In a cleanroom environment, the n-type silicon substrate 1 and the bonding glass are accurately aligned (error < 2 μm), placed on the metal surface plate, and then transferred to the working stage of the sealing machine, and a slight pressure (0.1 - 1 N / cm 2 ) is applied to the contact surface.

[0081] The n-type silicon substrate 1 is connected to the positive pole of the DC power supply through a heating plate, and the bonding glass is connected to the negative pole of the DC power supply through the metal surface electrode.

[0082] Control the vacuum degree ≤ 1 - 5×10-4 Pa, heat up to 200 - 400 °C, and keep the temperature for 0.5 - 1 h.

[0083] Apply a DC voltage (800 - 1000 V), and the initial current density reaches 1 - 10 mA / cm 2 , and it drops to the μA level with the bonding process (completed in about 5 - 15 minutes) to complete the anodic bonding.

[0084] The bonding method of the bonded silicon wafers adopts silicon - silicon bonding, specifically: Adopt the RCA standard cleaning method to remove particle, organic matter, and metal ion contamination, and the surface roughness needs to be controlled below 0.5 nm.

[0085] Through oxygen plasma treatment (power 200 - 400 W, oxygen flow rate 100 - 300 sccm, time 5 - 30 min) or wet chemical oxidation (H2O2 solution), form surface hydroxyl groups (-OH) to enhance the bonding activity.

[0086] In a clean - room environment, fit the surfaces of the two silicon wafers together, and achieve initial bonding through van der Waals forces and hydrogen - bond interactions. Apply a uniform pressure (0.1 - 1 N / cm 2 ), and remove air bubbles. After fitting, it needs to be quickly fixed to prevent interface slippage.

[0087] Anneal in nitrogen or inert gas at a temperature of 800 - 1200 °C for 2 - 4 h to complete the silicon - silicon bonding.

[0088] On the basis of including all the beneficial effects of the low - stress silicon - based pressure sensor chip described in the above embodiments, by selecting an n - type double - polished silicon wafer as the substrate, combining regional doping and annealing treatment to form the p - type pressure - sensitive resistor 2, using thermal oxidation or chemical vapor deposition to prepare the silicon dioxide layer 3 and the silicon nitride layer 4, and forming the electrical contact area 5 and the stress - release area 6 through a combination of various etching processes, cooperating with magnetron sputtering or electron beam evaporation to form the metal electrode layer 7 and achieving ohmic contact through annealing treatment, and finally forming the silicon cup 8 and the pressure - sensitive diaphragm 9 through wet etching or deep silicon etching, and then completing the device packaging through the bonding process. This method can optimize the stress distribution of the device, improve the stability of the p - type pressure - sensitive resistor 2, improve the electrical contact performance, and at the same time enhance the mechanical reliability of the diaphragm structure, thereby improving the overall performance of the sensor.

[0089] In some embodiments, the process gases of the inductively coupled plasma etching process and the reactive ion etching process are one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen, the etching solution of the wet etching process is the BOE solution, and the BOE solution is a mixed solution prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0090] It should be understood that, due to their high reactivity characteristics, CF4 and CHF3 can significantly improve the etching efficiency. By precisely controlling the gas ratio and mixing ratio, the etching of micro-nano scale patterns can be accurately achieved. The mixed use of different process gases can not only optimize the consistency of the etching profile, but also achieve differential selective etching for different material systems through the synergistic effect at the molecular level. This gas combination scheme can maintain the stability of the plasma state by dynamically balancing the concentration of active species in the plasma, thereby effectively suppressing process fluctuations and ensuring the repeatability of the etching process and yield control.

[0091] As a key wet etching agent in integrated circuit manufacturing, the core components of the BOE solution are a buffer system composed of hydrofluoric acid (HF) and ammonium fluoride (NH4F). This solution effectively regulates the fluoride ion concentration through the buffering action of NH4F, which can not only maintain the selective etching ability for silicon dioxide, but also inhibit the non-specific corrosion of photoresist and silicon substrate by pure hydrofluoric acid, realizing the controllable removal of oxide layer structures from micrometers to nanometers. This characteristic gives it an irreplaceable precise regulation advantage in processes such as gate oxide layer etching and dielectric layer planarization.

[0092] In some embodiments, the process gas for the deep silicon etching process is one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0093] By using one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as the deep silicon etching process gas, the selectivity and anisotropy in the etching process can be optimized, the etching residues can be reduced, and the sidewall morphology of the silicon cup 8 structure can be improved, thereby enhancing the processing accuracy and mechanical properties of the pressure sensitive diaphragm 9.

[0094] As can be seen from the above technical solutions, the embodiments of the present application provide a low-stress silicon-based pressure sensor chip and a processing method. The chip includes: an n-type silicon substrate 1, p-type piezoresistors 2, a passivation layer, a metal electrode layer 7, and a bonding component; the p-type piezoresistors 2 are arranged in the resistor placement grooves at the top of the n-type silicon substrate 1, and the p-type piezoresistors 2 and the n-type silicon substrate 1 are electrically isolated through a PN junction, and the upper surface of the p-type piezoresistors 2 is on the same plane as the n-type silicon substrate 1; the passivation layer includes a silicon dioxide layer 3 and a silicon nitride layer 4, the silicon dioxide layer 3 is arranged on the n-type silicon substrate 1 and the p-type piezoresistors 2, and the silicon nitride layer 4 is arranged on the silicon dioxide layer 3; an electrical contact area 5 and a stress release area 6 are provided on the silicon dioxide layer 3 and the silicon nitride layer 4; the electrical contact area 5 is arranged at the outer end of the top of the p-type piezoresistors 2, and the metal electrode layer 7 is arranged on the electrical contact area 5; a silicon cup 8 is provided at the bottom of the n-type silicon substrate 1, so that the n-type silicon substrate 1 in the area above the silicon cup 8 forms a pressure-sensitive diaphragm 9, and the stress release area 6 is arranged on the upper surface of the pressure-sensitive diaphragm 9; the bonding component is bonded to the bottom of the n-type silicon substrate 1 to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip.

[0095] For the similarities between the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other implementation manner extended based on the solution of the present application without creative work belongs to the protection scope of the present application.

Claims

1. A low-stress silicon-based pressure sensor chip, characterized in that, Comprising: An n-type silicon substrate (1), a p-type piezoresistor (2), a passivation layer, a metal electrode layer (7), and a bonding member; The p-type piezoresistor (2) is disposed in a resistor placement groove on the top of the n-type silicon substrate (1). The p-type piezoresistor (2) is electrically isolated from the n-type silicon substrate (1) through a PN junction. The upper surface of the p-type piezoresistor (2) is in the same plane as the n-type silicon substrate (1); The passivation layer includes a silicon dioxide layer (3) and a silicon nitride layer (4). The silicon dioxide layer (3) is disposed on the n-type silicon substrate (1) and the p-type piezoresistor (2). The silicon nitride layer (4) is disposed on the silicon dioxide layer (3); An electrical contact area (5) and a stress release area (6) are formed on the silicon dioxide layer (3) and the silicon nitride layer (4). The electrical contact area (5) is disposed at the outer end of the top of the p-type piezoresistor (2). The metal electrode layer (7) is disposed on the electrical contact area (5); A silicon cup (8) is formed at the bottom of the n-type silicon substrate (1), so that the n-type silicon substrate (1) in the area above the silicon cup (8) forms a pressure-sensitive diaphragm (9). The stress release area (6) is disposed on the upper surface of the pressure-sensitive diaphragm (9); The bonding member is bonded to the bottom of the n-type silicon substrate (1).

2. The low-stress silicon-based pressure sensor chip according to claim 1, wherein The bonding member is one of bonding glass and bonding silicon wafer.

3. The low-stress silicon-based pressure sensor chip according to claim 1, characterized in that, The n-type silicon substrate (1) is a double-polished silicon wafer, and the thickness range of the n-type silicon substrate (1) is 300 μm - 800 μm; the doping concentration range of the p-type pressure-sensitive resistor (2) is 3E18 cm -3 or 2E20 cm -3 ; the junction depth range of the PN junction is 0.5 μm - 3 μm; the thickness range of the silicon dioxide layer (3) is 50 nm - 300 nm; the thickness range of the silicon nitride layer (4) is 50 nm - 300 nm; the thickness range of the metal electrode layer (7) is 500 nm - 2 μm; the thickness range of the pressure-sensitive diaphragm (9) is 15 μm - 300 μm.

4. The low-stress silicon-based pressure sensor chip according to claim 1, characterized in that, The number of the p-type piezoresistors (2) is four. Each p-type piezoresistor (2) is provided with two electrical contact areas (5). The metal electrode layer (7) is electrically connected to the p-type piezoresistor (2) through the electrical contact area (5). The four p-type piezoresistors (2) are connected by wiring through the metal electrode layer (7) to form a Wheatstone bridge.

5. The low-stress silicon-based pressure sensor chip according to claim 1, wherein There are multiple stress release areas (6). The stress release areas (6) are disposed on the pressure-sensitive diaphragm (9) in the area far from the p-type piezoresistor (2). The interval between two adjacent stress release areas (6) is 5 μm - 200 μm, and the width of each stress release area (6) is 5 μm - 300 μm.

6. A processing method for a low-stress silicon-based pressure sensor chip, characterized in that, For manufacturing the low-stress silicon-based pressure sensor chip according to any one of claims 1 - 5, the method includes: Selecting an n-type double-polished silicon wafer as the n-type silicon substrate (1); Performing regional doping and annealing treatment on the n-type silicon substrate (1) by ion implantation or diffusion to form the p-type piezoresistor (2); Preparing the silicon dioxide layer (3) and the silicon nitride layer (4) on the n-type silicon substrate (1) and the p-type piezoresistor (2) by thermal oxidation or chemical vapor deposition or magnetron sputtering; Etching the silicon nitride layer (4) and the silicon dioxide layer (3) by using one or a combination of inductively coupled plasma etching process, reactive ion etching process, and wet etching process to form the electrical contact area (5) and the stress release area (6); Forming the metal electrode layer (7) by magnetron sputtering or electron beam evaporation; The metal electrode layer (7) is processed by annealing to form an ohmic contact; The bottom of the n-type silicon substrate (1) is etched by wet etching or deep silicon etching process to form a silicon cup (8) and a pressure-sensitive diaphragm (9); The bonding part is bonded to the bottom of the n-type silicon substrate (1) by anodic bonding or silicon-silicon bonding method.

7. The processing method of the low-stress silicon-based pressure sensor chip according to claim 6, characterized in that, The impurity used in the ion implantation is boron atoms, and the diffusion method is doped with a boron source wafer.

8. The processing method of the low-stress silicon-based pressure sensor chip according to claim 6, characterized in that The process gases of the inductively coupled plasma etching process and the reactive ion etching process are one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen. The etching solution of the wet etching process is a BOE solution, and the BOE solution is a mixed solution prepared by mixing a 40% ammonium fluoride solution and a 49% hydrofluoric acid solution in a volume ratio of 6:

1.

9. The processing method of the low-stress silicon-based pressure sensor chip according to claim 6, wherein, The silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

10. The processing method of the low-stress silicon-based pressure sensor chip according to claim 6, wherein, The process gases of the deep silicon etching process are one or more of perfluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

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