Substrate circuit structure

Abstract

The invention provides a substrate circuit structure. The substrate circuit structure comprises a substrate and a circuit layer, the substrate comprises an actuating area and a peripheral area adjacent to the actuating area. The circuit layer is disposed on the substrate and includes an electrostatic test region disposed in at least one of the actuation region and the peripheral region. The static test area comprises a first test pad and a second test pad. The first test pad corresponds to a first breakdown voltage. The second test pad is disposed adjacent to the first test pad and corresponds to a second breakdown voltage different from the first breakdown voltage.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to a substrate circuit structure. Background Art

[0002] In the initial stage of product development, an electrostatic test structure is required to understand the allowable electrostatic value range of the product and to monitor whether there are any suspicious factors in the environment or process that may cause component damage or even product failure. Summary of the Invention

[0003] The present disclosure provides a substrate circuit structure that can be used to monitor electrostatic discharge (ESD) phenomena in a process.

[0004] According to an embodiment of the present disclosure, the substrate circuit structure includes a substrate and a circuit layer. The substrate includes an active region and a peripheral region adjacent to the active region. The circuit layer is disposed on the substrate and includes an electrostatic test region disposed in at least one of the active region and the peripheral region. The electrostatic test region includes a first test pad and a second test pad. The first test pad corresponds to a first breakdown voltage. The second test pad is disposed adjacent to the first test pad and corresponds to a second breakdown voltage different from the first breakdown voltage.

[0005] To make the above features and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings. Brief Description of the Drawings

[0006] Figure 1 is a top view schematic diagram of a substrate circuit structure according to some embodiments of the present disclosure;

[0007] Figure 2 is Figure 1 the first enlarged schematic diagram of the electrostatic test region in

[0008] Figure 3 is Figure 2 the cross-sectional schematic diagram of the cutting line I-I' in

[0009] Figure 4 is Figure 1 the second enlarged schematic diagram of the electrostatic test region in

[0010] Figure 5 is Figure 4 the cross-sectional schematic diagram of the cutting line II-II' in

[0011] Figure 6 is Figure 1 the third enlarged schematic diagram of the electrostatic test region in

[0012] Figure 7 and Figure 8 are respectively Figure 6Schematic cross-sectional view of the middle section line III-III' and the section line IV-IV';

[0013] Figure 9 is Figure 1 The fourth enlarged schematic view of the electrostatic test area in the middle;

[0014] Figure 10 and Figure 11 are respectively Figure 9 Schematic cross-sectional view of the middle section line V-V' and the section line VI-VI';

[0015] Figure 12 It is a schematic flowchart of a method for detecting electrostatic discharge according to some embodiments of the present disclosure. Detailed implementation manners

[0016] Now, reference will be made in detail to the exemplary embodiments of the present invention. Examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0017] Throughout this specification and the appended claims, certain terms will be used to refer to particular elements. Those skilled in the art should understand that electronic device manufacturers may refer to the same element by different names. This document is not intended to distinguish between elements that perform the same function but have different names. In the following specification and claims, words such as "comprising" and "including" are open-ended terms and should therefore be interpreted as "including but not limited to...".

[0018] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in a particular embodiment. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0019] A structure (or layer, element, substrate) described in the present disclosure is located on / above another structure (or layer, element, substrate), which may refer to the two structures being adjacent and directly connected, or it may refer to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate gap) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may refer to a certain structure being "directly" on the other structure, or a certain structure being "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0020] The terms "approximately," "substantially," or "approximately" are generally interpreted as being within 10% of a given value or range, or as being within a range of 5%, 3%, 2%, 1%, or 0.5% of a given value. In addition, the phrases "a range from a first value to a second value," "a range between a first value and a second value," and "a range between a first value and a second value" indicate that the range includes the first value, the second value, and other values therebetween.

[0021] The use of ordinal numbers such as "first" and "second" in the specification and claims to modify an element does not, by itself, imply or indicate any prior ordinal number of the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. Such ordinal numbers are used solely to clearly distinguish one element from another with the same name. The claims and the specification may not use the same terminology; thus, the first element in the specification may be the second element in the claim.

[0022] The electrical connection or coupling described in this disclosure may refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the two circuit elements are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable element, or a combination of the above elements between the endpoints of the two circuit elements, but it is not limited thereto.

[0023] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), and the thickness or width can be measured from a cross-sectional image in an electron microscope, but this is not limited thereto. Additionally, there may be a certain error between any two numerical values or directions used for comparison. Furthermore, the phrases "a given range is from a first numerical value to a second numerical value", "a given range falls within the range from the first numerical value to the second numerical value", or "a given range is between the first numerical value and the second numerical value" mean that the given range includes the first numerical value, the second numerical value, and other numerical values therebetween. If a first direction is perpendicular to a second direction, the angle between the first direction and the second direction can be between 80 degrees and 100 degrees; if a first direction is parallel to a second direction, the angle between the first direction and the second direction can be between 0 degrees and 10 degrees.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, for example, when defined in a commonly used dictionary, should be interpreted to have a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0025] In the present disclosure, the electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a packaging device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphor, quantum dot (QD), other suitable display media, or a combination of the foregoing. The antenna device may include, for example, a Reconfigurable Intelligent Surface (RIS), a Frequency Selective Surface (FSS), a radio frequency filter (RF-Filter), a polarizer, a resonator, or an antenna. The antenna may be an antenna in a liquid crystal form or an antenna of varactor diodes. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diodes may include light-emitting diodes, varactor diodes, or photodiodes. The light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (quantum dot LEDs), but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. The packaging device may be a packaging device suitable for Wafer-Level Package (WLP) technology or Panel-Level Package (WLP) technology, such as a chip first process or a chip last process. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, wearable devices (such as including augmented reality or virtual reality), in-vehicle devices (such as including automotive windshields), or splicing devices.

[0026] Figure 1It is a top view schematic diagram of a substrate circuit structure according to some embodiments of the present disclosure. Figure 2 is Figure 1 a first enlarged schematic diagram of the electrostatic test area in Figure 3 is Figure 2 a cross-sectional schematic diagram of the cutting line I-I' in Figure 4 is Figure 1 a second enlarged schematic diagram of the electrostatic test area in Figure 5 is Figure 4 a cross-sectional schematic diagram of the cutting line II-II' in Figure 6 is Figure 1 a third enlarged schematic diagram of the electrostatic test area in Figure 7 and Figure 8 are respectively Figure 6 cross-sectional schematic diagrams of the cutting line III-III' and the cutting line IV-IV' in Figure 9 is Figure 1 a fourth enlarged schematic diagram of the electrostatic test area in Figure 10 and Figure 11 are respectively Figure 9 cross-sectional schematic diagrams of the cutting line V-V' and the cutting line VI-VI' in Figure 12 It is a flowchart schematic diagram of a method for detecting electrostatic discharge according to some embodiments of the present disclosure. It should be noted that, without departing from the spirit of the present disclosure, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily mixed and used.

[0027] Please first refer to Figures 1 to 3 , the substrate circuit structure 1 may include a substrate 10 and a circuit layer 12. The substrate 10 includes an active area R1 and a peripheral area R2 adjacent to the active area R1. The circuit layer 12 is disposed on the substrate 10 and includes an electrostatic test area RT disposed in at least one of the active area R1 and the peripheral area R2. The electrostatic test area RT includes a first test pad TP1 and a second test pad TP2. The first test pad TP1 corresponds to a first breakdown voltage. The second test pad TP2 is disposed adjacent to the first test pad TP1 and corresponds to a second breakdown voltage different from the first breakdown voltage.

[0028] Specifically, the substrate 10 may be a rigid substrate or a flexible substrate. The material of the substrate 10 includes, for example, glass, quartz, ceramics, sapphire, or plastic, etc., but is not limited thereto. The plastic may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or a combination of the foregoing materials, but is not limited thereto. In addition, the light transmittance of the substrate 10 is not restricted, that is, the substrate 10 may be a light-transmitting substrate, a semi-light-transmitting substrate, or a light-impermeable substrate.

[0029] According to different requirements, the substrate 10 may be divided into multiple regions, such as an active region R1 and a peripheral region R2, etc., but is not limited thereto. The active region R1 may be provided with active components (for example, switching components such as transistors), passive components (for example, resistors, capacitors, and / or inductors, etc.), or a combination of the above. Taking a display device as an example, the active region R1 may include a plurality of pixels to provide a display image, and the peripheral region R2 may include peripheral circuits and / or driver chips, and the peripheral circuits may be used to electrically connect the signal lines in the active region R1 to external circuits or driver chips. In some embodiments, the peripheral region R2 may be located on one or more sides of the active region R1. In some embodiments, the peripheral region R2 may surround the active region R1, but is not limited thereto.

[0030] In some embodiments, the substrate 10 may further include a redundant region R3 adjacent to the active region R1 and the peripheral region R2, and the circuit layer 12 may further include another electrostatic test region RT provided in the redundant region R3. In some embodiments, such as Figure 1As shown, the substrate 10 may be a substrate that has not undergone the singulation process, and the substrate 10 may include a plurality of active regions R1, a plurality of peripheral regions R2, and a redundant region R3, wherein the plurality of active regions R1 are arranged in an array along a direction D1 and a direction D2. The direction D1 and the direction D2 intersect each other and are both perpendicular to the thickness direction of the substrate 10 (for example, the direction D3). In some embodiments, the direction D1 and the direction D2 are perpendicular to each other, but this is not limiting. Each peripheral region R2 is disposed on at least one side of a corresponding active region R1 and forms a singulation unit U with the corresponding active region R1. The redundant region R3 surrounds, for example, the plurality of singulation units U. The redundant region R3 may include a plurality of scribe lines extending along the direction D1 or the direction D2. After the singulation process, the redundant region R3 is removed, and a plurality of separated singulation units U are formed. The substrate circuit structure 1 may include a substrate that has not undergone the singulation process (for example, a substrate including the active region R1, the peripheral region R2, and the redundant region R3) or a substrate after the singulation process (for example, a substrate including the active region R1 and the peripheral region R2 but not including the redundant region R3).

[0031] The circuit layer 12 is disposed on the substrate 10. The position of the electrostatic test region RT of the circuit layer 12 is not limited. For example, the electrostatic test region RT may be set according to the product design, or the electrostatic test region RT may be set according to the high-risk region of electrostatic discharge. In some embodiments, the electrostatic test region RT may be set in the active region R1 to monitor the overall electrostatic condition of the region with a greater relevance to the actual product. In some embodiments, the electrostatic test region RT may be set in the peripheral region R2 to monitor the high-risk region of electrostatic discharge. In some embodiments, the electrostatic test region RT may be set in the redundant region R3, giving the electrostatic test region RT greater design flexibility and layout space. Figure 1 It is schematically shown that each active region R1 is provided with five electrostatic test regions RT, each peripheral region R2 is provided with two electrostatic test regions RT, and the redundant region R3 is provided with five electrostatic test regions RT. However, the number of electrostatic test regions RT in each region and their setting positions may be changed according to actual needs and are not limited to Figure 1 that shown.

[0032] The circuit layer 12 may include a plurality of conductive layers and a plurality of insulating layers. For Figure 3For example, the circuit layer 12 may include a conductive layer 120, an insulating layer 121, a conductive layer 122, an insulating layer 123, a conductive layer 124, an insulating layer 125, a conductive layer 126, an insulating layer 127, a conductive layer 128, and an insulating layer 129, which are sequentially disposed on the substrate 10, but not limited thereto. According to different requirements, the circuit layer 12 may include more or fewer conductive layers and / or insulating layers. The materials of the conductive layer 120, the conductive layer 122, the conductive layer 124, the conductive layer 126, and the conductive layer 128 may include transparent conductive materials or opaque conductive materials. The transparent conductive materials may include metal oxides, graphene, other suitable transparent conductive materials, or combinations thereof. The metal oxides may include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other metal oxides. The opaque conductive materials may include metals, alloys, or combinations thereof. The materials of the insulating layer 121, the insulating layer 123, the insulating layer 125, the insulating layer 127, and the insulating layer 129 may include organic insulating materials, inorganic insulating materials, or combinations thereof. The organic insulating materials, for example, include polymethyl methacrylate (PMMA), epoxy resin, acrylic-based resin, silicone, polyimide polymer, or combinations thereof, but not limited thereto. The inorganic insulating materials, for example, include silicon oxide or silicon nitride, but not limited thereto.

[0033] The electrostatic test area RT can adopt the stack structure design of the circuit layer 12 itself, and no additional process may be required. Taking Figure 2 and Figure 3 as an example, the electrostatic test area RT may include a plurality of test pads TP, and the plurality of test pads TP may respectively belong to different conductive layers. For example, the first test pad TP1 and the second test pad TP2 among the plurality of test pads TP respectively belong to the conductive layer 122 and the conductive layer 124.

[0034] In some embodiments, the electrostatic test area RT may further include a plurality of conductive patterns CP. For example, the electrostatic test area RT may further include a first conductive pattern CP1 that at least partially overlaps with the first test pad TP1 and a second conductive pattern CP2 that at least partially overlaps with the second test pad TP2, but not limited thereto. The plurality of conductive patterns CP, for example, belong to the same conductive layer, such as the conductive layer 120.

[0035] According to the formula of parallel plate capacitance, V bd = E ds * d', where V bd is the breakdown voltage, E ds is the dielectric strength of the material of the insulating layer, and d' is the thickness of the insulating layer. Under the same insulating layer material (i.e., E dsbeing the same), the breakdown voltage increases as the thickness of the insulating layer increases. That is, the breakdown voltage corresponding to the test pad TP can be adjusted by changing the distance between the test pad TP and the corresponding conductive pattern CP (for example, in the direction D3, the distance d between the lower surface of the test pad TP and the upper surface of the conductive pattern CP). In Figure 3 , the distance d1 between the first conductive pattern CP1 and the first test pad TP1 is different from the distance d2 between the second conductive pattern CP2 and the second test pad TP2, so that the first breakdown voltage corresponding to the first test pad TP1 is different from the second breakdown voltage corresponding to the second test pad TP2. In Figure 3 , the distance d between the test pad TP and the corresponding conductive pattern CP gradually increases from left to right, for example, so that the breakdown voltages corresponding to the four test pads TP gradually increase from left to right. For example, the breakdown voltages corresponding to the four test pads TP are 250 volts (volt, V), 500 volts, 1000 volts, and 2000 volts in sequence from left to right, but not limited thereto. In other embodiments, the electrostatic test region RT may include more test pads and / or more conductive patterns.

[0036] In addition to adjusting the corresponding breakdown voltage by increasing the distance d between the test pad TP and the corresponding conductive pattern CP as described above, the corresponding breakdown voltage of the test pad TP can also be adjusted by adjusting the overlapping area A of the conductive pattern CP and the corresponding test pad TP c and / or adjusting the area A of the test pad TP exposed by the opening A of the insulating layer probe .

[0037] According to the formula of parallel plate capacitance, E real = Q probe / (ε * A c ), where E real is the applied electric field, Q probe is the accumulated charge amount, ε is the dielectric constant of the insulating layer, and A c is the overlapping area of the conductive pattern CP and the corresponding test pad TP. In the above formula, Q probe is proportional to A probe , where A probe is the area of the test pad TP exposed by the opening A of the insulating layer.

[0038] As can be seen from the above description, under the same insulating layer material (i.e., ε is the same), when A c is the same, the larger A probe is, the larger Q probe is, and the larger the formed applied electric field E real is, so the easier it is to cause electrostatic injury. In addition, under the same insulating layer material (i.e., ε is the same), when A probe is the same, Q probeis also the same, A c The larger it is, the externally applied electric field E formed real The smaller it is, so it is less likely to cause electrostatic shock. In some embodiments, A can be further changed probe and A c Of at least one of them, change the probability of ESD occurring on different test pads TP, thereby observing the high and low risks of ESD occurring at each process site.

[0039] Figure 2 and Figure 3 An embodiment is shown in which by changing the distance d between the test pad TP and the corresponding conductive pattern CP, different test pads TP correspond to different breakdown voltages, wherein the overlapping area A of each conductive pattern CP and the corresponding test pad TP c can be all the same, and the area A of each test pad TP exposed by the opening A of the corresponding insulating layer probe can be all the same. For example, the overlapping area A of the first conductive pattern CP1 and the first test pad TP1 c1 can be the same as the overlapping area A of the second conductive pattern CP2 and the second test pad TP2 c2 . In addition, the electrostatic test area RT may include an insulating layer 123 and an insulating layer 125, wherein the insulating layer 123 includes a first opening A1 exposing the first test pad TP1, the insulating layer 125 includes a second opening A2 exposing the second test pad TP2, and the area A of the first test pad TP1 exposed by the first opening A1 probe1 can be the same as the area A of the second test pad TP2 exposed by the second opening A2 probe2 . However, the present disclosure is not limited to detecting different levels of breakdown voltage values by changing the distance d between the test pad TP and the corresponding conductive pattern CP. In other embodiments, A can be further changed probe and A c Of at least one of them, to change the probability of ESD occurring on different test pads TP.

[0040] In some embodiments, multiple conductive patterns CP can be electrically connected to a reference voltage. For example, the first conductive pattern CP1 and the second conductive pattern CP2 can be electrically connected to a reference voltage (such as V com)。In contrast, in order to detect the breakdown voltage corresponding to electrostatic injury, multiple test pads TP may be in a floating state without being electrically connected to other voltages. When the test pad TP is electrostatically injured, a short circuit will occur between the test pad TP and the corresponding conductive pattern CP. In some embodiments, a multimeter can be used to measure the resistance value between the test pad TP and the corresponding conductive pattern CP. If the resistance value between the test pad TP and the corresponding conductive pattern CP is less than or equal to a threshold value (for example, less than or equal to 1000 ohms), it indicates that the test pad TP and the corresponding conductive pattern CP are short-circuited, that is, the test pad TP may be electrostatically injured; if the resistance value between the test pad TP and the corresponding conductive pattern CP is greater than the threshold value (for example, greater than 1000 ohms), it indicates that the test pad TP and the corresponding conductive pattern CP are not short-circuited, that is, the test pad TP may not be electrostatically injured. Additionally, in the case where the test pad TP may be electrostatically injured, a secondary confirmation can be further performed through an optical microscope.

[0041] Please refer to Figure 4 and Figure 5 . In Figure 2 and Figure 3 , the test pad TP and the conductive pattern CP are, for example, in a one-to-one setting relationship, while in Figure 4 and Figure 5 , the test pad TP and the conductive pattern CP are, for example, in a two-to-one setting relationship. Specifically, two adjacent test pads TP correspond to the same breakdown voltage, and the two test pads TP and a conductive pattern CP at least partially overlap, where the overlapping area of each of the two test pads TP with the corresponding conductive pattern CP is the same, and the area A probe exposed by the opening A of the corresponding insulating layer for each of the two test pads TP is the same. For example, as Figure 4 and Figure 5 shown, the electrostatic test area RT further includes a fifth test pad TP5 disposed adjacent to the first test pad TP1 and corresponding to the first breakdown voltage, where the fifth test pad TP5 at least partially overlaps with the first conductive pattern CP1 and does not overlap with the second conductive pattern CP2.

[0042] In some embodiments, the first test pad TP1 and the fifth test pad TP5 may be at the same potential. When the test pad TP is damaged by electrostatic shock, a short circuit may occur between the test pad TP and the corresponding conductive pattern CP. For example, the first test pad TP1 and the fifth test pad TP5 may be short-circuited due to electrostatic shock. In some embodiments, a multimeter can be used to measure the resistance value between two test pads TP overlapping the same conductive pattern CP. If the resistance value between the two test pads TP is less than or equal to a threshold value (for example, less than or equal to 1000 ohms), it indicates that a short circuit may be formed between any test pad TP and the conductive pattern CP, or between the two test pads TP, thereby reducing the resistance value. That is, the test pad TP may be damaged by electrostatic shock. If the resistance value between the two test pads TP is greater than the threshold value (for example, greater than 1000 ohms), it indicates that there is no short circuit between any test pad TP and the conductive pattern CP, and there is no short circuit between the two test pads TP. That is, the test pad TP may not be damaged by electrostatic shock. In the case where the test pad TP may be damaged by electrostatic shock, a secondary confirmation can be further performed through an automatic optical inspection system.

[0043] Please refer to Figures 6 to 8 。 Figure 6 The cross-sectional views of the first to third horizontal rows counted from top to bottom in Figure 3 、 Figure 7 and Figure 8 respectively. In Figure 6 , the distances d between multiple test pads TP in the same vertical row and the corresponding multiple conductive patterns CP are all the same, and the distances d between multiple test pads TP in different vertical rows and the corresponding multiple conductive patterns CP are all different, so that multiple test pads TP in the same vertical row correspond to similar breakdown voltages, and multiple test pads TP in different vertical rows correspond to different breakdown voltages.

[0044] Figure 6 The main difference between the second horizontal row and the first horizontal row counted from top to bottom in c lies in the difference in the overlapping area A c3 . For example, the electrostatic test area RT further includes a third test pad TP3 disposed adjacent to the first test pad TP1 and a third conductive pattern CP3 that at least partially overlaps with the third test pad TP3, wherein the distance d (for example, distance d1) between the first conductive pattern CP1 and the first test pad TP1 is the same as the distance d between the third conductive pattern CP3 and the third test pad TP3, and the overlapping area A c1 of the third conductive pattern CP3 and the third test pad TP3 is different from the overlapping area A Figure 6 of the first conductive pattern CP1 and the first test pad TP1. Taking c as an example, the overlapping area A c, making the second horizontal row less likely to cause electrostatic shock than the first horizontal row, but not limited thereto. In other embodiments, although not shown, the overlapping area A of the second horizontal row c may be smaller than the overlapping area A of the first horizontal row c , making the second horizontal row more likely to cause electrostatic shock than the first horizontal row.

[0045] Figure 6 The difference between the third horizontal row and the first horizontal row from top to bottom in is mainly the area A probe exposed by the opening A of the corresponding insulating layer of the test pad TP. For example, the electrostatic test area RT further includes a fourth test pad TP4 disposed adjacent to the first test pad TP1 and a conductive pattern CP disposed adjacent to the first conductive pattern CP1 and at least partially overlapping with the fourth test pad TP4, wherein the distance d (e.g., distance d1) between the first conductive pattern CP1 and the first test pad TP1 is the same as the distance d between the conductive pattern CP and the fourth test pad TP4, the insulating layer 123 further includes a fourth opening A4 exposing the fourth test pad TP4, and the area A probe1 exposed by the first opening A1 of the first test pad TP1 is different from the area A probe4 exposed by the fourth opening A4 of the fourth test pad TP4. Taking Figure 6 as an example, the A probe of the third horizontal row may be greater than the A probe of the first horizontal row, making the third horizontal row more likely to cause electrostatic shock than the first horizontal row, but not limited thereto. In other embodiments, although not shown, the A probe of the third horizontal row may be smaller than the A probe of the first horizontal row, making the third horizontal row less likely to cause electrostatic shock than the first horizontal row.

[0046] As mentioned above, in addition to adjusting the corresponding breakdown voltage by increasing the distance d between the test pad TP and the corresponding conductive pattern CP, the breakdown voltage corresponding to the test pad TP can also be adjusted by adjusting the overlapping area A c between the conductive pattern CP and the corresponding test pad TP and / or adjusting the area A probe exposed by the opening A of the insulating layer of the test pad TP.

[0047] Therefore, Figures 6 to 8 in the embodiment of , the breakdown voltage is adjusted by adjusting the overlapping area A c between the conductive pattern CP and the corresponding test pad TP and the area A probeTo fine-tune the breakdown voltage corresponding to the test pad TP to detect a finer breakdown voltage value. For example, the test pad TP at the leftmost of the first horizontal row may correspond to a breakdown voltage of 250 volts, the test pad TP at the leftmost of the second horizontal row may correspond to a breakdown voltage of 300 volts, and the test pad TP at the leftmost of the third horizontal row may correspond to a breakdown voltage of 200 volts, and so on for other test pads TP.

[0048] Please refer to Figures 9 to 11 . Figure 9 The cross-sectional views of the first to third horizontal rows counted from top to bottom in Figure 5 、 Figure 10 and Figure 11 . In Figure 9 , the distance d between multiple test pads TP in the same vertical row and the corresponding multiple conductive patterns CP is the same, and the distance d between multiple test pads TP in different vertical rows and the corresponding multiple conductive patterns CP is different, so that multiple test pads TP in the same vertical row correspond to the same breakdown voltage, and multiple test pads TP in different vertical rows correspond to different breakdown voltages.

[0049] Similar to Figure 6 , Figure 9 The main difference between the second horizontal row and the first horizontal row counted from top to bottom in c lies in the different overlapping areas A c . For example, the overlapping area A c of the second horizontal row can be larger than the overlapping area A c of the first horizontal row, making the second horizontal row less likely to be damaged by electrostatic discharge (corresponding to a higher breakdown voltage), but not limited thereto. In other embodiments, although not shown, the overlapping area A c of the second horizontal row can be smaller than the overlapping area A probe of the first horizontal row, making the second horizontal row more likely to be damaged by electrostatic discharge (corresponding to a lower breakdown voltage).

[0050] Figure 9 The main difference between the third horizontal row and the first horizontal row counted from top to bottom in lies in the different areas A probe exposed by the openings A of the corresponding insulating layers of the test pads TP. For example, the A probe of the third horizontal row can be smaller than the A probe of the first horizontal row, making the third horizontal row less likely to be damaged by electrostatic discharge (corresponding to a higher breakdown voltage), but not limited thereto. In other embodiments, although not shown, the A probe of the third horizontal row can be larger than the A

[0051] of the first horizontal row, making the third horizontal row more likely to be damaged by electrostatic discharge (corresponding to a lower breakdown voltage).

[0051] The method for detecting electrostatic discharge may include measuring the resistance value of a test pad before performing the next process. If the measured resistance value is greater than the threshold, the next process is executed. If the measured resistance value is less than or equal to the threshold, it is further confirmed whether there is electrostatic injury.

[0052] Take Figure 12 as an example. The method for detecting electrostatic discharge may include executing Process 1 (Step ST100). For example, Process 1 can be one of the processes for manufacturing a panel or a semiconductor component, such as photoresist coating, but not limited thereto.

[0053] After completing Process 1 and before executing the next process (such as Process 2), it can be first confirmed whether the resistance value is less than or equal to the threshold (Step ST102). For example, two pointers of a multimeter can be respectively contacted with Figure 2 or Figure 6 one of the test pads TP and a detection pad (not shown) electrically connected to a plurality of conductive patterns CP to measure whether the resistance value between the test pad TP and the detection pad is less than or equal to the threshold; or, two pointers of a multimeter can be respectively contacted with Figure 3 or Figure 9 two adjacent test pads TP overlapping with the same conductive pattern CP to measure whether the resistance value between the two adjacent test pads TP is less than or equal to the threshold.

[0054] If the resistance value exceeds the threshold, Process 2 is executed (Step ST104). Process 2 can also be one of the processes for manufacturing a panel or a semiconductor component, such as an exposure process, but not limited thereto. If the resistance value is less than or equal to the threshold, it is confirmed whether there is electrostatic injury (Step ST106). For example, an optical microscope can be used to confirm the defect type of the detection pad. Then, an Automated Optical Inspection (AOI) system can be used to confirm whether there are electrostatic discharge burn marks outside the electrostatic test area (Step ST108). Then, the electrostatic value (for example, the electrostatic value of the process, machine, and / or environment experienced) is confirmed to find out the suspicious factors (Step ST110). Thereby, it is judged how to improve the process, machine, and / or environment, etc. to reduce the electrostatic discharge phenomenon, or how to improve the electrostatic protection ability of the area subjected to electrostatic discharge during product design.

[0055] After completing Process 2 and before executing the next process (such as Process 3), it can be first confirmed whether the resistance value is less than or equal to the threshold (Step ST112). The method for confirming the resistance value can refer to the foregoing and will not be repeated here.

[0056] If the resistance value exceeds the threshold, Process Three (step ST114) is executed. Process Three can also be one of the processes for manufacturing a panel or a semiconductor component, such as a developing process, but is not limited thereto. If the resistance value is less than or equal to the threshold, steps ST106, ST108, and ST110 can be continued.

[0057] After Process Three is completed and before the next process (such as Process Four) is executed, it can be first confirmed whether the resistance value is less than or equal to the threshold (step ST116). The method for confirming the resistance value can refer to the foregoing and will not be repeated here.

[0058] If the resistance value exceeds the threshold, Process Four (step ST118) is executed. Process Four can also be one of the processes for manufacturing a panel or a semiconductor component, such as an etching process, but is not limited thereto. If the resistance value is less than or equal to the threshold, steps ST106, ST108, and ST110 can be continued.

[0059] It should be understood that Figure 12 These are only examples. In other embodiments, more processes and more steps for confirming the resistance value can be included, and the number of processes and / or the number of steps for confirming the resistance value are not limited herein.

[0060] In summary, in the embodiments of the present disclosure, an electrostatic test area can be set in at least one of the active area and the peripheral area of the substrate to monitor the electrostatic discharge phenomenon in the process. Thus, corresponding corrections or designs can be made according to the monitoring results, thereby improving the yield or reliability of the product.

[0061] The above embodiments are only used to illustrate the technical solutions of the present disclosure and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0062] Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure. Moreover, the features between various embodiments can be arbitrarily mixed and replaced to form other new embodiments. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods, and steps developed currently or in the future from the disclosed content of the present disclosure. As long as they can perform substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claim and embodiment. The protection scope of the present disclosure shall be defined by the appended claims.

Claims

1. A substrate circuit structure, characterized in that, Comprising: a substrate including an active region and a peripheral region adjacent to the active region; and a circuit layer disposed on the substrate and including an electrostatic test region disposed in at least one of the active region and the peripheral region, wherein the electrostatic test region includes: a first test pad corresponding to a first breakdown voltage; and a second test pad disposed adjacent to the first test pad and corresponding to a second breakdown voltage different from the first breakdown voltage.

2. The substrate circuit structure according to claim 1, wherein The electrostatic test region further includes: a first conductive pattern at least partially overlapping with the first test pad; and a second conductive pattern at least partially overlapping with the second test pad.

3. The substrate circuit structure according to claim 2, wherein The distance between the first conductive pattern and the first test pad is different from the distance between the second conductive pattern and the second test pad.

4. The substrate circuit structure according to claim 2, wherein, The overlapping area of the first conductive pattern and the first test pad is the same as the overlapping area of the second conductive pattern and the second test pad.

5. The substrate circuit structure according to claim 2, wherein The electrostatic test region further includes: an insulating layer including a first opening exposing the first test pad; and another insulating layer including a second opening exposing the second test pad, wherein the area of the first test pad exposed by the first opening is the same as the area of the second test pad exposed by the second opening.

6. The substrate circuit structure according to claim 5, wherein, The electrostatic test region further includes: a third test pad disposed adjacent to the first test pad; and a third conductive pattern disposed adjacent to the first conductive pattern and at least partially overlapping with the third test pad; wherein the distance between the first conductive pattern and the first test pad is the same as the distance between the third conductive pattern and the third test pad, the insulating layer further includes a third opening exposing the third test pad, and the area of the first test pad exposed by the first opening is different from the area of the third test pad exposed by the third opening.

7. The substrate circuit structure according to claim 2, wherein The electrostatic test region further includes: a fourth test pad disposed adjacent to the first test pad; and a fourth conductive pattern at least partially overlapping with the fourth test pad, wherein the distance between the first conductive pattern and the first test pad is the same as the distance between the fourth conductive pattern and the fourth test pad, and the overlapping area of the fourth conductive pattern and the fourth test pad is different from the overlapping area of the first conductive pattern and the first test pad.

8. The substrate circuit structure according to claim 2, wherein, The electrostatic test region further includes: a fifth test pad disposed adjacent to the first test pad and corresponding to the first breakdown voltage, wherein the fifth test pad at least partially overlaps with the first conductive pattern and does not overlap with the second conductive pattern.

9. The substrate circuit structure according to claim 2, characterized in that, The first conductive pattern and the second conductive pattern are electrically connected to a reference voltage.

10. The substrate circuit structure according to claim 1, wherein, The substrate further includes a redundant region adjacent to the active region and the peripheral region, and the circuit layer further includes another electrostatic test region disposed in the redundant region.

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