Double-gear GaN power tube grid bias control integrated circuit

Abstract

The invention belongs to the technical field of integrated circuit design, and particularly relates to a double-gear GaN power tube grid bias control integrated circuit. The integrated circuit comprises a GaN power tube, a positive voltage power supply, a DC-DC negative voltage power supply, a negative voltage linear voltage stabilizing circuit, a 11-bit digital-to-analog converter, a gate driving buffer, a gate voltage operation control module, a gate voltage adjusting circuit, a current detection module, a temperature detection module and a 11-bit analog-to-digital converter. Aiming at the application of the GaN power tube in a radio frequency front-end transmitting channel, the invention provides a bias solution which is highly integrated and low in power consumption and aims at the GaN power tube technology, so that the number of off-chip elements is greatly reduced, and a power amplifier is enabled to work in a required optimal bias state no matter how voltage, temperature and other environmental parameters change.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a dual-gear GaN power transistor gate bias control integrated circuit. Background Art

[0002] The GaN power transistor is a new type of wide-bandgap power semiconductor device mainly made of gallium nitride. The heterostructure represented by AIGaN / GaN has a higher electron mobility. Its high-concentration two-dimensional electron gas enables it to have a large-density current, low on-resistance, high switching speed, and high operating frequency, and is widely used in fields such as driverless, radar base stations, photovoltaic power generation, and consumer electronics fast charging.

[0003] In the 5G era, the mobile communication infrastructure will undergo a comprehensive update. Since 5G generally adopts a large-scale MIMO architecture, the number of antenna channels in the base station has increased sharply. The broadband modulation of 5G transmission requires the PA to provide higher gain, higher efficiency, and more stringent linearity. Moreover, the operating frequency points of 5G are 2.5 GHz and 3.5 GHz, and will be extended to 4.9 GHz in the future, and even 28 GHz. Therefore, the key technology part in the 5G system - the radio frequency power device has also undergone major changes. Currently, the base station power amplifier is mainly LDMOS technology and GaAs technology. The GaN radio frequency power amplifier has a wider bandwidth, higher power-added efficiency, larger power density, and smaller volume, and can be better applied to large-scale MIMO. Therefore, the GaN radio frequency power amplifier for 5G base stations will become the mainstream technology, gradually occupying the markets of LDMOS and GaAs, and becoming the mainstream technology for RF power applications.

[0004] When the GaN power transistor is used as power amplification in the radio frequency front-end transmission channel, it is necessary to apply a suitable bias to its gate voltage, including: the negative power supply for the gate of the GaN power transistor, the positive power supply for the gate of the GaN power transistor, the operation of the gate bias voltage of the GaN power transistor, the real-time adjustment of the gate bias voltage of the GaN power transistor, the monitoring of the drain current of the GaN power transistor, the monitoring of the operating temperature of the GaN power transistor, the AD / DA conversion of the drain current and operating temperature information of the GaN power transistor, and the gate current drive of the GaN power transistor.

[0005] In the prior art, the currently common GaN power transistor gate bias circuits mostly use discrete components to independently drive it, and a negative voltage power supply needs to be externally connected. In the actual application process, the independent gate bias circuits of each part are difficult to integrate, which is not conducive to the miniaturization of the device, and there are many externally connected power supplies, which does not conform to the engineering design; for the application of the GaN power transistor in the radio frequency front-end transmission channel, a highly integrated and low-power bias solution is required to reduce the number of off-chip components and simplify the closed-loop system design. Therefore, the present invention proposes a dual-gear GaN power transistor gate bias control integrated circuit architecture.

[0006] In summary, there is currently no GaN power transistor gate bias control integrated circuit architecture with full-module multi-function integration.

[0007] To promote the highly integrated, low-power, and fast dynamic adjustment development of the transmission channel in the mobile communication radio frequency front end, it is necessary to invent a GaN power transistor gate bias control integrated circuit that meets the application requirements in the transmission channel of the mobile communication radio frequency front end. Therefore, the present invention proposes a dual-gear GaN power transistor gate bias control integrated circuit architecture. Summary of the Invention

[0008] The purpose of the present invention is to provide a dual-gear GaN power transistor gate bias control integrated circuit architecture to solve the problems arising in the above background.

[0009] The dual-gear GaN power transistor gate bias control integrated circuit provided by the present invention has an architecture including: a GaN power transistor, a positive voltage power supply, a DC-DC negative voltage power supply, a negative voltage linear voltage regulator module, an 11-bit digital-to-analog converter, a gate drive buffer, a gate voltage operation control module, a gate voltage adjustment module, a current detection module, a temperature detection module, an 11-bit analog-to-digital converter, and a MIPI interface; where:

[0010] The positive voltage power supply is used to convert the input voltage V bat into a fixed supply voltage VDD to supply power to the DC-DC negative voltage power supply, the negative voltage linear voltage regulator circuit, the 11-bit digital-to-analog converter, the gate drive buffer, the gate voltage operation control module, the gate voltage adjustment module, the current detection module, the temperature detection module, and the 11-bit analog-to-digital converter;

[0011] The DC-DC negative voltage power supply is used to convert the input voltage V bat into a fixed negative voltage V NEG to provide the required negative voltage potential for the negative voltage linear voltage regulator circuit and to have driving ability for the GaN power transistor, the negative voltage linear voltage regulator circuit, the 11-bit digital-to-analog converter, and the gate drive buffer;

[0012] The negative voltage linear voltage regulator module linearly regulates the negative power supply voltage output by the DC-DC negative voltage power supply to provide a fixed ripple-free negative voltage V EE for the 11-bit digital-to-analog converter and the gate drive buffer and to have driving ability;

[0013] The 11-bit digital-to-analog converter is used to convert the 11-bit gate voltage control digital signal V gs_ctrl <0:10> generated by the gate voltage operation control module into a gate voltage analog signal V gs_Analog and output it to the gate drive buffer to provide the required DC gate voltage for the GaN power transistor;

[0014] The gate drive buffer drives and isolates the gate voltage generated by the 11-bit digital-to-analog converter, and provides the required gate bias voltage V gs for the GaN power transistor, and has current driving ability;

[0015] The gate voltage operation control module generates a gate voltage control digital signal V gs_ctrl <0:10> according to the working requirements of the GaN power transistor to modulate the gate voltage Vgs. The working modes are divided into two modes: open-loop control mode and loop real-time control mode; in the open-loop control mode, the gate voltage operation control module obtains the gate voltage control digital signal according to the input data sdata; in the loop real-time control mode, the gate voltage operation control module generates a gate voltage control digital signal for V gs_SEN <0:10> according to the input data sdata and the gate voltage adjustment data V gs <0:10> generated by the gate voltage adjustment module to adjust the amplitude of V

[0016] The gate voltage adjustment module generates gate voltage adjustment data V i_SEN <0:10> according to the current detection data V T_SEN <0:10> and temperature detection data V gs_SEN <0:10> obtained by the current detection module and the temperature detection module, and real-time controls the gate voltage of the GaN power transistor to ensure that the current flowing through the GaN power transistor remains constant with the change of temperature and time, and ensure that the power amplifier works within the adjusted output power range;

[0017] The current detection module outputs the voltage detected on the resistor R sense to the 11-bit analog-to-digital converter, so as to obtain the current value flowing through the GaN power transistor;

[0018] The temperature detection module, when the power amplifier is working, monitors the temperature of the GaN power transistor in real time, and outputs the temperature information to the 11-bit analog-to-digital converter, so as to obtain the temperature value of the GaN power transistor;

[0019] The 11-bit analog-to-digital converter is used to quantify the drain current and working temperature of the GaN power transistor, and converts the analog quantities of the current information and temperature information obtained by the current detection module and the temperature detection module into 11-bit digital quantities: temperature detection data V T_SEN <0:10> and current detection data V i_SEN <0:10>, and outputs them to the gate voltage adjustment circuit to adjust the gate voltage V gs .

[0020] The MIPI interface, as a serial communication interface, enables the GaN power transistor gate bias control system to communicate with external information. The open-loop control data signal sdata is processed and then output to the gate voltage operation control module.

[0021] Furthermore:

[0022] The positive voltage power supply includes a low dropout linear regulator (LDO) and an under-voltage lockout (UVLO) protection circuit; the low dropout linear regulator is used to convert the input voltage into a fixed supply voltage V DD ; the under-voltage lockout protection circuit UVLO monitors in real time whether the supply voltage V DD drops below the voltage for the system to operate normally and protects against this situation.

[0023] The DC-DC negative voltage power supply adopts an Inverting Buck-Boost structure to convert the input voltage V bat into a fixed negative voltage V NEG ; there are two working modes in total: the CCM mode and the DCM mode to ensure the conversion efficiency.

[0024] The negative voltage linear voltage regulation module includes a low dropout linear regulator (LDO) and an under-voltage lockout (UVLO) protection circuit; the low dropout linear regulator is used to convert the negative voltage V NEG into a fixed ripple-free negative voltage V EE ; the under-voltage lockout protection circuit UVLO monitors in real time whether the negative voltage V EE is within the specified voltage range and controls whether the 11-bit digital-to-analog converter and the gate drive buffer operate.

[0025] The gate voltage adjustment module receives the temperature detection data V T_SEN <0:10> and the current detection data V i_SEN <0:10> in real time; when either the temperature detection data V T_SEN <0:10> or the current detection data V i_SEN <0:10> is valid, the gate voltage adjustment module (8) updates the gate voltage adjustment data V gs_SEN <0:10> and outputs it to the gate voltage operation module, so that the current flowing through the GaN power transistor does not change with temperature and time.

[0026] When in the open-loop control mode, the gate voltage operation control module only calculates and generates the digital control quantity V gs_ctrl <0:10> of the bias voltage in real time through the input data sdata; when in the loop real-time control mode, the gate voltage operation control module receives the input data sdata and also receives the quantization data of the drain current and operating temperature of the GaN power transistor in real time, that is, the gate voltage adjustment data V gs_SEN<0:10>, calculate the digital control quantity V of the gate bias voltage gs_ctrl <0:10>, adjust the gate voltage in real time according to the environmental parameters.

[0027] The current detection module amplifies the small differential voltage V generated on the current detection resistor R under the condition of high input common-mode voltage sense to obtain a current detection voltage V that reflects the drain current information of the GaN power transistor sense i .

[0028] The temperature detection module monitors the working temperature of the GaN power transistor in real time and outputs a temperature detection voltage V T which is linearly proportional to the temperature and has a fixed DC offset that can meet the detection from -40 degrees to 125 degrees.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] The present invention provides a highly integrated gate voltage bias management scheme for the application of GaN power transistors in the radio frequency front-end transmission channel. The present invention has fewer off-chip components, highly integrated internal modules, and is easy to miniaturize; by dynamically controlling the gate voltage of the GaN power transistor, quantifying the drain current and working temperature of the power amplifier, and calculating the digital control quantity of the bias voltage in real time, the power amplifier can work in the required optimal bias state regardless of changes in voltage, temperature, and other environmental parameters. Specifically:

[0031] A circuit scheme for generating a negative voltage power supply is provided, which can convert the input voltage V bat into a fixed negative voltage V NEG ; reduce the external power supply of the system, realize the integration of negative voltage power supply, and be more in line with the engineering design.

[0032] A circuit scheme for gate voltage driving is provided, designing a high-bandwidth and high-swing gate voltage driving buffer to effectively drive small loads and at the same time follow the changes of the digital-to-analog converter in real time to improve the GaN driving ability.

[0033] A circuit scheme for real-time gate voltage operation control is provided. According to the working requirements of the GaN power transistor, a two-gear working mode is set, and the gate voltage is modulated in real time according to the input data. The working gears are divided into an open-loop control mode and a loop real-time control mode; in the open-loop control mode, according to the input data, a gate voltage control digital signal is obtained; in the loop real-time control mode, according to the input data and the gate voltage adjustment data generated by the gate voltage adjustment module, a gate voltage control digital signal is generated to adjust the amplitude of V gs in real time.

[0034] ​A circuit solution for real-time gate voltage adjustment is provided. According to the current detection data and temperature detection data, gate voltage adjustment data is generated to control the gate voltage of the GaN power transistor in real time, ensuring that the current flowing through the GaN power transistor remains constant with changes in temperature and time, and ensuring that the power amplifier operates within the adjusted output power range.

[0035] A circuit solution for drain current monitoring is provided. The drain current is monitored in real time through a sampling resistor, and then the gate voltage is adjusted in real time through analog-to-digital conversion and data processing.

[0036] A circuit solution for real-time temperature detection is provided. When the power amplifier is operating, the temperature of the GaN power transistor is monitored in real time, and the temperature information is output to an 11-bit analog-to-digital converter to obtain the temperature value of the GaN power transistor, and the gate voltage is adjusted in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the dual-gear GaN power transistor gate bias control integrated circuit architecture provided by the present invention.

[0038] Figure 2 Schematic diagram of the positive voltage power supply in the embodiment of the present invention.

[0039] Figure 3 Schematic diagram of the external circuit of the DC-DC negative voltage power supply chip in the embodiment of the present invention.

[0040] Figure 4 Schematic diagram of the internal circuit of the DC-DC negative voltage power supply chip in the embodiment of the present invention.

[0041] Figure 5 Schematic diagram of the negative voltage linear voltage regulator module in the embodiment of the present invention.

[0042] Figure 6 Schematic diagram of the 11-bit digital-to-analog converter in the embodiment of the present invention.

[0043] Figure 7 Schematic diagram of the gate drive buffer in the embodiment of the present invention.

[0044] Figure 8 Schematic diagram of the 11-bit analog-to-digital converter in the embodiment of the present invention.

[0045] Figure 9 Schematic diagram of the current detection, temperature detection, and 11-bit analog-to-digital converter in the embodiment of the present invention.

[0046] Reference numerals in the figure: 1. GaN power transistor; 2. Positive voltage power supply; 3. DC-DC negative voltage power supply; 4. Negative voltage linear voltage regulator module; 5. 11-bit digital-to-analog converter; 6. Gate drive buffer; 7. Gate voltage operation control module; 8. Gate voltage adjustment module; 9. Current detection module; 10. Temperature detection module; 11. 11-bit analog-to-digital converter; 12. MIPI interface. Detailed implementation

[0047] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] The present invention discloses a dual-gear GaN power transistor gate bias control integrated circuit architecture, as Figure 1 shown, including: GaN power transistor (1), positive voltage power supply (2), DC-DC negative voltage power supply (3), negative voltage linear voltage regulator module (4), 11-bit digital-to-analog converter (5), gate drive buffer (6), gate voltage operation control module (7), gate voltage adjustment module (8), current detection module (9), temperature detection module (10), 11-bit analog-to-digital converter (11), MIPI interface (12).

[0049] The positive voltage power supply (2) is connected to the DC-DC negative voltage power supply (3), negative voltage linear voltage regulator module (4), 11-bit digital-to-analog converter (5), gate drive buffer (6), gate voltage operation control module (7), gate voltage adjustment module (8), current detection module (9), temperature detection module (10), 11-bit analog-to-digital converter (11), and converts the input voltage V bat into a fixed supply voltage V DD , and provides positive voltage for each connected module.

[0050] The DC-DC negative voltage power supply (3) is connected to the negative voltage linear voltage regulator module (4), and converts the input voltage V bat into a fixed negative voltage, and has driving ability for the GaN power transistor (1), negative voltage linear voltage regulator module (4), 11-bit digital-to-analog converter (5), and gate drive buffer (6).

[0051] The negative voltage linear voltage regulator module (4) is connected to the 11-bit digital-to-analog converter (5) and the gate drive buffer (6), linearly stabilizes the negative power supply voltage output by the DC-DC negative voltage power supply (3), and provides a fixed negative voltage V EE, and has driving ability, while providing V for the 11-bit digital-to-analog converter (5) and the gate drive buffer (6) EE The undervoltage latch protection signal V EE UVLO .

[0052] The 11-bit digital-to-analog converter (5) is connected to the gate drive buffer (6) and the gate voltage operation control module (7), and converts the 11-bit gate voltage control digital signal V gs_ctrl <0:10> generated by the gate voltage operation control module (7) into a gate voltage analog signal V gs_Analog , and outputs it to the gate drive buffer (6) to provide the required DC gate voltage bias for the GaN power transistor (1).

[0053] The gate drive buffer (6) is connected to the 11-bit digital-to-analog converter (5) and the gate of the GaN power transistor (1), isolates the drive of the gate voltage analog signal V gs_Analog generated by the 11-bit digital-to-analog converter (5), and provides the required gate bias voltage V gs for the GaN power transistor (1), and has current driving ability.

[0054] The gate voltage operation control module (7) is connected to the 11-bit digital-to-analog converter (5), the gate voltage adjustment module (8) and the MIPI interface (12), and divides the operation of the GaN power transistor (1) into two gears. In the open-loop control mode, the gate voltage operation control module (7) obtains the gate voltage control digital signal V gs_ctrl <0:10> according to the input data sdata; in the loop real-time control mode, the gate voltage operation control module (7) generates the gate voltage control digital signal V gs_SEN <0:10> according to the input data sdata and the gate voltage adjustment data V gs_ctrl <0:10> generated in the gate voltage adjustment module (8) to adjust the amplitude of V gs in real time.

[0055] The gate voltage adjustment module (8) is connected to the gate voltage operation control module (7) and the 11-bit analog-to-digital converter (11), and obtains the gate voltage adjustment data V i_SEN <0:10> and the temperature detection data V T_SEN <0:10> generated by the 11-bit analog-to-digital converter (11), and outputs the gate voltage adjustment data V gs_SEN <0:10> to the gate voltage operation control module (7) to control the gate voltage of the GaN power transistor (1) in real time, ensure that the current flowing through the GaN power transistor remains constant with the change of temperature and time, and ensure that the power amplifier works within the adjusted output power range.

[0056] The current detection module (9) is connected to the drain sampling resistor R of the GaN power transistor (1) senseis connected to the 11-bit analog-to-digital converter (11), and outputs the current detection voltage V i to the 11-bit analog-to-digital converter (11), so as to obtain the current information flowing through the GaN power transistor (1).

[0057] The temperature detection module (10) is connected to the GaN power transistor (1) and the 11-bit analog-to-digital converter (11). When the power amplifier is working, it monitors the temperature of the GaN power transistor (1) in real time, and outputs the temperature detection voltage V T to the 11-bit analog-to-digital converter (11), so as to obtain the working temperature information of the GaN power transistor (1).

[0058] The 11-bit analog-to-digital converter (11) is connected to the gate voltage adjustment module (8), the current detection module (9) and the temperature detection module (10), and converts the analog quantities of the current information and temperature information obtained by the current detection module (9) and the temperature detection module (10) into 11-bit digital quantities: the temperature detection data V T_SEN <0:10> and the current detection data V i_SEN <0:10>, and outputs them to the gate voltage adjustment module (8) to adjust the gate voltage V gs .

[0059] The MIPI interface (12) is connected to the gate voltage operation control module (7), processes the open-loop control data signal sdata through operation, and outputs it to the gate voltage operation control module (7).

[0060] The following further describes the positive power supply (2), the DC-DC negative power supply (3), the negative voltage linear voltage regulator module (4), the 11-bit digital-to-analog converter (5), the gate driver buffer (6), the gate voltage operation control module (7), the gate voltage adjustment module (8), the current detection module (9), the temperature detection module (10), and the 11-bit analog-to-digital converter (11).

[0061] Referring to Figure 2 as shown, the positive power supply (2) includes a low-dropout linear regulator LDO and an under-voltage lockout protection circuit N5; the low-dropout linear regulator LDO includes a bandgap reference source N1, a soft-start circuit N2, an amplifier N3, a compensation network N4, a resistor R1, a resistor R2, a capacitor C L , and a power transistor MP.

[0062] The VDD port of the bandgap reference source N1 is respectively connected to the input voltage V bat, the VDD port of the soft start circuit N2, the VDD port of the amplifier N3, the source of the power transistor MP, the VSS port of the bandgap reference source N1 is connected to ground, and the VBG port of the bandgap reference source N1 is connected to the VREF port of the soft start circuit N2. The VSS port of the soft start circuit N2 is connected to ground, and the OUT port of the soft start circuit N2 is connected to the INP port of the amplifier N3. The OUT port of the amplifier N3 is respectively connected to the gate of the power transistor MP and the D1 port of the compensation network N4. The INN port of the amplifier N3 is respectively connected to the D3 port of the compensation network N4, one end of the resistor R1, and one end of the resistor R2. The VSS port of the amplifier N3 is connected to ground. The D2 port of the compensation network N4 is respectively connected to the drain of the power transistor MP, the other end of the resistor R1, the capacitor C L one end, the VDD port of the under-voltage lockout protection circuit N5, the output terminal V DD . The other end of the resistor R2 is connected to ground. The capacitor C L the other end is connected to ground. The VSS port of the under-voltage lockout protection circuit N5 is connected to ground, and the VDD_UVLO port of the under-voltage lockout protection circuit is an output of the positive power supply (2).

[0063] The bandgap reference source N1 in this embodiment has the characteristics of low temperature drift and low mismatch. The amplifier N3 has the characteristics of high gain and low mismatch.

[0064] Working principle of the positive power supply (2): Refer to Figure 2 As shown, the bandgap reference source N1 provides a reference voltage for the GaN power transistor gate bias control integrated circuit system. The soft start circuit N2 is used to avoid excessive charging current caused by the charging of the capacitor C L by the VDD port during the power-on process of the low-dropout linear regulator LDO. The amplifier N3 clamps the voltage at the INN port and the INP port to ensure that the two voltages are equal. The compensation network N4 and the capacitor C L perform frequency compensation on the low-dropout linear regulator LDO to ensure loop stability. The resistor R1 and the resistor R2 form a resistor feedback network, and the reference voltage is divided by the resistors to make the output voltage V DD a constant voltage value. Since the output voltage V DD is used as the power supply voltage to supply power to multiple modules of the system, the under-voltage lockout protection circuit N5 monitors the value of V DD in real time to ensure normal system power supply and avoid damage to the system.

[0065] Refer to Figure 3 As shown, the external circuit of the DC-DC negative power supply (3) chip includes a DC-DC negative power supply module N11, a capacitor C in , a capacitor C2, a capacitor C3, a capacitor C O , and an inductor L1.

[0066] The VBAT port of the DC-DC negative voltage power supply module N11 is respectively connected to one end of capacitor C in One end, one end of capacitor C2, V bat Input port. The VSS port of the DC-DC negative voltage power supply module N11 is connected to ground. The VDD port of the DC-DC negative voltage power supply module N11 is connected to one end of C3. The VNEG port of the DC-DC negative voltage power supply module N11 is respectively connected to the other end of C2, the other end of C3, one end of C O One end, V NEG Output port. The SW port of the DC-DC negative voltage power supply module N11 is connected to one end of inductor L1. The other end of inductor L1 is respectively connected to the other end of C O The other end and ground.

[0067] Operating principle of the external circuit of the DC-DC negative voltage power supply (3) chip: Refer to Figure 3 As shown, the DC-DC negative voltage power supply module N11, inductor L1 and capacitor C O constitute a complete power stage, converting the input voltage Vbat into a negative voltage V NEG , while ensuring the conversion efficiency. Capacitor C in and capacitor C2 decouple and filter the input voltage V bat . Capacitor C3 is used for voltage stabilization power supply and improves the stability of the voltage at the VDD port.

[0068] Refer to Figure 4 As shown, the internal circuit of the DC-DC negative voltage power supply (3) chip, that is, the DC-DC negative voltage power supply module N11, includes a power supply module N12, a conduction time control module N13, a turn-off time control module N14, a ZCS detection module N15, a PWM logic control module N16, a drive module N17, a soft start module N18, a ripple control module N19, and a power stage N20.

[0069] The VSS of the power supply module N12 is connected to ground. The VBAT port of the power supply module N12 is respectively connected to the V bat Input port, the VBAT port of the drive module N17, and the VBAT port of the power stage N20. The VDD port of the power supply module N12 is respectively connected to the V DDThe output port, the VDD port of the turn-on time control module N13, the VDD port of the turn-off time control module N14, the VDD port of the ZCS detection module N15, the VDD port of the PWM logic control module N16, the VDD port of the drive module N17, the VDD port of the soft start module N18, the VDD port of the ripple control module N19, and the VDD port of the power stage N20. The VSS port of the turn-on time control module N13 is connected to the ground. The TON port of the turn-on time control module N13 is connected to the TON port of the PWM logic control module N16. The VSS port of the turn-off time control module N14 is connected to the ground. The TOFF port of the turn-off time control module N14 is connected to the TOFF port of the PWM logic control module N16. The VSS port of the ZCS detection module N15 is connected to the ground. The ZCS port of the ZCS detection module N15 is connected to the ZCS port of the PWM logic control module N16. The VSS port of the soft start module N18 is connected to the ground. The CL port of the soft start module N18 is connected to the CL port of the PWM logic control module N16. The VSS port of the ripple control module N19 is connected to the ground. The RIP port of the ripple control module N19 is connected to the RIP port of the PWM logic control module N16. The VNEG port of the ripple control module N19 is respectively connected to V NEG The output port, the VNEG port of the drive module N17, and the VNEG port of the power stage N20. The VSS port of the drive module N17 is connected to the ground. The PWMH port of the drive module N17 is connected to the PWMH port of the PWM logic control module N16. The PWML port of the drive module N17 is connected to the PWML port of the PWM logic control module N16. The VGH port of the drive module N17 is connected to the VGH port of the power stage N20. The VGL port of the drive module N17 is connected to the VGL port of the power stage N20. The SW port of the power stage N20 is connected to the SW output port. The VSS port of the PWM logic control module N16 is connected to the ground.

[0070] The working principle of the internal circuit of the DC-DC negative voltage power supply (3) chip: Refer to Figure 4 As shown, the power supply module N12 converts the input voltage V bat into the supply voltage V of the GaN power transistor gate bias control integrated circuit system DD。The signal of the TON port of the conduction time control module N13 is used to control the time when the PWMH port signal of the drive module N17 is at a high level. The signal of the TOFF port of the turn-off time control module N14 is used to control the time when the PWML port signal of the drive module N17 is at a high level, and the TOFF port signal is enabled and effective when the DC-DC negative voltage power supply (3) is in the soft start stage and the CCM operating mode. The ZCS port signal of the ZCS detection module N15 is also used to control the time when the PWML port signal of the drive module N17 is at a high level. When the current of the inductor L1 is less than 0, the ZCS port signal controls the PWML port signal to change from a high level to a low level, and the ZCS port signal is enabled and effective when the DC-DC negative voltage power supply (3) is in the DCM operating mode. The soft start module N18 is used to detect when the output signal is powered up, that is, to judge when the DC-DC negative voltage power supply (3) ends the soft start. NEG The ripple control module N19 is enabled and effective when the DC-DC negative voltage power supply (3) is in the DCM operating mode, and is used to judge and control the time when the PWMH port signal and the PWML port signal of the PWM logic control module N16 are both at a low level. The drive module N17 performs a level shift operation on the PWMH port signal and the PWML port signal, and makes them have driving ability, generating the VGH port signal and the VGL port signal, which can drive the power transistors in the power stage N20 and control the switching of the power transistors. The power stage N20 controls the switching of two internal power transistors and combines with the external circuit of the DC-DC negative voltage power supply (3) chip to achieve the function of converting the input voltage V bat to the negative voltage V NEG .

[0071] Referring to Figure 5 as shown, the negative voltage linear voltage regulator module (4) includes a negative voltage linear regulator LDO and an under-voltage lockout protection circuit N9; the negative voltage linear regulator LDO includes a soft start circuit N6, an amplifier N7, a compensation network N8, a resistor R3, a resistor R4, a capacitor C1, and a power transistor MN.

[0072] The VDD port of the soft start circuit N6 is respectively connected to the V DD output port of the positive voltage power supply (2), the VDD port of the amplifier N7, one end of the resistor R4, one end of the capacitor C1, and the VDD port of the under-voltage lockout protection circuit N9. The VREF port of the soft start circuit N6 is connected to the V BG port of the bandgap reference source N1 of the positive voltage power supply (2). The VSS port of the soft start circuit N6 is respectively connected to the output V NEGThe VSS port of the port, amplifier N7, and the source of the power transistor MN. The OUT port of the soft start circuit N6 is connected to the INN port of the amplifier N7. The INP port of the amplifier N7 is respectively connected to the D1 port of the compensation network N8, one end of the resistor R3, and one end of the resistor R4. The OUT port of the amplifier N7 is respectively connected to the D3 port of the compensation network N8 and the gate of the power transistor MN. The drain of the power transistor MN is connected to one end of the resistor R3. The D2 port of the compensation network N8 is respectively connected to one end of the resistor R3, one end of the capacitor C1, the VSS port of the undervoltage lockout protection circuit N9, V EE Output port. The VEE_UVLO port of the undervoltage lockout protection circuit N9 is an output port of the negative voltage linear voltage regulator module (4).

[0073] The amplifier N7 in this embodiment features high gain and low mismatch.

[0074] Operating principle of the negative voltage linear voltage regulator module (4): Refer to Figure 5 As shown, the soft start circuit N6 is used to avoid excessive charging current caused by the charging of the capacitor C1 at the V EE port when the negative voltage linear regulator LDO is powered on. The amplifier N7 clamps the voltage at the INN port and the INP port to ensure that the two voltages are equal. The compensation network N8 and the capacitor C1 perform frequency compensation on the negative voltage linear regulator LDO to ensure loop stability. The resistors R3 and R4 form a resistor feedback network, and the reference reference voltage is divided by the resistors to make the output voltage V EE a constant voltage value. Since the output voltage V EE is used as a negative power supply voltage to supply power to multiple modules of the system, the undervoltage lockout protection circuit N9 monitors the value of V EE in real time to ensure normal system power supply and avoid damage to the system.

[0075] Refer to Figure 6 As shown, the 11-bit digital-to-analog converter (5) includes a clock generation and drive circuit N21, an input register N22, a thermometer decoding circuit N23, a synchronous delay circuit N24, a synchronous latch and switch drive circuit N25, a bandgap reference source N26, a reference current source generation circuit N27, a current source bias voltage generation circuit N28, a four-phase differential switch current source array N29, a resistor Rp, and a resistor Rn.

[0076] The CLK_REG port of the clock generation and drive circuit N21 is connected to the CLK port of the input register N22. The CLK_DEC port of the clock generation and drive circuit N21 is respectively connected to the CLK port of the thermometer decoding circuit N23 and the CLK port of the synchronous delay circuit N24. The CLK_SW port of the clock generation and drive circuit N21 is connected to the CLK port of the synchronous latch and switch drive circuit N25. The VEE_UVLO input port is respectively connected to the EN port of the clock generation and drive circuit N21, the EN port of the input register N22, and the EN port of the synchronous latch and switch drive circuit N25. V gs_ctrl <0:10> The input port is connected to the REG_IN port of the input register N22. The REG_OUT port of the input register N22 is respectively connected to the IN port of the thermometer decoding circuit N23 and the IN port of the synchronous delay circuit N24. The OUT port of the thermometer decoding circuit N23 is connected to the MSB_IN port of the synchronous latch and switch drive circuit N25. The OUT port of the synchronous delay circuit N24 is connected to the LSB_IN port of the synchronous latch and switch drive circuit N25. The MSB_OUT port and the LSB_OUT port of the synchronous latch and switch drive circuit N25 are both connected to the four-phase differential switch current source array N29 to control the switch switching. The VBG port of the bandgap reference circuit N26 is connected to the VREF port of the reference current source N27. The IREF port of the reference current source N27 is connected to the IREF port of the current source bias voltage generation circuit N28. The Vbias1 port and the Vbias2 port of the current source bias voltage generation circuit N28 are respectively connected to the gates of M1 and M2 in all the cells of the four-phase differential switch current source array N29. One end of the resistor Rp and one end of the resistor Rn are connected to the drains of the switching transistors S1, S2, S3, and S4 in the four-phase differential switch current source array N29. The other end of the resistor Rp and the other end of the resistor Rn are connected to V NEG input port. The VDD ports of all the modules are all connected to V DD input port, and the VSS ports of all the modules are all connected to the VNEG input port.

[0077] Working principle of the 11-bit digital-to-analog converter (5): Refer to Figure 6As shown, the overall DAC uses parallel input and adopts 5-bit thermometer decoding and 6-bit binary decoding methods. VEE_UVLO enables the circuit. The reference voltage generated by the bandgap reference source N26 is sent into the reference current source circuit N27 to generate the reference current of the DAC, and based on this, the bias is generated through the current source bias voltage generation circuit N28. The CLK signal is provided to each module of the DAC with a clock after passing through the clock generation and driving circuit N21. After the 11-bit digital signal is input, it first passes through the input register N22 to ensure consistent delays in each path. Then, the high 5-bit MSB signal is sent to the thermometer decoding circuit N23 for decoding, and the low 6-bit LSB signal continues to align with the high-bit signal after passing through the synchronous delay circuit N24. Subsequently, all signals are synchronously latched and processed at the crosspoints by the switch driving circuit N25 to prevent the switching current source from entering the dead zone. The processed 31-bit thermometer code switch signal and 6-bit binary code switch signal are sent to the four-phase differential switch current source array N29 to control the current source. The four-phase differential switch is jointly controlled by the input signal and the clock signal, reducing the glitches and non-linearity of the DAC output. The currents in the current source array are respectively controlled to flow through the positive output terminal resistor and the negative output terminal resistor to generate the output voltage.

[0078] Referring to Figure 7 As shown, the gate drive buffer (6) includes an amplifier N10 and a resistor R5.

[0079] The VDD port of the amplifier N10 is connected to the V DD output port of the positive power supply (2). The INP port of the amplifier N10 is connected to the V gs_Analog output port of the 11-bit digital-to-analog converter N29. The EN port of the amplifier N10 is connected to the VEE_UVLO output port of the negative voltage linear voltage regulator module (4). The INN port of the amplifier N10 is respectively connected to the OUT port of the amplifier N10 and one end of the resistor R5. The VSS port of the amplifier N10 is connected to the V EE output port of the negative voltage linear voltage regulator module (4). The OUT port of the amplifier N10 is connected to one end of the resistor R5 to output the V gs_Buffer signal. One end of the resistor R5 is connected to the output terminal V gs_in .

[0080] The amplifier N10 in this embodiment has a wide bandwidth, high speed, and high driving ability. It adopts a two-stage structure. The first stage uses a PMOS transistor input to meet the lower input voltage range, and the second stage uses a class B output structure to improve the driving ability.

[0081] The working principle of the gate drive buffer (6): Referring to Figure 7 As shown, the amplifier N10 is connected through unity gain to form a buffer, and the V gs_Buffer signal output from the OUT port can promptly follow the output signal V of the 11-bit digital-to-analog convertergs_Analog , while improving the driving ability of V gs_Analog to be able to drive a 10Ω resistor.

[0082] Referring to Figure 8 As shown, the 11-bit analog-to-digital converter (11) includes a sample-and-hold circuit N30, a digital-to-analog converter N31, a comparator N32, an asynchronous logic control circuit N33, a switch circuit N34, a decoding circuit N35, a voltage-time converter N36, a phase detector N37, a time selector N38, a time-to-digital converter N39, a temperature code to binary code converter N40, and a two-way selector N41.

[0083] The INN port of the sample-and-hold circuit N30 is respectively connected to V refInput port, VCM port of digital-to-analog converter N31. The INP port of sample-and-hold circuit N30 is connected to the OUT port of two-way selector N41. The OUTP port of sample-and-hold circuit N30 is connected to the INP port of digital-to-analog converter N31. The OUTN port of sample-and-hold circuit N30 is connected to the INN port of digital-to-analog converter N31. The CAPB port of digital-to-analog converter N31 is connected to the CONTROL port of switch circuit N34. The VDACP port of digital-to-analog converter N31 is respectively connected to the INP port of comparator N32 and the VIP port of voltage-time converter N36. The VDACN terminal of digital-to-analog converter N31 is respectively connected to the INN port of comparator N32 and the VIN port of voltage-time converter N36. The OP port of comparator N32 is connected to the VCP port of asynchronous logic control circuit N33. The ON port of comparator N32 is connected to the VCN port of asynchronous logic control circuit N33. The CLKC port of comparator N32 is connected to the CLKC port of asynchronous logic control circuit N33. The CONTROL port of asynchronous logic control circuit N33 is connected to the INPUT port of switch circuit N34. The SELECT port of asynchronous logic control circuit N33 is connected to the SELECT port of two-way selector N41. The ST port of asynchronous logic control circuit N33 is connected to the ST port of voltage-time converter N36. The B1<0:7> port of switch circuit N34 is connected to the REGI1 port of decoder circuit N35. The OUTP port of voltage-time converter N36 is respectively connected to the VIP port of phase detector N37 and the VIP port of time selector N38. The OUTN port of voltage-time converter N36 is respectively connected to the VIN port of phase detector N37 and the VIN port of time selector N38. The OUT port of phase detector N37 is connected to the VI2 port of temperature code to binary code N40. The OUTP port of time selector N38 is connected to the VIP port of time-to-digital converter N39. The OUTN port of time selector N38 is connected to the VIN port of time-to-digital converter N39. The OUT port of time-to-digital converter N39 is connected to the VI1 port of temperature code to binary code N40. The OUT port of temperature code to binary code N40 is connected to the REGI2 port of decoder circuit N35. The REGO port of decoder circuit N35 is connected to V SEN <0:10> output port. The V1 port of two-way selector N41 is connected to V i Input port. The V2 port of two-way selector N41 is connected to V T Input port. The VDD ports of all modules are connected to V DD Input port, and the VSS ports of all modules are connected to the VNEG input port.

[0084] Working principle of 11-bit analog-to-digital converter (11): Refer to Figure 8As shown, when the system is powered on, the two-way selector N41 outputs the V i signal, and the output V SEN <0:10> is the digital code of the V i signal of the current signal. After 3 clock cycles, the two-way selector N41 starts to output the V T signal, which is input to the sample and hold circuit N30. The sampled voltage is output to the positive and negative input terminals of the comparator N32 for comparison, and the comparison result is input to the asynchronous logic control circuit N33 by VCP and VCN. The asynchronous logic control circuit N33 adjusts the output digital code of CONTORL according to the comparison result, which is input from the INPUT terminal of the switch circuit N34, controls the voltage of the lower capacitor plate of the digital-to-analog converter, adjusts the output voltages VDACP and VDACN of N31, and compares VDACP and VDACN again in the next comparison cycle. This process is repeated until the comparator completes 8 comparisons, that is, an 8-bit digital code is obtained, which is the high 8 bits of the sampled signal. After the high 8-bit comparison is completed, the ST port of N33 outputs an enable signal to control the voltage-time converter N36 to start working. The residual voltage of the high 8-bit comparison is converted into a time signal by N36, and then the phase detector N37 determines the positive and negative of the residual voltage, and the result is sent to the VI2 port of the temperature N40 through OUT. At the same time, the time signal is input to the VIP and VIN terminals of the time selector N38 to complete the delay path allocation of the time digital converter N39. The time digital converter N39 converts the input time signal into a digital signal and inputs it to the VI2 of the temperature code to binary code N40. N40 integrates the results of VI1 and VI2 and converts them into a binary code, that is, a 3.5-bit low-order digital code is obtained, and then it is input to the REGI2 of the decoding circuit N35. The decoding circuit integrates the high 8 bits and the low 3.5 bits, eliminates the redundancy of 0.5 bits, and outputs an 11-bit digital code V SEN <0:10>.

[0085] Referring to Figure 9 As shown, the current detection module (9), the temperature detection module (10) and the 11-bit analog-to-digital converter (11) include the sampling resistor R sense , the V to I converter N42, the amplifier N43, the analog-to-digital converter N44, the analog-to-digital converter N45, and the temperature detection module N46.

[0086] V DD The input ports are respectively connected to the VDD port of the V to I converter N42, the VDD port of the amplifier N43, the VDD port of the analog-to-digital converter N44, the VDD port of the analog-to-digital converter N45, and the VDD port of the temperature detection module N46. The INP port of the V to I converter N42 is connected to the sampling resistor R senseOne end, the INN port of the V-to-I converter N42 is respectively connected to the sampling resistor R sense The other end, the drain of the GaN power transistor (1). The OUT1 port of the V-to-I converter N42 is connected to the INP port of the amplifier N43. The OUT2 port of the V-to-I converter N42 is respectively connected to the INN port of the amplifier N43 and one end of the resistor R6. The VSS port of the V-to-I converter N42 is connected to the ground. The OUT port of the amplifier N45 is respectively connected to the IN port of the analog-to-digital converter and the other end of R6. The VSS port of the amplifier N43 is connected to the ground. The OUT port of the analog-to-digital converter N44 is connected to the V i SEN <0:10> output port. The VSS port of the analog-to-digital converter N44 is connected to the ground. The OUT port of the analog-to-digital converter N45 is connected to the V T_SEN <0:10> output port. The IN port of the analog-to-digital converter N45 is connected to the OUT port of the temperature detection module N46. The VSS port of the analog-to-digital converter N45 is connected to the ground. The VSS port of the temperature detection module N46 is connected to the ground.

[0087] Working principle of the current detection module (9), temperature detection module (10) and 11-bit analog-to-digital converter (11): The V-to-I converter N42 detects the voltage across the sampling resistor R sense At both ends, it is converted into current through the internal precision input resistor, and differentially amplified by the amplifier N43 to generate the current detection voltage V i Transmitted to the analog-to-digital converter N44 and converted into current detection data V i_SEN <0:10>. Inside the temperature detection module N46, through a triode, resistor and operational amplifier, the operating temperature of the GaN power transistor (1) is detected in real time to generate a temperature detection voltage V that is linearly proportional to the temperature T And generate temperature detection data V through the analog-to-digital converter N45 T_SEN <0:10>.

[0088] Although the embodiments of the present invention have been shown and described (see the above detailed description), for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A dual - gear GaN power transistor gate bias control integrated circuit, characterized in that: It includes a GaN power transistor (1), a positive voltage power supply (2), a DC-DC negative voltage power supply (3), a negative voltage linear voltage regulator module (4), an 11-bit digital-to-analog converter (5), a gate driver buffer (6), a gate voltage operation control module (7), a gate voltage adjustment module (8), a current detection module (9), a temperature detection module (10), an 11-bit analog-to-digital converter (11), and a MIPI interface (12); The positive-pressure power supply (2) is used to convert the input voltage V bat into a fixed supply voltage V DD , and supply power to the DC-DC negative-pressure power supply (3), the negative-pressure linear voltage regulation module (4), the 11-bit digital-to-analog converter (5), the gate drive buffer (6), the gate voltage operation control module (7), the gate voltage adjustment module (8), the current detection module (9), the temperature detection module (10), and the 11-bit analog-to-digital converter (11); The DC-DC negative voltage power supply (3) is used to convert the input voltage V bat into a fixed negative voltage V NEG , provide the required negative voltage potential for the negative voltage linear voltage regulator module (4), and have the driving ability for the GaN power transistor (1), the negative voltage linear voltage regulator module (4), the 11-bit digital-to-analog converter (5), and the gate drive buffer (6); The negative voltage linear voltage regulation module (4) linearly regulates the negative power supply voltage V output by the DC-DC negative power supply (3), NEG providing a constant and ripple-free fixed negative voltage V for the 11-bit digital-to-analog converter (5) and the gate drive buffer (6), EE and having a driving capability; The 11-bit digital-to-analog converter (5) is used to convert the 11-bit gate voltage control digital signal V gs_ctrl <0:10> generated by the gate voltage operation control module (7) into a gate voltage analog signal V gs_Analog , and output it to the gate drive buffer (6) to provide the required DC gate voltage for the GaN power transistor (1); The gate drive buffer (6) drives and isolates the gate voltage generated by the 11-bit digital-to-analog converter (5) to provide the required gate bias voltage V gs for the GaN power transistor (1) and has current driving capability; The gate voltage operation control module (7) generates a gate voltage control digital signal V gs_ctrl <0:10> to modulate the gate voltage V gs . The working gears are divided into two gears: open-loop control mode and loop real-time control mode. In the open-loop control mode, the gate voltage operation control module (7) obtains the gate voltage control digital signal according to the input data sdata. In the loop real-time control mode, the gate voltage operation control module (7) generates the gate voltage control digital signal to adjust the amplitude of V gs_SEN <0:10> in real time according to the input data sdata and the gate voltage adjustment data V gs generated by the gate voltage adjustment module (8). The gate voltage adjustment module (8), according to the current detection data V obtained by the current detection module (9) and the temperature detection module (10) i_SEN <0:10> and the temperature detection data V T_SEN <0:10>, generates gate voltage adjustment data V gs_SEN <0:10>, and real-time controls the gate voltage of the GaN power transistor (1) to ensure that the current flowing through the GaN power transistor remains constant with the change of temperature and time, and ensures that the power amplifier operates within the adjusted output power range; The current detection module (9) outputs the voltage detected across the resistor R sense to an 11-bit analog-to-digital converter (11), thereby obtaining the current value flowing through the GaN power transistor (1). The temperature detection module (10) monitors the temperature of the GaN power transistor (1) in real time when the power amplifier is working, and outputs the temperature information to the 11-bit analog-to-digital converter (11), so as to obtain the temperature value of the GaN power transistor (1); The 11-bit analog-to-digital converter (11) is used to quantify the drain current and operating temperature of the GaN power transistor (1), and convert the analog quantities of the current information and temperature information obtained by the current detection module (9) and the temperature detection module (10) into 11-bit digital quantities: temperature detection data V T_SEN <0:10> and current detection data V i_SEN <0:10>, and output them to the gate voltage adjustment circuit (8) to adjust the gate voltage V gs ; The MIPI interface (12), as a serial communication interface, enables the GaN power transistor gate bias control system to communicate with external information; processes the open-loop control data signal sdata and outputs it to the gate voltage operation control module (7).

2. The dual-gear GaN power transistor gate bias control integrated circuit according to claim 1, wherein: The positive voltage supply (2) includes a low dropout linear regulator (LDO) and an under-voltage lockout (UVLO) protection circuit; the low dropout linear regulator is used to convert the input voltage into a fixed supply voltage V DD ; the under-voltage lockout (UVLO) protection circuit monitors in real time whether the supply voltage V DD drops below the voltage for the system to operate normally and protects against this situation; The DC-DC negative voltage power supply (3) adopts an Inverting Buck-Boost structure to convert the input voltage V bat into a fixed negative voltage V NEG ; there are two working modes: CCM mode and DCM mode to ensure the conversion efficiency.

3. The dual-gear GaN power transistor gate bias control integrated circuit according to claim 1, wherein: The negative voltage linear voltage regulator module (4) includes a low dropout linear regulator (LDO) and an under-voltage lockout (UVLO) protection circuit; the low dropout linear regulator is used to convert the negative voltage V NEG into a fixed negative voltage V without ripple EE ; the under-voltage lockout (UVLO) protection circuit monitors in real time whether the negative voltage V EE is within the specified voltage range, and controls whether the 11-bit digital-to-analog converter (5) and the gate drive buffer (6) operate; The gate voltage adjustment module (8) receives the temperature detection data V T_SEN <0:10> and the current detection data V i_SEN <0:10> in real time; when either the temperature detection data V T_SEN <0:10> or the current detection data V i_SEN <0:10> is valid, the gate voltage adjustment module (8) updates the gate voltage adjustment data V gs_SEN <0:10> and outputs it to the gate voltage operation module (7) to make the current flowing through the GaN power transistor (1) not change with temperature and time.

4. The dual - gear GaN power transistor gate bias control integrated circuit according to claim 1, wherein: When the gate voltage operation control module (7) is in the open-loop control mode, only through the input data sdata, the digital control quantity V of the bias voltage is calculated and generated in real time. gs_ctrl <0:10>; When the gate voltage operation control module (7) is in the loop real-time control mode, through the input data sdata, and the quantization data of the drain current and the operating temperature of the GaN power transistor (1) are received in real time, that is, the gate voltage adjustment data V gs_SEN <0:10>, the digital control quantity V of the gate bias voltage is calculated and generated gs_ctrl <0:10>, and the gate voltage is adjusted in real time according to the environmental parameters. The current detection module (9) amplifies the small differential voltage V sense generated across the current detection resistor R sense under the condition of a high input common-mode voltage, and obtains a current detection voltage V i that reflects the drain current information of the GaN power transistor (1); The temperature detection module (10) monitors the operating temperature of the GaN power transistor (1) in real time and outputs a temperature detection voltage V T that is linearly proportional to the temperature and has a fixed DC offset that can meet the detection range from -40 degrees to 125 degrees.

5. The dual - gear GaN power transistor gate bias control integrated circuit according to claim 2, wherein: The positive power supply (2) includes a low dropout linear regulator (LDO) and an under-voltage lockout protection circuit N5; the low dropout linear regulator (LDO) includes a bandgap reference source N1, a soft start circuit N2, an amplifier N3, a compensation network N4, a resistor R1, a resistor R2, and a capacitor C L , and a power transistor MP; where: The VDD port of the bandgap reference source N1 is respectively connected to the input voltage V bat , the VDD port of the soft-start circuit N2, the VDD port of the amplifier N3, and the source of the power transistor MP. The VSS port of the bandgap reference source N1 is connected to ground, and the VBG port of the bandgap reference source N1 is connected to the VREF port of the soft-start circuit N2; the VSS port of the soft-start circuit N2 is connected to ground, and the OUT port of the soft-start circuit N2 is connected to the INP port of the amplifier N3; the OUT port of the amplifier N3 is respectively connected to the gate of the power transistor MP and the D1 port of the compensation network N4, and the INN port of the amplifier N3 is respectively connected to the D3 port of the compensation network N4, one end of the resistor R1, and one end of the resistor R2. The VSS port of the amplifier N3 is connected to ground; the D2 port of the compensation network N4 is respectively connected to the drain of the power transistor MP, the other end of the resistor R1, one end of the capacitor C L , the VDD port of the under-voltage lockout protection circuit N5, and the output terminal V DD ; the other end of the resistor R2 is connected to ground; the other end of the capacitor C L is connected to ground; the VSS port of the under-voltage lockout protection circuit N5 is connected to ground, and the VDD_UVLO port of the under-voltage lockout protection circuit is an output of the positive voltage power supply (2).

6. The dual - gear GaN power transistor gate - bias control integrated circuit according to claim 2, characterized in that: The external circuit of the DC-DC negative voltage power supply (3) chip includes a DC-DC negative voltage power supply module N11, a capacitor C in , a capacitor C2, a capacitor C3, a capacitor C O , and an inductor L1; where: The VBAT port of the DC-DC negative voltage power supply module N11 is respectively connected to one end of the capacitor C in one end, one end of the capacitor C2, V bat input port; the VSS port of the DC-DC negative voltage power supply module N11 is connected to the ground; the VDD port of the DC-DC negative voltage power supply module N11 is connected to one end of C3; the VNEG port of the DC-DC negative voltage power supply module N11 is respectively connected to the other end of C2, the other end of C3, C O one end, V NEG output port; the SW port of the DC-DC negative voltage power supply module N11 is connected to one end of the inductor L1; the other end of the inductor L1 is respectively connected to C O the other end and the ground; The internal circuit of the DC-DC negative voltage power supply (3) chip, i.e., the DC-DC negative voltage power supply module N11, includes a power supply module N12, a conduction time control module N13, a turn-off time control module N14, a ZCS detection module N15, a PWM logic control module N16, a drive module N17, a soft start module N18, a ripple control module N19, and a power stage N20; among them: The VSS of the power supply module N12 is connected to the ground; the VBAT port of the power supply module N12 is respectively connected to the V bat input port, the VBAT port of the drive module N17, and the VBAT port of the power stage N20; the VDD port of the power supply module N12 is respectively connected to the V DD output port, the VDD port of the turn-on time control module N13, the VDD port of the turn-off time control module N14, the VDD port of the ZCS detection module N15, the VDD port of the PWM logic control module N16, the VDD port of the drive module N17, the VDD port of the soft start module N18, the VDD port of the ripple control module N19, and the VDD port of the power stage N20; the VSS port of the turn-on time control module N13 is connected to the ground; the TON port of the turn-on time control module N13 is connected to the TON port of the PWM logic control module N16; the VSS port of the turn-off time control module N14 is connected to the ground; the TOFF port of the turn-off time control module N14 is connected to the TOFF port of the PWM logic control module N16; the VSS port of the ZCS detection module N15 is connected to the ground; the ZCS port of the ZCS detection module N15 is connected to the ZCS port of the PWM logic control module N16; the VSS port of the soft start module N18 is connected to the ground; the CL port of the soft start module N18 is connected to the CL port of the PWM logic control module N16; the VSS port of the ripple control module N19 is connected to the ground; the RIP port of the ripple control module N19 is connected to the RIP port of the PWM logic control module N16; the VNEG port of the ripple control module N19 is respectively connected to the V NEG output port, the VNEG port of the drive module N17, and the VNEG port of the power stage N20; the VSS port of the drive module N17 is connected to the ground; the PWMH port of the drive module N17 is connected to the PWMH port of the PWM logic control module N16; the PWML port of the drive module N17 is connected to the PWML port of the PWM logic control module N16; the VGH port of the drive module N17 is connected to the VGH port of the power stage N20; the VGL port of the drive module N17 is connected to the VGL port of the power stage N20; the SW port of the power stage N20 is connected to the SW output port; the VSS port of the PWM logic control module N16 is connected to the ground.

7. The dual-gear GaN power transistor gate bias control integrated circuit according to claim 3, wherein: The negative voltage linear voltage regulator module (4) includes a negative voltage linear regulator LDO and an under-voltage lockout protection circuit N9; the negative voltage linear regulator LDO includes a soft start circuit N6, an amplifier N7, a compensation network N8, a resistor R3, a resistor R4, a capacitor C1, and a power transistor MN; among them: The VDD port of the soft start circuit N6 is respectively connected to the V output port of the positive voltage power supply (2), the VDD port of the amplifier N7, one end of the resistor R4, one end of the capacitor C1, and the VDD port of the undervoltage lock - up protection circuit N9; the VREF port of the soft start circuit N6 is connected to the V port of the bandgap reference source N1 of the positive voltage power supply (2). DD The VSS port of the soft start circuit N6 is respectively connected to the output V port of the DC - DC negative voltage power supply (3), the VSS port of the amplifier N7, and the source of the power transistor MN; the OUT port of the soft start circuit N6 is connected to the INN port of the amplifier N7; the INP port of the amplifier N7 is respectively connected to the D1 port of the compensation network N8, one end of the resistor R3, and one end of the resistor R4; the OUT port of the amplifier N7 is respectively connected to the D3 port of the compensation network N8 and the gate of the power transistor MN; the drain of the power transistor MN is connected to one end of the resistor R3; the D2 port of the compensation network N8 is respectively connected to one end of the resistor R3, one end of the capacitor C1, the VSS port of the undervoltage lock - up protection circuit N9, and the V BG output port; the VEE_UVLO port of the undervoltage lock - up protection circuit N9 is an output port of the negative voltage linear voltage - regulating module (4). NEG output port; the VEE_UVLO port of the undervoltage lock - up protection circuit N9 is an output port of the negative voltage linear voltage - regulating module (4). EE output port; the VEE_UVLO port of the undervoltage lock - up protection circuit N9 is an output port of the negative voltage linear voltage - regulating module (4).

8. The dual - gear GaN power transistor gate bias control integrated circuit according to claim 1, wherein: The 11-bit digital-to-analog converter (5) includes a clock generation and drive circuit N21, an input register N22, a thermometer decoding circuit N23, a synchronous delay circuit N24, a synchronous latch and switch drive circuit N25, a bandgap reference source N26, a reference current source generation circuit N27, a current source bias voltage generation circuit N28, a four-phase differential switch current source array N29, a resistor Rp, and a resistor Rn; among them: The CLK_REG port of the clock generation and driving circuit N21 is connected to the CLK port of the input register N22; the CLK_DEC port of the clock generation and driving circuit N21 is respectively connected to the CLK port of the thermometer decoding circuit N23 and the CLK port of the synchronous delay circuit N24; the CLK_SW port of the clock generation and driving circuit N21 is connected to the CLK port of the synchronous latch and switch driving circuit N25; the VEE_UVLO input port is respectively connected to the EN port of the clock generation and driving circuit N21, the EN port of the input register N22, and the EN port of the synchronous latch and switch driving circuit N25; V gs_ctrl <0:10>The input port is connected to the REG_IN port of the input register N22; the REG_OUT port of the input register N22 is respectively connected to the IN port of the thermometer decoding circuit N23 and the IN port of the synchronous delay circuit N24; the OUT port of the thermometer decoding circuit N23 is connected to the MSB_IN port of the synchronous latch and switch driving circuit N25; the OUT port of the synchronous delay circuit N24 is connected to the LSB_IN port of the synchronous latch and switch driving circuit N25; the MSB_OUT port and the LSB_OUT port of the synchronous latch and switch driving circuit N25 are both connected to the four-phase differential switch current source array N29 to control the switch switching; the VBG port of the bandgap reference circuit N26 is connected to the VREF port of the reference current source N27; the IREF port of the reference current source N27 is connected to the IREF port of the current source bias voltage generation circuit N28; the Vbias1 port and the Vbias2 port of the current source bias voltage generation circuit N28 are respectively connected to the gates of M1 and M2 in all the cells of the four-phase differential switch current source array N29; one end of the resistor Rp and one end of the resistor Rn are connected to the drains of the switching transistors S1, S2, S3, S4 in the four-phase differential switch current source array N29; the other end of the resistor Rp and the other end of the resistor Rn are connected to V NEG input port; the VDD ports of all the modules are all connected to V DD input port, and the VSS ports of all the modules are all connected to the VNEG input port.

9. The dual - gear GaN power transistor gate bias control integrated circuit according to claim 1, characterized in that: The gate driver buffer (6) includes an amplifier N10 and a resistor R5; among them: The VDD port of amplifier N10 is connected to the V of the positive power supply (2). DD output port, and the INP port of amplifier N10 is connected to the V of the 11-bit digital-to-analog converter N29. gs_Analog output port; the EN port of amplifier N10 is connected to the VEE_UVLO output port of the negative voltage linear voltage regulator module (4); the INN port of amplifier N10 is respectively connected to the OUT port of amplifier N10 and one end of resistor R5; the VSS port of amplifier N10 is connected to the V of the negative voltage linear voltage regulator module (4). EE output port; the OUT port of amplifier N10 is connected to one end of resistor R5 to output V gs_Buffer signal; one end of resistor R5 is connected to the output terminal V gs_in .

10. The dual - gear GaN power transistor gate bias control integrated circuit according to claim 1, characterized in that: The 11-bit analog-to-digital converter (11) includes a sample and hold circuit N30, a digital-to-analog converter N31, a comparator N32, an asynchronous logic control circuit N33, a switch circuit N34, a decoding circuit N35, a voltage-time converter N36, a phase detector N37, a time selector N38, a time-to-digital converter N39, a temperature code to binary code N40, and a two-way selector N41; among them: The INN port of the sample and hold circuit N30 is respectively connected to the V ref input port and the VCM port of the digital-to-analog converter N31; the INP port of the sample and hold circuit N30 is connected to the OUT port of the two-way selector N41; the OUTP port of the sample and hold circuit N30 is connected to the INP port of the digital-to-analog converter N31; the OUTN port of the sample and hold circuit N30 is connected to the INN port of the digital-to-analog converter N31; the CAPB port of the digital-to-analog converter N31 is connected to the CONTROL port of the switch circuit N34; the VDACP port of the digital-to-analog converter N31 is respectively connected to the INP port of the comparator N32 and the VIP port of the voltage-time converter N36; the VDACN terminal of the digital-to-analog converter N31 is respectively connected to the INN port of the comparator N32 and the VIN port of the voltage-time converter N36; the OP port of the comparator N32 is connected to the VCP port of the asynchronous logic control circuit N33; the ON port of the comparator N32 is connected to the VCN port of the asynchronous logic control circuit N33; the CLKC port of the comparator N32 is connected to the CLKC port of the asynchronous logic control circuit N33; the CONTROL port of the asynchronous logic control circuit N33 is connected to the INPUT port of the switch circuit N34; the SELECT port of the asynchronous logic control circuit N33 is connected to the SELECT port of the two-way selector N41; the ST port of the asynchronous logic control circuit N33 is connected to the ST port of the voltage-time converter N36; the B1<0:7> ports of the switch circuit N34 are connected to the REGI1 port of the decoding circuit N35; the OUTP port of the voltage-time converter N36 is respectively connected to the VIP port of the phase detector N37 and the VIP port of the time selector N38; the OUTN port of the voltage-time converter N36 is respectively connected to the VIN port of the phase detector N37 and the VIN port of the time selector N38; the OUT port of the phase detector N37 is connected to the VI2 port of the temperature code to binary code N40; the OUTP port of the time selector N38 is connected to the VIP port of the time-to-digital converter N39; the OUTN port of the time selector N38 is connected to the VIN port of the time-to-digital converter N39; the OUT port of the time-to-digital converter N39 is connected to the VI1 port of the temperature code to binary code N40; the OUT port of the temperature code to binary code N40 is connected to the REGI2 port of the decoding circuit N35; the REGO port of the decoding circuit N35 is connected to the V SEN <0:10> output port; the V1 port of the two-way selector N41 is connected to the V i input port; the V2 port of the two-way selector N41 is connected to the V T input port; the VDD ports of all modules are all connected to the V DD input port, and the VSS ports of all modules are all connected to the VNEG input port.

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