Function safety design method for reading data path and Cache of eFLASH controller

Abstract

The invention relates to the technical field of embedded flash memory data reading, and discloses a function safety design method of a read data path and a read Cache of an eFLASH controller, which is characterized in that three groups of Dataath + Cache are arranged in the FLASH controller to realize triple modular redundancy and heterogeneous redundancy, and hierarchical redundancy and circuit recombination are realized through a Cross module; and the CPU realizes module configuration through an APB (Advanced Performance Bus), and the CPU or other Master accesses the Flash Memory through an AXI (Advanced Extensible Interface) via the Cache and the Datapath. According to the functional security design method for reading the data path and the Cache of the eFLASH controller, by combining triple modular redundancy, hierarchical redundancy and heterogeneous redundancy, simultaneously adopting a hierarchical circuit recombination design, and adopting a functional security design of front and back four stages of registers and phase inverters, the data path can be flexibly configured, and the reliability of the read data path and the read Cache of the eFLASH controller is improved. The composite redundancy design of the read data path and the read prefetch Cache of the eFlash controller is achieved, the whole scheme is more reliable, more efficient and more flexible, the eFLASH read efficiency can be effectively improved, and the safety requirement of the vehicle gauge function is met.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded flash data reading, and specifically to a functional safety design method for the read data path of an eFLASH controller and the read Cache. Background Art

[0002] In automotive electronic systems, eFLASH (embedded flash) is an important storage component, and the reliability of its data reading is crucial for the safe operation of vehicles. In order to improve the stability and safety of the read operation of the eFLASH controller, a read Cache redundancy architecture and a functional safety design method have emerged.

[0003] The read Cache redundancy architecture is divided into:

[0004] (1) Dual-read Cache redundancy structure, which constructs an architecture where the main read Cache and the standby read Cache work simultaneously. When the eFLASH controller receives a read request, data is synchronously loaded from the eFLASH memory into both the main and standby Caches. This dual-Cache structure is like putting "double insurance" on data reading. Even if one Cache fails, the other Cache can still provide data normally to ensure the uninterrupted operation of the system. For example, in the engine control unit of a vehicle, for the reading of engine control parameters stored in the eFLASH, the dual-read Cache redundancy structure can ensure that the engine control unit can obtain the required parameters in a timely and accurate manner under various complex working conditions to maintain the stable operation of the engine;

[0005] Distributed read Cache redundancy method, which adopts a distributed design, divides the read Cache into multiple sub-Cache modules, and distributes them in different physical locations. This layout effectively improves the fault tolerance of the system. When a certain area is affected by local hardware failures, such as when a sub-Cache module fails due to vehicle vibration or electromagnetic interference, other sub-Cache modules can still work normally. For example, in the core computing module of an autonomous vehicle, for the reading of key information such as map data and decision-making algorithms stored in the eFLASH, the distributed read Cache redundancy architecture can ensure that during vehicle driving, even if some sub-Cache modules are abnormal due to surrounding environmental factors, the autonomous driving system can still obtain data from other normal sub-Cache modules to maintain the stable operation of the autonomous driving function.

[0006] To implement a composite redundancy design for the read data path of the eFlash controller and the read prefetch Cache to achieve a more reliable, efficient, and flexible functional safety design, the present application proposes a functional safety design method for the read data path of an eFLASH controller and the read Cache. Summary of the Invention

[0007] (1) Technical problem to be solved

[0008] Aiming at the deficiencies of the existing technology, the present invention provides a functional safety design method for the read data path of an eFLASH controller and the read Cache, which, as a functional safety design method, can flexibly improve the eFLASH read efficiency and meet the automotive functional safety requirements.

[0009] (2) Technical solution

[0010] To achieve the above object, the present invention provides the following technical solution: a functional safety design method for the read data path of an eFLASH controller and the read Cache, which realizes triple modular redundancy and heterogeneous redundancy by setting three groups of Datapath+Cache in the FLASH controller, and realizes hierarchical redundancy and circuit recombination through the Cross module; the CPU realizes module configuration through APB, and the CPU or other Masters access the Flash Memory through AXI via the Cache and the Data_path.

[0011] Preferably, the circuit working mechanism of the triple modular redundancy is as follows: -

[0012] The input data is compared and voted at FENC_Poll0 after passing through DataPath0, DataPath1 and DataPath2; the data is compared and voted at FENC_Poll1 after passing through Cache0, Cache1 and Cache2;

[0013] The circuit working mechanism supports two modes: redundant mode or non-redundant mode.

[0014] Preferably, in the redundant mode:

[0015] The output of DataPath0 and the output of DataPath1 are compared. If they are the same, it is determined that the result output to Cross is correct;

[0016] Otherwise, the output of DataPath1 and the output of DataPath2 are compared. If they are the same, it is determined that the result output to Cross is correct;

[0017] Otherwise, the output of DataPath0 and the output of DataPath2 are compared. If they are the same, it is determined that the result output to Cross is correct;

[0018] Otherwise, this section of the circuit is determined to be in error;

[0019] The output of Cache0 and the output of Cache1 are compared. If they are the same, it is determined that the output is correct;

[0020] Otherwise, compare the output of Cache1 and the output of Cache2. If they are the same, it is determined that the output is correct;

[0021] Otherwise, compare the output of Cache0 and the output of Cache2. If they are the same, it is determined that the output is correct;

[0022] Otherwise, this section of the circuit is determined to be in error;

[0023] DataPathX can work in cross combination with CacheY.

[0024] Preferably, in the non-redundant mode:

[0025] Three groups of the DataPath and Cache work simultaneously, supporting data caching for three different address segments, and DataPathX can work in cross combination with CacheY.

[0026] Preferably, the working mechanism of the heterogeneous redundant circuit is: Cache0 uses ECC to protect data, and Cache1 and Cache2 use CRC to protect data;

[0027] The working mechanism of the hierarchical redundant circuit is: the read data path is divided into two layers, DataPath and Cache, for redundancy and comparison respectively.

[0028] Preferably, configure DataPathX and CacheY through the Cross to form a complete data path.

[0029] Preferably, the Cache structure and mechanism are as follows:

[0030] It includes an address unit and eight data units. The address stored in the address unit corresponds to the data in the first data unit; when the data at address ADDR is read, the data of ADDR+1 is shifted sequentially to the first data unit. After sequential shifting, the data in the last data unit is pre-read from the FLASH;

[0031] In the redundant mode:

[0032] The same addresses are stored in the address units of the three Caches, which is equivalent to only one Cache existing;

[0033] Non-redundant mode:

[0034] The three Caches work simultaneously, supporting data caching for three different address segments;

[0035] When the access to address A arrives, the data is cached in Cache0;

[0036] When an access to address B arrives, determine whether B falls within [A + 1, A + 8]. If so, still use Cache0 to cache the data; otherwise, cache the data and the address in Cache1.

[0037] When an access to address C arrives, determine whether C falls within [A + 1, A + 8] or [B + 1, B + 8]. If so, still use Cache0 / Cache1 to cache the data; otherwise, cache the data and the address in Cache2.

[0038] When an access to address D arrives, determine whether D falls within [A + 1, A + 8] or [B + 1, B + 8] or [C + 1, C + 8]. If so, still use Cache0 / Cache1 / Cache2 to cache the data; otherwise, update the oldest Cache0 and cache the data and the address in Cache0.

[0039] Preferably, the DataPath and the Cache are respectively designed with separate error injection paths, supporting the injection of error 0 or error 1.

[0040] Preferably, the circuit data path of the method includes:

[0041] In the redundancy mode, DataPath0 is in the Front mode and DataPath1 / 2 are in the Back mode;

[0042] In the redundancy mode, DataPath1 is in the Front mode and DataPath0 / 2 are in the Back mode;

[0043] In the redundancy mode, DataPath2 is in the Front mode and DataPath0 / 1 are in the Back mode;

[0044] In the redundancy mode, Cache0 is in the Front mode and Cache1 / 2 are in the Back mode;

[0045] In the redundancy mode, Cache1 is in the Front mode and Cache0 / 2 are in the Back mode;

[0046] In the redundancy mode, Cache2 is in the Front mode and Cache0 / 1 are in the Back mode;

[0047] Non - redundancy mode.

[0048] (III) Beneficial effects

[0049] Compared with the prior art, the present invention provides a functional safety design method for the read data path of an eFLASH controller and the read Cache, having the following beneficial effects:

[0050] This method combines triple modular redundancy, hierarchical redundancy, and heterogeneous redundancy, and simultaneously adopts hierarchical circuit restructuring design, as well as functional safety design with four-stage registers + inverters before and after, enabling flexible configuration of the data path, achieving composite redundancy design for the read data path of the eFlash controller and the read prefetch Cache. The entire solution is more reliable, efficient, and flexible, can effectively improve the eFLASH read efficiency, and meet the automotive functional safety requirements. Brief Description of the Drawings

[0051] Figure 1 It is a schematic diagram of the solution architecture of the present invention;

[0052] Figure 2 It is a schematic circuit diagram of redundancy and comparison of the present invention;

[0053] Figure 3 It is a schematic diagram of the internal structure of the Cache of the present invention;

[0054] Figure 4 It is a schematic diagram of the data path of redundancy and comparison of the present invention. Detailed Embodiments

[0055] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0056] Please refer to Figure 1 , to implement composite redundancy design for the read data path of the eFlash controller and the read prefetch Cache, so as to achieve a more reliable, efficient, and flexible functional safety design, the present invention proposes a functional safety design method for the read data path and read Cache of the eFLASH controller. This method sets three groups of Datapath + Cache in the FLASH controller to achieve triple modular redundancy and heterogeneous redundancy, and realizes hierarchical redundancy and circuit recombination through the Cross module; the CPU configures the module through APB, and the CPU or other Masters access the Flash Memory through AXI via the Cache and Data_path.

[0057] The circuit working mechanism is as Figure 2 shown, including a triple modular redundancy mechanism, a hierarchical redundancy mechanism, a cross-switch mechanism, a heterogeneous redundancy mechanism, a Cache structure and mechanism, and an error injection mechanism.

[0058] Among them, the circuit working mechanism of triple modular redundancy is as follows:

[0059] The input data is compared and voted at FENC_Poll0 after passing through DataPath0, DataPath1, and DataPath2; the data is compared and voted at FENC_Poll1 after passing through Cache0, Cache1, and Cache2.

[0060] The circuit working mechanism supports two modes: redundant mode or non-redundant mode.

[0061] In the redundant mode:

[0062] The output of DataPath0 and the output of DataPath1 are compared. If they are consistent, it is determined that the result output to Cross is correct.

[0063] Otherwise, the output of DataPath1 and the output of DataPath2 are compared. If they are consistent, it is determined that the result output to Cross is correct.

[0064] Otherwise, the output of DataPath0 and the output of DataPath2 are compared. If they are consistent, it is determined that the result output to Cross is correct.

[0065] Otherwise, this section of the circuit is determined to be in error.

[0066] The output of Cache0 and the output of Cache1 are compared. If they are consistent, it is determined that the output is correct.

[0067] Otherwise, the output of Cache1 and the output of Cache2 are compared. If they are consistent, it is determined that the output is correct.

[0068] Otherwise, the output of Cache0 and the output of Cache2 are compared. If they are consistent, it is determined that the output is correct.

[0069] Otherwise, this section of the circuit is determined to be in error.

[0070] DataPathX can work in cross combination with CacheY.

[0071] In the non-redundant mode:

[0072] The three groups of DataPath and Cache work simultaneously, supporting data caching for three different address segments, and DataPathX can work in cross combination with CacheY.

[0073] The circuit working mechanism of heterogeneous redundancy is as follows: Cache0 uses ECC to protect data, and Cache1 and Cache2 use CRC to protect data.

[0074] The working mechanism of the hierarchical redundant circuit is as follows: The data read path is divided into two layers, namely DataPath and Cache, which perform redundancy and comparison respectively.

[0075] The crossbar switch mechanism configures DataPathX and CacheY through Cross to form a complete data path.

[0076] In addition, the Cache structure and mechanism are as Figure 3 shown. It contains an address unit and eight data units. The address stored in the address unit corresponds to the data in the first data unit. When the data at address ADDR is read, the data at ADDR + 1 is shifted sequentially to the first data unit. After sequential shifting, the data in the last data unit is pre-read from the FLASH.

[0077] In the redundant mode:

[0078] The same address is stored in the address units of the three Caches, which is equivalent to having only one Cache.

[0079] Non-redundant mode:

[0080] The three Caches work simultaneously and support data caching for three different address segments.

[0081] When address A arrives, the data is cached in Cache0.

[0082] When address B arrives, it is judged whether B falls within [A + 1, A + 8]. If so, the data is still cached in Cache0; otherwise, the data and the address are cached in Cache1.

[0083] When address C arrives, it is judged whether C falls within [A + 1, A + 8] or [B + 1, B + 8]. If so, the data is still cached in Cache0 / Cache1; otherwise, the data and the address are cached in Cache2.

[0084] When address D arrives, it is judged whether D falls within [A + 1, A + 8] or [B + 1, B + 8] or [C + 1, C + 8]. If so, the data is still cached in Cache0 / Cache1 / Cache2; otherwise, the oldest Cache0 is updated and the data and the address are cached in Cache0.

[0085] The error injection mechanism designs separate error injection paths for DataPath and Cache respectively, and supports injecting error 0 or error 1.

[0086] The circuit data path is as Figure 4 shown. The circuit data path includes:

[0087] In the redundant mode, DataPath0 is in the Front mode and DataPath1 / 2 are in the Back mode:

[0088] After the input Input is sent from path0 through the MUX to DataPath0, it is sent to the Cross module through Path6;

[0089] After the input Input is sent from path0 through the MUX to DataPath0, it performs a NXOR operation with the error injection signal of Fault_Inject0 through Path7. The result performs a NXOR operation with the output from DataPath1 after passing through an inverter. This result is sent to FENC_Poll0 for decoding and Poll decision;

[0090] After the input Input is sent from path2 through the MUX to DataPath1, it is sent to the Cross module through Path9;

[0091] After the input Input is sent from path2 through the MUX to DataPath1, it performs an XOR operation with the error injection signal of Fault_Inject2 through Path9a. This result performs an XOR operation with the output from DataPath2. This result is sent to FENC_Poll0 for decoding and Poll decision;

[0092] After the input Input is sent from path4 through the MUX to DataPath2, it is sent to the Cross module through Path10;

[0093] After the input Input is sent from path4 through the MUX to DataPath2, it performs an XOR operation with the error injection signal of Fault_Inject0 through Path10a. This result performs a NXOR operation with the output from DataPath0. This result is sent to FENC_Poll0 for decoding and Poll decision.

[0094] In the redundant mode, DataPath1 is in the Front mode and DataPath0 / 2 are in the Back mode:

[0095] After the input Input is sent from path1 through the MUX to DataPath0, it is sent to the Cross module through Path6;

[0096] After the input "Input" is sent from path1 through the MUX to DataPath0, it undergoes a NAND-XOR operation with the error injection signal of Fault_Inject0 via Path6a. The result is then inverted and undergoes a NAND-XOR operation with the output from DataPath1. This result is sent to FENC_Poll0 for decoding and Poll decision;

[0097] After the input "Input" is sent from path3 through the MUX to DataPath1, it is sent to the Cross module via Path9;

[0098] After the input "Input" is sent from path3 through the MUX to DataPath1, it undergoes an XOR operation with the error injection signal of Fault_Inject2 via Path8. The result is then XORed with the output from DataPath2. This result is sent to FENC_Poll0 for decoding and Poll decision;

[0099] After the input "Input" is sent from path4 through the MUX to DataPath2, it is sent to the Cross module via Path10;

[0100] After the input "Input" is sent from path4 through the MUX to DataPath2, it undergoes an XOR operation with the error injection signal of Fault_Inject0 via Path10a. The result is then NAND-XORed with the output from DataPath0. This result is sent to FENC_Poll0 for decoding and Poll decision.

[0101] In the redundant mode, DataPath2 is in the Front mode and DataPath0 / 1 are in the Back mode:

[0102] After the input "Input" is sent from path1 through the MUX to DataPath0, it is sent to the Cross module via Path6;

[0103] After the input "Input" is sent from path1 through the MUX to DataPath0, it undergoes a NAND-XOR operation with the error injection signal of Fault_Inject0 via Path6a. The result is then inverted and undergoes a NAND-XOR operation with the output from DataPath1. This result is sent to FENC_Poll0 for decoding and Poll decision;

[0104] After the input "Input" is sent from path2 through the MUX to DataPath1, it is sent to the Cross module via Path9;

[0105] After the input is sent from path2 to DataPath1 through the MUX, it undergoes an exclusive-OR operation with the error injection signal of Fault_Inject2 via Path9a. This result is then exclusive-ORed with the output from DataPath2. This final result is sent to FENC_Poll0 for decoding and Poll decision-making;

[0106] The input is sent from path5 to DataPath2 through the MUX and then sent to the Cross module via Path10;

[0107] The input is sent from path5 to DataPath2 through the MUX and then undergoes an exclusive-OR operation with the error injection signal of Fault_Inject0 via Path11. This result is then exclusive-NORed with the output from DataPath0. This final result is sent to FENC_Poll0 for decoding and Poll decision-making.

[0108] In the redundant mode, Cache0 is in the Front mode and Cache1 / 2 are in the Back mode:

[0109] The input from Cross is sent from path12 to Cache0 through the MUX and then sent out via Path18;

[0110] The input from Cross is sent from path12 to Cache0 through the MUX and then undergoes an exclusive-NOR operation with the error injection signal of Fault_Inject1 via Path18a. After passing through an inverter, this result is exclusive-NORed with the output from Cache1. This final result is sent to FENC_Poll1 for decoding and Poll decision-making;

[0111] The input from Cross is sent from path14 to Cache1 through the MUX and then sent out via Path21;

[0112] The input from Cross is sent from path14 to Cache1 through the MUX and then undergoes an exclusive-OR operation with the error injection signal of Fault_Inject1 via Path21a. This result is exclusive-ORed with the output from Cache2. This final result is sent to FENC_Poll1 for decoding and Poll decision-making;

[0113] The input from Cross is sent from path16 to Cache2 through the MUX and then sent out via Path22;

[0114] The input from Cross is sent from path16 through the MUX to Cache2, and then undergoes an exclusive OR operation with the error injection signal of Fault_Inject1 via Path22a. The result is subjected to an exclusive NOR operation with the output from Cache0. This result is sent to FENC_Poll1 for decoding and Poll decision.

[0115] In the redundant mode, Cache1 is in the Front mode, and Cache0 / 2 are in the Back mode:

[0116] The input from Cross is sent from path15 through the MUX to Cache1 and then sent out via Path21;

[0117] The input from Cross is sent from path15 through the MUX to Cache1, and then undergoes an exclusive OR operation with the error injection signal of Fault_Inject1 via Path20. The result is subjected to an exclusive NOR operation with the output from Cache0. This result is sent to FENC_Poll1 for decoding and Poll decision;

[0118] The input from Cross is sent from path13 through the MUX to Cache0 and then sent out via Path18;

[0119] The input from Cross is sent from path13 through the MUX to Cache0, and then undergoes an exclusive NOR operation with the error injection signal of Fault_Inject1 via Path18a. The result is subjected to an exclusive NOR operation with the output from Cache1. This result is sent to FENC_Poll1 for decoding and Poll decision;

[0120] The input from Cross is sent from path16 through the MUX to Cache2 and then sent out via Path22;

[0121] The input from Cross is sent from path16 through the MUX to Cache2, and then undergoes an exclusive OR operation with the error injection signal of Fault_Inject1 via Path22a. The result is subjected to an exclusive NOR operation with the output from Cache0. This result is sent to FENC_Poll1 for decoding and Poll decision.

[0122] In the redundant mode, Cache2 is in the Front mode, and Cache0 / 1 are in the Back mode:

[0123] The input from Cross is sent from path17 through the MUX to Cache2 and then sent out via Path22;

[0124] The input from Cross is sent to Cache2 via path17 through the MUX, and then XOR - operated with the error - injection signal of Fault_Inject1 via Path23. The result is NXOR - operated with the output from Cache0. This result is sent to FENC_Poll1 for decoding and Poll decision;

[0125] The input from Cross is sent to Cache0 via path13 through the MUX, and then sent out via Path18;

[0126] The input from Cross is sent to Cache0 via path13 through the MUX, and then XOR - operated with the error - injection signal of Fault_Inject1 via Path18a. The result is NXOR - operated with the output from Cache2. This result is sent to FENC_Poll1 for decoding and Poll decision;

[0127] The input from Cross is sent to Cache1 via path14 through the MUX, and then sent out via Path21;

[0128] The input from Cross is sent to Cache1 via path14 through the MUX, and then XOR - operated with the error - injection signal of Fault_Inject1 via Path21a. The result is XOR - operated with the output from Cache2. This result is sent to FENC_Poll1 for decoding and Poll decision.

[0129] Non - redundant mode:

[0130] The input Input is sent to DataPath0 via path0 through the MUX, and then sent to the Cross module via Path6;

[0131] The input Input is sent to DataPath1 via path3 through the MUX, and then sent to the Cross module via Path9;

[0132] The input Input is sent to DataPath2 via path5 through the MUX, and then sent to the Cross module via Path10;

[0133] The input from Cross is sent to Cache0 via path12 through the MUX, and then sent out via Path18;

[0134] The input from Cross is sent to Cache1 via path15 through the MUX, and then sent out via Path21;

[0135] The input from Cross is sent to Cache2 via path17 through the MUX and then sent out through Path22.

[0136] By combining triple modular redundancy, hierarchical redundancy, and heterogeneous redundancy, and at the same time adopting hierarchical circuit restructuring design and functional safety design with four - stage registers + inverters before and after, the data path can be flexibly configured, realizing the composite redundancy design of the read data path of the eFlash controller and the read prefetch Cache. The whole scheme is more reliable, efficient, and flexible, can effectively improve the eFLASH read efficiency, and meet the requirements of automotive functional safety.

[0137] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A functional safety design method for the read data path of an eFLASH controller and the read Cache, characterized in that By setting three groups of Datapath + Cache in the FLASH controller, triple modular redundancy and heterogeneous redundancy are achieved, and hierarchical redundancy and circuit recombination are realized through the Cross module; the CPU configures the module through APB, and the CPU or other Masters access the Flash Memory through AXI via the Cache and Data_path.

2. The functional safety design method for the read data path and read cache of an eFLASH controller according to claim 1, wherein The circuit working mechanism of the triple modular redundancy is as follows: The input data is compared and voted at FENC_Pol l 0 after passing through DataPath0, DataPath1, and DataPath2; the data is compared and voted at FENC_Pol l 1 after passing through Cache0, Cache1, and Cache2. The circuit working mechanism supports two modes: redundant mode or non-redundant mode.

3. The functional safety design method for the read data path and read Cache of an eFLASH controller according to claim 2, characterized in that, In the redundant mode: The output of DataPath0 and the output of DataPath1 are compared. If they are the same, it is determined that the result output to Cross is correct. Otherwise, the output of DataPath1 and the output of DataPath2 are compared. If they are the same, it is determined that the result output to Cross is correct. Otherwise, the output of DataPath0 and the output of DataPath2 are compared. If they are the same, it is determined that the result output to Cross is correct. Otherwise, this section of the circuit is determined to be in error. The output of Cache0 and the output of Cache1 are compared. If they are the same, it is determined that the output is correct. Otherwise, the output of Cache1 and the output of Cache2 are compared. If they are the same, it is determined that the output is correct. Otherwise, the output of Cache0 and the output of Cache2 are compared. If they are the same, it is determined that the output is correct. Otherwise, this section of the circuit is determined to be in error. DataPathX can work in cross combination with CacheY.

4. The functional safety design method for the read data path and read Cache of an eFLASH controller according to claim 2, characterized in that, In the non-redundant mode: The three groups of DataPath and Cache work simultaneously, supporting data caching for three different address segments, and DataPathX can work in cross combination with CacheY.

5. The functional safety design method for the read data path and read cache of an eFLASH controller according to claim 3 or 4, characterized in that, The circuit working mechanism of the heterogeneous redundancy is: Cache0 uses ECC to protect data, and Cache1 and Cache2 use CRC to protect data. The circuit working mechanism of the hierarchical redundancy is: the read data path is divided into two layers, DataPath and Cache, for redundancy and comparison respectively.

6. The functional safety design method for the read data path of an eFLASH controller and the read Cache according to claim 5, wherein The Cross is used to configure the combination of DataPathX and CacheY into a complete data path.

7. The functional safety design method for the read data path and read Cache of an eFLASH controller according to claim 6, characterized in that, The Cache structure and mechanism are as follows: It contains an address unit and 8 data units. The address saved in the address unit corresponds to the data in the first data unit; when the data at the address ADDR is read, the data of ADDR + 1 is shifted sequentially to the first data unit. After sequential shifting, the data in the last data unit is pre-read from the FLASH. In the redundant mode: The same addresses are stored in the address units of the three Caches, which is equivalent to having only one Cache; Non-redundant mode: The three Caches work simultaneously and support data caching for three different address segments; When an access to address A arrives, the data is cached in Cache0; When an access to address B arrives, it is judged whether B falls within [A + 1, A + 8]. If so, Cache0 is still used to cache the data. Otherwise, the data and the address are cached in Cache1; When an access to address C arrives, it is judged whether C falls within [A + 1, A + 8] or [B + 1, B + 8]. If so, Cache0 / Cache1 is still used to cache the data. Otherwise, the data and the address are cached in Cache2; When an access to address D arrives, it is judged whether D falls within [A + 1, A + 8] or [B + 1, B + 8] or [C + 1, C + 8]. If so, Cache0 / Cache1 / Cache2 is still used to cache the data. Otherwise, the oldest Cache0 is updated and the data and the address are cached in Cache0.

8. The functional safety design method for the read data path and read Cache of an eFLASH controller according to claim 7, characterized in that, Separate error injection paths are designed for the DataPath and the Cache respectively, supporting the injection of error 0 or error 1.

9. The functional safety design method for the read data path and read cache of an eFLASH controller according to claim 8, wherein, The circuit data path of the method includes: In the redundant mode, DataPath0 is in the Front mode and DataPath1 / 2 are in the Back mode; In the redundant mode, DataPath1 is in the Front mode and DataPath0 / 2 are in the Back mode; In the redundant mode, DataPath2 is in the Front mode and DataPath0 / 1 are in the Back mode; In the redundant mode, Cache0 is in the Front mode and Cache1 / 2 are in the Back mode; In the redundant mode, Cache1 is in the Front mode and Cache0 / 2 are in the Back mode; In the redundant mode, Cache2 is in the Front mode and Cache0 / 1 are in the Back mode; Non-redundant mode.

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