Reconfigurable heterogeneous radar data calculation module and calculation device

Abstract

The invention discloses a reconfigurable heterogeneous radar data computing module and computing device, and relates to the technical field of computing devices, the reconfigurable heterogeneous radar data computing module comprises a ZYNQ processor, a digital signal processor (DSP) and a neural processing unit (NPU), the ZYNQ processor is connected with the DSP and the NPU; the ZYNQ processor comprises an ARM processor and an FPGA (Field Programmable Gate Array) logic resource; the FPGA logic resource is used for carrying out parallel class algorithm processing on the radar data; the DSP is used for carrying out serial algorithm processing on the radar data; the NPU is used for performing artificial intelligence algorithm processing on the radar data; the ARM processor is used for scheduling FPGA logic resources according to the calculation tasks, and the DSP and the NPU execute corresponding algorithms. According to the reconfigurable heterogeneous radar data calculation module, the high-performance calculation requirement can be met.

Description

Technical Field

[0001] This application relates to the technical field of computing devices, and particularly to a reconfigurable heterogeneous radar data calculation module and a computing device. Background Art

[0002] The development of informatization has brought about an explosion in the amount of information, resulting in a significant increase in the computing volume and processing complexity of computers. As a result, higher requirements have been placed on the computing performance of devices such as computers. In related technologies, heterogeneous computing platforms can be achieved through various interface chips such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), and FPGAs (Field-Programmable Gate Arrays). The CPU is used for control, and the GPU and FPGA are used to implement service control and related algorithms.

[0003] For a radar system with high requirements for data processing and calculation, the computing platform is required to perform high-speed and accurate processing of the digital signals collected by the radar, and at the same time, functions such as target intelligent recognition need to be achieved quickly and accurately. However, in related technologies, the computing power of the computing platform architecture still has limitations and is difficult to meet the high-performance computing requirements of the above-mentioned radar system. Summary of the Invention

[0004] The main purpose of this application is to provide a reconfigurable heterogeneous radar data calculation module and a computing device, aiming to solve the technical problem that the calculation module in related technologies is difficult to meet the high-performance computing requirements of the radar system.

[0005] To achieve the above object, this application proposes a reconfigurable heterogeneous radar data calculation module. The reconfigurable heterogeneous calculation module includes: a ZYNQ processor, a Digital Signal Processor (DSP), and a Neural Processing Unit (NPU). The ZYNQ processor is respectively connected to the DSP and the NPU. The ZYNQ processor includes an ARM processor and FPGA logic resources.

[0006] The FPGA logic resources are used for parallel algorithm processing of radar data.

[0007] The DSP is used for serial algorithm processing of radar data.

[0008] The NPU is used for artificial intelligence algorithm processing of radar data.

[0009] The ARM processor is used to schedule the FPGA logic resources, DSP, and NPU according to the calculation task to execute the corresponding algorithms.

[0010] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes a first DDR memory, and the first DDR memory is connected to the ARM processor;

[0011] The first DDR memory stores a heterogeneous cooperative real-time runtime library, and the heterogeneous cooperative real-time runtime library is used to provide an API function interface. The ARM processor schedules the FPGA logic resources, DSP, and NPU through the API function interface to execute corresponding algorithms.

[0012] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes a second DDR memory, and the second DDR memory is connected to the FPGA logic resources; the first operator library is stored in the second DDR memory;

[0013] The ARM processor is used to determine a first target operator program from the first operator library through the heterogeneous cooperative real-time runtime library, and load the first target operator program into the FPGA logic resources;

[0014] The FPGA logic resources are used to execute corresponding parallel algorithm processing tasks according to the first target operator program.

[0015] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes a third DDR memory, and the third DDR memory is connected to the DSP; the second operator library is stored in the third DDR memory;

[0016] The ARM processor is used to determine a second target operator program from the second operator library through the heterogeneous cooperative real-time runtime library, and load the second target operator program into the DSP;

[0017] The DSP is used to execute corresponding serial algorithm processing tasks according to the second target operator program.

[0018] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes a fourth DDR memory, and the fourth DDR memory is connected to the NPU; the third operator library is stored in the fourth DDR memory;

[0019] The ARM processor is used to determine a third target operator program from the third operator library through the heterogeneous cooperative real-time runtime library, and load the third target operator program into the NPU;

[0020] The NPU is used to execute corresponding artificial intelligence algorithm processing tasks according to the third target operator program.

[0021] In one embodiment, the ZYNQ processor is connected to the DSP through the high-speed serial communication bus SRIO; and / or

[0022] The ZYNQ processor is connected to the NPU through the Peripheral Component Interconnect Express bus PCIe.

[0023] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes an optical port, a GPIO interface, and an RS422 interface;

[0024] The optical port is connected to the ZYNQ processor through an optical module, and the optical port is used to receive radar data;

[0025] The GPIO interface is connected to the ZYNQ processor through a buffer component Buffer, and the ZYNQ processor controls external devices through the GPIO interface;

[0026] The RS422 interface is connected to the ZYNQ processor through an RS422 interface chip, and the ZYNQ processor is communicatively connected to external devices through the RS422 interface.

[0027] In one embodiment, the reconfigurable heterogeneous radar data calculation module further includes an Ethernet port, and the Ethernet port is connected to the NPU through a PHY chip.

[0028] In one embodiment, the ZYNQ processor is a Fudan Micro FMQL45T900 chip; and / or

[0029] The DSP is a Galaxy Flying Dragon FT-M6678 chip; and / or

[0030] The NPU is an Ascend 310 chip.

[0031] In addition, to achieve the above object, the present application also proposes a computing device, and the computing device includes the reconfigurable heterogeneous radar data calculation module as described above.

[0032] One or more technical solutions proposed by the present application have at least the following technical effects:

[0033] The reconfigurable heterogeneous radar data calculation module provided by the present application includes a ZYNQ processor, a digital signal processor DSP, and a neural processing unit NPU. The ZYNQ processor is respectively connected to the DSP and the NPU. The ZYNQ processor includes an ARM processor and FPGA logic resources. Among them, the FPGA logic resources are used for parallel algorithm processing of radar data; the DSP is used for serial algorithm processing of radar data; the NPU is used for artificial intelligence algorithm processing of radar data; the ARM processor is used to schedule the FPGA logic resources, DSP, and NPU to execute corresponding algorithms according to the calculation tasks.

[0034] This application constructs a heterogeneous computing module using a ZYNQ processor, a DSP, and an NPU. The ZYNQ processor has the advantages of control, signal transmission, and algorithm calculation. The DSP has strong processing capabilities in signal processing and can be compatible with algorithm designs in signal processing. At the same time, the NPU also has powerful AI processing capabilities. With the above architecture, the ARM processor can flexibly allocate computing resources according to computing tasks and dynamically schedule each processor to process different types of algorithm tasks respectively, thereby giving full play to the advantages of each processor. Through dynamic task scheduling and flexible utilization of hardware resources, not only the overall performance of the computing module is improved, but also the flexibility and adaptability of the computing module are enhanced, meeting the high-performance requirements of the radar system for high-speed and accurate processing and intelligent recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following briefly introduces the drawings required for use in the description of the embodiments or related technologies. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a schematic diagram of the hardware structure of the first embodiment of the reconfigurable heterogeneous radar data computing module of this application;

[0038] Figure 2 It is a schematic diagram of the architecture of the processor data stream in the reconfigurable heterogeneous radar data computing module;

[0039] Figure 3 It is a schematic diagram of the software architecture of the processing flow of the reconfigurable heterogeneous radar data computing module;

[0040] Figure 4 It is a schematic diagram of the multi-processing flow of the reconfigurable heterogeneous radar data computing module.

[0041] The realization of the objectives, functional features, and advantages of this application will be further described with reference to the embodiments and the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts belong to the scope of protection of this application.

[0043] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of this application, the directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0044] In addition, if there are descriptions such as "first", "second", etc. involved in the embodiments of this application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one such feature. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel scenarios. Taking "A and / or B" as an example, it includes scenario A, or scenario B, or the scenario where A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0045] The development of informatization has brought about an explosive increase in the amount of information, resulting in a significant increase in the computing volume and processing complexity of computers. Therefore, higher requirements are also put forward for the computing performance of devices such as computers. In related technologies, the heterogeneity of the computing platform can be achieved through various interface chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), and FPGA (Field-Programmable Gate Array). The CPU is used for control, and the GPU and FPGA are used to implement service control and related algorithms.

[0046] However, for a radar system with high requirements for data processing and calculation, the computing platform is required to perform high-speed and accurate processing on the digital signals collected by the radar, and at the same time, functions such as target intelligent recognition need to be realized quickly and accurately. However, the computing power of the computing platform architecture in related technologies still has limitations and is difficult to meet the high-performance computing requirements of the above-mentioned radar system.

[0047] To solve this technical problem, a reconfigurable heterogeneous radar data calculation module of the present application is proposed. The reconfigurable heterogeneous radar data calculation module is a heterogeneous calculation module built using a ZYNQ processor, a DSP, and an NPU. Among them, the ZYNQ processor has the advantages of control, signal transmission, and algorithm calculation. The DSP has a powerful processing ability in signal processing and can be compatible with algorithm design in signal processing. At the same time, the NPU also has a powerful AI processing ability. With the above architecture, the ARM processor in the ZYNQ processor can flexibly allocate computing resources according to the calculation tasks, dynamically schedule each processor to process different types of algorithm tasks respectively, thereby giving full play to the advantages of each processor. Through dynamic task scheduling and flexible use of hardware resources, not only the overall performance of the calculation module is improved, but also the flexibility and adaptability of the calculation module are enhanced, and it can meet the high-performance requirements of the radar system for high-speed and accurate processing and intelligent recognition.

[0048] The following will be described and introduced through multiple embodiments.

[0049] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the hardware structure of the first embodiment of the reconfigurable heterogeneous radar data calculation module of the present application.

[0050] In this embodiment, the reconfigurable heterogeneous radar data calculation module may include a ZYNQ processor, a digital signal processor DSP, and a neural processing unit NPU. The ZYNQ processor is respectively connected to the DSP and the NPU. The ZYNQ processor includes an ARM processor and FPGA logic resources.

[0051] The FPGA logic resources are used for parallel algorithm processing of radar data.

[0052] The DSP is used for serial algorithm processing of radar data.

[0053] The NPU is used for artificial intelligence algorithm processing of radar data.

[0054] The ARM processor is used to schedule the FPGA logic resources, the DSP, and the NPU according to the calculation tasks to execute the corresponding algorithms.

[0055] Specifically, the ZYNQ processor is a heterogeneous processor integrating an ARM (Advanced RISC Machine Processor, advanced reduced instruction set computer processor) and FPGA (Field-Programmable Gate Array, field programmable gate array) logic resources. This architecture combines the flexibility of the ARM processor and the programmability of the FPGA logic resources, and is applicable to application scenarios that require high-performance computing and customized hardware acceleration.

[0056] As Figure 1 shown, the ZYNQ processor has a PS (Processing System) side and a PL (Programmable Logic) side; among them, the PS side contains one or more ARM processors, which can be used to run the operating system and handle general computing tasks; the PL side contains FPGA logic resources, and the FPGA logic resources refer to a large number of programmable logic units (Logic Elements, LEs) and programmable interconnection resources. These logic units can be configured into various digital logic functions, such as AND gates, OR gates, registers, etc.; the parallel architecture of the FPGA allows it to process multiple tasks simultaneously. Different from general serial processors (such as CPUs), the FPGA can configure multiple logic units in parallel, so as to execute multiple operations simultaneously; for example, in the processing of radar data, the FPGA logic resources can simultaneously execute multiple processing algorithms, such as fast Fourier transform, eigen decomposition, wave velocity synthesis, etc., to preprocess the radar data. This parallel processing ability makes the FPGA very efficient in processing a large amount of parallel data. In addition, the FPGA logic resources can also be configured into specific hardware accelerators for executing specific computing tasks. This hardware acceleration function makes the FPGA logic resources more efficient than CPUs or GPUs in processing complex algorithms; at the same time, the hardware implementation of the FPGA logic resources also reduces the latency of software execution, which is suitable for applications with high real-time requirements. In this embodiment, the FPGA logic resources can be mainly used for the preprocessing of radar data (i.e., data preprocessing). After a large amount of radar data is preprocessed in parallel by the FPGA logic resources, the ZYNQ distributes it to the corresponding DSP (Digital Signal Processor) and NPU (Neural Processing Unit) according to specific computing tasks for further processing.

[0057] The DSP is a microprocessor dedicated to performing digital signal processing tasks. It is usually used to process and analyze digital signals and can be used for serial algorithm tasks for processing radar data. For example, in radar data calculation, it can perform tasks such as MTD (Moving Target Detection) and CFAR (Constant False Alarm Rate). The corresponding algorithms can be target data fusion, trajectory calculation, etc. After the FPGA logic resources complete the preprocessing of radar data, the ZYNQ can distribute the preprocessed data to the DSP. The DSP can utilize its powerful processing capabilities in digital signal processing to further perform serial task calculations and achieve post-processing of radar data to optimize the data processing results. The NPU is a processor dedicated to accelerating artificial intelligence algorithms and deep learning tasks. It is usually used to process and optimize neural network models and can provide high-performance computing capabilities during the inference process (such as tasks like target classification and target recognition based on radar data).

[0058] When performing radar data calculation, the user can arrange the data processing flow through the ARM processor, that is, design the processing flow and the corresponding calculation tasks for each process. Thus, the ARM processor can schedule the corresponding FPGA logic resources, DSP, and NPU according to the calculation tasks to execute the corresponding algorithms to complete the entire processing flow of radar data. Among them, the ARM processor can transmit data with the FPGA logic resources through the AXI (Advanced Extensible Interface) bus inside the ZYNQ. The AXI bus ensures the input / output bandwidth of radar data, reduces data transmission loss, and can meet the requirements for data processing real-time performance. As Figure 1 shown, the ZYNQ processor can be connected to the DSP through SRIO (Serial RapidIO). SRIO is a point-to-point, distributed, high-bandwidth interconnection technology designed to provide low-latency, high-throughput communication capabilities, which can ensure the input / output bandwidth of data between the ZYNQ processor and the DSP, reduce data transmission loss, and meet the user's requirements for data processing real-time performance. The ZYNQ processor is also connected to the NPU through PCIe (Peripheral Component Interconnect Express). PCIe adopts a high-performance, low-latency, scalable serial bus standard, which can reduce the data transmission loss between the ZYNQ processor and the NPU, ensure data transmission efficiency, and meet the user's requirements for data processing real-time performance.

[0059] In a feasible implementation, the reconfigurable heterogeneous radar data calculation module further includes a first DDR memory, and the first DDR memory is connected to the ARM processor; a heterogeneous cooperative real-time runtime library is stored in the first DDR memory, and the heterogeneous cooperative real-time runtime library is used to provide an API function interface, and the ARM processor schedules the FPGA logic resources, DSP, and NPU through the API function interface to execute corresponding algorithms.

[0060] The reconfigurable heterogeneous radar data calculation module further includes a second DDR memory, and the second DDR memory is connected to the FPGA logic resources; a first operator program library is stored in the second DDR memory; the ARM processor is used to determine a first target operator program from the first operator program library through the heterogeneous cooperative real-time runtime library, and load the first target operator program into the FPGA logic resources; the FPGA logic resources are used to execute corresponding parallel algorithm processing tasks according to the first target operator program.

[0061] The reconfigurable heterogeneous radar data calculation module further includes a third DDR memory, and the third DDR memory is connected to the DSP; a second operator program library is stored in the third DDR memory; the ARM processor is used to determine a second target operator program from the second operator program library through the heterogeneous cooperative real-time runtime library, and load the second target operator program into the DSP; the DSP is used to execute corresponding serial algorithm processing tasks according to the second target operator program.

[0062] The reconfigurable heterogeneous radar data calculation module further includes a fourth DDR memory, and the fourth DDR memory is connected to the NPU; a third operator program library is stored in the fourth DDR memory; the ARM processor is used to determine a third target operator program from the third operator program library through the heterogeneous cooperative real-time runtime library, and load the third target operator program into the NPU; the NPU is used to execute corresponding artificial intelligence algorithm processing tasks according to the third target operator program.

[0063] It should be noted that the DDR memory (Double Data Rate, double data rate synchronous dynamic random access memory) can transmit data simultaneously at the rising edge and falling edge of the clock, so as to achieve a higher bandwidth than the single data transfer rate (SDR). Such as Figure 1As shown, the first DDR memory is connected to the PS side of the ZYNQ processor. After the user completes the data processing flow arrangement operation based on the ARM processor and determines the computing task, the ARM processor can call the corresponding operators in the operator program libraries of the FPGA logic resources, DSP, and NPU through the API function interface of the heterogeneous collaborative real-time runtime library to complete the computing task. All operator program libraries in this embodiment adopt standard API (Application Programming Interface) interfaces. The operator program libraries can be hooked through the heterogeneous collaborative real-time runtime library and virtually mapped as the operator running resources of the ARM processor. Thus, the ARM processor can execute the computing task at high speed through operator calls, greatly improving the development efficiency and reducing the development difficulty.

[0064] The above-mentioned second DDR memory stores a first operator program library. The first operator program library includes various logic acceleration computing operator programs for data preprocessing (such as fast Fourier transform, matrix inversion, eigen decomposition, wave speed synthesis, normalization, etc. operator programs). When the reconfigurable heterogeneous radar data calculation module is powered on, all operator programs in the first operator program library will be pre-loaded into the second DDR memory; after the ARM processor determines the computing task (that is, determines which computing subtasks should be executed by the FPGA logic resources, DSP, and NPU respectively), it can be scheduled and managed through the API function interface of the heterogeneous collaborative real-time runtime library, and a first target operator program is determined from the first operator program library. The first target operator program refers to one or more operator programs required to complete the computing subtask corresponding to the FPGA logic resources (that is, the parallel algorithm processing task). The first target operator program is loaded into the FPGA logic resources to complete the dynamic reconfiguration of the FPGA logic resources, and the FPGA logic resources execute the corresponding parallel algorithm processing task according to the first target operator program.

[0065] The second operator library is stored in the third DDR memory. The second operator library includes a variety of serial algorithm acceleration calculation operator programs for data post - processing (such as feed - forward algorithm, genetic algorithm, threshold filtering, target data fusion, trajectory calculation and other operator programs). When the reconfigurable heterogeneous radar data calculation module is powered on, all operator programs in the second operator library will also be pre - loaded into the third DDR memory; after the ARM processor determines the calculation task, it can perform scheduling management through the API function interface of the heterogeneous cooperative real - time runtime library, and determine the second target operator program from the second operator library. The second target operator program refers to one or more operator programs required to complete the calculation subtask corresponding to the DSP (i.e., the serial algorithm processing task), load the second target operator program into the DSP, complete the dynamic reconfiguration of the DSP, and the DSP executes the corresponding serial algorithm processing task according to the second target operator program.

[0066] Similarly, the third operator library is stored in the fourth DDR memory. The third operator library includes a variety of AI (Artificial Intelligence) acceleration calculation operator programs (such as YOLO, RESNET, SSD, VGG and other AI operator programs). All operator programs in the third operator library are also pre - loaded into the fourth DDR memory; after the ARM processor determines the calculation task, it performs scheduling management through the API function interface of the heterogeneous cooperative real - time runtime library, and determines the third target operator program from the third operator library. The third target operator program refers to one or more operator programs required to complete the calculation subtask corresponding to the NPU (i.e., the artificial intelligence algorithm processing task), load the third target operator program into the NPU, complete the dynamic reconfiguration of the NPU, and the NPU executes the corresponding artificial intelligence algorithm processing task according to the third target operator program. After each processor completes the corresponding task, the corresponding calculation results will be returned to the ZYNQ processor, and the ZYNQ processor will uniformly output the final calculation results.

[0067] In the above architecture, the ARM processor of ZYNQ is the task management and processing scheduling center of the reconfigurable heterogeneous radar data calculation module, responsible for the task scheduling of the three DDR memories (the second DDR memory, the third DDR memory and the fourth DDR memory). It has a high degree of freedom in task and processing flow design. The operator programs to be scheduled can be called through the API function interface of the heterogeneous cooperative real - time runtime library, without caring about the execution hardware call of the operator processor. The hardware algorithm acceleration execution and software scheduling are completely decoupled. The operator library has high independence and can be continuously enriched and increased, suitable for a variety of application scenarios and with high flexibility.

[0068] To enhance the generality and applicability of the reconfigurable heterogeneous radar data calculation module and facilitate data interaction with external devices, such as Figure 1 As shown, the reconfigurable heterogeneous radar data calculation module may further include an optical port, a GPIO interface (General Purpose Input / Output), and an RS422 interface. Among them, the optical port can be connected to the ZYNQ processor through an optical module and is used to receive radar data. The GPIO interface is connected to the ZYNQ processor through a buffer component Buffer, and the ZYNQ processor controls external devices through the GPIO interface. The RS422 interface is connected to the ZYNQ processor through an RS422 interface chip, and the ZYNQ processor communicates with external devices through the RS422 interface.

[0069] It can be understood that the optical port can be used to receive radar data collected by the front end and achieve high-speed data transmission through optical fibers and other means. The optical port is connected to the ZYNQ processor through an optical module, and the optical module converts the radar data in the form of optical signals into electrical signals for the ZYNQ processor to process. The GPIO interface is a general input / output interface that can be configured as an input or output mode and is used to control and read the status of external devices. The ZYNQ processor can control external devices, such as sensors and actuators, through the GPIO interface. The GPIO interface is connected to the ZYNQ processor through Buffer, and Buffer can temporarily store data to ensure stable data transmission. The RS422 interface is a serial communication interface that supports long-distance and high-speed data transmission. The ZYNQ processor communicates and controls external devices through the RS422 interface, which is suitable for scenarios that require long-distance communication in the radar system.

[0070] The above-mentioned reconfigurable heterogeneous radar data calculation module realizes various data input / output functions through the optical port, GPIO interface, and RS422 interface. The combination of these interfaces enables the system to flexibly adapt to different application scenarios and improves the overall performance and reliability of the reconfigurable heterogeneous radar data calculation module.

[0071] In addition, the reconfigurable heterogeneous radar data calculation module may further include an Ethernet port, such as Figure 1 As shown, the Ethernet port can be connected to the NPU through a PHY chip. The PHY (Physical Layer) chip can convert electrical signals into signals suitable for transmission over physical media. In Ethernet communication, the PHY chip is responsible for converting digital signals into analog signals for transmission through Ethernet cables. To ensure the integrity and anti-interference ability of signals during transmission between different media, such as Figure 1As shown, a transformer can also be connected between the Ethernet port and the PHY chip. This transformer is usually used to isolate the signals between the PHY and the Ethernet port, prevent signal interference and power supply noise, reduce electromagnetic interference in signal transmission, and improve the transmission quality of signals. In practical applications, the ZYNQ processor usually also includes other peripheral interfaces such as an Ethernet interface. The processing results of the NPU can also be transmitted to the ZYNQ processor through the above Ethernet port. As Figure 1 shown, the ZYNQ processor, DSP, and NPU of the reconfigurable heterogeneous radar data calculation module can all be connected to a Flash (Flash Memory) chip. Flash is a non-volatile memory that can still retain the stored data without power supply to ensure data integrity.

[0072] It is worth mentioning that the above ZYNQ processor can be the Fudan Micro FMQL45T900 chip; the DSP can be the Galaxy Flying Dragon FT-M6678 chip; the NPU can be the Ascend 310 chip. The Fudan Micro FMQL45T900 chip uses the processor core of ARM Cortex-A9 and has high-performance general computing capabilities. The Galaxy Flying Dragon FT-M6678 chip has a high-performance DSP core and can support high-precision mathematical operations. The Ascend 310 chip is a chip designed specifically for deep learning and artificial intelligence tasks and supports efficient neural network inference. By using the Fudan Micro FMQL45T900 chip as the ZYNQ processor, the Galaxy Flying Dragon FT-M6678 chip as the DSP, and the Ascend 310 chip as the NPU, the reconfigurable heterogeneous radar data calculation module can achieve efficient data processing and intelligent recognition. The combination of these chips makes the calculation module have high performance, flexibility, and adaptability, and is suitable for scenarios such as radar systems that require high-performance computing and customized hardware acceleration.

[0073] It is not difficult to understand that the reconfigurable heterogeneous radar data calculation module provided by the embodiments of the present application is a heterogeneous calculation module built using a ZYNQ processor, a DSP, and an NPU. Among them, the ZYNQ processor has the advantages of control, signal transmission, and algorithm calculation. The DSP has strong processing capabilities in signal processing and can be compatible with algorithm design in signal processing. At the same time, the NPU also has strong AI processing capabilities. Using the above architecture, the ARM processor in the ZYNQ processor can flexibly allocate computing resources according to the calculation tasks and dynamically schedule each processor to process different types of algorithm tasks respectively. Thus, the advantages of each processor can be fully utilized. Through dynamic task scheduling and flexible use of hardware resources, not only the overall performance of the calculation module is improved, but also the flexibility and adaptability of the calculation module are enhanced, and it can meet the high-performance requirements of the radar system for high-speed and accurate processing and intelligent recognition.

[0074] Exemplarily, to facilitate the understanding of the reconfigurable heterogeneous radar data calculation module of this embodiment, please refer to Figures 2 to 4 .

[0075] Specifically, Figure 2 is a schematic diagram of the architecture of the processor data stream in the reconfigurable heterogeneous radar data calculation module. As Figure 2 shown, the Fudan Micro FMQL45T900 chip is used as the ZYNQ processor of the reconfigurable heterogeneous radar data calculation module, the Galaxy Flying Dragon FT-M6678 chip is used as the DSP, and the Ascend 310 chip is used as the NPU. The 4-core ARM processor in the Fudan Micro FMQL45T900 chip can transmit data to the outside through Gigabit Ethernet interface, fiber optic interface and RS422 interface. Radar data can be input to the 4-core ARM processor through the fiber optic interface, etc. After the 4-core ARM processor completes the workflow design and determines the corresponding calculation task, it sends the corresponding data to the FPGA logic resources for logic acceleration. According to the calculation requirements, the corresponding logic acceleration calculation operator program is selected from the second DDR memory for dynamic loading and reconstruction, so that the FPGA logic resources execute the corresponding calculation task; the ZYNQ processor can transmit the data to be processed to the Ascend 310 chip through the PCIe high-speed interface for AI processing acceleration. According to the calculation requirements, the corresponding AI acceleration calculation operator program is selected from the fourth DDR memory for dynamic loading and reconstruction, so that the NPU executes the corresponding calculation task; similarly, the ZYNQ processor transmits the data to be processed to the Galaxy Flying Dragon FT-M6678 chip through the SRIO high-speed interface for signal processing acceleration to post-process the radar data (such as MTD, CFAR, etc.). According to the calculation requirements, the corresponding acceleration calculation operator program is selected from the third DDR memory for dynamic loading and reconstruction, so that the DSP executes the corresponding calculation task.

[0076] As Figure 3 shown, Figure 3 is a schematic diagram of the software architecture of the processing flow of the reconfigurable heterogeneous radar data calculation module. As Figure 3As shown, users can build a heterogeneous processing system master platform (hereinafter referred to as the master platform) based on the ARM processor. The master platform conducts data transmission with the outside through Gigabit Ethernet interfaces, fiber optic interfaces, and RS422 interfaces. Users can design the process of computing tasks on the master platform according to actual needs, determine the computing tasks that each processor needs to handle. The master platform can schedule the NPU through the heterogeneous cooperation real-time runtime library, select the target operator program from the AI model program library (i.e., the third operator program library) for dynamic reconstruction to accelerate AI processing. The master platform schedules the DSP through the heterogeneous cooperation real-time runtime library, selects the target operator program from the DSP accelerated computing operator program library (i.e., the second operator program library) for dynamic reconstruction to accelerate signal processing (i.e., radar data post-processing). The master platform schedules the FPGA logic resources through the heterogeneous cooperation real-time runtime library, selects the target operator program from the logic acceleration operator program library (i.e., the first operator program library) for dynamic reconstruction to accelerate logic processing (i.e., radar data preprocessing).

[0077] In addition, users can also build multiple work processes on the ARM processor for switching, such as Figure 4 shown Figure 4 is a schematic diagram of multiple processing processes of a reconfigurable heterogeneous radar data calculation module. After the radar data is input into the reconfigurable heterogeneous radar data calculation module, the ARM processor determines the corresponding API function 1 according to calculation task 1, and then calls the corresponding acceleration processing units (FPGA logic resources, DSP, and NPU) through the heterogeneous cooperation implementation runtime library. Each acceleration processing unit selects the corresponding operator from the corresponding operator library for dynamic reconstruction to complete the processing process of calculation task 1. The processing result (result 1) of task 1 is saved to the ARM processor. The ARM processor then determines the corresponding API function 2 according to calculation task 2, and then calls the corresponding acceleration processing units through the heterogeneous cooperation implementation runtime library. Each acceleration processing unit selects the corresponding operator from the corresponding operator library for dynamic reconstruction to complete the processing process of calculation task 2. Similarly, continue the above process until calculation task n is completed, and finally output the processing results of calculation task 1, calculation task 2... calculation task n. The call of the operator is operated through the API function, and the execution of the operator is carried out through dynamic reconstruction and real-time loading and switching on different processors. Each processing process (calculation task) consists of several operators. The preprocessing of intelligent computing data is mainly realized by FPGA logic resources, the AI intelligent computing processing is realized by the NPU, and the result post-processing is realized by the DSP. Through this design, a reconfigurable intelligent computing platform with certain generality and scalability is realized.

[0078] It is not difficult to see that in the above reconfigurable heterogeneous radar data calculation module, by calling the API function interface of the heterogeneous cooperative real-time runtime library, the collaborative calculation of basic operators on the ARM and heterogeneous acceleration processing units (FPGA logic resources, DSP, and NPU) is achieved. The calculation operator library is a specification library that integrates the calculation of scalar, vector, and matrix type data and various AI algorithm models, covering the calculation interface specifications in the fields of signal processing, linear algebra, equation solving, matrix operations, AI algorithm models, etc. The heterogeneous cooperative real-time runtime library provides a set of user-level interfaces for the underlying devices, which are used to complete the interaction between the host side (ARM) and the coprocessor side (DSP, NPU, or FPGA logic resources) and the invocation of the built-in calculation functions of the heterogeneous processors. The above design realizes the flexibility of use of the reconfigurable heterogeneous radar data calculation module.

[0079] It should be noted that the above examples are only for understanding the present application and do not constitute a limitation on the reconfigurable heterogeneous radar data calculation module of the present application. Based on this technical concept, more forms of simple transformations are within the protection scope of the present application.

[0080] Based on the same inventive concept, the present application also provides a computing device, which includes the reconfigurable heterogeneous radar data calculation module as described above.

[0081] It should be noted that the specific structure of the reconfigurable heterogeneous radar data calculation module in the computing device of the present application can refer to the above embodiments. Since the computing device adopts all the technical solutions of the above embodiments of the reconfigurable heterogeneous radar data calculation module, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one.

[0082] The above are only some embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A reconfigurable heterogeneous radar data calculation module, characterized in that, The reconfigurable heterogeneous computing module includes: a ZYNQ processor, a digital signal processor (DSP), and a neural processing unit (NPU). The ZYNQ processor is respectively connected to the DSP and the NPU. The ZYNQ processor includes an ARM processor and FPGA logic resources. The FPGA logic resources are used for processing parallel-class algorithms of radar data. The DSP is used for processing serial-class algorithms of radar data. The NPU is used for processing artificial intelligence algorithms of radar data. The ARM processor is used for scheduling the FPGA logic resources, the DSP, and the NPU to execute corresponding algorithms according to the computing tasks.

2. The reconfigurable heterogeneous radar data calculation module according to claim 1, wherein The reconfigurable heterogeneous radar data computing module further includes a first DDR memory, and the first DDR memory is connected to the ARM processor. The first DDR memory stores a heterogeneous cooperative real-time runtime library, and the heterogeneous cooperative real-time runtime library is used to provide an API function interface. The ARM processor schedules the FPGA logic resources, the DSP, and the NPU to execute corresponding algorithms through the API function interface.

3. The reconfigurable heterogeneous radar data calculation module according to claim 2, wherein The reconfigurable heterogeneous radar data computing module further includes a second DDR memory, and the second DDR memory is connected to the FPGA logic resources. The second DDR memory stores a first operator program library. The ARM processor is used to determine a first target operator program from the first operator program library through the heterogeneous cooperative real-time runtime library and load the first target operator program into the FPGA logic resources. The FPGA logic resources are used to execute corresponding parallel-class algorithm processing tasks according to the first target operator program.

4. The reconfigurable heterogeneous radar data calculation module according to claim 2, wherein, The reconfigurable heterogeneous radar data computing module further includes a third DDR memory, and the third DDR memory is connected to the DSP. The third DDR memory stores a second operator program library. The ARM processor is used to determine a second target operator program from the second operator program library through the heterogeneous cooperative real-time runtime library and load the second target operator program into the DSP. The DSP is used to execute corresponding serial-class algorithm processing tasks according to the second target operator program.

5. The reconfigurable heterogeneous radar data calculation module as described in claim 2, wherein, The reconfigurable heterogeneous radar data computing module further includes a fourth DDR memory, and the fourth DDR memory is connected to the NPU. The fourth DDR memory stores a third operator program library. The ARM processor is used to determine a third target operator program from the third operator program library through the heterogeneous cooperative real-time runtime library and load the third target operator program into the NPU. The NPU is used to execute corresponding artificial intelligence algorithm processing tasks according to the third target operator program.

6. The reconfigurable heterogeneous radar data calculation module according to claim 1, characterized in that, The ZYNQ processor is connected to the DSP through a high-speed serial communication bus (SRIO); and / or The ZYNQ processor is connected to the NPU through a peripheral component interconnect express bus (PCIe).

7. The reconfigurable heterogeneous radar data calculation module according to claim 1, wherein The reconfigurable heterogeneous radar data calculation module further includes an optical port, a GPIO interface, and an RS422 interface; The optical port is connected to the ZYNQ processor through an optical module, and the optical port is used to receive radar data; The GPIO interface is connected to the ZYNQ processor through a buffer component Buffer, and the ZYNQ processor controls external devices through the GPIO interface; The RS422 interface is connected to the ZYNQ processor through an RS422 interface chip, and the ZYNQ processor is communicatively connected to external devices through the RS422 interface.

8. The reconfigurable heterogeneous radar data calculation module according to claim 1, wherein The reconfigurable heterogeneous radar data calculation module further includes an Ethernet port, and the Ethernet port is connected to the NPU through a PHY chip.

9. The reconfigurable heterogeneous radar data calculation module according to any one of claims 1 to 8, characterized in that The ZYNQ processor is a Fudan Microelectronics FMQL45T900 chip; and / or The DSP is a Galaxy Flying Dragon FT-M6678 chip; and / or The NPU is an Ascend 310 chip.

10. A computing device, characterized in that, The computing device includes the reconfigurable heterogeneous radar data calculation module according to any one of claims 1 to 9.

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