Memory circuit and operation method thereof

Abstract

The invention discloses a memory circuit and an operation method thereof. The memory circuit can comprise a memory array, a data mode detector and a write-in driver. The memory array may include a plurality of memory bit cells. The data pattern detector may be used to: (i) receive a plurality of data bits; (ii) identifying a first number of a first subset of the plurality of data bits each equal to a first logic state and a second number of a second subset of the plurality of data bits each equal to a second logic state; and (iii) selectively adjusting a plurality of respective logic states of the plurality of data bits based on comparing the first number with the second number. The write driver may be used to write selectively adjusted logic states of the plurality of data bits into the plurality of memory bit cells, respectively.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory circuit for detecting a data pattern and an operation method thereof, and more particularly to a memory circuit for detecting a data pattern and an operation method thereof. Background Art

[0002] Memory devices are integrated components of an electronic system that store data in a manner that allows for quick access and modification. Traditionally, memory devices have been designed to store binary information in the form of "0"s and "1"s in a large number of memory cells. Due to manufacturing variations and design constraints, these cells often exhibit unbalanced physical structures, resulting in different electrical characteristics. One such characteristic is leakage current, which represents the flow of current within a memory cell when the memory cell is not being actively accessed or modified. Summary of the Invention

[0003] In some embodiments, a memory circuit is provided, including: a memory array including a plurality of memory bit cells; a data pattern detector configured to: (i) receive a plurality of data bits; (ii) identify a first number of a first subset of these data bits each equal to a first logical state and a second number of a second subset of these data bits each equal to a second logical state; and (iii) selectively adjust the respective logical states of these data bits based on comparing the first number with the second number; and a write driver configured to write the selectively adjusted logical states of these data bits into these memory bit cells, respectively.

[0004] In some embodiments, a memory circuit is provided, including: a memory array including a plurality of memory bit cells; a data pattern detector configured to: (i) identify that a first number of a first subset of a plurality of data bits each equal to a first logical state is greater than a second number of a second subset of these data bits each equal to a second logical state or greater than a threshold value; and (ii) logically invert the respective logical states of these data bits; and a write driver configured to write the logically inverted logical states of these data bits into these memory bit cells, respectively.

[0005] In some embodiments, an operation method of a memory circuit is provided, including the steps of: identifying that a first number of a first subset of a plurality of data bits each equal to a first logical state is greater than a second number of a second subset of these data bits each equal to a second logical state or greater than a threshold value; and logically inverting the respective logical states of these data bits. Brief Description of the Drawings

[0006] Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 FIG. 4 shows a block diagram of a memory circuit 100 according to some embodiments of the present disclosure;

[0008] Figure 2 FIG. shows a detailed schematic diagram of a memory circuit 100 according to some embodiments of the present disclosure; Figure 1 of

[0009] Figure 3 FIG. shows a detailed schematic diagram of an example of a data pattern detector 130 according to some embodiments of the present disclosure; Figure 1 of

[0010] Figure 4 FIG. shows an example performance evaluation of a memory circuit 100 according to some embodiments of the present disclosure; Figure 1 of

[0011] Figure 5 is a flowchart of an example method for operating a memory circuit 100 according to some embodiments of the present disclosure; Figure 1 and Figure 2 of

[0012]

Reference Signs

[0013] 100: Memory circuit

[0014] 110: Memory array

[0015] 112: Arrow

[0016] 120: Write driver

[0017] 130: Data pattern detector

[0018] 131: Flag bit

[0019] 140: Read driver

[0020] 150: Inverter

[0021] 160: Word line driver

[0022] 170: Control circuit

[0023] 310: Counter

[0024] 312: First adder

[0025] 314: Second adder

[0026] 316: Third adder

[0027] 318: Fourth adder

[0028] 320: Comparator

[0029] 500: Method

[0030] 502: Operation

[0031] 504: Operation

[0032] 506: Operation

[0033] 508: Operation

[0034] WL: Word line

[0035] CTRL: Control circuit

[0036] INV_Flag: Flag bit

[0037] DS[S:0]: Data bit

[0038] D[S:0]: Data bit

[0039] D[0]-D

[15] : Data

[0040] HA: Adder

[0041] Sum: Result Detailed implementation manners

[0042] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the embodiments of this disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. In addition, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0043] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship of one element or feature depicted in the figures to another element or feature. Except for the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0044] In a conventional memory system, data is directly stored into a memory cell array without considering the pattern of the data. For example, if the data to be written is "00011000" or "11101001", it is written into the memory cell array as it is. Traditional methods for low-power design mainly focus on adjusting the threshold voltage (VT) or modulating the supply voltage (VDD). However, these methods do not take into account specific data patterns that may affect power consumption. For example, in some neural network layers, negative weights are prevalent, which are represented by binary patterns such as "1111XXXX" or "11111XXX". When these patterns are accessed or modified frequently, it can result in a large amount of energy consumption during read and write operations, which highlights the need for a more data-pattern-aware power management method in memory design.

[0045] The present disclosure embodiments are directed to memory devices, and more particularly, to systems and methods for addressing energy consumption during read / write operations in memory devices to achieve low power consumption. Unbalanced cell structures in memory devices can lead to variations in the energy required to read from or write to memory cells. This difference further results in inefficiencies because the power consumption for writing a "0" may be different from that for writing a "1", and the power consumption for read operations is also different. In low-power applications where energy efficiency is crucial, these power consumption differences can be particularly problematic. Previous methods for designing low-power memory devices have largely ignored these variations in cell structure and their impact on power consumption. Therefore, a memory design method is needed that takes into account the energy consumption during read / write operations to minimize the power consumption during both read and write operations.

[0046] Embodiments of the present disclosure provide various embodiments of a memory circuit to solve these problems. For example, as disclosed herein, a memory circuit includes a memory array, a data pattern detector, and a write driver. The data pattern detector can detect a data pattern before storing the data. For example, if the power consumption for standby, read, or write of a "1" is greater than that for a "0", the data pattern detector evaluates the data: if the "1" count exceeds the "0", the data pattern detector reverses the data (e.g., from "1111_0011_1110_0101" to "0000_1100_0001_1010"), and sets a reverse flag (e.g., INV_FLAG) to 1.

[0047] Figure 1 FIG. illustrates a block diagram of a memory circuit 100 according to some embodiments of the present disclosure. The memory circuit 100 may include a memory array 110, a write driver 120, and a data pattern detector 130. In some embodiments, the memory circuit 100 may include a memory array 110, a read driver 140, and a plurality of inverters 150.

[0048] The memory array 110 may include a plurality of memory bit cells. One or more peripheral circuits (not shown) may be located at one or more regions on the periphery or inside the memory array 110. The memory bit cells and the peripheral circuits may be coupled via word lines and / or complementary bit lines BL and BLB, and data may be read from and written to the memory bit cells via the complementary bit lines BL and BLB. Different voltage combinations applied to the word lines and the bit lines may define read, erase, or write (program) operations on the memory bit cells. In some embodiments, the memory array 110 architecture may incorporate various types of non-volatile or volatile memory technologies, including but not limited to static random-access memory (SRAM), resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), and phase-change random access memory (PCRAM). The proposed low-power memory circuit design is general and can be applied to improve the power efficiency of various memory technologies, addressing the common challenge of energy consumption in different memory systems.

[0049] In some embodiments, the data pattern detector 130 may detect a data pattern (represented by the hollow arrow 112) before writing data into the memory cell array 110. The data pattern detector 130 may be used to receive a plurality of data bits (represented by the hollow arrow 112). For example, the data pattern detector 130 may receive one or more 16-bit data strings. Examples of such 16-bit data strings may be "1100_0000_1100_0101" or "1111_0011_1110_0101". In some embodiments, the data pattern detector 130 may include a counter that includes a plurality of adders and at least one comparator.

[0050] In some embodiments, the data pattern detector 130 may further be used to identify a first number of a first subset of data bits each equal to a first logic state (e.g., logic "1") and a second number of a second subset of data bits each equal to a second logic state (e.g., logic "0"). For example, the first logic state may be logic 1, and the second logic state may be logic 0. In certain embodiments, the data pattern detector 130 may be designed to identify the data pattern before the start of the write process to the memory cell array 110, as indicated by the hollow arrow 112. The data pattern detector 130 may be good at handling multiple bits simultaneously; for example, it can process 16-bit data strings (e.g., "1100_0000_1100_0101" or "1111_0011_1110_0101"), etc. By examining these patterns, the memory circuit can make an informed decision on how to store data effectively and reduce power consumption.

[0051] In some embodiments, the data pattern detector 130 may further be used to determine a first number (e.g., capable of determining the count of the initial logic "1" values in a given data string). For example, the data pattern detector 130 can determine that the number of logic "1"s (e.g., the first number) in the data string "1100_0000_1100_0101" is 6. In different scenarios, the data pattern detector 130 may identify that the first number of the data string "1111_0011_1110_0101" is 11. In addition, the data pattern detector 130 has the function of comparing the first number with a threshold value. The data pattern detector 130 may further be used to determine the threshold value as half of the total number of data bits (e.g., 16) (e.g., 8). The threshold value may be defined as half of the total bit count of the data string; for example, for a 16-bit data string, it may be 8. In certain embodiments, the threshold value may be preset / pre-configured as a half value relative to the total bit count of the analyzed data string (e.g., half of the total number of data bits). In some embodiments, the inverted threshold value is adjustable.

[0052] In some embodiments, the data pattern detector 130 may further be used to selectively adjust the respective logic states of the data bits based on comparing a first number with a second number. In some embodiments, since storing / reading / programming the data "1" has a greater read / write energy consumption, when the number of logic 1s is greater than the number of logic 0s, the data pattern detector 130 may selectively adjust the respective logic states of the data bits. If the number of logic "1"s is greater than the number of logic "0"s, the data pattern detector 130 may invert the data before writing to the memory cell array 110. For example, in the data string "1111_0011_1110_0101", the number of logic "1"s (e.g., the first number) is 11, and the number of logic "0"s (e.g., the second number) is 5. In this case, the number of logic "1"s (e.g., the first number) is greater than the number of logic "0"s (e.g., the second number). In response to the first number being greater than the second number, the data pattern detector 130 may logically invert the respective logic states of the data string "1111_0011_1110_0101" to "0000_1100_0001_101"

[0053] In some embodiments, the data pattern detector 130 may further be configured to logically invert the respective logical states of the data bits in response to the first number being greater than a threshold value. For example, for the data string “1111_0011_1110_0101”, the number of logical “1”s (e.g., the first number) is 11, and the threshold value (e.g., half of the total number of data bits) is 8. In this case, the number of logical “1”s (e.g., 11) is greater than the threshold value (e.g., 8). In response to the first number being greater than the threshold value, the data pattern detector 130 may logically invert the respective logical states of the data string “1111_0011_1110_0101” to “0000_1100_0001_1010”. In some embodiments, the threshold value is pre-configured to be half of the total number of data bits. In some embodiments, the data pattern detector 130 may further be configured to provide a flag bit (e.g., INV_Flag) indicating whether the first number is greater than (or equal to or less than) the threshold value. When the first number is greater than the threshold value, the flag bit may be equal to a first value (e.g., 1). When the first number is equal to or less than the threshold value, the flag bit may be equal to a second value (e.g., 0). In some embodiments, the data pattern detector 130 may further be configured to provide a flag bit indicating whether the first number is greater than (or equal to or less than) a second number. When the first number is greater than the second number, the flag bit may be equal to a first value (e.g., 1). When the first number is equal to or less than the second number, the flag bit may be equal to a second value (e.g., 0). For example, the flag bit of the inverted data string “0000_1100_0001_1010” may be 1 (e.g., INV_Flag = 1). Additional flag storage and counters may be required. The bit width of the data string used for detection may be adjustable. The write driver 120 may be used to write the selectively adjusted logical states of the data bits (e.g., “0000_1100_0001_1010”) and the flag bit (e.g., INV_Flag = 1) into a plurality of memory bit cells 110.

[0054] In some embodiments, the data pattern detector 130 may further be used to logically maintain the respective logical states of the data bits in response to the first number being less than or equal to a threshold value. For example, in the data string “1100_0000_1100_0101”, the number of logical “1”s (e.g., the first number) is 6, and the number of logical “0”s (e.g., the second number) is 10. In this case, the number of logical “1”s (e.g., the first number) is less than the number of logical “0”s (e.g., the second number). In response to the first number being less than the second number, the data pattern detector 130 may logically maintain / preserve the respective logical states of the data string “1100_0000_1100_0101”. In some embodiments, the data pattern detector 130 may further be used to provide a flag bit (e.g., INV_Flag) indicating whether the first number is greater than (or equal to or less than) the threshold value. When the first number is greater than the threshold value, the flag bit may be equal to a first value (e.g., 1). When the first number is equal to or less than the threshold value, the flag bit may be equal to a second value (e.g., 0). In certain embodiments, the data pattern detector 130 may further be used to provide a flag bit indicating whether the first number is greater than (or equal to or less than) the second number. When the first number is greater than the second number, the flag bit may be equal to a first value (e.g., 1). When the first number is equal to or less than the second number, the flag bit may be equal to a second value (e.g., 0). For example, the flag bit for the maintained / preserved data string “1100_0000_1100_0101” may be 0 (e.g., INV_Flag = 0). Additional flag storage and counters may be required. The bit width of the data string used for detection may be adjustable. The write driver 120 may be used to write the maintained / preserved logical states of the data bits (e.g., “1100_0000_1100_0101”) and the flag bit (e.g., INV_Flag = 0) into the plurality of memory bit cells 110.

[0055] In some embodiments, the read driver 140 may be used to read the logical state of the data bits and / or the flag bit (e.g., INV_Flag) from the memory bit cell 110. For example, the read driver 140 may read the logical state and the flag bit INV_Flag = 1 of the data string “0000_1100_0001_1010”. In another example, the read driver 140 may read the logical state and the flag bit INV_Flag = 0 of the data string “1100_0000_1100_0101”. When the flag bit is equal to the first value (e.g., 1), the flag bit may indicate that the first number is greater than the threshold value. When the flag bit is equal to the second value (e.g., 0), the flag bit may indicate that the first number is equal to or less than the threshold value.

[0056] Multiple inverters 150 can be used to selectively and logically invert the read logic state based on a flag bit (e.g., INV_Flag). In some embodiments, the multiple inverters 150 can be activated in response to the flag bit being equal to a first value (e.g., 1), and / or can remain deactivated in response to the flag bit being equal to a second value (e.g., 0). For example, the read driver 140 can read the logic state of the data string "0000_1100_0001_1010" and the flag bit INV_Flag = 1. In response to the flag bit being equal to 1, the multiple inverters 150 can logically invert the read logic state of the data string "0000_1100_0001_1010" to "1111_0011_1110_0101". For another example, the read driver 140 can read the logic state of the data string "1100_0000_1100_0101" and the flag bit INV_Flag = 0. In response to the flag bit being equal to 0, the multiple inverters 150 can remain deactivated and not logically invert the read logic state of the data string "1100_0000_1100_0101".

[0057] Figure 2 Illustrating a detailed schematic diagram of a Figure 1 memory circuit 100 according to some embodiments of the present disclosure. The memory circuit 100 may include a memory array 110, a write driver 120, a data pattern detector 130, a control circuit 170, and a word line (WL) driver 160. In some embodiments, the memory circuit 100 may include a memory array 110, a read driver 140, multiple inverters 150, a control circuit 170, and a word line (WL) driver 160. Figure 2 The memory circuit 100 of Figure 1 is substantially similar to the Figure 2 memory device 100. Unless it is necessary to introduce the cooperation relationship with the components shown in

[0058] In the write mode, data pattern detector 130 may receive a plurality of data bits (e.g., D[S:0]). The data pattern detector 130 may identify that a first number of a first subset of the plurality of data bits each equal to a first logic state (e.g., 1) is greater than a second number of a second subset of the data bits each equal to a second logic state (e.g., 0). In some embodiments, the data pattern detector 130 may identify that a first number of a first subset of the plurality of data bits each equal to a first logic state (e.g., 1) is greater than a threshold value. In this case, the data pattern detector 130 may logically invert the respective logic states of the data bits (e.g., DS[S:0]), and provide a flag bit (e.g., INV_Flag) 131. The write driver 120 may be used to write the logically inverted logic states of the data bits (e.g., DS[S:0]) and the flag bit (e.g., INV_Flag = 1) 131 into the plurality of memory bit cells 110, respectively. In some embodiments, the data pattern detector 130 may identify that a first number of a first subset of the plurality of data bits each equal to a first logic state (e.g., 1) is less than a threshold value. In this case, the data pattern detector 130 may maintain the respective logic states of the data bits (e.g., DS[S:0]), and provide a flag bit (e.g., INV_Flag = 0) 131. The write driver 120 may be used to write the logically maintained logic states of the data bits (e.g., DS[S:0]) and the flag bit (e.g., INV_Flag = 0) 131 into the plurality of memory bit cells 110, respectively.

[0059] In the read mode, the read driver 140 may be used to read the logic states of the data bits and the flag bit (e.g., INV_Flag) 131 from the memory bit cells 110. For example, the read driver 140 may read the logic states of the data string “0000_1100_0001_1010” and the flag bit 131 (INV_Flag = 1). In response to the flag bit 131 being equal to 1, a plurality of inverters 150 may logically invert the read logic states of the data string “0000_1100_0001_1010” to “1111_0011_1110_0101”. For another example, the read driver 140 may read the logic states of the data string “1100_0000_1100_0101” and the flag bit INV_Flag = 0. In response to the flag bit 131 being equal to 0, the plurality of inverters 150 may remain deactivated and not logically invert the read logic states of the data string “1100_0000_1100_0101”.

[0060] The control circuit 170 can capture data from the temporary storage source via complementary DLB and DL inputs. These input signals can control the rows of transistors, thereby affecting the BL and BLB voltages, which are converted into binary signals for the control circuit. In this configuration, the write latch can hold the DL data during the clock cycle for writing to the memory cell. During a read operation, the write latch is largely inactive. This configuration facilitates write operations based on the input, enabling data to be stored in the corresponding locations.

[0061] The word line (WL) driver 160 can be responsible for activating the word lines within the memory array 110. When data needs to be read from or written to a column of the memory cells 110, the word line (WL) driver 160 can select the appropriate word line by driving it to a higher voltage level. Subsequently, the selected column of cells can be read or written through sense amplifiers or write drivers connected to the bit lines, which extend vertically and intersect the word lines.

[0062] Figure 3 Illustrating an example detailed schematic diagram of Figure 1 the data pattern detector 130 according to some embodiments of the present disclosure. The data pattern detector 130 can include a counter 310 and at least one comparator 320.

[0063] In some embodiments, the counter 310 can include a plurality of adders. For example, in Figure 3In [the figure], the counter 310 includes a plurality of first adders 312, a plurality of second adders 314, a plurality of third adders 316, and a plurality of fourth adders 318. The first adder 312 can be configured at a first level to receive a data string (e.g., a 16-bit data string: D[0], D[1],..., D

[14] , and D

[15] ). The second adder 314 can be configured at a second level to receive the output from the first level. The third adder 316 can be configured at a third level to receive the output from the second level. The fourth adder 318 can be configured at a fourth level to receive the output from the third level. The second adder 314, the third adder 316, and the fourth adder 318 can include a plurality of full adders. In various embodiments, the second adder 314 can be connected to two first adders 312. As a non-limiting example, such a configuration can be implemented for a 16-bit data string (e.g., D[0], D[1],..., D

[14] , and D

[15] ) in various embodiments. For example, for the data string "1110_1011_0110_1101", D[0]=1, D[1]=1, D[2]=1, D[3]=0, D[4]=1, D[5]=0, D[6]=1, D[7]=1, D[8]=0, D[9]=1, D

[10] =1, D

[11] =0, D

[12] =1, D

[13] =1, D

[14] =0, and D

[15] =1. In Figure 3 In [the figure], the leftmost first adder 312 can receive inputs from D[0] and D[1], and can output a result of 2 to the second adder 314. The rightmost first adder 312 can receive inputs from D

[14] and D

[15] , and can output a result of 1 to the second adder 314. For the data string "1110_1011_0110_1101", the fourth adder 318 can output a result of 11 to the comparator 320. However, it should be understood that the number of half adders and / or the number of full adders provided can depend on the size of the data string. The plurality of adders 312, 314, 316, 318 can generate a result (e.g., Sum[4:0]) of the data string for the comparator 320.

[0064] Comparator 320 can be used to provide an output (e.g., INV_Flag) 131 based on the results of adders 312, 314, 316, 318 (e.g., Sum[4:0]) and a threshold value (e.g., 8). Comparator 320 can be used to evaluate the sum of a subset of designated bits within a 16-bit data width represented as D[15:0]. The focus of the evaluation is on the results from adders 312, 314, 316, 318 (e.g., Sum[4:0]). When the result of the data string exceeds the value of 8, the flag bit (e.g., INV_Flag) is set to 1. For the data string "1110_1011_0110_1101", the result of the data string from the adder is 11, which exceeds the threshold value 8. Comparator 320 sets the flag bit to 1. This flag bit signals the system to invert the entire 16-bit data string (e.g., from "1110_1011_0110_1101" to "0001_0100_1001_0010"), effectively switching the values of each bit. Conversely, if the result of the data string is less than or equal to 8, INV_Flag is set to 0, indicating that the data should remain in its initial state without any inversion. This conditional flag allows for dynamic data operations based on a predefined threshold value, thereby optimizing data for processes that may benefit from such inversion, such as power reduction or enhanced data integrity in memory storage operations.

[0065] Figure 4 Illustrates an example performance evaluation of Figure 1 memory circuit 100 according to some embodiments of the present disclosure. As Figure 4 shown, the effectiveness of the embodiments of the present disclosure is proportional to the number of "1" bits present in the data string. In some embodiments, storing / reading / programming data "1" has a greater read / write energy consumption. Figure 4 The relationship in

[0066] When pursuing a low-power design for a memory system, several strategies can be employed to minimize energy consumption. Adjusting the threshold voltage (VT) is one method, which involves calibrating the voltage at which a transistor switches from off to on, thus controlling the power consumption during the active and standby modes of the transistor. Another method is to fine-tune the supply voltage (VDD), where reducing the voltage can result in significant power savings, although there is a potential trade-off with performance due to the slower transistor switching speed. In addition to hardware-level adjustments, data compression techniques can also be integrated to improve storage efficiency; for example, run-length encoding and Huffman encoding are methods that can reduce the amount of data to be written to and read from the memory, thereby reducing the total power required for these operations. These data compression methods are particularly effective because they reduce the number of memory accesses, which are often the main consumers of power in a memory system.

[0067] Figure 5 An example method 500 for operating Figure 1 and Figure 2 memory circuit 100 according to some embodiments of the present disclosure is shown in the flowchart. Method 500 can be used to operate memory circuit 100. For example, at least some of the operations described in method 500 can be performed during the write mode or read mode of memory circuit 100. It should be noted that method 500 is only an example and is not intended to limit the embodiments of the present disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after Figure 5 method 500, and some other operations may only be briefly described herein.

[0068] Method 500 begins with an operation in which memory circuit 100 can receive a plurality of data bits. Method 500 continues to operation 502, where memory circuit 100 can identify that a first number of a first subset of a plurality of data bits (e.g., D[S:0]) each equal to a first logic state (e.g., "1") is greater than a second number of a second subset of data bits (e.g., D[S:0]) each equal to a second logic state (e.g., "0"), or greater than a threshold value (e.g., "8"). The first logic state is logic 1, and the second logic state is logic 0. In certain embodiments, method 500 continues to an operation where memory circuit 100 can identify that a first number of a first subset of a plurality of data bits (e.g., D[S:0]) each equal to a first logic state (e.g., "1") is equal to or less than a second number of a second subset of data bits (e.g., D[S:0]) each equal to a second logic state (e.g., "0"), or equal to or less than a threshold value (e.g., "8").

[0069] Method 500 proceeds to operation 504, where memory circuit 100 may logically invert the respective logical states of the data bits. For example, for the data string “1111_0011_1110_0101”, the number of logical “1”s (e.g., the first number) is 11, and the threshold value (e.g., half of the total number of data bits) is 8. In this case, the number of logical “1”s (e.g., 11) is greater than the threshold value (e.g., 8). In response to the first number being greater than the threshold value, data pattern detector 130 may logically invert the respective logical states of the data string “1111_0011_1110_0101” to “0000_1100_0001_1010”. In some embodiments, method 500 proceeds to an operation where memory circuit 100 may maintain the respective logical states of the data bits when the first number is equal to or less than the second number, or equal to or less than the threshold value.

[0070] Method 500 proceeds to an operation where memory circuit 100 may provide a flag bit 131 indicating whether the first number is greater than or less than the threshold value. For example, the flag bit for the inverted data string “0000_1100_0001_1010” may be 1 (e.g., INV_Flag = 1). Additional flag storage and counters may be required. The bit width of the data string used for detection may be adjustable. Write driver 120 may be used to write the selectively adjusted logical states of the data bits (e.g., “0000_1100_0001_1010”) and the flag bit (e.g., INV_Flag = 1) to a plurality of memory bit cells 110. In some embodiments, for the maintained data string, the flag bit may be 0 (e.g., INV_Flag = 0) if the first number is equal to or less than the second number, or equal to or less than the threshold value.

[0071] Method 500 proceeds to operation 506, where memory circuit 100 may write / program the selectively inverted or maintained data and flag bit to memory array 110. In some embodiments, method 500 proceeds to operation 508, where memory circuit 100 may read the inverted or maintained data and flag bit from memory array 110. Method 500 proceeds to an operation where memory circuit 100 may selectively logically invert the read logical state based on the flag bit (e.g., INV_Flag).

[0072] Embodiments of the present disclosure provide a memory macro that is designed to have complex features to optimize power consumption based on data patterns. A first feature involves detecting a data pattern before storing data. For example, if the additional load for standby, read, or write of "0" is greater than that of "1", the memory macro will evaluate the data: if the count of "0" exceeds that of "1", the memory macro will invert the data and set an inversion flag (e.g., INV_FLAG) to 1. Conversely, if there are fewer "0"s, the memory macro will keep the data unchanged and set INV_FLAG to 0. Conversely, if the additional load of "1" is greater than that of "0", the memory macro will invert the data when "1" exceeds "0", again setting INV_FLAG to 1, or keep the data when "1" is in the minority and keep INV_FLAG as 0. A third feature ensures that after reading the data, the memory macro can invert the data pattern by adopting a flag bit (e.g., INV_FLAG). This function allows dynamic adaptation to the most energy-efficient data state, thereby reducing power consumption during various operations of the memory macro.

[0073] In some embodiments, a memory circuit is provided, including: a memory array including a plurality of memory bit cells; a data pattern detector configured to: (i) receive a plurality of data bits; (ii) identify a first number of a first subset of these data bits each equal to a first logic state and a second number of a second subset of these data bits each equal to a second logic state; and (iii) selectively adjust the respective logic states of these data bits based on comparing the first number with the second number; and a write driver configured to write the selectively adjusted logic states of these data bits into these memory bit cells, respectively.

[0074] In some embodiments, the data pattern detector includes a counter, and the counter includes a plurality of adders and at least one comparator.

[0075] In some embodiments, the first logic state is logic 1 and the second logic state is logic 0.

[0076] In some embodiments, the data pattern detector is further configured to: (i) determine the first number; (ii) compare the first number with a threshold value; (iii) in response to the first number being greater than the threshold value, logically invert the respective logic states of these data bits; and (iv) in response to the first number being less than the threshold value, logically maintain the respective logic states of these data bits.

[0077] In some embodiments, the data pattern detector is further configured to determine the threshold value as half of the total number of these data bits.

[0078] In some embodiments, the threshold value is pre-configured to be half of the total number of these data bits.

[0079] In some embodiments, the data pattern detector is further configured to provide a flag bit indicating whether the first number is greater than or less than the threshold value.

[0080] In some embodiments, the memory circuit further includes: a read driver for reading the logical states of these data bits from these memory bit cells; and a plurality of inverters for selectively and logically inverting these read logical states based on the flag bit.

[0081] In some embodiments, when the first number is greater than the threshold value, the flag bit is equal to a first value, and when the first number is less than the threshold value, the flag bit is equal to a second value.

[0082] In some embodiments, these inverters are activated in response to the flag bit being equal to the first value and remain deactivated in response to the flag bit being equal to the second value.

[0083] In some embodiments, there is provided a memory circuit including: a memory array including a plurality of memory bit cells; a data pattern detector configured to: (i) identify that a first number of a first subset of a plurality of data bits each equal to a first logical state is greater than a second number of a second subset of these data bits each equal to a second logical state or greater than a threshold value; and (ii) logically invert the respective logical states of these data bits; and a write driver for writing these logically inverted logical states of these data bits into these memory bit cells respectively.

[0084] In some embodiments, the data pattern detector includes a counter, and the counter includes a plurality of adders and at least one comparator.

[0085] In some embodiments, the first logical state is logic 1 and the second logical state is logic 0.

[0086] In some embodiments, the data pattern detector is further configured to determine the threshold value as half of the total number of these data bits.

[0087] In some embodiments, the threshold value is pre-configured to be half of the total number of these data bits.

[0088] In some embodiments, the data pattern detector is further configured to provide a flag bit indicating whether the first number is greater than or less than the threshold value.

[0089] In some embodiments, the memory circuit further includes: a read driver for reading the logical states of the data bits from the memory bit cells; and a plurality of inverters for selectively and logically inverting the read logical states based on a flag bit.

[0090] In some embodiments, a method of operating a memory circuit is provided, including the steps of: identifying that a first number of a first subset of a plurality of data bits each equal to a first logical state is greater than a second number of a second subset of the data bits each equal to a second logical state or greater than a threshold value; and logically inverting the respective logical states of the plurality of data bits.

[0091] In some embodiments, the first logical state is logic 1 and the second logical state is logic 0.

[0092] In some embodiments, the method of operation further includes the step of: providing a flag bit indicating whether the first number is greater than or less than the threshold value.

[0093] As used herein, the terms "about" and "substantially" generally indicate a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10% to 30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0094] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the disclosed embodiments. Those skilled in the art should appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the disclosed embodiments.

Claims

1. A memory circuit, characterized in that, Comprising: A memory array including a plurality of memory bit cells; A data pattern detector for: (i) receiving a plurality of data bits; (ii) identifying a first number of a first subset of the plurality of data bits each equal to a first logic state and a second number of a second subset of the plurality of data bits each equal to a second logic state; And (iii) selectively adjusting the respective logic states of the plurality of data bits based on comparing the first number with the second number; and A write driver for writing the selectively adjusted logic states of the plurality of data bits into the plurality of memory bit cells respectively.

2. The memory circuit according to claim 1, characterized in that, Wherein the data pattern detector includes a counter, and the counter includes a plurality of adders and at least one comparator.

3. The memory circuit according to claim 1, wherein Wherein the first logic state is a logic 1 and the second logic state is a logic 0, and the data pattern detector is further for: (i) determining the first number; (ii) comparing the first number with a threshold value; (iii) in response to the first number being greater than the threshold value, logically inverting the respective logic states of the plurality of data bits; and (iv) in response to the first number being less than the threshold value, logically maintaining the respective logic states of the plurality of data bits.

4. The memory circuit according to claim 3, wherein Wherein the data pattern detector is further for determining the threshold value as half of a total number of the plurality of data bits.

5. The memory circuit according to claim 3, wherein Wherein the threshold value is pre-configured as half of a total number of the plurality of data bits.

6. The memory circuit as claimed in claim 3, wherein, Wherein the data pattern detector is further for providing a flag bit indicating whether the first number is greater than or less than the threshold value, Wherein the memory circuit further includes: A read driver for reading the respective logic states of the plurality of data bits from the plurality of memory bit cells; and A plurality of inverters for selectively logically inverting the plurality of read logic states based on the flag bit, Wherein when the first number is greater than the threshold value, the flag bit is equal to a first value, and when the first number is less than the threshold value, the flag bit is equal to a second value, Wherein the plurality of inverters are activated in response to the flag bit being equal to the first value and remain deactivated in response to the flag bit being equal to the second value.

7. A memory circuit, characterized in that, Comprising: A memory array including a plurality of memory bit cells; A data pattern detector for: (i) identifying that a first number of a first subset of a plurality of data bits each equal to a first logic state is greater than a second number of a second subset of the plurality of data bits each equal to a second logic state or greater than a threshold value; And (ii) logically inverting the respective logic states of the plurality of data bits; And A write driver for writing the logically inverted logic states of the plurality of data bits into the plurality of memory bit cells respectively.

8. The memory circuit according to claim 7, wherein Wherein the data pattern detector is further for providing a flag bit indicating whether the first number is greater than or less than the threshold value, Wherein the memory circuit further includes: A read driver for reading the logical states of the plurality of data bits from the plurality of memory bit cells; and A plurality of inverters for selectively and logically inverting a plurality of read logical states based on the flag bit.

9. A method for operating a memory circuit, characterized in that, Comprising the steps of: Identifying that a first number of a first subset of the plurality of data bits each equal to a first logical state is greater than a second number of a second subset of the plurality of data bits each equal to a second logical state or greater than a threshold value; and Logically inverting the respective logical states of the plurality of data bits.

10. The operating method according to claim 9, characterized in that, Further comprising the steps of: Providing a flag bit indicating whether the first number is greater than or less than the threshold value.

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