Packaging electronic device and packaging electronic device structure

Abstract

A packaged electronic device and a packaged electronic device structure. A packaged electronic device includes a substrate having a first major surface and an opposing second major surface. The electronic device is attached to the first major surface of the substrate, and the first conductive structure is connected to at least a first portion of the substrate. The dielectric layer covers at least a portion of the first conductive structure. A conductive layer covers the dielectric layer and is connected to the second portion of the substrate. The first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure, and are further configured to enclose one or more of an enclosure structure or a reinforcement structure of the electronic device.

Description

[0001] This case is a divisional application of a patent application for an encapsulated electronic device and an encapsulated electronic device structure, with an application date of December 06, 2019, a priority date of December 12, 2018, an application number of 201911238383.5, and an invention title of Encapsulated Electronic Device and Encapsulated Electronic Device Structure. Technical Field

[0002] The present disclosure generally relates to electronic devices, and more particularly to semiconductor packages, their structures, and methods of forming semiconductor packages. Background Art

[0003] Existing semiconductor packages and methods for forming semiconductor packages have deficiencies, such as excessive cost, poor thermal performance, reduced reliability, relatively low performance, or large package size. For those skilled in the art, additional limitations and disadvantages of such methods will become apparent by comparing conventional and traditional methods with the present disclosure and referring to the accompanying drawings.

[0004] More specifically, some semiconductor packages contain a combination of passive components and one or more semiconductor dies. In the past, passive components such as capacitors were mounted on a package substrate adjacent to a semiconductor die laterally, and the semiconductor die was also mounted to the package substrate. This conventional assembly method consumes valuable substrate space and significantly increases the overall size of the semiconductor package. Next-generation semiconductor packages will require a significant increase in the total capacitance value per package, which will greatly increase the size of such packages formed using conventional assembly methods.

[0005] Therefore, it is desirable to have a package structure and method for an encapsulated electronic device that overcomes the disadvantages of the prior art. It is also desirable to make the structure and method easily incorporated into the manufacturing process, adaptable to multiple die interconnect schemes, and cost-effective. Summary of the Invention

[0006] This specification includes, among other features, an encapsulated electronic device structure and an associated method. The encapsulated electronic device structure includes one or more capacitor structures embedded within or as part of a lid or reinforcement component. In some instances, 3D printing technology is used to provide one or more portions of the capacitor structure. The structure and method provide one or more higher-capacity capacitors, which reduce the bill of materials count and increase the assembly yield, for example, by reducing the package size. In some instances, this specification provides a capacitance structure that replaces a lid area of every 25 square millimeters (mm 2 ) with a 0201 capacitor. For example, a 65 mm × 65 mm lid according to this specification can provide an equivalent capacitance of approximately 170 0201 capacitors, and the required substrate space is less than that required for so many 0201 capacitors.

[0007] More specifically, in one example, a method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposite second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer covering at least a portion of the first conductive structure. The method includes forming a conductive layer covering the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure of the packaged electronic device.

[0008] In another example, a method for forming a packaged electronic device includes providing a substrate. The method includes electrically coupling an electronic device to the substrate; providing a first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate. The method includes providing a dielectric structure covering at least a portion of the upper surface of the first conductive structure. The method includes providing a conductive layer covering the dielectric structure and coupled to a second portion of the substrate such that the conductive layer has a first portion overlapping the dielectric structure and is coupled to the second portion of the substrate, wherein the first conductive structure, the dielectric structure, and the conductive layer include a capacitor structure. In one example, the first conductive structure includes a lid structure configured to cover an enclosure structure of the electronic device. In another example, the first conductive structure, the dielectric structure, and the conductive structure are configured as a reinforcement structure of the packaged electronic device.

[0009] In yet another example, a packaged electronic device structure includes a substrate and an electronic device electrically coupled to the substrate. A first conductive structure is coupled to at least a first portion of the substrate, and a dielectric structure covers at least a portion of the first conductive structure. A conductive layer covers the dielectric layer and is coupled to a second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure.

[0010] In another example, a packaged electronic device includes: a substrate having a first major surface and an opposite second major surface; an electronic device attached to the first major surface of the substrate; a first conductive structure coupled to at least a first portion of the substrate; a dielectric layer covering at least a portion of the first conductive structure; and a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an encapsulation structure or a reinforcement structure of the packaged electronic device. Further, the first conductive structure includes a lid structure attached to the substrate such that the lid structure encapsulates the electronic device; and the dielectric layer is located on an upper surface of the lid structure. Further, the lid structure is attached to a conductive pattern that is part of the substrate; and the conductive layer is coupled to the substrate using a second conductive structure. Further, the lid structure is attached to the electronic device via an attachment layer. Further, the attachment layer includes a 3D printed layer. Further, the lid structure includes fin structures extending outwardly from an outer surface of the lid structure. Further, the dielectric layer includes a 3D printed layer. Further, the dielectric layer includes one or more of alumina, zirconia, or hafnium dioxide; and the thickness of the dielectric layer is in the range of about 2 microns to about 5 microns. Further, the packaged electronic device further includes a second conductive structure adjacent to the substrate, wherein: the conductive layer is attached to the second conductive structure; the conductive layer includes a 3D printed layer; and the conductive layer spans a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. Further, the first conductive structure, the dielectric layer, and the conductive layer include the capacitor structure and the reinforcement structure of the packaged electronic device; and at least two of the first conductive structure, the dielectric layer, and the conductive layer are 3D printed layers.

[0011] In another example, an encapsulated electronic device includes: a substrate; an electronic device electrically coupled to the substrate; a first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate; a dielectric structure covering at least a portion of the upper surface of the first conductive structure; and a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, such that the conductive layer has a first portion overlapping the dielectric layer and is coupled to the second portion of the substrate, wherein: the first conductive structure, the dielectric layer, and the conductive layer define a capacitor structure. Further, the first conductive structure includes a lid structure coupled to the substrate such that the lid structure encloses the electronic device; the dielectric layer is located above the upper surface of the lid structure; the conductive layer is coupled to the substrate using a second conductive structure; and the conductive layer includes a third portion overlapping a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. Further, the first conductive structure includes a lid structure coupled to the substrate such that the lid structure encloses the electronic device; and the lid structure includes fin structures extending outward from an outer surface of the lid structure. Further, the dielectric layer includes a 3D printed dielectric layer; the dielectric layer includes one or more of alumina, zirconia, or hafnium dioxide; and the thickness of the dielectric layer is in the range of 2 to 5 microns. Further, the first conductive structure, the dielectric layer, and the conductive layer further include a strengthening structure for the encapsulated electronic device; the conductive layer does not overlap the electronic device in a cross-sectional view; and at least one of the first conductive structure, the dielectric layer, or the conductive layer includes a 3D printed layer.

[0012] In another example, an encapsulated electronic device structure includes: a substrate; an electronic device electrically coupled to the substrate;

[0013] A lid structure coupled to at least a first portion of the substrate; a dielectric structure covering at least a portion of the first conductive structure; a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, wherein: the lid structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an encapsulation structure or a reinforcement structure. Further, the lid structure is attached to the substrate such that the lid structure encapsulates the electronic device. Further, the lid structure includes fin structures extending outwardly from an outer surface of the lid structure. Further, the dielectric layer includes a 3D printed dielectric layer; the dielectric layer includes one or more of alumina, zirconia, or hafnium dioxide; and the thickness of the dielectric layer is in the range of 2 microns to 5 microns. Further, the first conductive structure, the dielectric layer, and the conductive layer further include a reinforcement structure for encapsulating the electronic device.

[0014] Other examples are included in this disclosure. Such examples may be present in the figures, claims, and / or description of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A cross-sectional view of an example encapsulated electronic device of this specification is illustrated;

[0016] Figure 2 is a flowchart of an example method of forming an encapsulated electronic device of this specification;

[0017] Figures 3-6 Cross-sectional views of an encapsulated electronic device in various manufacturing stages in accordance with this specification are illustrated;

[0018] Figure 7 A cross-sectional view of an example encapsulated electronic device of this specification is illustrated; and

[0019] Figure 8 A cross-sectional view of an example encapsulated electronic device of this specification is illustrated.

[0020] For simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale, and like reference numerals in different figures indicate like elements. Additionally, to simplify the description, the description and details of well-known steps and elements are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Additionally, the terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the disclosure. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, quantities, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or groups thereof. It should be understood that although the terms "first", "second", etc. may be used herein to describe various members, elements, regions, layers, and / or sections, these members, elements, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer, and / or section from another. Thus, for example, without departing from the teachings of the disclosure, the first member, first element, first region, first layer, and / or first section discussed below may be referred to as a second member, second element, second region, second layer, and / or second section. References to "one example" or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one example of the invention. Thus, the phrases "in one example" or "in an example" that appear in various places in this specification are not necessarily all referring to the same example, but in some cases they may. Additionally, in one or more example embodiments, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art. Additionally, the term "while" means that an action occurs at least during a portion of the duration of the initiating action. The use of the words "about", "approximately", or "substantially" means that the value of the element is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent the value or position from being stated exactly. Unless otherwise specified, as used herein, the words "above" or "on" include the orientation, placement, or relationship in which the specified element may be in direct or indirect physical contact. It should be further understood that the examples described and illustrated below may have examples and / or may be practiced in the absence of any elements not specifically disclosed herein. Detailed Description

[0021] Figure 1Illustrated is a cross-sectional view of an encapsulated electronic device 10 (such as an encapsulated semiconductor device 10) in accordance with an example of the present specification. Although the example is illustrated as a semiconductor device structure in a ball grid array (BGA) package, the present specification is not limited to such a package. In Figure 1 In the illustrated example, the encapsulated semiconductor device 10 includes a substrate 11, an electronic component 16 (such as a semiconductor device 16), a protective layer 17, an attachment material 18, conductive interconnect structures 19 and 21, and a capacitor structure 31. In accordance with the present specification and this example, the capacitor structure 31 is configured not only as a capacitive device but also as a structure that encapsulates and protects the semiconductor device 16.

[0022] The conductive interconnect structures 19 and 21, the substrate 11, the protective layer 17, the attachment material 18, and the capacitor structure 31 may be referred to as a semiconductor package 190, and the package 190 may protect the semiconductor device 16 from external elements and / or environmental exposure. Additionally, the semiconductor package 190 may provide electrical coupling of external electronic components (not shown) to the conductive interconnect structures 19 and the semiconductor device 16.

[0023] The semiconductor device 16 may be attached to the capacitor structure 31 by an attachment material 18, which may be an insulating material, a thermally and electrically conductive material, or a thermally conductive but non-conductive material. In some examples, the attachment material 18 includes a dielectric material such as alumina, zirconia, hafnium dioxide, or similar materials known to those skilled in the art. The semiconductor device 16 may be further electrically connected to the substrate 11 using an interconnect structure 19, which may include solder balls, solder bumps, copper bumps, nickel-gold bumps, or similar materials known to those of ordinary skill in the art. The protective layer 17 may comprise an underfill material configured to reduce the level of interconnect strain generated through the conductive interconnect structure 19. Such materials may comprise a mixture of a liquid organic resin binder and inorganic fillers and may be formed using, for example, capillary dispensing techniques.

[0024] The substrate 11 may be selected from common circuit boards (e.g., rigid circuit boards and flexible circuit boards), multi-layer substrates, laminated substrates, core substrates with stacked layers, coreless substrates, ceramic substrates, lead frame substrates, molded lead frame substrates, or similar substrates known to those of ordinary skill in the art. In this regard, the present specification is not intended to be limited to any particular type of substrate 11. By way of example and not limitation, the substrate 11 may comprise an insulating structure 114 having opposing generally planar top and bottom surfaces. It should be understood that multiple insulating layer portions may be used to provide the insulating structure 114. A conductive pattern 112 or conductive pattern layer 112 may be disposed near the top surface of the insulating structure 114, and conductive pads 113 may be disposed near the bottom surface of the insulating structure 114.

[0025] The conductive pattern 112 and the conductive pad 113 are electrically interconnected with each other in a prescribed pattern or arrangement using a conductive interconnect path 111 extending from the conductive pattern 112 through the insulating structure 114 to the conductive pad 113 defined by a portion of one or more conductive layers. The conductive pattern 112, the conductive pad 113, and the conductive interconnect layer 111 comprise a conductive material, such as one or more metals. In some examples, the conductive pattern 112, the conductive pad 113, and the conductive interconnect layer 111 comprise copper. In some examples, a solder mask 115 may be provided near at least a plurality of portions of the conductive pattern 112 and the top surface of the insulating structure 114. Additionally, in some examples, a solder mask 116 may be provided on at least a plurality of portions of the pad 113 and the bottom surface of the insulating structure 114. The solder mask 115 is used to protect portions of the conductive pattern 112 that would be prone to electrical short circuit problems. The solder mask 116 is used to protect portions of the pad 113 that would be exposed to the surrounding environment.

[0026] The semiconductor device 16 may be attached to a portion of the conductive pattern 112 in a flip-chip configuration through the conductive interconnect structure 19. In other examples, the semiconductor device 16 may be attached to the substrate 11 in a device active area up (or die up) configuration, and the semiconductor device 16 may be electrically connected to the conductive pattern 112 using wire bonding. In some examples, a conductive interconnect structure 21 may be attached to the conductive pad 113 and may comprise a conductive material, such as a solder ball, a solder bump, a copper bump, a nickel-gold bump, or similar materials known to those of ordinary skill in the art. In other examples, the conductive pad 113 may be configured to be directly connected or attached to a next-level assembly, such as a printed circuit board.

[0027] In some examples, the semiconductor device 16 is an integrated circuit device, a power semiconductor device, an optical device, any type of sensor device, or other devices known to those of skill in the art. Those of ordinary skill in the art should understand that the semiconductor device 16 is illustrated in a simplified form and may further include a plurality of diffusion regions, a plurality of conductive layers, and a plurality of dielectric layers.

[0028] According to this example, the capacitor structure 31 includes a lid structure 310, a cap structure 310, a first conductive structure 310, a first conductive layer 310, an electrode layer 310, or an encapsulation structure 310 that contains a conductive material such as metal. In some examples, the lid structure 310 includes copper; aluminum; a metal alloy material such as ASTM-F15 alloy (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; a clad material such as aluminum-copper; a metal-coated ceramic material; or other similar materials known to those of ordinary skill in the art. In some examples, the lid structure 310 can be attached to the conductive pattern 112 using an attachment layer 311, which can include a conductive material such as a welding material, an adhesive, an epoxy resin, or similar materials known to those of ordinary skill in the art. In some examples, the lid structure 310 can be provided using stamping, punching, drawing, etching, laser micromachining, and / or electroplating techniques.

[0029] Additionally, the capacitor structure 31 includes a dielectric layer 314, a dielectric structure 314, or a dielectric region 314 that is disposed to cover the upper surface of the lid structure 310. In some examples, the dielectric layer 314 includes an oxide material such as alumina, zirconia, hafnium dioxide, or other similar materials known to those of ordinary skill in the art. In one example, the dielectric layer 314 can be zirconia in a polymer suspension (e.g., polyvinylpyrrolidone (PVP)), and its thickness can be in the range of about 2 microns to about 5 microns.

[0030] In some examples, the dielectric layer 314 is provided using 3D printing technology, which generally refers to a method of forming an object using an additive process based on a digitally created file of a three-dimensional object. More specifically, the object can be produced by continuously laying down multiple thin layers of material using a 3D printing device. Examples of types of 3D printing include metal printing such as selective laser melting (SLM) and electron beam melting (EBM); selective laser sintering (SLS); jetting processes; stereolithography (SLA); and fused deposition modeling (FDM). In other examples, the dielectric layer 314 can be formed using deposition, coating, or screen printing techniques. In additional examples, the dielectric layer 314 can include one or more layers comprising different materials. In some examples, the lid structure 310 can also be formed using 3D printing technology.

[0031] The capacitor structure 31 further includes a conductive electrode layer 317, a top electrode layer 317, or a second conductive layer 317 disposed to cover the dielectric layer 314, such as the upper surface or outer surface of the dielectric layer 314. In some examples, the conductive layer 317 includes one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some examples, a conductive stud structure 318, a conductive structure 318, or a conductive structure 318 can be used to connect or attach the conductive layer 317 to the substrate 11. In some examples, the conductive structure 318 is attached to a portion of the conductive pattern 112 of the substrate 11, such as Figure 1 generally illustrated, and can include materials similar to the conductive layer 317. The conductive structure 318 is configured to provide an attachment location or a stand-off structure for the conductive layer 317. The conductive structure 318 can be formed or disposed directly onto the conductive pattern 112, such as by 3D printing, without an intermediate attachment layer, as Figure 1 generally illustrated. In other examples, the conductive structure 318 can be attached to the substrate 11 using an attachment layer 311.

[0032] In some examples, the conductive layer 317 is provided using 3D printing. In an example, the conductive layer 317 is arranged such that it overlaps with an air gap 56 that can be less than about 50 micrometers and is located between the outer edge of the lid structure 310 and / or the dielectric layer 314 and the inner edge of the conductive structure 318. In another example, the gap 56 is less than about 30 micrometers. The size of the gap 56 is particularly suitable for allowing the use of 3D printing techniques that can allow spanning the void to some extent. In other examples, the conductive layer 317 is provided in the form of an external lid structure that incorporates connection structures for attaching the external lid structure to the substrate 11. There can be examples where the conductive structure 318 can be formed in the same process or steps as the conductive layer 317, and / or the conductive structure 318 can be integral with and / or include a portion of the conductive layer 317.

[0033] According to this example, the capacitor structure 31 is configured as a parallel plate capacitor, where the resistance value depends on the area of the plates (i.e., the overlapping area of the conductive layer 317 and the lid structure 310), as well as the thickness of the dielectric layer 314 (i.e., the distance between the conductive layer 317 and the lid structure 310) and the relative dielectric constant. By providing the capacitor structure 31 configured according to this specification, the packaged semiconductor device 10 can have a high capacitance without increasing the lateral size of the substrate 11 as in previous devices. Another advantage of the capacitor structure 31 is that it is provided in a structure that can provide a capacitor function, an EMI (electromagnetic interference) shielding function, and / or a protection function by enclosing the semiconductor device 16. More specifically, the capacitor structure 31 is configured as both a capacitor structure and an enclosure structure that encloses the semiconductor device 16.

[0034] Figure 2 is a flowchart illustrating an example method 200 for manufacturing a packaged semiconductor device 10 according to this specification, and Figures 3-6 illustrates cross-sectional views of the packaged semiconductor device 10 at various manufacturing stages according to Figure 2 In block S10, a semiconductor device sub-assembly is provided, which includes a substrate and a semiconductor device attached to the surface of the substrate. In block S20, a first conductive structure is attached to the semiconductor sub-assembly, such as the substrate.

[0035] Figure 3 illustrates the packaged semiconductor device 10 at a certain manufacturing stage and further illustrates Figure 2 examples of block S10 and block S20 of Figure 1 The substrate of the semiconductor device sub-assembly 201 can be similar to Figure 1The semiconductor device 16 (or its variant) in []. In one example, the semiconductor device 16 can be attached to the conductive pattern 112 on the substrate 11 using the interconnect structure 19. The interconnect structure 19 can include solder bumps, metal bumps (such as silver bumps, gold bumps, or copper bumps), or other conductive structures known to those of ordinary skill in the art. In this example, the protective layer 17 can be added before or after attaching the semiconductor device 16 to the substrate 11, such that the protective layer 17 is interposed between the semiconductor device 16 and the substrate 11. In some examples, the protective layer 17 can be formed using capillary dispensing techniques and can include materials such as a mixture of a liquid organic resin adhesive and an inorganic filler. In some examples, the protective layer 17 can contain a flux material for assisting the reflow process of the interconnect structure 19. In some examples, the conductive interconnect structure 21 can be attached to the conductive pad 13. The conductive interconnect structure 21 can be a metal bump, including a solder bump, or other conductive structures known to those of ordinary skill in the art. In other examples, the conductive interconnect structure 21 can be absent, and the conductive pad 113 can be configured to be attached to the next-level assembly.

[0036] According to block S20 of method 200, a first conductive structure such as the lid structure 310 is attached to the substrate 11, and in some examples, the first conductive structure is further attached to the semiconductor device 16 using the attachment material 18. In some examples, the lid structure 310 includes copper; aluminum; a metal alloy material such as ASTM-F15 alloy (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; a clad material such as aluminum-copper; a metal-coated ceramic material; or other similar materials known to those of ordinary skill in the art. In one example, the attachment material 18 can be formed using 3D printing techniques (e.g., 3D printing onto the semiconductor device 16 or the lid structure 310) and can include a dielectric material such as alumina, zirconia, hafnium dioxide, or similar materials known to those skilled in the art. In some examples, the lid structure 310 is electrically connected to a portion of the conductive pattern 112 of the substrate 11 using, for example, the attachment layer 311, which can include a conductive material such as a soldering material, an adhesive, an epoxy resin, or similar materials known to those of ordinary skill in the art. In some examples, the lid structure 310 can be electrically connected to the semiconductor device 16 through the conductive pattern 112. In the same or other examples, the lid structure 310 can be electrically connected to an external device through the conductive pattern 112, the conductive interconnect layer 111, the conductive pad 113, and the conductive interconnect structure 21.

[0037] Method 200 further includes block S30 of forming a dielectric layer that covers the upper surface of the first conductive structure. Figure 4Illustrated is the packaged semiconductor device 10 after processing of block S30 of method 200. In some instances, subassembly 201 having lid structure 310 is placed within a 3D printing device, and a dielectric layer 314 is provided that covers an upper or outer surface 310A of lid structure 310. In some instances, dielectric layer 314 includes an oxide material such as alumina, zirconia, hafnium dioxide, or similar materials known to those of ordinary skill in the art. In one instance, dielectric layer 314 can be zirconia in a polymer suspension (e.g., PVP), and its thickness can be in the range of about 2 microns to about 5 microns. In other instances, dielectric layer 314 can be formed using deposition, coating, or screen printing techniques. In additional instances, dielectric layer 314 can include one or more different material layers. In some instances, dielectric layer 314 can further extend to cover a portion of a lower sidewall of lid structure 310. In the same or other instances, dielectric layer 314 can further extend to reach a top surface of substrate 11.

[0038] Method 200 includes block S40 of forming a second conductive structure on a semiconductor device subassembly such as a substrate. Figure 5 Illustrated is the packaged semiconductor device 10 after processing of block S40 of method 200. In some instances, the second conductive structure of block S40 can include Figure 1 conductive structure 318 that can be formed on a portion of substrate 11 and is laterally spaced apart from semiconductor device 16. In some instances, conductive structure 318 is a continuous structure that laterally encloses semiconductor device 16 without interruption or break. In one instance, conductive structure 318 is formed using 3D printing techniques and can include one or more metal materials such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some instances, conductive structure 318 is electrically connected to another portion of conductive pattern 112 of substrate 11 and can be electrically connected to semiconductor device 16 and / or to an external device through conductive pattern 112, conductive interconnect layer 111, conductive pad 113, and conductive interconnect structure 21.

[0039] Method 200 includes block S50 of forming a conductive layer that is located over the dielectric layer and connected to the second conductive structure. Figure 6 Illustrated is the packaged semiconductor device 10 after processing of block S50 of method 200. The conductive layer of block S50 can include Figure 1The conductive layer 317. In some instances, the conductive layer 317 includes one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. The conductive layer 317 may include one or more sub-layers composed of any such one or more metal materials stacked on top of each other. In some instances, the conductive layer 317 is provided using 3D printing. In one instance, the conductive layer 317 is arranged such that it overlaps with the air gap 56, which may be less than or equal to about 50 microns. In another instance, the gap 56 is less than or equal to about 30 microns. In one instance, both the conductive structure 318 and the conductive layer 317 are provided in the form of an integral structure using a single 3D printing step.

[0040] According to method 200, the packaged semiconductor device 10 is provided with a capacitor structure 31, which includes a lid structure 310, a dielectric layer 314, and a conductive layer 317. In some instances of method 200, one or more (including all) of the attachment layer 18, the dielectric layer 314, the conductive structure 318, and the conductive layer 317 are provided using 3D printing technology.

[0041] Figure 7 A cross-sectional view of an exemplary packaged electronic device 70 (such as a packaged semiconductor device 70) is illustrated. The packaged semiconductor device 70 is another example of the semiconductor package 190 according to this specification. The packaged semiconductor device 70 is similar to the packaged semiconductor device 10, and only the differences will be described below. The packaged semiconductor device 70 includes a capacitor structure 71, which is different from Figure 1 the capacitor structure 31 of the packaged semiconductor device 10 illustrated in. According to this specification, the capacitor structure 71 includes a lid structure 710 including one or more fin structures 710A, a cap structure 710, a first conductive layer 710, an electrode layer 710, or an enclosure structure 710, and the fin structures extend outward from the outer surface 710B of the lid structure 710. The fin structure 710A is configured to provide a capacitor structure 71 with an increased conductive plate surface area and thus a structure with a higher capacitance without increasing the lateral dimensions. The number of fins can be increased or decreased according to the desired capacitance value.

[0042] Similar to the lid structure 310, the lid structure 710 includes a conductive material such as a metal. In some instances, the lid structure 710 includes copper; aluminum; a metal alloy material, such as ASTM-F15 alloy (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; a clad material, such as aluminum-copper; a metal-coated ceramic material; or other similar materials known to those of ordinary skill in the art.

[0043] In addition, the capacitor structure 71 further includes a dielectric layer 714, dielectric structure 714, or dielectric region 714 disposed to cover a lid structure 710 that includes fin structures 710A. That is, the dielectric layer 714 conforms to the shape of the lid structure 710. The dielectric layer 714 may include materials similar to those described previously for the dielectric layer 314 of the packaged semiconductor device 10. In an example, the dielectric layer 714 is formed using 3D printing techniques.

[0044] The capacitor structure 71 further includes a conductive electrode layer 717, top electrode layer 717, or second conductive layer 717 disposed to cover the dielectric layer 714 and the lid structure 710 that includes fin structures. That is, the conductive layer 717 conforms to the shape of the dielectric layer 714 and the lid structure 710. The conductive layer 717 may include materials similar to those described previously for the conductive layer 317 of the packaged semiconductor device 10. Similar to the capacitor structure 31, the conductive layer 717 may be connected or attached to the substrate 11 using a conductive structure 318. In an example, the conductive layer 717 is formed using 3D printing techniques. In the same or other examples, the conductive layer 717 is arranged such that it overlaps with an air gap 56, which may be less than or equal to about 50 micrometers. In another example, the gap 56 is less than or equal to about 30 micrometers. These dimensions are suitable for 3D printing techniques that may allow for spanning the void to some extent when forming the conductive layer 717.

[0045] Figure 2 The method 200 described in may be used to form the packaged semiconductor device 70. By way of example, the first conductive structure of block S20 may be the lid structure 710 having one or more fin structures 710A; the dielectric layer of block S30 may be the dielectric layer 714; the second conductive structure of block S40 may be the conductive structure 318; and the conductive layer of block S50 may be the conductive layer 717.

[0046] Figure 8 A cross-sectional view of an example packaged electronic device 80 (such as a packaged semiconductor device 80) is illustrated. The packaged semiconductor device 80 is another example of the semiconductor package 190 according to this specification. The packaged semiconductor device 80 is similar to the packaged semiconductor device 10, and only the differences will be described below. The packaged semiconductor device 80 includes a capacitor structure 81 that is different from the capacitor structure 31 of the packaged semiconductor device 10. According to this specification, the capacitor structure 81 is configured as a reinforcement structure or reinforcement ring structure for the substrate 11.

[0047] In some examples, in such as Figure 8In the cross-sectional view generally described, the capacitor structure 81 is disposed on the substrate 11 at a peripheral position laterally separated from the side edge of the semiconductor device 16. More specifically, the capacitor structure 81 can be configured as a continuous annular structure that laterally encloses the semiconductor device 16 without breaks or interruptions. The capacitor structure 81 includes a conductive layer 810, a first conductive structure 810, a first conductive electrode structure 810, or a conductive structure 810. In some instances, the conductive structure 810 can provide a strengthening structural property to the substrate 11 and can include one or more metallic materials such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some instances, the conductive structure 810 can be attached to the conductive pattern 112 using an attachment layer 311, which can include a conductive material such as a solder material, an adhesive, an epoxy resin, or similar materials known to those of ordinary skill in the art. In one instance, the conductive structure 810 is formed using 3D printing technology. In other instances, the conductive structure 810 can be formed using electroplating, evaporation, sputtering, or other deposition techniques. In additional instances, the conductive structure can be directly disposed on the conductive pattern 112 without an intermediate attachment layer. One difference between the conductive structure 810 and the conductive structure 310 is that the conductive structure 810 is configured not to laterally overlap any part of the semiconductor device, while the conductive structure 310 completely laterally overlaps the semiconductor device 16.

[0048] The capacitor structure 81 further includes a dielectric layer 814, a dielectric structure 814, or a dielectric region 814 that is disposed to cover the upper surface of the conductive structure 810. In some instances, the dielectric layer 814 includes an oxide material such as aluminum oxide, zirconium oxide, hafnium dioxide, or other similar materials known to those of ordinary skill in the art. In one instance, the dielectric layer 814 can be zirconium oxide in a polymer suspension (e.g., polyvinylpyrrolidone (PVP)), and its thickness can be in the range of about 2 microns to about 5 microns. In one instance, the dielectric layer 814 is formed using 3D printing technology. In other instances, the dielectric layer 814 can be formed using deposition, coating, or screen printing techniques. In additional instances, the dielectric layer 814 can include one or more different material layers.

[0049] The capacitor structure 81 further includes a conductive electrode layer 817, a top electrode layer 817, or a second conductive layer 817 that is disposed to cover the dielectric layer 814. In some instances, the conductive layer 817 includes one or more metallic materials such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some instances, the conductive layer 817 can be connected or attached to the substrate 11 using a conductive stud structure 818 or a conductive structure 818. In some instances, the conductive structure 818 is attached to a portion of the conductive pattern 112, such as Figure 8is generally described and may include materials similar to conductive layer 817. The conductive structure 818 may be attached to the substrate 11 through the attachment layer 311. In other examples, the conductive structure 818 may be directly disposed on the conductive pattern 112 without an intermediate attachment layer. In some examples, the conductive layer 817 and the conductive structure 818 are formed using 3D printing technology. In the same or other examples, the conductive layer 817 is arranged such that it overlaps with the air gap 856, which may be less than about 50 micrometers. In another example, the gap 856 is less than about 30 micrometers. The size of the gap 856 is suitable for the 3D printing technology, which may allow a specific span of voids when forming the conductive layer 817. Although this example shows the conductive structure 818 located above the substrate 11 inside the conductive structure 810, there may be examples where this relationship is reversed, for example, to allow adjustment of the strengthening effect of the capacitor structure 81 on the substrate 11.

[0050] As Figure 8 generally described, the conductive layer 817 includes: a first portion 817A, which in a cross-sectional view directly laterally overlaps with the dielectric layer 814 and the conductive structure 810; a second portion 817B, which in a cross-sectional view overlaps with the air gap 856; and further includes a third portion 817C, which in a cross-sectional view laterally overlaps with the conductive structure 818. In other examples, the conductive layer 817 and the conductive structure 818 may be a single component or an integrated structure. In additional examples, the packaged semiconductor device 80 may include a package body that includes, for example, a encapsulation material that encapsulates at least the semiconductor device 16.

[0051] According to this specification, the capacitor structure 81 provides multiple functions including a capacitance function and a strengthening function for the packaged semiconductor device 80. This allows a packaged semiconductor device using a separate strengthening structure and capacitor to have more functions in a smaller package space because the additional capacitance structure that occupied space on the substrate 11 in previous devices can be replaced by the capacitor structure 81 that also provides the function of the strengthening structure. In other examples, the capacitor structure 81 may be combined with the capacitor structure 31 or the capacitor structure 71 in a packaged electronic device.

[0052] Figure 2 The method 200 described in may be used to form the packaged semiconductor device 80. By way of example, the first conductive structure in block S20 may be the conductive structure 810; the dielectric layer in block S30 may be the dielectric layer 814; the second conductive structure in block S40 may be the conductive structure 818; and the conductive layer in block S50 may be the conductive layer 817.

[0053] In summary, those of ordinary skill in the art can determine that, according to one example, a method for forming a packaged semiconductor device includes: providing a substrate having a first major surface and an opposite second major surface; attaching an electronic device to the first major surface of the substrate; providing a first conductive structure coupled to at least a first portion of the substrate; forming a dielectric layer covering at least a portion of the first conductive structure; and forming a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an encapsulation structure or a reinforcement structure for encapsulating the electronic device.

[0054] In another example, providing the first conductive structure includes attaching a lid structure to the substrate such that the lid structure encapsulates the electronic device; and forming the dielectric layer includes forming the dielectric layer on an upper surface of the lid structure. In yet another example, attaching the lid structure includes attaching the lid structure to a conductive pattern provided in the form of a portion of the substrate; and forming the conductive layer includes coupling the conductive layer to the substrate using a second conductive structure. In still yet another example, attaching the lid structure further includes attaching the lid structure to the electronic device via an attachment layer.

[0055] In another example, the method includes using 3D printing to form the attachment layer over at least a portion of the electronic device; and attaching the lid structure to the attachment layer. In yet another example, attaching the lid structure includes attaching the lid structure including a fin structure that extends outwardly from an outer surface of the lid structure. In still yet another example, forming the dielectric layer includes 3D printing the dielectric layer. In another example, the dielectric layer includes one or more of aluminum oxide, zirconium oxide, or hafnium dioxide; and the thickness of the dielectric layer is in the range of about 2 microns to about 5 microns. In yet another example, the method further includes forming a second conductive structure adjacent to the substrate; forming the conductive layer includes attaching the conductive layer to the second conductive structure; forming the conductive layer includes 3D printing the conductive layer; and the conductive layer spans a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. In still yet another example, the first conductive structure, the dielectric layer, and the conductive layer include the capacitor structure and the reinforcement structure for encapsulating the electronic device; and at least two of the first conductive structure, the dielectric layer, and the conductive layer are formed using 3D printing.

[0056] In summary, those of ordinary skill in the art can determine that, according to one example, a method for forming a packaged electronic device may include providing a substrate; electrically coupling an electronic device to the substrate; providing a first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate; providing a dielectric structure covering at least a portion of the upper surface of the first conductive structure; and providing a conductive layer covering the dielectric layer and coupled to a second portion of the substrate such that the conductive layer has a first portion overlapping the dielectric layer and coupled to the second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer define a capacitor structure.

[0057] In another example, providing the first conductive structure may include attaching a lid structure to the substrate such that the lid structure encloses the electronic device; providing the dielectric layer may include providing the dielectric layer on an upper surface of the lid structure; providing the conductive layer may include providing the conductive layer coupled to the substrate using a second conductive structure; and the conductive layer may include a third portion overlapping a gap of less than about 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. In still another example, providing the first conductive structure may include attaching a lid structure to the substrate such that the lid structure encloses the electronic device. In yet another example, attaching the lid structure may include attaching the lid structure including a fin structure extending outward from an outer surface of the lid structure. In another example, providing the dielectric layer may include 3D printing the dielectric layer. In another example, the dielectric layer may include one or more of alumina, zirconia, or hafnium dioxide. In still another example, the thickness of the dielectric layer may be in the range of about 2 microns to about 5 microns. In another example, the first conductive structure, the dielectric layer, and the conductive layer may further include a reinforcing structure for the packaged electronic device. In another example, the conductive layer does not overlap the electronic device in a cross-sectional view. In another example, at least one of the first conductive structure, the dielectric layer, or the conductive layer is formed using 3D printing.

[0058] In summary, methods for forming encapsulated electronic devices and related encapsulated electronic device structures including capacitor structures are disclosed. In one example, the capacitor structure is configured as part of a conductive lid structure. In another example, the capacitor structure is part of a reinforcement structure. According to one method, one or more portions of the capacitor structure are formed using 3D printing techniques. The structures and methods provide one or more higher-capacity capacitors, which reduce the bill of materials count and increase the assembly yield rate, for example, by reducing the package size. In some examples, this specification provides for replacing the lid area per 25 mm 2 with the capacitance structure of a 0201 capacitor. For example, a 65 mm × 65 mm lid according to this specification can provide an equivalent capacitance of approximately 170 0201 capacitors, and the substrate space required is less than that required for that many 0201 capacitors.

[0059] Although the subject matter of the present invention has been described using specific example steps and example embodiments, the foregoing drawings and description of the drawings depict only typical examples of the subject matter and should not be considered to limit its scope. It is apparent that many alternatives and variations will be apparent to those skilled in the art. By way of example, multiple electronic devices can be attached to pads in a side-by-side configuration, a stacked configuration, a combination thereof, or other configurations known to those skilled in the art.

[0060] As reflected in the following claims, inventive aspects may lie in less than all of the features of a single foregoing disclosed example. Accordingly, the claims set forth below are hereby expressly incorporated into this detailed description, where each claim stands on its own as a separate example of the present invention. Moreover, although some of the examples described herein include some but not other features included in other examples, as will be understood by those skilled in the art, combinations of features of different examples are intended to be within the scope of the present invention and are intended to form different examples.

Claims

1. An encapsulated electronic device, comprising: A substrate; An electronic device, the electronic device being coupled to the substrate, the electronic device including an edge; A single-component lid structure, the single-component lid structure being coupled to the substrate and to the electronic device by an attachment material, the single-component lid structure including a conductive structure having a top portion and a side portion, the side portion extending from the top portion, wherein: The single-component lid structure forms an enclosure structure that vertically and horizontally encloses the electronic device; And A dielectric structure, the dielectric structure being above the single-component lid structure; And A conductive structure, the conductive structure being above the dielectric structure and coupled to the substrate, wherein: The single-component lid structure forms a first capacitor plate; The dielectric structure forms a capacitor dielectric; The conductive structure forms a second capacitor plate; and The first capacitor plate, the capacitor dielectric, and the second capacitor plate form a capacitor structure for the encapsulated electronic device.

2. The encapsulated electronic device according to claim 1, wherein: The side portion includes a continuous portion that laterally encloses the edge of the electronic device without break.

3. The encapsulated electronic device according to claim 1, wherein: The single-component lid structure includes one or more fin structures that extend outward in a direction perpendicular to the top side of the electronic device and cover above the top side of the electronic device.

4. The encapsulated electronic device according to claim 1, wherein: The dielectric structure includes a 3D printed dielectric structure.

5. The encapsulated electronic device according to claim 1, wherein: The thickness of the dielectric structure is in the range of 2 micrometers to 5 micrometers.

6. An encapsulated electronic device, comprising: A substrate; An electronic device, the electronic device being coupled to the substrate, wherein the electronic device includes: A top side; and An edge; A first conductive structure, the first conductive structure being coupled to the substrate and laterally enclosing the edge of the electronic device without break; A dielectric structure, the dielectric structure being above the first conductive structure; and A second conductive structure, the second conductive structure being above the dielectric structure; Wherein: The first conductive structure serves as a first capacitor plate; The dielectric structure serves as a capacitor dielectric; The second conductive structure serves as a second capacitor plate; and The first capacitor plate, the capacitor dielectric, and the second capacitor plate form a capacitor structure for the encapsulated electronic device.

7. The encapsulated electronic device according to claim 6, wherein: The substrate includes a peripheral edge; The first conductive structure, the dielectric structure, and the second conductive structure include a ring-shaped reinforcement near the peripheral edge; and The ring-shaped reinforcement laterally encloses the edge of the electronic device without covering the top side of the electronic device.

8. The encapsulated electronic device according to claim 7, wherein: The first conductive structure includes a first end and an opposite second end, the first end being coupled to the substrate, and the opposite second end being remote from the substrate; The dielectric structure is above the opposite second end; The second conductive structure includes a first side that is generally perpendicular to the opposite second end; A first portion of the first side is above the dielectric structure; and A second portion of the first side is coupled to the substrate.

9. The packaged electronic device according to claim 6, wherein: The first conductive structure includes a first portion and a second portion, the first portion being coupled to the substrate, and the second portion being coupled to the first portion; and The second portion is coupled to the top side of the electronic device by an attachment material.

10. The packaged electronic device according to claim 6, wherein: The packaged electronic device has no encapsulation material between the first conductive structure and the edge of the electronic device.

11. A packaged electronic device, comprising: A substrate; An electronic device coupled to the substrate; A single-component lid structure including a first conductive structure, a second conductive structure, a third conductive structure, and a dielectric structure; The first conductive structure and the second conductive structure are coupled to the substrate by an attachment material; The third conductive structure includes: A first portion coupled to the dielectric structure and laterally overlapping the dielectric structure; A second portion laterally overlapping the gap between the first conductive structure and the second conductive structure; A third portion coupled to the first conductive structure and laterally overlapping the first conductive structure.

12. The packaged electronic device according to claim 11, wherein: The dielectric structure is located above the second conductive structure.

13. The packaged electronic device according to claim 12, wherein: The third conductive structure is located above the first conductive structure and the dielectric structure.

14. The packaged electronic device according to claim 11, wherein: The single-component lid structure forms an encapsulation structure that vertically and horizontally encapsulates the electronic device.

15. The packaged electronic device according to claim 11, wherein: The thickness of the dielectric structure is in the range of 2 micrometers to 5 micrometers.

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