Time pendulum amplitude detection circuit and time pendulum amplitude detection method
Through the clock pendulum detection circuit of common mode voltage adjustment and NMOS tube detection, the problems of low efficiency and high cost of clock signal pendulum detection in the prior art are solved, and a low-cost and efficient clock pendulum detection effect is achieved.
Patent Information
- Application Number
- CN202510477633.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-07-29
AI Technical Summary
In the prior art, the swing detection efficiency of clock signals is low and the cost is high, especially when detecting high-speed clock signals, the hardware requirements and accuracy requirements of the ADC are high.
The common mode voltage adjustment module is used to adjust the common mode voltage of the clock signal to the preset voltage value, and the clock pendulum is detected through the NMOS tube, and the source voltage of the NMOS tube reflects the clock pendulum size, and the reference voltage and comparator are used for accurate detection.
It realizes low-cost and efficient clock pendulum detection, which can accurately reflect the swing size of the clock signal, has a simple structure and high implementation ability.
Smart Images
Figure CN120389731A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and particularly to a clock swing detection circuit and a clock swing detection method. Background Art
[0002] In modern high-performance integrated circuit design, clock signals, such as high-speed clock signals, etc., serve as the system timing reference, and their quality directly affects the overall performance of the chip. In order to achieve quality management of clock signals, it is necessary to monitor clock-related parameters to ensure stable clock quality. Among them, the clock swing is one of the key parameters affecting clock performance. Therefore, the detection of clock swing is crucial.
[0003] Currently, an ADC (Analog-to-Digital Converter) is usually used to sample the clock signal, and based on the sampled signal, clock swing analysis is performed. However, when facing high-speed clock signals, the ADC needs to have an extremely high sampling rate and resolution, which poses higher hardware requirements and accuracy requirements for the ADC, resulting in higher costs and lower detection efficiency. Summary of the Invention
[0004] The present invention provides a clock swing detection circuit and a clock swing detection method to solve the problems in the prior art that it is not convenient to detect the swing of clock signals and the detection cost is relatively high.
[0005] A clock swing detection circuit provided by the present invention includes:
[0006] A common-mode voltage adjustment module, which accesses a first positive-phase clock signal and a first anti-phase clock signal, adjusts the common-mode voltage in the first positive-phase clock signal and the common-mode voltage in the first anti-phase clock signal to a preset voltage value, and obtains and outputs a second positive-phase clock signal and a second anti-phase clock signal after the common-mode voltage adjustment is completed;
[0007] A clock swing detection module, which includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor accesses the second anti-phase clock signal, the gate of the second NMOS transistor accesses the second positive-phase clock signal. The source of the first NMOS transistor is interconnected with the source of the second NMOS transistor, and a fixed current is accessed at the connection point. The drain of the first NMOS transistor is interconnected with the drain of the second NMOS transistor, and a preset power supply voltage is accessed at the connection point. The voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor reflects the magnitude of the clock swing. The preset voltage value is greater than the threshold voltage of the first NMOS transistor and greater than the threshold voltage of the second NMOS transistor.
[0008] In an embodiment of the present invention, the common-mode voltage adjustment module includes: a first capacitor, a second capacitor, a first resistor, and a second resistor;
[0009] One end of the first capacitor is connected to the first positive-phase clock signal to filter out the original common-mode voltage component in the first positive-phase clock signal; the other end of the first capacitor is connected to the gate of the second NMOS transistor;
[0010] One end of the second capacitor is connected to the first inverted-phase clock signal to filter out the original common-mode voltage component in the first inverted-phase clock signal; the other end of the second capacitor is connected to the gate of the first NMOS transistor;
[0011] The first ends of the first resistor and the second resistor are respectively connected to a target voltage, the voltage value of the target voltage is the preset voltage value, the second end of the first resistor is connected to the gate of the second NMOS transistor to adjust the common-mode voltage in the first positive-phase clock signal to the preset voltage value to obtain the second positive-phase clock signal; the second end of the second resistor is connected to the gate of the first NMOS transistor to adjust the common-mode voltage in the first inverted-phase clock signal to the preset voltage value to obtain the second inverted-phase clock signal.
[0012] In an embodiment of the present invention, it further includes:
[0013] A reference voltage module for outputting a preset reference voltage;
[0014] A comparator module for comparing the reference voltage with the clock swing voltage and outputting a comparison result, where the clock swing voltage refers to the voltage at the target connection point, and the target connection point refers to the connection point between the sources of the first NMOS transistor and the second NMOS transistor.
[0015] In an embodiment of the present invention, the reference voltage module includes a third NMOS transistor, the gate of the third NMOS transistor is connected to a preset control voltage to control the conduction state of the third NMOS transistor, the drain of the third NMOS transistor is connected to the power supply voltage, and the source of the third NMOS transistor is the output end of the reference voltage module.
[0016] In an embodiment of the present invention, the comparator module includes at least one comparator, and the reference voltage module corresponds to the comparator in the comparator module one by one;
[0017] If the number of comparators in the comparator module is one, the non-inverting input terminal of the comparator is connected to the reference voltage, the inverting input terminal of the comparator is connected to the clock swing voltage, and the output terminal of the comparator is the output terminal of the comparator module;
[0018] If the number of comparators in the comparator module is multiple, the inverting input terminals of each comparator in the comparator module are connected to the clock swing voltage, and the non-inverting input terminals of the comparators in the comparator module are connected to the reference voltages output by the corresponding reference voltage modules, and the reference voltages output by each reference voltage module are different.
[0019] In an embodiment of the present invention, it further includes: a current mirror module, which provides the fixed current for a target connection point, and the target connection point refers to the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor.
[0020] In an embodiment of the present invention, the current mirror module includes: a current source, a fourth NMOS transistor, a fifth NMOS transistor, and at least one sixth NMOS transistor, and the sixth NMOS transistors correspond to the reference voltage modules one by one;
[0021] The drain of the fourth NMOS transistor is connected to the output terminal of the current source, the gate of the fourth NMOS transistor is short-circuited to its drain, the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the target connection point, and the sources of the fourth NMOS transistor and the fifth NMOS transistor are both grounded;
[0022] When there is one reference voltage module, the gate of the corresponding sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the third NMOS transistor, and the source of the sixth NMOS transistor is grounded.
[0023] In an embodiment of the present invention, when there are multiple reference voltage modules, the gate of each sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the drain of each sixth NMOS transistor is connected to the source of the corresponding third NMOS transistor.
[0024] In an embodiment of the present invention, it further includes:
[0025] A third capacitor, one end of which is connected to the drain of the fifth NMOS transistor, and the other end of which is grounded to reduce the oscillation degree of the signal output by the target connection point.
[0026] The present invention also provides a clock swing detection method based on the clock swing detection circuit as described in any one of the above, including:
[0027] Input the first positive-phase clock signal and the first inverted clock signal into the common-mode voltage adjustment module to obtain the clock swing voltage detected by the clock swing detection module. The clock swing voltage refers to the voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor.
[0028] Based on the clock swing voltage, complete the clock swing detection.
[0029] Advantages of the present invention: The clock swing detection circuit and the clock swing detection method provided by the present invention. The circuit includes: a common-mode voltage adjustment module, which accesses the first positive-phase clock signal and the first inverted clock signal, adjusts the common-mode voltage in the first positive-phase clock signal and the common-mode voltage in the first inverted clock signal to a preset voltage value, and obtains and outputs the second positive-phase clock signal and the second inverted clock signal after the common-mode voltage adjustment is completed; a clock swing detection module, which includes a first NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor) transistor and a second NMOS transistor. The gate of the first NMOS transistor accesses the second inverted clock signal, the gate of the second NMOS transistor accesses the second positive-phase clock signal, the sources of the first NMOS transistor and the second NMOS transistor are interconnected, and a fixed current is connected to the connection point. The drains of the first NMOS transistor and the second NMOS transistor are interconnected, and a preset power supply voltage is connected to the connection point. The voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor reflects the clock swing magnitude. The preset voltage value is greater than the threshold voltage of the first NMOS transistor and greater than the threshold voltage of the second NMOS transistor. The above circuit can better realize the swing detection of the clock signal, that is, based on the voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor, determine the clock signal swing magnitude, with low cost and high feasibility. Description of the Drawings
[0030] Figure 1 Schematic diagram of the structure of the clock swing detection circuit provided by an embodiment of the present invention Figure 1 ;
[0031] Figure 2 Schematic diagram of the structure of the clock swing detection circuit provided by an embodiment of the present invention Figure 2 ;
[0032] Figure 3 Schematic diagram of the structure of the clock swing detection circuit provided by an embodiment of the present invention Figure 3 ;
[0033] Figure 4Schematic diagram of the simulation effect of the clock swing detection circuit provided by an embodiment of the present invention;
[0034] Figure 5 Schematic flow chart of the clock swing detection method provided by an embodiment of the present invention. Detailed implementation manners
[0035] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0036] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0037] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.
[0038] The following combines Figures 1 to 5 to explain the clock swing detection circuit and the clock swing detection method provided by the present invention.
[0039] Please refer to Figure 1 , Figure 1 Structural schematic of the clock swing detection circuit provided by an embodiment of the present invention Figure 1 ,as Figure 1 shown. The circuit includes:
[0040] A common-mode voltage adjustment module 110, which accesses a first positive-phase clock signal CLKP and a first anti-phase clock signal CLKN, adjusts the common-mode voltage in the first positive-phase clock signal CLKP and the common-mode voltage in the first anti-phase clock signal CLKN to a preset voltage value, and obtains and outputs a second positive-phase clock signal and a second anti-phase clock signal after the common-mode voltage adjustment is completed;
[0041] The clock swing detection module 120 includes a first NMOS transistor M1 and a second NMOS transistor M2. The gate of the first NMOS transistor M1 is connected to the second inverted clock signal, the gate of the second NMOS transistor M2 is connected to the second non-inverted clock signal. The sources of the first NMOS transistor M1 and the second NMOS transistor M2 are interconnected, and a connection point thereof is connected to a fixed current. The drains of the first NMOS transistor M1 and the second NMOS transistor M2 are interconnected, and a connection point thereof is connected to a preset power supply voltage AVDD. The voltage at the connection point between the sources of the first NMOS transistor M1 and the second NMOS transistor M2 reflects the clock swing magnitude. The preset voltage value is greater than the threshold voltage of the first NMOS transistor M1 and greater than the threshold voltage of the second NMOS transistor M2.
[0042] It should be noted that the clock in the above embodiments is a differential clock. The differential clock includes complementary non-inverted clock signals and inverted clock signals, that is, the first non-inverted clock signal CLKP and the first inverted clock signal CLKN in the above embodiments. Both the first non-inverted clock signal CLKP and the first inverted clock signal CLKN include a common-mode voltage component (it can be understood that the common-mode voltage is the common level of CLKP and CLKN relative to the same reference point (such as ground or other reference points)) and a differential signal component (effective signal), and its common-mode voltage is usually low. Therefore, in the above embodiments, by using the common-mode voltage adjustment module 110, the common-mode voltages in the first non-inverted clock signal CLKP and the first inverted clock signal CLKN are both adjusted to a preset voltage value, which is greater than the threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2, and can ensure that the first NMOS transistor M1 and the second NMOS transistor M2 are turned on, avoiding circuit failure. It can be understood that if the common-mode voltages in the first non-inverted clock signal CLKP and the first inverted clock signal CLKN are less than the threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2, it will cause the first NMOS transistor M1 and the second NMOS transistor M2 to fail to work properly, and further cause the entire circuit to fail.
[0043] In some embodiments, the threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are the same.
[0044] It should also be noted that the clock signal swing refers to the voltage difference between the first non-inverted clock signal CLKP and the first inverted clock signal CLKN.
[0045] It can be understood that the clock swing detection circuit in the above embodiments can convert the swing of a clock signal (such as a high-speed clock signal, etc., and most high-speed clock signals are oscillating sine waveforms) into an analog voltage signal, that is, the voltage at the connection point between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2. The principle is as follows:
[0046] By interconnecting the drains of the first NMOS transistor M1 and the second NMOS transistor M2, connecting the power supply voltage AVDD to their connection point, and interconnecting the sources of the first NMOS transistor M1 and the second NMOS transistor M2, and connecting a fixed current to their connection point, it can ensure that the currents of the first NMOS transistor M1 and the second NMOS transistor M2 are fixed (the source voltage of the first NMOS transistor M1 in the above circuit is equal to the source voltage of the second NMOS transistor M2). When the currents of the first NMOS transistor M1 and the second NMOS transistor M2 are fixed, the source voltages of both the first NMOS transistor M1 and the second NMOS transistor M2 satisfy the following relational expression:
[0047]
[0048] V GS =V G -V S
[0049] For the source voltage, there is
[0050] where, I D represents the drain current, μ n represents the electron mobility of the NMOS transistor (the electron mobilities of the first NMOS transistor M1 and the second NMOS transistor M2 are the same), C ox represents the gate oxide capacitance of the NMOS transistor (the gate oxide capacitances of the first NMOS transistor M1 and the second NMOS transistor M2 are the same), W represents the width of the NMOS transistor (the widths of the first NMOS transistor M1 and the second NMOS transistor M2 are the same), L represents the length of the NMOS transistor (the lengths of the first NMOS transistor M1 and the second NMOS transistor M2 are the same), V Gs represents the gate-source voltage, V TH represents the threshold voltage (the threshold voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are the same), V S represents the source voltage, V G represents the gate voltage.
[0051] Since I DIt is fixed. Therefore, the source voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are only related to their respective gate voltages. Assuming that the gate voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are equal, i.e., a constant voltage, the source voltages of the first NMOS transistor M1 and the second NMOS transistor M2 are at the minimum voltage value at this time. When the gate voltages of the first NMOS transistor M1 and the second NMOS transistor M2 change, that is, when the swing of the clock signal increases (the voltage difference between the second inverted clock signal and the second non-inverted clock signal becomes larger), restricted by the fixed current, the source voltages of the first NMOS transistor M1 and the second NMOS transistor M2 will also increase. Therefore, the source voltages of the first NMOS transistor M1 and the second NMOS transistor M2 reflect the swing magnitude of the clock signal, and the change in the source voltages of the first NMOS transistor M1 and the second NMOS transistor M2 reflects the change in the swing of the clock signal.
[0052] Please refer to Figure 2 , in some embodiments, the common-mode voltage adjustment module 110 includes: a first capacitor, a second capacitor, a first resistor, and a second resistor;
[0053] One end of the first capacitor is connected to the first non-inverted clock signal CLKP to filter out the original common-mode voltage component in the first non-inverted clock signal CLKP; the other end of the first capacitor is connected to the gate of the second NMOS transistor M2;
[0054] One end of the second capacitor is connected to the first inverted clock signal CLKN to filter out the original common-mode voltage component in the first inverted clock signal CLKN; the other end of the second capacitor is connected to the gate of the first NMOS transistor M1;
[0055] The first end of the first resistor and the first end of the second resistor are respectively connected to the target voltage VCM, the voltage value of the target voltage VCM is the preset voltage value, the second end of the first resistor is connected to the gate of the second NMOS transistor M2 to adjust the common-mode voltage in the first non-inverted clock signal CLKP to the preset voltage value to obtain the second non-inverted clock signal; the second end of the second resistor is connected to the gate of the first NMOS transistor M1 to adjust the common-mode voltage in the first inverted clock signal CLKN to the preset voltage value to obtain the second inverted clock signal.
[0056] It should be noted that, by virtue of their high-pass filtering characteristics, the first capacitor and the second capacitor can filter out the original common-mode voltage component (low frequency) and output the differential component in the signals (the first inverted clock signal CLKN and the first non-inverted clock signal CLKP). By connecting the target voltage to the first capacitor and the second capacitor respectively, a new common-mode voltage component, that is, the target voltage, can be added on the basis of the above differential component, so as to obtain the second non-inverted clock signal and the second inverted clock signal. The common-mode voltage in the second non-inverted clock signal is greater than the threshold voltage of the second NMOS transistor M2, and the common-mode voltage in the second inverted clock signal is greater than the threshold voltage of the first NMOS transistor M1. The first resistor and the second resistor in the above embodiments can also play an isolation role.
[0057] In some embodiments, the circuit further includes:
[0058] a reference voltage module 130 for outputting a preset reference voltage;
[0059] a comparator module 140 for comparing the reference voltage with the clock swing voltage and outputting a comparison result, where the clock swing voltage refers to the voltage at the target connection point, and the target connection point refers to the connection point between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2.
[0060] It should be noted that by comparing the reference voltage with the clock swing voltage, it is convenient to determine the deviation between the clock swing voltage and the reference voltage, so as to facilitate the subsequent adjustment of the clock swing.
[0061] In some embodiments, the reference voltage module 130 includes a third NMOS transistor M3. The gate of the third NMOS transistor M3 is connected to a preset control voltage VREF to control the on-state of the third NMOS transistor M3. The drain of the third NMOS transistor M3 is connected to the power supply voltage AVDD, and the source of the third NMOS transistor M3 is the output terminal of the reference voltage module 130.
[0062] It can be understood that by adjusting the control voltage VREF, that is, setting different control voltages VREF, the magnitude of the source voltage of the third NMOS transistor M3 can be controlled, so that the source of the third NMOS transistor M3 remains at a relatively stable and appropriate voltage, which is convenient for subsequent comparison with the clock swing voltage.
[0063] Please refer to Figure 2 and Figure 3 , in some embodiments, the comparator module 140 includes at least one comparator COMP, and the reference voltage module 130 corresponds to the comparator in the comparator module 140 one by one;
[0064] If the number of comparators in the comparator module 140 is one, the non-inverting input terminal of the comparator is connected to the reference voltage, the inverting input terminal of the comparator is connected to the clock swing voltage, and the output terminal of the comparator is the output terminal of the comparator module 140;
[0065] If the number of comparators in the comparator module 140 is multiple, the inverting input terminals of each comparator in the comparator module 140 are all connected to the clock swing voltage, the non-inverting input terminals of the comparators in the comparator module 140 are connected to the reference voltages output by the corresponding reference voltage modules 130, and the reference voltages output by each reference voltage module 130 are different.
[0066] It should be noted that by setting multiple comparators in the comparator module 140 and setting multiple reference voltage modules 130 corresponding to the comparators one by one (refer to M3_1, M3_2, M3_3...... in Figure 3 ), it is convenient to determine the accurate value or accurate range of the clock swing voltage, so as to facilitate subsequent adjustment of the clock swing to improve the device accuracy. It can be understood that multiple reference voltage modules 130 mean comparing multiple different reference voltages with the clock swing voltage respectively. According to the comparison results output by multiple comparators, the specific value of the clock swing voltage can be limited within a smaller range, so as to facilitate subsequent clock swing adjustment. The structure is relatively simple and easy to implement.
[0067] As Figure 3 shown, when the number of comparators in the comparator module 140 is multiple, the target connection point is connected to the non-inverting input terminals of all comparators, and the sources of the third NMOS transistors (such as M3_1, M3_2, M3_3...... in Figure 3 ) in each reference voltage module 130 are respectively connected to the inverting input terminals of the corresponding comparators.
[0068] In some embodiments, the circuit further includes: a current mirror module 150, which provides the fixed current for the target connection point, and the target connection point refers to the connection point between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2.
[0069] It should be noted that by setting the current mirror module 150, it is convenient to ensure that a fixed current is provided for the target connection point.
[0070] In some embodiments, the current mirror module 150 includes: a current source, a fourth NMOS transistor M4, a fifth NMOS transistor M5, and at least one sixth NMOS transistor M6, and the sixth NMOS transistor M6 corresponds to the reference voltage module 130 one by one;
[0071] The drain of the fourth NMOS transistor M4 is connected to the output terminal of the current source. The gate of the fourth NMOS transistor M4 is shorted to its drain. The gate of the fourth NMOS transistor M4 is connected to the gate of the fifth NMOS transistor M5. The drain of the fifth NMOS transistor M5 is connected to the target connection point. The sources of the fourth NMOS transistor M4 and the fifth NMOS transistor M5 are both grounded (AGND);
[0072] When there is one reference voltage module 130, the gate of the corresponding sixth NMOS transistor M6 is connected to the gate of the fourth NMOS transistor M4. The drain of the sixth NMOS transistor M6 is connected to the source of the third NMOS transistor M3. The source of the sixth NMOS transistor M6 is grounded.
[0073] In some embodiments, when there are multiple reference voltage modules 130, the gate of each sixth NMOS transistor M6 (such as M6_1, M6_2, M6_3...... in Figure 3 is connected to the gate of the fourth NMOS transistor M4. The drain of each sixth NMOS transistor M6 is connected to the source of the corresponding third NMOS transistor M3.
[0074] It can be understood that through the above settings, it is possible to ensure that the same fixed current is provided to the target connection point and each third NMOS transistor M3, ensuring the normal operation of the circuit.
[0075] In some embodiments, the circuit further includes:
[0076] A third capacitor, one end of which is connected to the drain of the fifth NMOS transistor M5, and the other end of which is grounded to reduce the oscillation degree of the output signal of the target connection point.
[0077] It can be understood that by setting the above third capacitor, it is possible to effectively filter out the oscillation generated when converting the clock signal swing into an analog voltage signal, thereby improving the detection accuracy.
[0078] The clock swing detection circuit in the above embodiments can be widely applied to circuits such as phase-locked loop oscillators and clock inputs. The structure is relatively simple, the implementation is relatively convenient, and the cost is relatively low.
[0079] To verify the detection effect of the clock swing detection circuit in the above embodiments, the following simulation tests were conducted in this embodiment. Under the 28-nanometer CMOS (Complementary Metal-Oxide-Semiconductor) process, 1V (volt) was used as the power supply voltage AVDD to implement the above clock swing detection circuit. The circuit was constructed and simulated. The frequency of the input differential clock was 8 GHz (gigahertz), and the single-ended swings of the input differential clock were 100 mV, 200 mV, 300 mV, 400 mV, and 500 mV respectively. The input VCM and VREF were both given 600 mV (millivolt), and the source voltage V_M3_S of M3 was 293.0942 mV. The simulation results are as Figure 4 shown. Please refer to Figure 4 , when the single-ended swings of the input differential clock are 100 mV, 200 mV, 300 mV, 400 mV, and 500 mV respectively, the source voltages of M1 and M2 are 379.0642 mV, 441.59218 mV, 510.31843 mV, 580.99691 mV, and 652.16694 mV respectively. Obviously, as the clock swing increases, the source voltages of M1 and M2 increase accordingly. Therefore, the above clock swing detection circuit can relatively accurately convert different swings into different voltage values, that is, the voltage at the connection point of the sources of M1 and M2. And by comparing the source voltages of M1 and M2 with the source voltage of M3, it can be determined whether the clock swing reaches the expected value, thus achieving the effect of swing detection and facilitating subsequent clock swing adjustment. It should be noted that Figure 4 in the coordinate system, the vertical axis is the voltage V with the unit of mV, and the horizontal axis is time with the unit of ns (nanosecond). Figure 4 V1 in
[0080] represents the voltage value of each simulation curve at the time of 494.24342 ns.
[0081] Please refer to Figure 5 , this embodiment also provides a clock swing detection method based on the clock swing detection circuit described in any one of the above, including:
[0082] S510: Input the first positive-phase clock signal CLKP and the first anti-phase clock signal CLKN into the common-mode voltage adjustment module 110 to obtain the clock swing voltage detected by the clock swing detection module 120. The clock swing voltage refers to the voltage at the connection point between the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2;
[0083] S520: Complete the clock swing detection based on the clock swing voltage. The clock swing detection method in this embodiment can better complete the clock swing detection, has high feasibility, and low cost.
[0084] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A clock swing detection circuit, characterized in that, Including: A common-mode voltage adjustment module, which accesses a first positive-phase clock signal and a first anti-phase clock signal, adjusts the common-mode voltage in the first positive-phase clock signal and the common-mode voltage in the first anti-phase clock signal to a preset voltage value, and obtains and outputs a second positive-phase clock signal and a second anti-phase clock signal after the common-mode voltage adjustment is completed; A clock swing detection module, which includes a first NMOS transistor and a second NMOS transistor. The gate of the first NMOS transistor accesses the second anti-phase clock signal, the gate of the second NMOS transistor accesses the second positive-phase clock signal. The source of the first NMOS transistor is interconnected with the source of the second NMOS transistor, and a connection point thereof accesses a fixed current. The drain of the first NMOS transistor is interconnected with the drain of the second NMOS transistor, and a connection point thereof accesses a preset power supply voltage. The voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor reflects the clock swing magnitude. The preset voltage value is greater than the threshold voltage of the first NMOS transistor and greater than the threshold voltage of the second NMOS transistor.
2. The clock swing detection circuit according to claim 1, wherein The common-mode voltage adjustment module includes: a first capacitor, a second capacitor, a first resistor, and a second resistor; One end of the first capacitor accesses the first positive-phase clock signal to filter out the original common-mode voltage component in the first positive-phase clock signal; the other end of the first capacitor is connected to the gate of the second NMOS transistor; One end of the second capacitor accesses the first anti-phase clock signal to filter out the original common-mode voltage component in the first anti-phase clock signal; the other end of the second capacitor is connected to the gate of the first NMOS transistor; The first end of the first resistor and the first end of the second resistor are respectively connected to a target voltage, and the voltage value of the target voltage is the preset voltage value. The second end of the first resistor is connected to the gate of the second NMOS transistor to adjust the common-mode voltage in the first positive-phase clock signal to the preset voltage value to obtain the second positive-phase clock signal; the second end of the second resistor is connected to the gate of the first NMOS transistor to adjust the common-mode voltage in the first anti-phase clock signal to the preset voltage value to obtain the second anti-phase clock signal.
3. The clock swing detection circuit according to claim 1, wherein Further including: A reference voltage module for outputting a preset reference voltage; A comparator module for comparing the reference voltage and the clock swing voltage and outputting a comparison result. The clock swing voltage refers to the voltage at a target connection point, and the target connection point refers to the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor.
4. The clock swing detection circuit according to claim 3, wherein: The reference voltage module includes a third NMOS transistor. The gate of the third NMOS transistor accesses a preset control voltage to complete the control of the on-state of the third NMOS transistor. The drain of the third NMOS transistor accesses the power supply voltage, and the source of the third NMOS transistor is the output end of the reference voltage module.
5. The clock swing detection circuit according to claim 4, wherein: The comparator module includes at least one comparator, and the reference voltage module corresponds to the comparator in the comparator module one by one; If the number of comparators in the comparator module is one, the non-inverting input terminal of the comparator is connected to the reference voltage, the inverting input terminal of the comparator is connected to the clock swing voltage, and the output terminal of the comparator is the output terminal of the comparator module; If the number of comparators in the comparator module is multiple, the inverting input terminals of each comparator in the comparator module are all connected to the clock swing voltage, the non-inverting input terminals of the comparators in the comparator module are connected to the reference voltages output by the corresponding reference voltage modules, and the reference voltages output by each reference voltage module are different.
6. The clock swing detection circuit according to claim 5, wherein It further includes: A current mirror module that provides the fixed current to a target connection point, where the target connection point refers to the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor.
7. The clock swing detection circuit according to claim 6, wherein The current mirror module includes: a current source, a fourth NMOS transistor, a fifth NMOS transistor, and at least one sixth NMOS transistor, and the sixth NMOS transistors correspond to the reference voltage modules one by one; The drain of the fourth NMOS transistor is connected to the output terminal of the current source, the gate of the fourth NMOS transistor is shorted to its drain, the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the target connection point, and the sources of the fourth NMOS transistor and the fifth NMOS transistor are both grounded; When there is one reference voltage module, the gate of the corresponding sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the third NMOS transistor, and the source of the sixth NMOS transistor is grounded.
8. The clock swing detection circuit according to claim 7, wherein When there are multiple reference voltage modules, the gate of each sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the drain of each sixth NMOS transistor is connected to the source of the corresponding third NMOS transistor.
9. The clock swing detection circuit according to claim 7 or 8, characterized in that, It further includes: A third capacitor, one end of which is connected to the drain of the fifth NMOS transistor and the other end of which is grounded to reduce the oscillation degree of the signal output at the target connection point.
10. A clock swing detection method based on the clock swing detection circuit according to any one of claims 1 to 9, characterized in that: It includes: Inputting the first positive-phase clock signal and the first anti-phase clock signal into the common-mode voltage adjustment module to obtain the clock swing voltage detected by the clock swing detection module, where the clock swing voltage refers to the voltage at the connection point between the source of the first NMOS transistor and the source of the second NMOS transistor; Based on the clock swing voltage, clock swing detection is completed.