Cascaded high-voltage pulse trigger circuit based on SiC DSRD

Abstract

The invention belongs to the technical field of power electronic devices, and particularly discloses a cascade high-voltage pulse trigger circuit based on SiC DSRD. The cascaded high-voltage pulse trigger circuit is formed by connecting a first-stage structure and a second-stage structure in series; the first-stage structure comprises a plurality of branch structures which are connected in parallel, the branch structures are completely the same, and each branch structure comprises a single SiC DSRD and is used for providing a reverse current; the second-stage structure comprises a single SiC DSRD and is used for reversely extracting a plurality of reverse currents gathered by the first-stage structure and generating high-voltage pulses on a load resistor. According to the invention, a plurality of branches are connected in parallel to provide a larger reverse extraction current for a rear-stage (output-stage) SiC DSRD, so that the rise time of an output pulse is reduced; meanwhile, forward pumping is carried out on the rear-stage (output-stage) SiC DSRD through an independent capacitor, larger forward pumping charges are guaranteed, and therefore the output pulse voltage of the single SiC DSRD is increased.

Description

Technical Field

[0001] This application belongs to the technical field of power electronic devices, and more specifically, relates to a cascaded high-voltage pulse trigger circuit based on SiC DSRD. Background Art

[0002] The drift step recovery diode (DSRD) is a two-terminal semiconductor open switch that can interrupt high currents on the nanosecond time scale, enabling the output of high-voltage nanosecond pulses with fast rising fronts. It has the advantages of small size, long life, and high reliability. Currently, DSRDs are widely used in radar, accelerators, air purification, and internal combustion engine ignition systems, etc.

[0003] With the continuous progress of science and technology and the increasingly strict application requirements, DSRDs should meet higher pulse output voltage and current cutoff speed standards. Compared with most silicon materials currently used for DSRDs, the critical breakdown field strength of SiC DSRDs (such as 4H-SiC) is more than ten times higher. Theoretically, when the drift layer thickness is the same, the breakdown voltage of 4H-SiC DSRDs is more than ten times that of Si DSRDs. In addition, the electron saturation drift velocity of 4H-SiC is more than twice that of Si, and the switching speed is significantly faster compared with Si DSRDs. Under ideal conditions, for the same blocking voltage, the current cutoff time of 4H-SiC DSRDs can be as short as 1 / 20 of that of Si DSRDs. SiC DSRDs were first proposed in 2002. So far, there have been two main dynamic characteristic research methods: one focuses on single-device configurations, and the other focuses on series stack configurations. Although series stacking increases the pulse output voltage, it also brings challenges such as larger volume and reduced stability. By selecting appropriate trigger circuits and SiC DSRD devices, higher pulse output voltages and shorter rise times can be obtained, thus expanding the application range of SiC DSRDs. Summary of the Invention

[0004] Aiming at the defects of the prior art, the purpose of this application is to provide a cascaded high-voltage pulse trigger circuit based on SiC DSRD, aiming to solve the problem that the output parameters of a single SiC DSRD are not optimal.

[0005] The first aspect of this application relates to a cascaded high-voltage pulse trigger circuit based on SiC DSRD, which is formed by connecting a first-stage structure and a second-stage structure in series; The first-stage structure includes a plurality of parallel branch structures, and each branch structure is exactly the same. Each branch structure includes a single SiC DSRD for providing a reverse current. The second - level structure includes a single SiC DSRD, which is used to reversely extract multiple reverse currents converged by the first - level structure and generate high - voltage pulses on the load resistor.

[0006] Preferably, the branch structure includes 1 protection resistor, 2 capacitors, 2 inductors, 1 power semiconductor switch, and 1 SiC DSRD. The power semiconductor switch (S 1a ) is used to open and close according to the received trigger signal. Among them, One end of the first protection resistor (R 1a ) is connected to the first DC power supply (V cc ), and the other end is connected to the power semiconductor switch (S 1a ) and the first capacitor (C 1a ); The other end of the power semiconductor switch (S 1a ) is grounded, and the other end of the first capacitor (C 1a ) is connected to the first inductor (L 1a ) and the second capacitor (C 2a ); The other end of the first inductor (L 1a ) is grounded, and the other end of the second capacitor (C 2a ) is connected to the second inductor (L 2a ); The other end of the second inductor (L 2a ) is connected to the cathode of the SiC DSRD, and the anode of the SiC DSRD is grounded.

[0007] Preferably, the number of branch structures in the first - level structure is greater than or equal to 4.

[0008] Preferably, the opening duration of the power semiconductor switch is 100ns - 120ns, and the first DC power supply is greater than 700V.

[0009] Preferably, the first capacitor is 20nF, the second capacitor is 10nF, the first inductor is 200nH, the second inductor is 200nH, and the first protection resistor is 1000Ω.

[0010] Preferably, the second - level structure includes 1 inductor, 1 SiC DSRD, 1 capacitor, 1 protection resistor, a second DC power supply, and 1 load resistor. Among them, One end of the third inductor (L3) is connected to the second inductor (L 2a ), and the other end is connected to the cathode of the SiC DSRD and the load resistor (R load ); The anode of the SiC DSRD is connected to the third capacitor (C3) and the second protection resistor (R2); The other end of the second protection resistor (R2) is connected to the second DC power supply (V1); The other ends of the third capacitor (C3) and the load resistor (R load ) are grounded.

[0011] Preferably, the second DC power supply is greater than 200V, the third capacitor is 20nF - 50nF, and the third inductor is 100nH - 150nH.

[0012] Preferably, the second protection resistor is 1000Ω.

[0013] Preferably, the SiC DSRD is a 4H-SiC DSRD, 6H-SiC DSRD or 3C-SiC DSRD.

[0014] Preferably, when the opening duration of the control power semiconductor switch is 110ns, the first DC power supply is selected as 700V, the second DC power supply is selected as 200V, the third capacitor is 20nF, and the load resistor is 50Ω, the peak value of the pulse output voltage of a single SiC DSRD reaches 7.62kV, the pulse output rise time is 1.563ns, and the rise rate reaches 3413kV / ns.

[0015] Generally speaking, compared with the prior art, the above technical solution conceived by this application has the following beneficial effects: This application proposes a cascaded high-voltage pulse trigger circuit based on SiC DSRD, which is composed of a first-stage structure and a second-stage structure connected in series; the first-stage structure includes multiple parallel branch structures, and each branch structure is exactly the same. Each branch structure includes a single SiC DSRD for providing a reverse current; the second-stage structure includes a single SiC DSRD for reversely extracting multiple reverse currents converged by the first-stage structure to generate a high-voltage pulse on the load resistor. This application provides a larger reverse extraction current for the subsequent stage (output stage) SiC DSRD through multiple branches in parallel, thereby reducing the output pulse rise time; at the same time, the subsequent stage (output stage) SiC DSRD is forward-pumped by a single capacitor, ensuring a larger forward pumping charge, thereby increasing the output pulse voltage of a single SiC DSRD. Description of the Drawings

[0016] Figure 1 is a schematic diagram of a cascaded high-voltage pulse trigger circuit based on SiC DSRD provided by an embodiment of this application.

[0017] Figure 2 is a schematic diagram of a single-channel pulse trigger circuit provided by an embodiment of this application.

[0018] Figure 3 is the simulation result of the current of DSRD1 and DSRD5 and the voltage on C 1a 、C 2a 、C3、R load when the forward pumping time is 90 ns provided by an embodiment of this application.

[0019] Figure 4 It is the four - layer structure diagram of the 4H - SiC DSRD provided by the embodiment of the present application.

[0020] Figure 5 It is the waveform diagram of the pulse output voltage and reverse current of DSRD5 provided by the embodiment of the present application under different forward pumping times.

[0021] Figure 6 It is about different V provided by the embodiment of the present application cc and the schematic diagram of the pulse peak output voltage under different V1 values.

[0022] Figure 7 It is the waveform diagram of the pulse output voltage and reverse current of DSRD1 and DSRD5 under different V1 values provided by the embodiment of the present application.

[0023] Figure 8 It is the waveform diagram of the pulse output voltage and reverse current of DSRD5 under different C3 values provided by the embodiment of the present application, where (a) C3 ranges from 10 nF to 50 nF, (b) C3 ranges from 60 nF to 100 nF, (c) C3 ranges from 110 nF to 150 nF, (d) C3 ranges from 160 nF to 200 nF.

[0024] Figure 9 It is the waveform diagram of the pulse output voltage and reverse current of DSRD5 under different L3 values provided by the embodiment of the present application, where (a) L3 ranges from 50 nH to 250 nH, (b) L3 ranges from 300 nH to 500 nH.

[0025] Figure 10 It is the waveform diagram of the pulse output voltage when the forward pumping time is 120 ns, V cc is 700 V, and V1 is 200 V provided by the embodiment of the present application. Detailed implementation manners

[0026] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0028] The present application relates to a cascaded high - voltage pulse trigger circuit based on SiC DSRD, which is formed by connecting a first - stage structure and a second - stage structure in series; The first - stage structure includes a plurality of parallel branch structures, and each branch structure is exactly the same. Each branch structure includes a single SiC DSRD for providing a reverse current; The second-stage structure includes a single SiC DSRD for reversely extracting multiple reverse currents converged by the first-stage structure to generate a high-voltage pulse across the load resistor.

[0029] Preferably, the branch structure includes 1 protection resistor, 2 capacitors, 2 inductors, 1 power semiconductor switch, and 1 SiC DSRD. The power semiconductor switch (S 1a ) is used to open and close according to the received trigger signal; where One end of the first protection resistor (R 1a ) is connected to the first DC power supply (V cc ), and the other end is connected to the power semiconductor switch (S 1a ) and the first capacitor (C 1a ); the other end of the power semiconductor switch (S 1a ) is grounded, and the other end of the first capacitor (C 1a ) is connected to the first inductor (L 1a ) and the second capacitor (C 2a ); the other end of the first inductor (L 1a ) is grounded, and the other end of the second capacitor (C 2a ) is connected to the second inductor (L 2a ); the other end of the second inductor (L 2a ) is connected to the cathode of the SiC DSRD, and the anode of the SiC DSRD is grounded.

[0030] Preferably, the number of branch structures in the first-stage structure is greater than or equal to 4.

[0031] Preferably, the on-time of the power semiconductor switch is controlled to be 100 ns - 120 ns, and the first DC power supply is greater than 700 V.

[0032] Preferably, the first capacitor is 20 nF, the second capacitor is 10 nF, the first inductor is 200 nH, the second inductor is 200 nH, and the first protection resistor is 1000 Ω.

[0033] Preferably, the second-stage structure includes 1 inductor, 1 SiC DSRD, 1 capacitor, 1 protection resistor, a second DC power supply, and 1 load resistor. Among them, One end of the third inductor (L3) is connected to the second inductor (L 2a ), and the other end is connected to the cathode of the SiC DSRD and the load resistor (R load ); the anode of the SiC DSRD is connected to the third capacitor (C3) and the second protection resistor (R2); the other end of the second protection resistor (R2) is connected to the second DC power supply (V1); the third capacitor (C3) and the load resistor (Rload The other end of () is grounded.

[0034] Preferably, the second DC power supply is greater than 200V, the third capacitor is 20nF - 50nF, and the third inductor is 100nH - 150nH.

[0035] Preferably, the second protection resistor is 1000Ω.

[0036] Preferably, the SiC DSRD is 4H-SiC DSRD, 6H-SiC DSRD or 3C-SiC DSRD.

[0037] Preferably, when the opening duration of the control power semiconductor switch is 110ns, the first DC power supply is selected as 700V, the second DC power supply is selected as 200V, the third capacitor is 20nF, and the load resistor is 50Ω, the peak value of the pulse output voltage of a single SiC DSRD reaches 7.62kV, the pulse output rise time is 1.563ns, and the rise rate reaches 3413kV / ns.

[0038] Embodiment In this embodiment, the SiC DSRD is 4H SiC DSRD. In the first-stage structure, the number of branch structures is equal to 4, the DC power supply is a pulsed DC power supply, each capacitor meets the withstand voltage requirement, and the power semiconductor switch is an IGBT or MOSFET switch.

[0039] As Figure 1 shown, there are four branches in the first-stage structure. The four branches are connected in parallel and are exactly the same.

[0040] The first branch (the subscript corresponds to a, and the subscripts of the other three branches correspond to b, c, d respectively): The pulsed DC power supply V cc is connected to the protection resistor R 1a , the protection resistor R 1a is connected to the capacitor C 1a and the switch S 1a , the other end of S 1a is grounded, the capacitor C 1a is connected to the capacitor C 2a and the inductor L 1a , the other end of the inductor L 1a is grounded, the other end of C 2a is connected to L 2a , the other end of L 2a is connected to the cathode of DSRD1, and the anode of DSRD1 is grounded.

[0041] As Figure 1 shown, the second-stage structure includes: One end of L3 is connected to the other end of L 2a , and the other end is connected to the cathode of DSRD5 and the load resistor Rload is connected, the anode of DSRD5 is connected to capacitor C3 and protection resistor R2, the other end of protection resistor R2 is connected to pulsed DC power supply V1, and the other end of capacitor C3 and load resistor R load is grounded.

[0042] The working principle of the multi-branch cascaded high-voltage pulse trigger circuit based on SiC DSRD is as follows: The four branches in the green box are parallel and identical to each other, as Figure 1 shown. For the convenience of understanding the working principle of the circuit, the single-branch pulse trigger circuit based on 4H-SiC DSRD is as Figure 2 shown. The currents passing through DSRD1 and DSRD5 and the voltages on C 1a , C 2a , C3 and R load are simulated, as Figure 3 shown.

[0043] Initially, S 1a is off, C 1a is charged by V cc , C 2a and C3 are charged by V1. According to the circuit structure, the voltages on each capacitor in the steady state are as shown in (1)-(3), and the charge quantity of C 2a / b / c / d is as shown in (4):

[0044] where, R DSRD is the internal resistance of DSRD, R load is the load resistor, is the charge quantity of C 2a / b / c / d , is the capacitance value of C 2a / b / c / d , is the voltage of C 2a / b / c / d .

[0045] The trigger signal is sent to S 1a through FPGA to turn it on. C 1a discharges through two branches: C 1a -S 1a -L 1a -C 1a and C 1a -S 1a -DSRD1-L 2a -C 2a -C 1a . C3 discharges through C3-DSRD5-L3-L 2a -C 2a -L 1aDischarge, so that DSRD1 and DSRD5 apply a forward current, injecting non-equilibrium carriers, accumulating a large number of electron-hole pairs at the PN junction. The two-stage DSRDs are respectively forward-pumped by different capacitors, ensuring the forward pumping charge of each DSRD, which will make the output voltage of the latter-stage (output stage) DSRD higher. At the same time, C 2a is charged, as Figure 2 [red line and green line] and Figure 3 [from t0 to t1] shown. S 1a 's turn-on time corresponds to the forward pumping time of all SiC DSRDs, and this time is set to 90 ns.

[0046] After the trigger signal ends (corresponding to t1), S 1a turns off, and C 2a discharges through three branches: C 2a -L 2a -DSRD1-L 1a -C 2a , C 2a -L 2a -L3-DSRD5-C3-L 1a -C 2a , C 2a -L 2a -L3-R load -L 1a -C 2a . Due to the inductance blocking, the discharge ratio of the three branches decreases in turn, and most of the current flows reversely through DSRD1. The forward-accumulated non-equilibrium carriers will be extracted.

[0047] When all non-equilibrium carriers are depleted (corresponding to t2), DSRD1 turns off, and the reverse current transfers to DSRD5, as Figure 2 [blue line] and Figure 3 [from t1 to t2]. The working principles of the other three branches are the same. The reverse currents from all four branches converge at DSRD5, resulting in stronger reverse extraction for DSRD5. Compared with traditional capacitor energy storage or inductor energy storage for discharging, using multiple DSRDs in parallel for discharging will greatly increase the reverse extraction current, which will reduce the reverse extraction time of DSRD5, generate a shorter high-voltage pulse on the load, and the corresponding rise time will be shorter and dv / dt will be higher, thus achieving the effect of sharpening the pulse.

[0048] Similarly, when all non-equilibrium carriers are depleted (corresponding to t3), DSRD5 turns off, and the reverse current transfers to the load (R load ), generating a high-voltage short pulse across the load, as Figure 2 [orange line and purple line] and Figure 3 [from t2 to t3].

[0049] After the forward pumping is completed (corresponding to t1), the rising edge of the pulsed output voltage on the load can generally be divided into three stages: The first stage [see Figure 3 : from t1 to t2 and the orange oval - prepulse stage 1], the second stage [see Figure 3 : from t2 to t3 and the orange oval - prepulse stage 2], the third stage [see Figure 3 : after t3]. The first - stage and the second - stage are the prepulse stages of the pulsed output voltage, also known as the pedestal effect. The reason for the occurrence of the pedestal effect is that during the reverse extraction process, the bipolar drift waves do not meet at the PN junction, resulting in a voltage plateau or a slow rise in the pulsed output voltage waveform.

[0050] Sequentially determine the optimal selection of the forward - pumping time ( ), DC input voltage sources (V cc , V1), capacitance (C3), and inductance (L3) parameter values in the trigger circuit. In the TCAD simulation software, the DSRD parameters match the actual values, and the SiC DSRD adopts a four - layer structure, as Figure 4 shown.

[0051] First, using 10 ns as the gradient, the pulsed output voltage and reverse current of DSRD5 at forward - pumping times in the range of 50 ns to 130 ns are simulated, as Figure 5 shown. From 50 ns to 110 ns, the pulsed peak output voltage (V peak ) continues to rise. After 110 ns, the pulsed peak output voltage begins to decline. At 130 ns, the pulsed output voltage shows obvious distortion with two spikes. The best pulsed output occurs when the forward - pumping time is between 100 ns and 120 ns.

[0052] Second, the circuit has two DC input voltage sources, V cc and V1. The pulsed peak output voltages at different V cc and V1 values are simulated, as Figure 6 shown. As V cc increases, the pulsed peak output voltage continues to rise and reaches the saturation point at about 700 V. As V cc further increases, the output voltage basically remains unchanged. According to (1), V cc affects the initial steady - state voltage of C 1a / b / c / d , which in turn affects the number of forward - pumping charges in DSRD 1 / 2 / 3 / 4 and ultimately affects the reverse current of DSRD5, thus changing the pulsed output voltage. As V1 increases, the pulsed output peak voltage first rises and then falls, reaching the maximum value at V1 = 200 V. According to (2) and (3), it can be seen that V1 affects C 2a / b / c / dand the initial steady-state voltage on C3. According to (4), it can be concluded that an increase in V1 increases the initial steady-state charge of C 2a / b / c / d and reduces the forward pumping charge in DSRD 1 / 2 / 3 / 4 and DSRD5. At the same time, an increase in V1 increases the initial steady-state charge of C3 and increases the forward pumping charge in DSRD5. Therefore, the optimal value of V1 cannot be easily determined through simple analysis. The waveforms of the pulsed output voltage and reverse current of DSRD at V1 from 100 V to 1000 V. V cc is 700 V and the forward pumping time is 110 ns, as shown in Figure 7 shown. As V1 increases, the pedestal effect on the pulsed output voltage becomes more obvious, as shown in Figure 7 shown [red circle]. This may lead to energy loss. However, when V1 is 100 V, the pulsed peak output voltage is too small. In summary, V cc is greater than 700 V and V1 greater than 200 V is a better choice.

[0053] Third, capacitor C3 determines the forward pumping charge of DSRD5 [see Figure 2 : green line], but it is also part of the reverse pumping circuit [see Figure 2 : blue line and orange line]. Therefore, the larger C3 is not necessarily better. With a gradient of 10 nF, the pulsed output voltage and reverse current waveforms of DSRD5 in the capacitance range of 10 nF to 200 nF of C3 were simulated when V cc is 700 V, V1 is 200 V, and the forward pumping time is 110 ns, as shown in Figure 8 shown. When C3 is 10 nF, a spike appears at the front end of the pulsed output voltage. At 20 nF, the pulsed output voltage is optimal. When it exceeds 30 nF, as the capacitance increases, the pedestal effect becomes more obvious and the voltage plateau time extends. After 110 nF, the voltage waveform is severely distorted and two plateaus appear. Therefore, the capacitance C3 of 20 nF - 50 nF is a better choice.

[0054] Fourth, there is an inductor L3 in both the forward and reverse circuits, and its optimal value cannot be determined through theoretical analysis. As shown in Figure 9 shown, using 50 nH as the gradient, when V ccWhen V is 700 V, V1 is 200 V, the forward pumping time is 110 ns, and C3 is 20 nF, for L3, in the inductance range of 50 nH to 500 nH, the waveforms of the pulse output voltage and reverse current of DSRD5 are simulated. As the inductance value increases, the pedestal effect becomes more obvious and the voltage plateau time extends. However, when L3 is 50 nH, the pulse peak output voltage is too low. When L3 is 100 nH, the pulse peak output voltage is the highest and the pedestal effect is not obvious. In summary, L3 being 100 nH - 150 nH is a better choice.

[0055] Based on the above simulation analysis, the selected parameters of the high-voltage pulse circuit and their corresponding values are as follows: is 110 ns, V cc is 700 V, V1 is 200 V, C3 is 20 nF, L3 is 100 nH, C 1a / b / c / d is 20 nF, C 2a / b / c / d is 10 nF, L 1a / b / c / d is 200 nH, L 2a / b / c / d is 200 nH, R 1a / b / b / d and R2 are 1000 Ω, load R load is 50 Ω. Based on the above parameters, as Figure 10 shown, in the experiment, a high-voltage short pulse with a single SiC DSRD pulse output voltage peak of 7.62 kV and a pulse output rise time of 1.563 ns is obtained, with a dv / dt reaching 3413 kV / ns, which is the highest value of the reported single-tube output parameters of 4H-SiC DSRD at home and abroad, increasing the application scenarios of 4H-SiC DSRD.

[0056] It should be understood that expressions such as "including" and "may include" that can be used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "including" and / or "having" can be interpreted as indicating a specific characteristic, number, operation, constituent element, component, or a combination thereof, but cannot be interpreted as excluding the existence or possibility of addition of one or more other characteristics, numbers, operations, constituent elements, components, or a combination thereof.

[0057] In addition, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" can include A, can include B, or can include both A and B.

[0058] In the description of the embodiments of the present application, it should be noted that unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the two are connected and the relative position relationship after connection remains unchanged. "Rotational connection" means that the two are connected and can rotate relative to each other after connection. "Sliding connection" means that the two are connected and can slide relative to each other after connection. The orientation terms mentioned in the embodiments of the present application, such as "top", "bottom", "inner", "outer", "left", "right", etc., are only references to the direction of the accompanying drawings. Therefore, the orientation terms are used to better and more clearly illustrate and understand the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present application.

[0059] In addition, in the embodiments of the present application, mathematical concepts such as symmetry, equality, parallelism, perpendicularity, etc. are mentioned. These limitations are all in view of the current technological level, rather than absolute strict definitions in the mathematical sense. A small deviation is allowed, and approximations such as approximate symmetry, approximate equality, approximate parallelism, approximate perpendicularity, etc. are all acceptable. For example, when A is parallel to B, it means that A and B are parallel or approximately parallel, and the included angle between A and B can be between 0 degrees and 10 degrees. When A is perpendicular to B, it means that A and B are perpendicular or approximately perpendicular, and the included angle between A and B can be between 80 degrees and 100 degrees.

[0060] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A cascaded high-voltage pulse trigger circuit based on SiC DSRD, characterized in that It is formed by connecting a first-level structure and a second-level structure in series; The first-level structure includes multiple parallel branch structures, and each branch structure is exactly the same. Each branch structure includes a single SiC DSRD for providing a reverse current; The second-level structure includes a single SiC DSRD for reversely extracting multiple reverse currents converged by the first-level structure to generate a high-voltage pulse across the load resistor.

2. The cascaded high-voltage pulse trigger circuit according to claim 1, wherein The branch structure includes one protection resistor, two capacitors, two inductors, one power semiconductor switch, and one SiC DSRD. The power semiconductor switch (S 1a ) is used to turn on and off according to the received trigger signal. Among them, The first protection resistor (R 1a ), one end of which is connected to the first DC power supply (V cc ), and the other end is connected to the power semiconductor switch (S 1a ) and the first capacitor (C 1a ); the other end of the power semiconductor switch (S 1a ) is grounded, and the other end of the first capacitor (C 1a ) is connected to the first inductor (L 1a ) and the second capacitor (C 2a ); the other end of the first inductor (L 1a ) is grounded, and the other end of the second capacitor (C 2a ) is connected to the second inductor (L 2a ); the other end of the second inductor (L 2a ) is connected to the cathode of the SiC DSRD, and the anode of the SiC DSRD is grounded.

3. The cascaded high-voltage pulse trigger circuit according to claim 2, wherein, The number of branch structures in the first-level structure is greater than or equal to 4.

4. The cascaded high-voltage pulse trigger circuit according to claim 2, wherein, The on-time of the control power semiconductor switch is 100 ns - 120 ns, and the first DC power supply is greater than 700 V.

5. The cascade high-voltage pulse trigger circuit according to claim 2, characterized in that, The first capacitor is 20 nF, the second capacitor is 10 nF, the first inductor is 200 nH, the second inductor is 200 nH, and the first protection resistor is 1000 Ω.

6. The cascade high-voltage pulse trigger circuit according to claim 1, characterized in that, The second-level structure includes 1 inductor, 1 SiC DSRD, 1 capacitor, 1 protection resistor, a second DC power supply, and 1 load resistor, where One end of the third inductor (L3) is connected to the second inductor (L 2a ), and the other end is connected to the cathode of the SiC DSRD and the load resistor (R load ); the anode of the SiC DSRD is connected to the third capacitor (C3) and the second protection resistor (R2); the other end of the second protection resistor (R2) is connected to the second DC power supply (V1); the other ends of the third capacitor (C3) and the load resistor (R load ) are grounded.

7. The cascaded high-voltage pulse trigger circuit according to claim 6, characterized in that, the second DC power supply is greater than 200 V, the third capacitor is 20 nF - 50 nF, and the third inductor is 100 nH - 150 nH.

8. The cascade high-voltage pulse trigger circuit according to claim 6, characterized in that, The second protection resistor is 1000 Ω.

9. The cascaded high-voltage pulse trigger circuit according to claim 1, characterized in that, The SiC DSRD is a 4H-SiC DSRD, 6H-SiC DSRD, or 3C-SiC DSRD.

10. The cascaded high-voltage pulse trigger circuit according to any one of claims 1 to 9, characterized in that, When the on-time of the control power semiconductor switch is 110 ns, the first DC power supply is selected as 700 V, the second DC power supply is selected as 200 V, the third capacitor is 20 nF, and the load resistor is 50 Ω, the peak value of the pulse output voltage of a single SiC DSRD reaches 7.62 kV, the pulse output rise time is 1.563 ns, and the rise rate reaches 3413 kV / ns.

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