NoC routing in multi-chip device

Abstract

Embodiments herein describe a multi-chip device comprising a plurality of ICs with interconnected NoCs. Embodiments herein provide address translation circuitry in these ICs. The address translation circuitry establishes a hierarchy in which traffic originating from the first IC intended for a destination on the second IC is first routed to the address translation circuitry on the second IC, which then performs address translation and inserts the traffic back onto the NoC in the second IC but having a destination ID corresponding to the destination. In this manner, the IC may have additional address apertures only to route traffic to address translation circuitry of other ICs, rather than having address apertures for each destination in these other ICs.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to address translation and utilization of inter-die connections in a network-on-chip (NoC). Background Art

[0002] A system-on-chip (SoC) (e.g., a field-programmable gate array (FPGA), a programmable logic device (PLD), or an application-specific integrated circuit (ASIC)) may include a packet network fabric known as a network-on-chip (NoC) to route data packets between logic blocks (e.g., programmable logic blocks, processors, memories, etc.) in the SoC.

[0003] The NoC may include an ingress logic block (e.g., a master block) that performs read requests or write requests to an egress logic block (e.g., a slave block). A multi-chip device may be formed by SoCs (e.g., integrated circuits) connected together. The SoC may include NoC connections that permit a NoC in one SoC to connect to a NoC in another SoC. This permits the NoCs on two or more SoCs to effectively act as a single NoC.

[0004] However, there are several performance challenges when interconnecting NoCs on different SoCs. For example, the address spaces of the individual NoCs may not have sufficient address apertures to directly route data to all destinations in other SoCs. In addition, NoC connections across the SoCs may be limited in both the horizontal and vertical cases. Further, due to the limited number of channel connections across the SoCs, deadlocks may occur in the case of forming loops. Summary of the Invention

[0005] One example is a multi-chip device that includes: a first integrated circuit (IC) that includes a first network-on-chip (NoC); and a second IC that includes a second NoC, wherein the first NoC and the second NoC are communicatively coupled. Further, when traffic is sent from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC and the second NoC to an address translation circuit in the second IC, wherein the address translation circuit is configured to perform address translation to identify a destination ID of the local destination and re-insert the traffic into the second NoC to reach the local destination.

[0006] Another example is a method that includes routing traffic between a first IC and a second IC in a multi-chip device. The method includes: routing traffic from a first ingress logic block coupled to a first NoC in the first IC to an address translation circuit coupled to a second NoC in the second IC, where the traffic is destined for a local destination in the second IC that is different from the address translation circuit; using the address translation circuit to perform address translation to identify a destination ID of the local destination of the traffic on the second IC; and using the destination ID to route the traffic from a second ingress logic block of the second NoC coupled to the address translation circuit to an egress logic block of the second NoC corresponding to the local destination.

[0007] Another example is a multi-chip device that includes: a first integrated circuit (IC) that includes a first network-on-chip (NoC) and a first redistribution circuit; and a second IC that includes a second NoC and a second redistribution circuit, where the first NoC and the second NoC are communicatively coupled. Additionally, when traffic is sent from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC to the first redistribution circuit in the first IC, where the traffic leaves the first NoC, traverses an inter-die connection between the first redistribution circuit and the second redistribution circuit, is inserted into the second NoC after reaching the second redistribution circuit, and is forwarded by the second NoC to the local destination. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To enable a detailed understanding of the manner in which the above-described features can be obtained, a more specific description of what has been briefly summarized above can be acquired by reference to specific examples of implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings only illustrate typical examples of implementations and should not be considered as limiting their scope.

[0009] Figure 1 is a block diagram of a SoC including a NoC according to one example.

[0010] Figures 2A to 2C illustrates a multi-chip device according to an example.

[0011] Figure 3 is a flowchart of a method for routing traffic between two NoCs in a multi-chip device according to an example.

[0012] Figure 4 illustrates a multi-chip device having an address translation circuit coupled to a NoC according to an example.

[0013] Figure 5 illustrates an address translation table according to an example.

[0014] Figure 6is a flowchart for routing traffic between two NoCs in a multi-chip device according to an example.

[0015] Figure 7 illustrates a multi-chip device having a traffic redistribution circuit connected to a NoC according to an example.

[0016] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that an element of an example may be advantageously incorporated into other examples. Detailed Description

[0017] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by like reference numerals throughout the drawings. It should be noted that the drawings are only intended to facilitate the description of the features. They are not intended as an exhaustive description of the present specification nor as a limitation on the scope of the claims. Additionally, the examples illustrated need not have all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or not so explicitly described.

[0018] Embodiments herein describe a multi-chip device including a plurality of SoCs having interconnected NoCs. Since the number of SoCs (or more generally, integrated circuits (ICs)) in a multi-chip device can vary (e.g., 2, 4, etc.), the NoCs on individual SoCs may not have sufficient address space to connect to various destinations on other SoCs. That is, the NoC on the first SoC may not have sufficient aperture to directly route to a destination connected to the NoC on the second SoC. Embodiments herein alleviate this problem by providing address translation circuitry in the SoC. The address translation circuitry establishes a hierarchy where traffic originating from the first SoC and destined for a destination on the second SoC is first routed to the address translation circuitry on the second SoC, which then performs address translation and reinserts the traffic onto the NoC in the second SoC but with a destination ID corresponding to a local destination. In this way, traffic originating from different SoCs can first be routed to the address translation circuitry on the local SoC. Thus, the SoC can have an additional address aperture only for routing traffic to the address translation circuitry on other SoCs, rather than having an address aperture for each destination in other SoCs in the multi-chip device.

[0019] The embodiments herein may also provide additional horizontal and vertical connections between NoCs in different SoCs by leveraging direct fabric connections. For example, the NoC in one SoC may have four horizontal channels, but due to the beachfront limitations of the SoC, only one or two of these channels may be connected to the horizontal channels in the NoC in an adjacent SoC. Instead of only using these direct NoC connections, the NoC compiler may alternatively route traffic to a traffic redistribution circuit in the same SoC. In one embodiment, a PL including a directional fabric connection to a programmable logic (PL) in an adjacent SoC may be used to implement the traffic redistribution circuit. These fabric connections may be used to route traffic to the PL in the adjacent SoC (e.g., another iteration of the traffic redistribution circuit), which then inserts the traffic onto the NoC on the adjacent SoC so that the traffic can reach its final destination.

[0020] The embodiments herein may also prevent deadlocks by establishing X-Y routing, where traffic originating from one SoC to different SoCs must first be routed in the X (horizontal) direction through an intermediate SoC and then in the Y (vertical) direction. This ensures that no loops are formed in the case where adjacent SoCs compete for the same resources.

[0021] Figure 1 is a block diagram of a SoC 100 including a NoC 105 according to an example. In one embodiment, a single IC is used to implement the SoC 100. In one embodiment, the SoC 100 includes a mixture of hardened logic and programmable logic. For example, hardened circuits may be used instead of programmable circuits to form the NoC 105, such that its footprint in the SoC 100 is reduced.

[0022] As shown, NoC 105 interconnects programmable logic (PL) blocks 125A, PL block 125B, processor 110, and memory 120. That is, NoC 105 can be used in SoC 100 to allow different hardened circuit elements and programmable circuit elements in SoC 100 to communicate. For example, PL block 125A can communicate with PL block 125B using one ingress logic block 115 (also referred to as a NoC master unit (NMU)) and communicate with processor 110 using another ingress logic block 115. However, in another embodiment, PL block 125A can communicate with both PL block 125B and processor 110 using the same ingress logic block 115 (assuming the endpoints use the same communication protocol). PL block 125A can send data to the respective egress logic blocks 140 (also referred to as NoC slave units or NoC subordinate units (NSUs)) for PL block 125B and processor 110, and the PL block and the processor can determine whether the data is intended for them based on the address (if using a memory-mapped protocol) or the destination ID (if using a streaming protocol).

[0023] PL block 125A can include an egress logic block 140 for receiving data sent by PL block 125B and processor 110. In one embodiment, a hardware logic block (or hardware logic circuit) can communicate with all other hardware logic blocks also connected to NoC 105, but in other embodiments, a hardware logic block can communicate only with a subset of other hardware logic blocks connected to NoC 105. For example, memory 120 may be able to communicate with PL block 125A but not with PL block 125B.

[0024] As described above, the ingress logic blocks 115 and egress logic blocks 140 can all communicate with PL blocks 125, processor 110, and memory 120 using the same communication protocol or different communication protocols. For example, PL block 125A can communicate with PL block 125B using a memory-mapped protocol, while processor 110 communicates with memory 120 using a streaming protocol. In one embodiment, NoC 105 can support multiple protocols.

[0025] In one embodiment, the SoC 100 is an FPGA that configures the PL block 125 according to a user design. That is, in this example, the FPGA includes both programmable logic blocks and hardened logic blocks. However, in other embodiments, the SoC 100 can be an ASIC that includes only hardened logic blocks. That is, the SoC 100 may not include the PL block 125. Even in this example, although the logic blocks are not programmable, the NoC 105 can still be programmable such that, for example, hardened logic blocks such as the processor 110 and the memory 120 can switch between different communication protocols, change the data width at the interface, or adjust the frequency.

[0026] In addition, Figure 1 Illustrated are the connections and various switches 135 (marked as boxes with "X") used by the NoC 105 to route packets between the ingress logic block 115 and the egress logic block ********

[0027] The positions of the PL block 125, the processor 110, and the memory 120 in the physical layout of the SoC 100 are merely an example of the arrangement of these hardware elements. In addition, the SoC 100 may include more hardware elements than shown. For example, the SoC 100 may include additional PL blocks, processors, and memories disposed at different locations on the SoC 100. In addition, the SoC 100 may include other hardware elements such as I / O modules and memory controllers, which may or may not be coupled to the NoC 105 using the corresponding ingress logic block 115 and egress logic block 140. For example, the I / O modules may be disposed around the periphery of the SoC 100.

[0028] Figures 2A to 2C Illustrated are multi-chip devices 200A - 200C according to an example. In one embodiment, the multi-chip devices 200A - 200C include Figure 1 two or more SoCs from the SoC 100 illustrated in. However, the multi-chip devices 200A - 200C are not limited to any specific SoC implementation. Generally, the multi-chip devices 200A - 200C can be formed from any number of ICs 205 that include the NoC 105.

[0029] Figure 2A Illustrated is the multi-chip device 200A that includes two vertically-connected ICs 205. Figure 2A Illustrated is a top view of the multi-chip device 200A, where the ICs 205 have been rotated 180 degrees relative to each other. That is, the ICs 205 are identical (e.g., generated from the same die), but one IC 205 has been rotated 180 degrees from the other IC 202. The arrows indicate the connections between the NoCs 105 in the two ICs 205.

[0030] In addition, IC 205 includes an address translation circuit 210. The NoC 105 on each IC 205 (or SOC) may not have enough address space to directly route to various destinations on another IC 205. Instead of routing traffic from a source on the NoC 105 in the first IC 205 to a destination connected to the NoC 105 in the second IC 205, the traffic is first routed to the address translation circuit 210 on the second IC 205. This is discussed in more detail in Figures 3 to 5 which is discussed in more detail in

[0031] Figure 2B Multi-chip device 200B is a multi-chip device including two IC 205s with a horizontal connection. Figure 2B FIG. illustrates a top view of multi-chip device 200B, where the IC 205s have the same orientation. Similar to Figure 2A as in Figure 2B the IC 205s in Figure 2A are the same (e.g., generated from the same die), but different from

[0032] here, the IC 205s have the same orientation. The arrows indicate the connections between the NoC 105s in the two IC 205s.

[0033] Figure 2C Multi-chip device 200C is a multi-chip device including two pairs of ICs with both vertical and horizontal connections. That is, device 200C includes a first pair of ICs containing IC 205s and a second pair of ICs containing IC 220s. Figure 2C FIG. illustrates a top view of multi-chip device 200C, where the IC 205s have been rotated 180 degrees relative to each other, and the IC 220s have been rotated 180 degrees relative to each other. In one embodiment, Figure 2C the IC 205s in

[0034] In one embodiment, each of the ICs 205 and 220 in the multi-chip device 200C may send traffic to each other using a direct NoC connection. That is, the ICs 205, 220 may use the NoC 105 to send traffic to any one of the three other ICs 205, 220. However, since there are four ICs in Figure 2C the, the address space required to directly route data from the NoC 105 of one IC to all three other ICs is even larger. To mitigate this, the ICs 205 and 220 include address translation circuitry 210 that provides a routing hierarchy where inter-IC traffic may first be routed to the address translation circuitry 210, which then performs address translation to identify the traffic and forward it to a local destination.

[0035] In addition, when routing traffic from a non-adjacent IC, the data may first be routed to the address translation circuitry 210 in an intermediate IC and then to the address translation circuitry 210 in the destination IC. For example, if the lower left IC205 of the device 200C wants to route data to a destination in the upper right IC 220, the IC 205 may first use its NoC to route the traffic to the address translation circuitry 210 in the lower right IC 220, which in turn routes the traffic to the address translation circuitry 210 in the upper right IC220. Then, the address translation circuitry 210 may forward the traffic to a local destination.

[0036] Alternatively, the lower left IC 205 may alternatively send the traffic through the NoC 105 in the lower right IC 220 and into the NoC 105 in the upper right IC 220 without the data being routed through the address translation circuitry 210 in the lower right IC 220. Then, the address translation circuitry 210 in the upper right IC 220 forwards the traffic to a local destination. In this case, the NoC 105 has an address aperture for the address translation circuitry 210 in the upper right IC 220 and may thus use the NoC105 to directly route the traffic there without the help of the address translation circuitry 210 in the intermediate IC.

[0037] Figure 3 is a flowchart of a method 300 for routing traffic between two NoCs in a multi-chip device according to an example. For ease of explanation, method 300 is discussed in connection with Figure 4 which illustrates a multi-chip device 400 according to an example having address translation circuitry connected to a NoC.

[0038] At block 305, an ingress logic block on a first IC routes traffic to address translation circuitry on a second IC in the multi-chip device. Using Figure 4As an example, client A on IC 405A wants to send traffic to a destination on IC 405B. Client A can be a PL, a processor, a memory, etc. in IC 405A. Additionally, ICs 405A - 405D can be related as Figure 2C shown, where ICs 405A and 405D are identical but rotated 180 degrees with respect to each other, and ICs 405B and 405C are mirror die of ICs 405A and 405D but rotated 180 degrees with respect to each other. However, this is not required. In other embodiments, the ICs 405 can all be different ICs, but their NoCs are interconnected. However, coupling ICs with the same (or mirror) layout together simplifies the process of forming a multi - chip device, but this is not required.

[0039] As shown, client A has four ingress logic blocks for inserting traffic into the NoC of IC 405A. In this example, it is assumed that the NoC in IC 405A does not have enough address space to directly route data to the destination in IC 405B. That is, ingress logic block 115A may not know the destination ID of the destination in IC 405B. However, the NoC in IC 405A does include an address aperture for the address translation circuit 210 in IC 405B. In one embodiment, the destination ID of the address translation circuit 210 in IC 405B can be stored in a remapping register for the NoC in IC 405A. Remapping registers provide flexibility for NoC addressing and are typically used for debugging purposes or in cases where there are errors. However, remapping registers can also be used when the ICs 405 are placed in a multi - chip device to provide the destination ID to destinations such as the address translation circuit 210 in other ICs.

[0040] In Figure 4 this case, the NoC in IC 405A routes the traffic to NoC connections 410, which allow the NoC in IC 405A to communicate with the NoC in IC 405B. In one embodiment, the NoC connections 410 are located at the periphery of the IC 405 and provide a direct connection such that the traffic does not first propagate through any input / output elements (e.g., transceivers) on the IC 405. In one embodiment, the NoC connections 410 can use connections in an interposer or substrate on which the IC 405 is placed. That is, the NoC connections 410 can be attached to connections or traces in the interposer that communicatively connect the two NoC connections 410. In one embodiment, the NoC connections 410 are referred to as inter - die connections for coupling two NoCs together.

[0041] In one embodiment, the destination ID of circuit 210 is used to route traffic from client A in IC 405A to circuit 210 in IC 405B. For example, the destination ID of circuit 210 can be used to route each packet or flit through switches in the NoC in ICs 405A and 405B. The NoC compiler programs the switches to know the next hop associated with the destination ID. In this way, traffic can proceed along the first path 415 through the switches in the NoC in both ICs 405A and 405B until it reaches the exit logic block 140A of the address translation circuit 210.

[0042] Returning to method 300, at block 310, the address translation circuit performs address translation to identify the local destination of the traffic on the second IC. That is, in addition to including the destination IC for routing the traffic through the NoC, the traffic can also include an address that the address translation circuit can then use to identify the local destination of the traffic on the IC. This address can be a source address or a destination address.

[0043] Referring again to Figure 4 , the address translation circuit 210 can perform address translation to determine the local destination of the traffic. That is, the result of the address translation is the destination ID of the local destination of the traffic on IC 405B. The address translation circuit 210 can then re-insert the traffic into the NoC using the ingress logic block 115B, but this time the traffic includes the destination ID of the local destination.

[0044] At block 315, the NoC on the second IC routes the traffic from the NoC ingress logic block on the second IC to the egress logic block on the second IC corresponding to the local destination. This is illustrated in Figure 4 where the NoC in IC 405B routes the traffic to the destination, as shown by the second path 420, where the traffic is received by the egress logic block 140B of the destination.

[0045] In this way, the NoC on IC 405A (or more specifically, the address aperture in the NoC) does not have to be programmed to identify the destination IDs of the local destinations on IC 405B. Instead, the NoC in IC 405A can be programmed with an address aperture for the address translation circuit 210, which then identifies the destination IDs of the various destinations in IC 405B. This can greatly reduce the number of address apertures required in each NoC in the NoC in IC 405 when forming a multi-chip device.

[0046] In one embodiment, the address translation circuit 210 is implemented in the PL in the IC 405. However, in another embodiment, the address translation circuit 210 can be hardened logic in the IC 405. While implementing the address translation circuit 210 using the PL provides greater flexibility (e.g., it can scale with the number of ICs in a multi-chip device), implementing the circuit 210 in hardened logic may require less space in the IC.

[0047] At block 320, the NoCs in the first IC and the second IC will route responses from the egress logic block corresponding to the local destination on the second IC to the ingress logic block on the first IC. Referring again to Figure 4 , the egress logic block 140B for the local destination on the IC 405B can route the response directly to the ingress logic block 115A of client A on the IC 405A. Notably, the response does not have to be routed through the address translation circuit 210 on the IC 405B (or any address translation circuit on the IC 405A). The known destination ID of client A can be used to route the response, and thus, no additional address translation is required.

[0048] Method 300 can also be used to route traffic between ICs that are not direct neighbors in the IC. That is, method 300 can be used to route traffic from Figure 4 IC 405A in to IC 405C, which are not directly connected to each other. If the IC 405A has sufficient available address aperture, the IC 405A can insert traffic flowing from its NoC to the NoC in the IC 405B, from the NoC in the IC 405B to the NoC in the IC 405C, and from the NoC in the IC 405C to the address translation circuit in the IC 405C. As discussed above, the address translation circuit in the IC 405C can perform address translation and re-insert the traffic into the NoC in the IC 405C so that it can reach the local destination.

[0049] However, the NoC in the IC 405A may not have sufficient address aperture to route the traffic to the address translation circuit in the IC 405C. In this case, the traffic can be routed to as Figure 4The address translation circuit 210 in the illustrated IC 405B. The address translation circuit 210 can then identify the destination ID of the address translation circuit in IC 405C, and then re-insert the traffic into the NoC in IC 405B, which then routes the traffic to the NoC in IC 405C and then to its address translation circuit, which performs additional address translation to route the traffic to a local destination on IC 405C. Thus, in this example, traffic flowing between non-adjacent ICs in a multi-chip device can be routed through the address translation circuit in an intermediate IC (e.g., IC 405B in this example), or can bypass the address translation circuit in the intermediate IC and instead rely only on the address translation circuit in the destination IC (e.g., IC 405C).

[0050] Figure 5 Illustrates address translation table 505 according to an example. As shown, address translation table 505 is included within address translation circuit 210. For example, address translation table 505 can be stored in a memory within address translation circuit 210.

[0051] Address translation circuit 210 receives traffic (labeled REQ ADDR A) at egress logic block 140. Address translation circuit 210 uses ADDR A in the request to index into table 505 to identify the entry corresponding to that address. In this example, ADDR A is the source address.

[0052] Table 505 then returns the destination address (ADDR B) and destination ID (5) for the local destination. Using this information, address translation circuit 210 re-inserts the traffic into the NoC using ingress logic block 115, which has the destination ID (5) of destination circuit 510. The NoC then routes the traffic to egress logic block 140 of destination circuit 510.

[0053] Once received, egress logic block 140 of destination circuit 510 can convey a response to the ingress logic block that originated the traffic (i.e., sent REQ ADDR A to address translation circuit 210). Note that this response can bypass address translation circuit 210. In other words, the response can be routed without having to pass through the address translation circuit.

[0054] Figure 6 Is a flowchart of method 600 for routing traffic between two NoCs in a multi-chip device according to an example. For ease of explanation, in conjunction with Figure 7 Discussing method 600, the figure illustrates a multi-chip device according to an example having a redistribution circuit connected to a NoC. In Figure 6 And Figure 7In this case, it is assumed that the multi-chip device does not have sufficient NoC connections (e.g., inter-die NoC-to-NoC connections) to facilitate the traffic that one IC wants to send to another IC.

[0055] At block 605, the NoC ingress logic block on the first IC routes traffic to the egress logic block on the first IC that corresponds to the redistribution circuit. In one implementation, the redistribution circuit is on the same IC as the egress logic block that inserts traffic into the NoC. For example, Figure 7 Illustrated are three ingress logic blocks 115B, 115C, and 115D that insert traffic received at egress logic blocks 140A, 140B, and 140C corresponding to the redistribution circuit 710A into the NoC of the IC 705A. In this case, "X" indicates a horizontal channel (e.g., virtual channel) in the NoC that is not connected to the corresponding horizontal channel in the NoC of the IC 705B. For example, there may not be enough interface area in the IC 705 to have a NoC connection for each horizontal channel in the horizontal channels. In this implementation, only one horizontal channel in the horizontal channels uses the corresponding NoC connection to directly connect to the horizontal channel in the NoC of the IC 705B.

[0056] However, in addition to the NoC connections, the ICs 705 also have other connections to each other. In this example, the PLs in the ICs have PL-to-PL connections (also referred to as fabric-to-fabric connections) between the ICs 705. These connections are illustrated as indirect paths 720 that provide indirect communication between the NoCs in two different ICs as compared to the direct NoC path 715. In any case, traffic can flow between the NoCs in the ICs 705A and 705B via the indirect path 720 and the direct NoC path 715 in parallel or simultaneously.

[0057] Returning to Figure 6 , at block 610, the redistribution circuit forwards the traffic received from the NoC to the redistribution circuit on the second IC using, for example, a PL-to-PL connection. Although the implementations herein describe using PL-to-PL connections, other multi-chip devices may have different types of inter-die connections, such as memory-to-memory connections. Thus, the implementations herein are not limited to using PL-to-PL connections to facilitate Figure 7 the indirect path 720 illustrated in

[0058] At block 615, the redistribution circuitry in the second IC routes traffic from the NoC ingress logic block on the second IC to the egress logic block on the second IC corresponding to the destination of the traffic. In other words, traffic leaves the NoC in the first IC and is forwarded to the redistribution circuitry in the second IC, which then inserts the traffic into the NoC in the second IC where the traffic is routed to a local destination. As an example, Figure 7 Illustrates three NoC traffic flows redirected through the indirect path 720 between the redistribution circuits 710A and 710B. The redistribution circuit 710B then uses three ingress logic blocks 115E, 115F, and 115G to insert these three traffic flows into the NoC on the IC 705B, which in turn routes the traffic to the egress logic blocks 140D, 140E, and 140F corresponding to the destinations of these three traffic flows in the IC 705B.

[0059] In contrast, traffic inserted by the ingress logic block 115A in the IC 705A can use the direct NoC path 715 (which uses NoC connections) to send the traffic directly from the NoC in the IC 705A to the NoC in the IC 705B where the traffic is routed to the egress logic block 140G at the local destination. Thus, this traffic flow bypasses the redistribution circuits 710A and 710B.

[0060] Although not shown, the redistribution circuit 710 and the indirect path 720 can be used in conjunction with Figures 3 to 5 the address translation circuitry discussed in. For example, the PL in the IC 705B can include address translation circuitry. In this case, the traffic flows inserted into the NoC by the ingress logic blocks 115B, 115C, and 115D still go to the redistribution circuit 710A and these traffic flows then use the indirect path 720 at this redistribution circuit to reach the IC 705B. However, instead of being immediately inserted into the NoC in the IC 705B, the address translation circuitry in the IC 705B can perform the address translation discussed above to identify the local destinations for the three traffic flows. Once the translation is performed, the three traffic flows are inserted into the NoC in the IC 705B.

[0061] Similarly, the traffic flow inserted into the NoC in the IC 705A by the ingress logic block 115A can still use the direct NoC path 715 to reach the IC 705B, but instead of the traffic going directly to the local destination, it is first routed to the address translation circuitry and then routed to its local destination, as illustrated in Figure 4 . Thus, Figures 3 to 5 the address translation discussed in can be used in conjunction with Figure 6 and Figure 7 the indirect path illustrated in, or these concepts can be used independently of each other.

[0062] In one embodiment, the redistribution circuitry 710 is implemented in the PL in the IC 705. However, in another embodiment, the redistribution circuitry 710 can be hardened logic in the IC 705 as long as the hardened logic is accessible to the inter-die connections. While implementing the redistribution circuitry 710 using the PL provides greater flexibility (e.g., can scale with the number of ICs in a multi-chip device), implementing the redistribution circuitry 710 in hardened logic may require less space in the IC.

[0063] In yet another embodiment, X-Y routing can be used to avoid deadlocks between the ICs in a multi-die device. Using Figure 7 As an example, an IC may attempt to send data using an X mode, where for example, IC 705A is attempting to send traffic to IC 705C while IC 705B is attempting to send traffic to IC 705D. IC 705A may wait for resources to be released in IC 705B in order to reach IC 705C, while IC 705B waits for resources to be released in IC 705C to reach IC 705D, and so on. In some scenarios, four ICs 705 may be waiting for resources, which can lead to a deadlock. In one embodiment, the deadlock is avoided by using an X-Y routing strategy, where the IC first routes in the X (horizontal) direction (e.g., the first dimension in the array), and then in the Y (vertical) direction (e.g., the dimension perpendicular to the first dimension in the array). This breaks any deadlock.

[0064] Previously, reference has been made to embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Instead, any combination of the described features and elements (whether or not they relate to different embodiments) is contemplated for implementing and practicing the contemplated embodiments. Additionally, although the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the scope of this disclosure. Thus, the foregoing aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0065] As will be understood by those skilled in the art, the embodiments disclosed herein may be embodied as a system, method, or computer program product. Accordingly, aspects may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Additionally, aspects may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0066] Any combination of one or more computer-readable media may be utilized. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0067] A computer-readable signal medium may include a propagated data signal having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0068] The program code embodied on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0069] Computer program code for operating on aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages (such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages (such as the "C" programming language or similar programming languages). The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0070] Aspects of the present disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0071] These computer program instructions can also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0072] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented method, such that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0073] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various examples of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by combinations of dedicated hardware and computer instructions.

[0074] While the foregoing is directed to specific examples, other and additional examples can be devised without departing from the basic scope of the present invention, and the scope of the present invention is determined by the appended claims.

Claims

1. A multi-chip device, comprising: A first integrated circuit (IC), the first IC including a first on-chip network (NoC); And A second IC, the second IC including a second NoC, wherein the first NoC and the second NoC are communicatively coupled, Wherein when traffic is sent from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC and the second NoC to an address conversion circuit in the second IC, wherein the address conversion circuit is configured to perform address conversion to identify a destination ID of the local destination and re-insert the traffic into the second NoC to reach the local destination.

2. The multi-chip device according to claim 1, wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC that is coupled to the second NoC, wherein the first NoC connection and the second NoC connection are disposed at a periphery of the first IC and the second IC.

3. The multi-chip device according to claim 1, wherein the first IC includes an ingress logic block that inserts the traffic into the first NoC, and the second IC includes an egress logic block that receives the traffic from the second NoC and forwards the traffic to the local destination, wherein after receiving the traffic, the egress logic block is configured to send a response to the ingress block, the response being routed via the first NoC and the second NoC without passing through the address conversion circuit.

4. The multi-chip device according to claim 1, wherein the first IC includes a first redistribution circuit coupled to the first NoC, and the second IC includes a second redistribution circuit coupled to the second NoC, Wherein the multi-chip device is configured to: when sending traffic from the first NoC to a local destination coupled to the second NoC in the second IC, route the traffic to the first redistribution circuit, at which the traffic leaves the first NoC, traverses an inter-die connection between the first redistribution circuit and the second redistribution circuit, is inserted into the second NoC after reaching the second redistribution circuit, and is forwarded by the second NoC to the local destination.

5. The multi-chip device according to claim 4, wherein the inter-die connection is at least one of a programmable logic (PL) to PL connection or a fabric to fabric connection.

6. The multi-chip device according to claim 1, further comprising: A third IC, the third IC including a third NoC communicatively coupled to the first NoC and the second NoC, wherein the first IC, the second IC, and the third IC are arranged in an array defining a first dimension and a second dimension perpendicular to the first dimension.

7. The multi-chip device according to claim 6, wherein when routing traffic to a non-adjacent IC, the first NoC, the second NoC, and the third NoC are configured to route first in a first dimension and then in the second dimension to prevent deadlocks.

8. A multi-chip device, comprising: a first integrated circuit (IC), the first IC including a first network-on-chip (NoC) and a first redistribution circuit; and a second IC, the second IC including a second NoC and a second redistribution circuit, wherein the first NoC and the second NoC are communicatively coupled, wherein when traffic is sent from the first NoC to a local destination coupled to the second NoC in the second IC, the traffic is first routed via the first NoC to the first redistribution circuit in the first IC, at the first redistribution circuit, the traffic leaves the first NoC, traverses an inter-die connection between the first redistribution circuit and the second redistribution circuit, is inserted into the second NoC after reaching the second redistribution circuit, and is forwarded by the second NoC to the local destination.

9. The multi-chip device according to claim 8, wherein the inter-die connection is at least one of a programmable logic (PL) to PL connection or a fabric to fabric connection.

10. The multi-chip device according to claim 8, wherein the first IC includes a first NoC connection that directly couples the first NoC to a second NoC connection in the second IC that is coupled to the second NoC, wherein the inter-die connection, the first NoC connection, and the second NoC connection can be used in parallel to send traffic between the first NoC and the second NoC.

11. The multi-chip device according to claim 8, wherein when the traffic is sent from the first NoC to the local destination coupled to the second NoC in the second IC, the traffic is first routed to an address translation circuit in the second IC, wherein the address translation circuit is configured to perform address translation to identify a destination ID of the local destination.

12. The multi-chip device according to any one of claims 1 to 11, wherein the address translation includes: Using an address in the traffic received from the first IC to index into a translation table to identify the destination ID of the local destination.

13. A method for routing traffic between a first IC and a second IC in a multi-chip device, comprising: routing traffic from a first ingress logic block coupled to a first NoC in the first IC to an address translation circuit coupled to a second NoC in the second IC, wherein the traffic is destined for a local destination in the second IC that is different from the address translation circuit; using the address translation circuit to perform address translation to identify a destination ID of the local destination of the traffic on the second IC; and Use the destination ID to route the traffic from the second ingress logic block of the second NoC coupled to the address translation circuit to the egress logic block of the second NoC corresponding to the local destination.

14. The method according to claim 13, further comprising: Route a response from the egress logic block on the second IC to the first ingress logic block on the first IC without the response passing through the address translation circuit.

15. The method according to claim 13, further comprising, before routing the traffic to the address translation circuit: Route the traffic to a first redistribution circuit in the first IC, where the traffic leaves the first NoC; and Route the traffic through an inter-die connection between the first redistribution circuit and a second redistribution circuit in the second IC.

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