Memory device and program operation thereof

Abstract

In certain aspects, a memory device includes a plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to program a selected memory cell among the memory cells in a selected memory string among the plurality of memory strings and inhibit a non-selected memory cell among the memory cells in a non-selected memory string among the plurality of memory strings in a program operation. The peripheral circuit includes a word line driver configured to turn off a DSG transistor in the non-selection string in a pre-pulse period and a post-pulse period in a first cycle of the program operation; and turning on a DSG transistor in the non-selective string in at least one of a pre-pulse period or a post-pulse period in a second cycle of the program operation after the first cycle.

Description

BACKGROUND OF THE INVENTION

[0001] The present disclosure relates to a storage device and an operation method thereof.

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. For NAND flash memory, an erase operation can be performed at the block level, and a programming operation or a reading operation can be performed at the page level. SUMMARY OF THE INVENTION

[0003] In one aspect, a storage device includes a plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the plurality of memory strings. The peripheral circuit is configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings and inhibit non-selected memory cells in non-selected memory strings among the plurality of memory strings. The peripheral circuit includes a word line driver configured to: turn off the DSG transistors in the non-selected memory strings during a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn on the DSG transistors in the non-selected memory strings during at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle.

[0004] In some embodiments, the programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

[0005] In some embodiments, the word line driver is further configured to: turn off the SSG transistors in the non-selected memory strings during a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn on the SSG transistors in the non-selected memory strings during at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation.

[0006] In some embodiments, the word line driver is further configured to: turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation.

[0007] In some embodiments, the word line driver is further configured to: turn off the DSG transistor and the SSG transistor in the unselected memory string during a pre-pulse period in a second cycle of the programming operation; and turn on the DSG transistor and the SSG transistor in the unselected memory string during a post-pulse period in the second cycle of the programming operation.

[0008] In some embodiments, the word line driver is further configured to: turn on the DSG transistor and the SSG transistor in the unselected memory string during a pre-pulse period in a second cycle of the programming operation; and turn off the DSG transistor and the SSG transistor in the unselected memory string during a post-pulse period in the second cycle of the programming operation.

[0009] In some embodiments, the DSG transistor in the selected memory string is electrically isolated from the DSG transistor in the unselected memory string.

[0010] In another aspect, a method for operating a memory device is provided. The memory device includes a plurality of memory strings, and each memory string of the plurality of memory strings includes a DSG transistor, a memory cell, and an SSG transistor. During a pre-pulse period and a post-pulse period in a first cycle of the programming operation, the DSG transistor in the unselected memory string among the plurality of memory strings is turned off. During at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle, the DSG transistor in the unselected memory string is turned on.

[0011] In some embodiments, the programming operation is ISPP, and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

[0012] In some embodiments, during a pre-pulse period and a post-pulse period in a first cycle of the programming operation, the SSG transistor in the unselected memory string is turned off; and during at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation, the SSG transistor in the unselected memory string is turned on.

[0013] In some embodiments, during a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned off; and during a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned off.

[0014] In some embodiments, during the pre-pulse period of the second cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned off; and during the post-pulse period of the second cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned on.

[0015] In some embodiments, during the pre-pulse period of the second cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned on; and during the post-pulse period of the second cycle of the programming operation, the DSG transistor and the SSG transistor in the unselected memory string are turned off.

[0016] In some embodiments, the DSG transistor in the selected memory string is electrically isolated from the DSG transistor in the unselected memory string.

[0017] In another aspect, a system includes a storage device configured to store data, and a memory controller coupled to the storage device and configured to control the storage device. The storage device includes a plurality of memory strings, each of the plurality of memory strings including a DSG transistor, a memory cell, and an SSG transistor, and peripheral circuitry coupled to the plurality of memory strings. The peripheral circuitry is configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings, and inhibit non-selected memory cells in non-selected memory strings among the plurality of memory strings. The peripheral circuitry includes a word line driver configured to: turn off the DSG transistor in the unselected memory string during a pre-pulse period and a post-pulse period of a first cycle of the programming operation; and turn on the DSG transistor in the unselected memory string during at least one of a pre-pulse period or a post-pulse period of a second cycle of the programming operation after the first cycle.

[0018] In some embodiments, the programming operation is ISPP, and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

[0019] In some embodiments, the word line driver is further configured to: turn off the SSG transistor in the unselected memory string during a pre-pulse period and a post-pulse period of the first cycle of the programming operation; and turn on the SSG transistor in the unselected memory string during at least one of a pre-pulse period or a post-pulse period of the second cycle of the programming operation.

[0020] In some embodiments, the word line driver is further configured to: turn off the DSG transistor and the SSG transistor in the unselected memory string during a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn off the DSG transistor and the SSG transistor in the unselected memory string during a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation.

[0021] In some embodiments, the word line driver is further configured to: turn off the DSG transistor and the SSG transistor in the unselected memory string during a pre-pulse period in a second cycle of the programming operation; and turn on the DSG transistor and the SSG transistor in the unselected memory string during a post-pulse period in the second cycle of the programming operation.

[0022] In some embodiments, the word line driver is further configured to: turn on the DSG transistor and the SSG transistor in the unselected memory string during a pre-pulse period in a second cycle of the programming operation; and turn off the DSG transistor and the SSG transistor in the unselected memory string during a post-pulse period in the second cycle of the programming operation.

[0023] In some embodiments, the DSG transistor in the selected memory string is electrically separated from the DSG transistor in the unselected memory string.

[0024] In some embodiments, the storage device is a NAND flash memory device.

[0025] In yet another aspect, a storage device includes a plurality of memory strings, each of the plurality of memory strings including a DSG transistor, a memory cell, and an SSG transistor, and a peripheral circuit coupled to the plurality of memory strings. The peripheral circuit is configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings and inhibit unselected memory cells in unselected memory strings among the plurality of memory strings. The peripheral circuit includes a word line driver configured to: turn on the DSG transistor in the unselected memory string during only one of a pre-pulse period or a post-pulse period in a first cycle of the programming operation; and turn on the DSG transistor in the unselected memory string during only one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle.

[0026] In some embodiments, the programming operation is ISPP, and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

[0027] In some embodiments, the word line driver is further configured to turn on the SSG transistors in the unselected memory strings during only one of the pre-pulse period or the post-pulse period in the first cycle of the programming operation; and turn on the SSG transistors in the unselected memory strings during only one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation.

[0028] In some embodiments, the word line driver is further configured to turn off the DSG transistors and the SSG transistors in the unselected memory strings during the verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation; and turn off the DSG transistors and the SSG transistors in the unselected memory strings during the verification period between the pre-pulse period and the post-pulse period in the second cycle of the programming operation.

[0029] In some embodiments, turn on the DSG transistors and the SSG transistors in the unselected memory strings during the pre-pulse period but not during the post-pulse period in the first cycle of the programming operation; and turn on the DSG transistors and the SSG transistors in the unselected memory strings during the pre-pulse period but not during the post-pulse period in the second cycle of the programming operation.

[0030] In some embodiments, the word line driver is further configured to turn on the DSG transistors and the SSG transistors in the unselected memory strings during the post-pulse period but not during the pre-pulse period in the first cycle of the programming operation; and turn on the DSG transistors and the SSG transistors in the unselected memory strings during the post-pulse period but not during the pre-pulse period in the second cycle of the programming operation.

[0031] In some embodiments, the DSG transistors in the selected memory strings are electrically separated from the DSG transistors in the unselected memory strings.

[0032] In yet another aspect, a method for operating a memory device is provided. The memory device includes a plurality of memory strings, and each of the plurality of memory strings includes a DSG transistor, a memory cell, and an SSG transistor. Turn on the DSG transistors in the unselected memory strings among the plurality of memory strings during only one of the pre-pulse period or the post-pulse period in the first cycle of the programming operation. Turn on the DSG transistors in the unselected memory strings during only one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation after the first cycle.

[0033] In some embodiments, the programming operation is ISPP, and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

[0034] In some embodiments, in only one of the pre-pulse period or the post-pulse period in the first cycle of the programming operation, turn on the SSG transistor in the non-selected memory string; and in only one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation, turn on the SSG transistor in the non-selected memory string.

[0035] In some embodiments, in the verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string; and in the verification period between the pre-pulse period and the post-pulse period in the second cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string.

[0036] In some embodiments, in the pre-pulse period but not in the post-pulse period in the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string; and in the pre-pulse period but not in the post-pulse period in the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string.

[0037] In some embodiments, in the post-pulse period but not in the pre-pulse period in the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string; and in the post-pulse period but not in the pre-pulse period in the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string.

[0038] In some embodiments, the DSG transistor in the selected memory string is electrically separated from the DSG transistor in the non-selected memory string.

[0039] In yet another aspect, a system includes a storage device configured to store data, and a memory controller coupled to the storage device and configured to control the storage device. The storage device includes a plurality of memory strings, each of the plurality of memory strings including a DSG transistor, a memory cell, and an SSG transistor, and a peripheral circuit coupled to the plurality of memory strings. The peripheral circuit is configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings, and inhibit a non-selected memory cell in a non-selected memory string among the plurality of memory strings. The peripheral circuit includes a word line driver configured to: turn on the DSG transistor in the non-selected memory string in only one of a pre-pulse period or a post-pulse period in a first cycle of the programming operation; and turn on the DSG transistor in the non-selected memory string in only one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle.

[0040] In yet another aspect, a storage device includes a plurality of memory strings, each of the plurality of memory strings including a DSG transistor, a memory cell, and an SSG transistor, and a peripheral circuit coupled to the plurality of memory strings. The peripheral circuit is configured to: in a programming operation, apply a select voltage to a first DSG transistor in a first memory string among the plurality of memory strings and apply a deselect voltage to a second DSG transistor in a second memory string among the plurality of memory strings in a pre-pulse period and a post-pulse period in a first cycle of the programming operation. The peripheral circuit is further configured to: in the programming operation, apply the select voltage to the first DSG transistor in the first memory string and apply the select voltage to the second DSG transistor in the second memory string in at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle.

[0041] In some embodiments, the peripheral circuit is further configured to: apply the select voltage to a first SSG transistor in the first memory string and apply the deselect voltage to a second SSG transistor in the second memory string in a verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation. In some embodiments, the peripheral circuit is further configured to: apply the select voltage to a first SSG transistor in the first memory string and apply the deselect voltage to a second SSG transistor in the second memory string in a verification period between the pre-pulse period and the post-pulse period in the second cycle of the programming operation.

[0042] In some embodiments, the select voltage is a positive voltage and the deselect voltage is a ground voltage.

[0043] In another aspect, a memory device includes a plurality of memory strings, each of the plurality of memory strings including a DSG transistor, a memory cell, and an SSG transistor, and a peripheral circuit coupled to the plurality of memory strings. The peripheral circuit is configured to: in a programming operation, apply a select voltage to a first DSG transistor in a first memory string of the plurality of memory strings during a pre-pulse period and a post-pulse period in a first cycle of the programming operation, and apply a deselect voltage to a second DSG transistor in a second memory string of the plurality of memory strings during one of the pre-pulse period or the post-pulse period in the first cycle of the programming operation. The peripheral circuit is further configured to: in the programming operation, apply the select voltage to the first DSG transistor in the first memory string during a pre-pulse period and a post-pulse period in a second cycle of the programming operation after the first cycle; and apply the deselect voltage to the second DSG transistor in the second memory string during one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation.

[0044] In some embodiments, the peripheral circuit is further configured to: during a verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation, apply the select voltage to a first SSG transistor in the first memory string, and apply the deselect voltage to a second SSG transistor in the second memory string. In some embodiments, the peripheral circuit is further configured to: during a verification period between the pre-pulse period and the post-pulse period in the second cycle of the programming operation, apply the select voltage to a first SSG transistor in the first memory string, and apply the deselect voltage to a second SSG transistor in the second memory string.

[0045] In some embodiments, the select voltage is a positive voltage and the deselect voltage is a ground voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings incorporated herein and forming a part of the specification illustrate some aspects of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable a person skilled in the relevant art to make and use the present disclosure.

[0047] Figure 1 A schematic diagram of a memory device including a peripheral circuit, according to some aspects of the present disclosure, is shown.

[0048] Figure 2 A side view of a cross-section of a memory cell array including NAND memory strings, according to some aspects of the present disclosure, is shown.

[0049] Figure 3A block diagram of a memory device including a memory cell array and peripheral circuits in accordance with some aspects of the present disclosure is shown.

[0050] Figure 4A and Figure 4B A schematic diagram of a plurality of three-dimensional (3D) NAND memory strings in accordance with some aspects of the present disclosure is shown.

[0051] Figure 5A and Figure 5B A waveform of a word line voltage applied to a select word line during a programming operation in accordance with some aspects of the present disclosure is shown.

[0052] Figure 6 A timing diagram of a programming operation having a plurality of cycles is shown.

[0053] Figure 7 A timing diagram of a programming operation having a plurality of cycles in accordance with some aspects of the present disclosure is shown.

[0054] Figure 8 A timing diagram of another programming operation having a plurality of cycles in accordance with some aspects of the present disclosure is shown.

[0055] Figure 9 A timing diagram of yet another programming operation having a plurality of cycles in accordance with some aspects of the present disclosure is shown.

[0056] Figure 10 A timing diagram of still another programming operation having a plurality of cycles in accordance with some aspects of the present disclosure is shown.

[0057] Figure 11 A flowchart of a method for programming a memory device in accordance with some aspects of the present disclosure is shown.

[0058] Figure 12 A flowchart of another method for programming a memory device in accordance with some aspects of the present disclosure is shown.

[0059] Figure 13 A block diagram of a system having a memory device in accordance with some aspects of the present disclosure is shown.

[0060] Figure 14A A diagram of a memory card having a memory device in accordance with some aspects of the present disclosure is shown.

[0061] Figure 14B A diagram of a solid state drive (SSD) having a memory device in accordance with some aspects of the present disclosure is shown.

[0062] Figure 15 Simulation results of the effect of post-pulse channel cleaning on channel potential in accordance with some aspects of the present disclosure are shown.

[0063] The present disclosure will be described with reference to the accompanying drawings. Detailed Description

[0064] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can, at least in part, depend on context and can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey a singular usage or to convey a plural usage, at least in part, depending on context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can, at least in part, depending on context, allow for the existence of other factors that are not necessarily explicitly described.

[0065] A storage device, such as a NAND flash device, can store more than a single bit of information per storage cell using multiple states to increase storage capacity and reduce cost per bit. The programming operation of a NAND flash device involves multiple programming cycles and verification periods. To save programming time (t PROG ), the industry has mainly focused on how to reduce the number of verification periods. On the other hand, for each verification period, after the corresponding programming cycle, a residual channel potential may remain in the channels of multiple non-selected memory strings, and by applying a verification voltage pulse, a hot carrier injection (HCI) effect may occur in the channels of multiple non-selected memory strings, both of which can have an adverse impact on subsequent read operations, e.g., by increasing the failure bit count (FBC). Thus, it is common practice to turn on the channels of multiple non-selected memory strings before and after applying a verification voltage pulse, respectively, in a so-called "pre-pulse period" and "post-pulse period" during each verification period to "clean" the channels. However, these operations during the pre-pulse period and the post-pulse period extend the duration of each verification period, thus becoming a bottleneck in saving programming time.

[0066] To solve one or more of the above problems, the present disclosure provides various "per-cycle" channel cleaning schemes that do not clean the channels of a plurality of non-selected memory strings during the pre-pulse period and the post-pulse period of each verification period, thereby saving programming time. In some embodiments, channel cleaning is skipped during the pre-pulse period and the post-pulse period of the verification period in the early cycles, e.g., performed only during the pre-pulse period and / or the post-pulse period of the verification period in the end cycle (i.e., the last verification period). In some embodiments, in each verification period, channel cleaning is performed only in one of the pre-pulse period and the post-pulse period, rather than in both. The loop channel cleaning scheme disclosed herein can reduce programming time while still mitigating the adverse effects caused by residual channel potential and HCI effects.

[0067] Figure 1 FIG. shows a schematic circuit diagram of a memory device 100 including peripheral circuits in accordance with some aspects of the present disclosure. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, where the memory cells 106 are provided in the form of an array of a plurality of NAND memory strings 108, and each of the plurality of memory strings 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of serially coupled and vertically stacked memory cells 106. Each memory cell 106 may hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell having a floating-gate transistor or a charge-trapping type memory cell having a charge-trapping transistor.

[0068] In some embodiments, each memory cell 106 is a SLC, which may have two possible levels (memory states) and thus can store one bit of data. For example, the first level "0" may correspond to a first threshold voltage range, while the second level "1" may correspond to a second threshold voltage range. In some embodiments, each memory cell 106 is an xLC capable of storing more than one bit of data at more than four levels. For example, the xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to assume a range of possible nominal storage values (i.e., corresponding to 2 N to N bits of data). In some embodiments, at least one memory cell 106 is set to one of 2 N levels corresponding to one piece of N-bit data, where N is an integer greater than 1.

[0069] As Figure 1As shown, each NAND memory string 108 may also include a source select gate (SSG) transistor 110 (also known as a bottom select gate (BSG) transistor) at its source extreme and a drain select gate (DSG) transistor 112 (also known as a top select gate (TSG) transistor) at its drain extreme. The SSG transistor 110 and the DSG transistor 112 may be configured to activate multiple selected NAND memory strings 108 (columns of the array) during read and program operations. In some embodiments, the sources of multiple NAND memory strings 108 in the same block 104 are coupled through the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage (e.g., a positive voltage higher than the threshold voltage of the DSG transistor 112) or a deselected voltage (e.g., a ground voltage) to the gate of the corresponding DSG transistor 112 through one or more DSG lines 113, and / or by applying a select voltage (e.g., a positive voltage higher than the threshold voltage of the SSG transistor 110) or a deselected voltage (e.g., a ground voltage) to the gate of the corresponding SSG transistor 110 through one or more SSG lines 115.

[0070] As Figure 1 shown, multiple NAND memory strings 108 may be organized into multiple blocks 104, each block may have a common source line 114, e.g., coupled to the ACS. In some embodiments, each block 104 is a basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase the memory cells 106 in the selected block 104, the source line 114 coupled to the selected block 104 and non-selected blocks 104 in the same plane as the selected block 104 may be biased with an erase voltage (Vers), e.g., a high positive bias voltage (e.g., 20V or higher). The memory cells 106 of multiple adjacent NAND memory strings 108 may be coupled through word lines 118, and the word line 318 selects which row of the memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to multiple memory cells 106. Each word line 118 may include multiple control gates (gate electrodes) at each memory cell 106 and a gate line coupling the control gates.

[0071] As Figure 1As shown, the memory cell array 101 may include an array of memory cells 106 in multiple rows and multiple columns in each block 104. According to some embodiments, a column of memory cells corresponds to one NAND memory string 108. Multiple rows of memory cells 106 may be coupled to word lines 118 respectively, and multiple columns of memory cells 106 may be coupled to bit lines 116 respectively. The peripheral circuit 102 may be coupled to the memory cell array 101 through the bit lines 116 and the word lines 118.

[0072] Figure 2 A side view of a cross-section of a memory cell array 101 including a NAND memory string 108 is shown according to some aspects of the present disclosure. As Figure 2 shown, the NAND memory string 108 may vertically extend through the memory stack 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0073] The memory stack 204 may include interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layer 206 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, a gate of the DSG transistor 112, or a gate of the SSG transistor 110, and may laterally extend as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0074] In some embodiments, the DSG cut 210 (also referred to as the TSG cut) is formed through the DSG line 113, which electrically separates the DSG lines 113 between adjacent regions (e.g., the "groups" referred to herein), such that the DSG lines 113 and DSG transistors 112 in different groups can be individually controlled during read and / or programming operations. Similarly, in some embodiments, the SSG cut 212 (also referred to as the BSG cut) is formed through the SSG line 115, which electrically separates the SSG lines 115 between adjacent regions (e.g., the "fingers" referred to herein), such that the SSG lines 115 and SSG transistors 110 in different fingers can be individually controlled during read and / or programming operations.

[0075] As Figure 2 shown, the NAND memory string 108 includes a channel structure that vertically extends through the memory stack 204. In some embodiments, the channel structure includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). It will be appreciated that although Figure 2 not shown in the figure, additional components of the memory cell array 101 can be formed, including but not limited to gate line slits / source contacts, local contacts, interconnect layers, etc.

[0076] Returning to Figure 1 , the peripheral circuit 102 can be coupled to the memory cell array 101 through the bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 101 by applying and sensing voltage signals and / or current signals to and from each selected memory cell 106 through the bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 can include various types of peripheral circuits formed using metal-oxide semiconductor (MOS) technology. For example, Figure 3 shows some exemplary peripheral circuits 601, which include page buffers / sense amplifiers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic 312, registers 314, interfaces (I / F) 316, and data buses 318. It should be understood that in some examples, additional peripheral circuits not shown in Figure 3 the figure can also be included.

[0077] The page buffer / sense amplifier 304 can be configured to sense (read) data from the memory cell array 101 and program (write) data to the memory cell array 401 according to control signals from the control logic 312. In one example, the page buffer / readout amplifier 304 can store one or more pages of programming data (write data, referred to herein as "data pages") to be programmed. In another example, the page buffer / sense amplifier 304 can verify the programmed selected memory cells 106 during each programming / verification period in a programming operation to ensure that data has been correctly programmed into the memory cells 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 can also sense a low-power signal from the bit line 116 representing the data bits stored in the memory cells 106 and amplify the small voltage swing to an identifiable logic level during a read operation.

[0078] The column decoder / bit line driver 306 can be configured to be controlled by the control logic 312 and select one or more NAND memory strings 108 by applying bit line voltages generated from the voltage generator 310. The row decoder / word line driver 308 can be configured to be controlled by the control logic 312, and select / deselect the blocks 104 of the memory cell array 101 and select / deselect the word lines 118 of the blocks 104. The row decoder / word line driver 308 can also be configured to drive the word lines 118 with the word line voltages generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive the SSG line 115 and the DSG line 113. The voltage generator 310 can be configured to be controlled by the control logic 312 and generate word line voltages (e.g., read voltage, program voltage, channel pass voltage, this ground voltage, verify voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 101.

[0079] The control logic 312 can be coupled to each of the above-mentioned peripheral circuits and is configured to control the operation of each peripheral circuit. The register 314 can be coupled to the control logic 312 and can include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 316 can be coupled to the control logic 312 and acts as a control buffer to buffer and relay the control commands received by the control logic 312 from a memory controller (not shown) and / or a host (not shown) and the status information received by the memory controller and / or the host from the control logic 312. The interface 316 can also be coupled to the column decoder / bit line driver 306 via the data bus 318 and acts as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory cell array 101.

[0080] Figure 4A and Figure 4B shows a schematic diagram of a plurality of 3D NAND memory strings according to some aspects of the present disclosure. Figure 4A shows an example of an array of a plurality of 3D NAND memory strings (e.g., 108 in Figure 1 ) in a block (e.g., 104 in Figure 1 ). As Figure 4A shown, from top to bottom in the z direction, each 3D NAND memory string can be coupled to multiple lines in different rows, e.g., DSG lines (DSG, e.g., 113 in Figure 1 ), pseudo DSG lines (top DMY), word lines (WL, e.g., 118 in Figure 1 ), pseudo SSG lines (bottom DMY), SSG lines (SSG, e.g., 115 in Figure 1 ), and a common source line (CSL, e.g., 114 in Figure 1 ). As Figure 4A shown, in the word line direction (x direction) and the bit line direction (y direction), the word lines can extend laterally to connect the memory cells of a plurality of 3D NAND memory strings. For the DSG lines and the SSG lines, the DSG lines and the SSG lines can be continuous in the word line direction (x direction) to connect the DSG transistors and the SSG transistors of a plurality of 3D NAND memory strings at the same positions in the y direction (e.g., DSG0 and DSG0, SSG0 and SSG0), but can be separated by DSG cuts 402 and SSG cuts 404 in the bit line direction (y direction) to form electrically separated groups 406 and fingers 408 respectively (as Figure 4B shown), which can be individually controlled in a programming operation.

[0081] As Figure 4B shown, an array of a plurality of 3D NAND memory strings can be divided into a plurality of groups 406 in the bit line direction (y direction) by DSG cuts 402, which electrically separate the DSG lines and the DSG transistors (e.g., each of DSG0, DSG1, DSG2, and DSG3 is separated in Figure 4A ). Thus, each group of a plurality of 3D NAND memory strings 406 can be individually controlled in a programming operation by separately selecting and controlling the corresponding DSG lines. As Figure 4B shown, an array of a plurality of 3D NAND memory strings can be divided into a plurality of fingers 408 in the bit line direction (y direction) by SSG cuts 404, which electrically separate the SSG lines and the SSG transistors (e.g., SSG0 and SSG1 are separated from Figure 4Athe SSG2 and SSG3 in it are separated). Thus, each of the multiple 3D NAND memory strings in each finger 408 can be individually selected and controlled during a programming operation by separately controlling the corresponding SSG lines. For Figure 4A example, an array of multiple 3D NAND memory strings can be divided into 4 groups 406 by 3 DSG cuts 402, and each group 406 includes 3D NAND memory strings having DSG0, DSG1, DSG2, and DSG3 respectively; the array of multiple 3D NAND memory strings can also be divided into 2 fingers 408 by 1 SSG cut 404, one finger includes multiple 3D NAND memory strings having SSG0 and SSG1, and the other finger includes multiple 3D NAND memory strings having SSG2 and SSG3. Consistent with the scope of the present disclosure, in some embodiments, an array of multiple 3D memory strings is divided into groups 406 and fingers 408 by DSG cuts 402 and SSG cuts 404 respectively during a programming operation, and each set 406 is a basic unit for implementing a programming operation scheme (such as 3-bit line or 4-bit line (3BL or 4BL) biased programming) of a programming operation.

[0082] It should be understood that the DSG cut 402 can be implemented as a physical cut that replaces part of the DSG line with a dielectric layer (e.g., Figure 2 the DSG cut 210 shown), or can be implemented as an electrical cut that pre-programs (also referred to as trimming) different DSG transistors to different threshold voltage levels. Similarly, it should be understood that the SSG cut 404 can be implemented as a physical cut that replaces part of the SSG line with a dielectric layer (e.g., Figure 2 the SSG cut 212 shown), or can be implemented as an electrical cut that pre-programs (also referred to as trimming) different SSG transistors to different threshold voltage levels. It should also be understood that the spacing between adjacent DSG cuts 402 or SSG cuts 404 (i.e., the number of multiple 3D NAND memory strings in each group 406 or each finger 408) can vary in different examples.

[0083] To perform a programming operation, in addition to the page buffer / sense amplifier 304 providing a corresponding piece of data to each selected memory cell 106, the row decoder / word line driver 308 can be configured to: apply a programming voltage and a verification voltage to the selected word line 118 of the selected row coupled to the memory cell 106 during one or more programming / verification cycles, so as to raise the threshold voltage of each selected memory cell 106 to a desired level (to a desired threshold voltage range) based on the corresponding piece of data. For example, Figure 5A and Figure 5B show waveforms of word line voltages applied to the selected word line during a programming operation according to some aspects of the present disclosure.

[0084] As Figure 5A and Figure 5B shown, according to some embodiments, a programming operation includes one or more loops 502, each loop including a programming period 504 and a verification period 506. As Figure 5B shown, in each loop 502, the row decoder / word line driver 308 can be configured to: apply a programming voltage (Vpgm) to the selected word line 118 during the programming period 504 to select a row of memory cells 106, and subsequently apply one or more verification voltages (Vvfy) having incremental changes in voltage levels during the verification period 506 to verify the selected row of memory cells 106. That is, in each loop 502, after applying the programming voltage during the programming period 504, the peripheral circuit 102 can perform verification of the selected row of memory cells 106 at one or more levels during the verification period 506. According to some embodiments, the number of verification voltages applied during the verification period 506 depends on the level programmed by a particular loop 502. As a result, at the end of the programming operation, for example, based on the corresponding N-bit data to be stored in the selected memory cells 106, the selected memory cells 106 can be programmed to one of 2 N levels, where N is a positive integer.

[0085] In some embodiments, the programming operation is incremental step pulse programming (ISPP), which gradually increases the programming voltage based on step voltages in different loops 502. The magnitude of this "step" (e.g., the increase in the magnitude of the programming voltage in each loop 502 relative to the programming voltage in the previous loop 502) is referred to as the "pulse step height". Consistent with the scope of the present disclosure, in some embodiments, the programming operation includes at least a first loop 502 and a second loop 502 after the first loop 502, and the first loop 502 and the second loop 502 are the starting loop and the ending loop of the ISPP, respectively.

[0086] Figure 6 shows a timing diagram of a programming operation having multiple loops. The programming operation can be an ISPP including multiple loops (e.g., N loops), such as a starting loop and an ending loop after the starting loop. For example, as Figure 6 shown, the programming operation can include a starting loop (loop 1), an ending loop (loop n), and at least one intermediate loop (loop k) between the starting loop and the ending loop. Each loop of the programming operation can include a programming period (PGM) and a verification period (VFY), as described above in Figure 5A and Figure 5B . Each verification period can include a verification period (phase), where one or more verification voltage pulses are applied to the selected word line (sel Wl) to verify the selected memory cells coupled to the selected word line at one or more levels. As Figure 6As shown, each verification cycle may also include a pre-pulse period (phase) immediately before the verification period, during which multiple NAND memory strings are readied for verification. As Figure 6 shown, each verification cycle may also include a post-pulse period (phase) (also referred to as a recovery cycle) immediately after the verification period, during which multiple NAND memory strings recover from verification and are readied for another operation (e.g., a read operation) after an end cycle or are readied for programming in the next cycle after any non-end cycle.

[0087] As Figure 6 shown, for each selected NAND memory string, a select voltage (e.g., a positive voltage) may be applied to each selected DSG line and selected SSG line to turn on each selected DSG transistor and selected SSG transistor during the verification period of each cycle, so as to verify the selected memory cells of each selected NAND memory string during the verification period. Conversely, for each non-selected NAND memory string, a deselect voltage (e.g., a ground voltage) may be applied to each non-selected DSG line and non-selected SSG line to turn off each non-selected DSG transistor and non-selected SSG transistor during the verification period of each cycle, so as to prohibit verification of the non-selected memory cells of each non-selected NAND memory string during the verification period.

[0088] On the other hand, the channel potential of the non-selected NAND memory string may be coupled up to a positive potential during the pre-pulse period, thereby causing HCI in the channel between the DSG transistor and the SSG transistor. Thus, as Figure 6 shown, during the pre-pulse period of each cycle, a select voltage may be applied to each non-selected DSG line and non-selected SSG line to turn on each non-selected DSG transistor and non-selected SSG transistor, so as to lower the channel potential and eliminate HCI before the verification period, also referred to as "pre-pulse channel cleaning". Similarly, the channel potential of the non-selected NAND memory string may be coupled down to a negative potential during the post-pulse period, thereby also causing HCI in the channel between the DSG transistor and the SSG transistor. Thus, as Figure 6 shown, during the post-pulse period of each cycle, a select voltage may be applied to each non-selected DSG line and non-selected SSG line to turn on each non-selected DSG transistor and non-selected SSG transistor again, so as to increase the channel potential and eliminate HCI before the next operation, also referred to as "post-pulse channel cleaning". However, the pre-pulse channel cleaning and post-pulse channel cleaning performed in each cycle (e.g., in each cycle from cycle 1 to cycle n in Figure 6 ) extend the duration of each verification cycle, thus becoming a bottleneck for saving programming time.

[0089] The inventors of the present disclosure have found that post-pulse channel clean-up performed in early cycles can be skipped without significantly affecting the channel potential, especially when implementing SSG cuts to divide multiple 3D NAND memory strings into fingers. For example, as Figure 15 reflected by the simulation results using computer-aided design techniques (TCAD) simulation, the post-pulse channel clean-up performed in early cycles has no significant impact on the channel potential. Therefore, the present disclosure provides various "per-cycle" channel clean-up schemes that do not clean the channels of multiple non-selected memory strings during both the pre-pulse period and the post-pulse period of each verification cycle, thereby saving programming time without sacrificing performance. For example, since non-selected DSG transistors can be turned off during certain periods (e.g., the pre-pulse period and / or the post-pulse period), the load can be reduced, thereby reducing the slew time of the word line voltage.

[0090] According to some aspects of the present disclosure, channel clean-up is skipped during the pre-pulse period and the post-pulse period of the verification cycle in early cycles, e.g., only performed during the pre-pulse period and / or the post-pulse period of the verification cycle at the end of the cycle (i.e., the last verification cycle). In some embodiments, during the pre-pulse period and the post-pulse period of the first cycle of the programming operation, the DSG transistors in the non-selected memory strings are turned off, and during at least one of the pre-pulse period or the post-pulse period of the second cycle of the programming operation after the first cycle, the DSG transistors in the non-selected memory strings are turned on. That is, during at least one of the early cycles (i.e., the first cycle, e.g., the starting cycle of ISPP), at least the DSG transistors in the non-selected memory strings can be turned off to skip the pre-pulse channel clean-up and the post-pulse channel clean-up in that cycle, thereby saving programming time.

[0091] For example, Figure 7 and Figure 8 show a timing diagram of a programming operation with multiple cycles according to some aspects of the present disclosure. The DSG transistors in the selected memory strings can be electrically separated from the DSG transistors in the non-selected memory strings through DSG cuts; the SSG transistors in the selected memory strings can be electrically separated from the SSG transistors in the non-selected memory strings through SSG cuts. As Figure 7 and Figure 8As shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the selected SSG line (sel SSG) and the selected SSG transistor in the selected NAND memory string to turn on the selected SSG transistor in both the pre-pulse period and the post-pulse period. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the selected DSG line (sel DSG) and the selected DSG transistor in the selected NAND memory string to turn on the selected DSG transistor in both the pre-pulse period and the post-pulse period.

[0092] In contrast, as Figure 7 and Figure 8 shown, in each non-ending cycle (e.g., cycle 1 and cycle k), the word line driver 308 of the peripheral circuit 102 can be configured to apply a deselect voltage (e.g., a ground voltage) to the unselected SSG line (unsel SSG) and the unselected SSG transistor in the unselected NAND memory string to turn off the unselected SSG transistor in both the pre-pulse period and the post-pulse period. Similarly, in each non-ending cycle (e.g., cycle 1 and cycle k), the word line driver 308 of the peripheral circuit 102 can be configured to apply a deselect voltage (e.g., a ground voltage) to the unselected DSG line (unsel SSG + unsel DSG) and the unselected DSG transistor in the unselected NAND memory string to turn off the unselected DSG transistor in both the pre-pulse period and the post-pulse period. In other words, for multiple unselected NAND memory strings in each non-ending cycle (e.g., having unselected SSG transistors and unselected DSG transistors), both pre-pulse channel cleaning and post-pulse channel cleaning can be skipped, thus saving programming time.

[0093] Note that Figures 6 - 10 the sel SSG + unsel DSG shown in Figure 4A and Figure 4B refers to the waveform of the voltage signal of the unselected DSG line in finger 408 applied to the selected SSG line (and the selected SSG transistor), as Figures 6 - 10 and Figure 4A shown, while Figure 4B the unsel SSG + unsel DSG shown in

[0094] To still be able to return the channel potential to normal and eliminate HCI before the next operation (e.g., a read operation), in the end cycle (e.g., cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a select voltage (e.g., a positive voltage) to the unselected SSG line (unsel SSG) and the unselected SSG transistors in the unselected NAND memory string to turn on the unselected SSG transistors during a post-pulse period (as shown in Figure 7 ), or during a pre-pulse period (as shown in Figure 8 ). Similarly, in the end cycle (e.g., cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a select voltage (e.g., a positive voltage) to the unselected DSG line (unsel SSG + unsel DSG) and the unselected DSG transistors in the unselected NAND memory string to turn on the unselected DSG transistors during a post-pulse period (as shown in Figure 7 ), or during a pre-pulse period (as shown in Figure 8 ). Although not shown, it should be understood that in some examples, the word line driver 308 can be configured to: apply a select voltage (e.g., a positive voltage) to the unselected SSG line (unsel SSG) and the unselected SSG transistors in the unselected NAND memory string to turn on the unselected SSG transistors during both the post-pulse period and the pre-pulse period. Similarly, the word line driver 308 can be configured to: apply a select voltage (e.g., a positive voltage) to the unselected DSG line (unsel SSG + unsel DSG) and the unselected DSG transistors in the unselected NAND memory string to turn on the unselected DSG transistors during both the post-pulse period and the pre-pulse period. It should also be understood that although pre-pulse channel cleaning and post-pulse channel cleaning are skipped in each non-end cycle, as shown in Figure 7 and Figure 8 , in some examples, pre-pulse channel cleaning and post-pulse channel cleaning can be skipped in at least one of the non-end cycles, which can still save programming time.

[0095] As shown in Figure 7 and Figure 8As shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a deselected voltage (e.g., ground voltage) to the unselected SSG line (unselSSG) and the unselected SSG transistors in the unselected NAND memory string to turn off the unselected SSG transistors during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a deselected voltage to the unselected SSG line (unsel SSG) and the unselected SSG transistors in the unselected NAND memory string to turn off the unselected SSG transistors throughout the verification cycle. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a deselected voltage (e.g., ground voltage) to the unselected DSG line (unsel SSG+unsel DSG) and the unselected DSG transistors in the unselected NAND memory string to turn off the unselected DSG transistors during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a deselected voltage to the unselected DSG line (unsel SSG+unsel DSG) and the unselected DSG transistors in the unselected NAND memory string to turn off the unselected DSG transistors throughout the verification cycle.

[0096] In contrast, as Figure 7 and Figure 8As shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a select voltage (e.g., a positive voltage) to the selected SSG line (sel SSG) and the selected SSG transistor in the selected NAND memory string to turn on the selected SSG transistor during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a select voltage to the selected SSG line (sel SSG) and the selected SSG transistor in the selected NAND memory string to turn on the selected SSG transistor throughout the verification cycle. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a select voltage (e.g., a positive voltage) to the selected DSG line (sel DSG) and the selected DSG transistor in the selected NAND memory string to turn on the selected DSG transistor during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a select voltage to the selected DSG line (sel DSG) and the selected DSG transistor in the selected NAND memory string to turn on the selected DSG transistor throughout the verification cycle.

[0097] According to some aspects of the present disclosure, in each verification cycle, channel cleaning is performed in only one of the pre-pulse period and the post-pulse period, rather than in both the pre-pulse period and the post-pulse period. In some embodiments, in only one of the pre-pulse period or the post-pulse period in the first cycle of the programming operation, the DSG transistor in the non-selected memory string is turned on; and in only one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation after the first cycle, the DSG transistor in the non-selected memory string is turned on.

[0098] For example, Figure 9 and Figure 10 FIG. shows a timing diagram of a programming operation with multiple cycles according to some aspects of the present disclosure. The DSG transistors in the selected memory string can be electrically separated from the DSG transistors in the non-selected memory string through DSG cuts; the SSG transistors in the selected memory string can be electrically separated from the SSG transistors in the non-selected memory string through SSG cuts. As Figure 9 and Figure 10As shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the selected SSG line (sel SSG) and the selected SSG transistor in the selected NAND memory string to turn on the selected SSG transistor during both the pre-pulse period and the post-pulse period. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the selected DSG line (sel DSG) and the selected DSG transistor in the selected NAND memory string to turn on the selected DSG transistor during both the pre-pulse period and the post-pulse period.

[0099] In comparison, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the unselected SSG line (unsel SSG) and the unselected SSG transistor in the unselected NAND memory string to turn on the unselected SSG transistor during the pre-pulse period (as Figure 9 shown) or the post-pulse period (as Figure 10 shown), rather than during both the pre-pulse period and the post-pulse period. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to apply a select voltage (e.g., a positive voltage) to the unselected DSG line (unsel SSG+unsel DSG) and the unselected DSG transistor in the unselected NAND memory string to turn on the unselected DSG transistor during the pre-pulse period (as Figure 9 shown) or the post-pulse period (as Figure 10 shown), but not during both the pre-pulse period and the post-pulse period. In other words, for multiple unselected NAND memory strings in each cycle (e.g., having unselected SSG transistors and unselected DSG transistors), pre-pulse channel cleaning or post-pulse channel cleaning can be performed, but not both pre-pulse channel cleaning and post-pulse channel cleaning, thus saving programming time. It should also be understood that although pre-pulse channel cleaning or post-pulse channel cleaning is skipped in each cycle, as Figure 9 and Figure 10 shown, in some examples, pre-pulse channel cleaning and post-pulse channel cleaning can be performed in one or more cycles but not all cycles in the cycle, which can still save programming time.

[0100] As Figure 9 and Figure 10As shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a deselected voltage (e.g., ground voltage) to the unselected SSG line (unselSSG) and the unselected SSG transistors in the unselected NAND memory strings to turn off the unselected SSG transistors during the verification period between the pre-pulse period and the post-pulse period. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a deselected voltage (e.g., ground voltage) to the unselected DSG line (unsel SSG+unsel DSG) and the unselected DSG transistors in the unselected NAND memory strings to turn off the unselected DSG transistors during the verification period between the pre-pulse period and the post-pulse period.

[0101] As a comparison, as Figure 9 and Figure 10 shown, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a selected voltage (e.g., positive voltage) to the selected SSG line (selSSG) and the selected SSG transistors in the selected NAND memory strings to turn on the selected SSG transistors during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a selected voltage to the selected SSG line (sel SSG) and the selected SSG transistors in the selected NAND memory strings to turn on the selected SSG transistors throughout the verification cycle. Similarly, in each cycle (e.g., cycle 1, cycle k, and cycle n), the word line driver 308 of the peripheral circuit 102 can be configured to: apply a selected voltage (e.g., positive voltage) to the selected DSG line (selDSG) and the selected DSG transistors in the selected NAND memory strings to turn on the selected DSG transistors during the verification period between the pre-pulse period and the post-pulse period. That is, in each cycle, the word line driver 308 can be configured to: apply a selected voltage to the selected DSG line (sel DSG) and the selected DSG transistors in the selected NAND memory strings to turn on the selected DSG transistors throughout the verification cycle.

[0102] Figure 11FIG. 1100 is a flow chart of a method 1100 for programming a storage device in accordance with some aspects of the present disclosure. The storage device may be any suitable storage device disclosed herein, such as storage device 100. The method 1100 may be implemented by the peripheral circuit 102, such as row decoder / word line driver 308, page buffer / sense amplifier 304, and control logic 312. It should be understood that the operations shown in method 1100 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of these operations may be performed simultaneously, or in a different order than that Figure 11 shown in

[0103] Referring Figure 11 to FIG. 1100, method 1100 begins at operation 1102, where the DSG transistor and the SSG transistor in the unselected memory string are turned off during the pre-pulse period and the post-pulse period in the first cycle of the programming operation. Method 1100 proceeds to operation 1104, as Figure 11 shown, where the DSG transistor and the SSG transistor in the unselected memory string are turned off during the verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation. For example, as Figures 1 - 3 FIGS. 1100, Figure 7 1101, Figure 8 and 1102 show, in cycle 1 or cycle k of the programming operation, the ground voltage can be applied to the unselected DSG line 113 (unsel SSG + unsel DSG) and the unselected SSG line 115 (unsel SSG) by the word line driver 308 of the peripheral circuit 102 through the verification period, so as to turn off the unselected DSG transistor 112 and the unselected SSG transistor 110 during the pre-pulse period, the verification period, and the post-pulse period.

[0104] Method 1100 proceeds to operation 1106, as Figure 11 shown, where the DSG transistor and the SSG transistor in the unselected memory string are turned on during at least one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation after the first cycle. For example, as Figures 1 - 3 FIGS. 1103, Figure 7 1104, Figure 8 and 1105 show, in cycle n of the programming operation, the positive voltage can be applied to the unselected DSG line 113 (unsel SSG + unsel DSG) and the unselected SSG line 115 (unsel SSG) by the word line driver 308 of the peripheral circuit 102 during the pre-pulse period ( Figure 8 ) or the post-pulse period ( Figure 7 ), and during the pre-pulse period ( Figure 8 ) or the post-pulse period ( Figure 7)Turn on the non - selected DSG transistor 112 and non - selected SSG transistor 110.

[0105] Method 1100 proceeds to operation 1108, as Figure 11 shown, where during the verification period between the pre - pulse period and the post - pulse period in the second cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non - selected memory string. For example, as Figures 1 - 3 , Figure 7 and Figure 8 shown, in cycle n of the programming operation, the non - selected DSG transistor 112 and non - selected SSG transistor 110 can be turned off during the verification period by the word - line driver 308 of the peripheral circuit 102 applying a ground voltage to the non - selected DSG line 113 (unsel SSG + unsel DSG) and the non - selected SSG line 115 (unsel SSG).

[0106] Figure 12 FIG. shows a flowchart of another method 1200 for programming a memory device according to some aspects of the present disclosure. The memory device can be any suitable memory device disclosed herein, such as memory device 100. Method 1200 can be implemented by the peripheral circuit 102, such as the row decoder / word - line driver 308, the page buffer / sense amplifier 304, and the control logic 312. It should be understood that the operations shown in method 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. Additionally, some of these operations may be performed simultaneously, or in an order different from that Figure 12 shown.

[0107] Referring to Figure 12 , method 1200 begins at operation 1202, where in only one of the pre - pulse period or the post - pulse period in the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non - selected memory string. For example, as Figures 1 - 3 , Figure 9 and Figure 10 shown, in cycle 1 or cycle k of the programming operation, the positive voltage can be applied to the non - selected DSG line 113 (unsel SSG + unsel DSG) and the non - selected SSG line 115 (unsel SSG) by the word - line driver 308 of the peripheral circuit 102 during the pre - pulse period but not during the post - pulse period ( Figure 9 ) or during the post - pulse period but not during the pre - pulse period ( Figure 10 ), so that during the pre - pulse period but not during the post - pulse period ( Figure 9 ) or during the post - pulse period but not during the pre - pulse period ( Figure 10)Turn on the non - selected DSG transistor 112 and non - selected SSG transistor 110.

[0108] Method 1200 proceeds to operation 1204, as Figure 12 shown, where during the verification period between the pre - pulse period and the post - pulse period in the first cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non - selected memory string. For example, as Figures 1 - 3 , Figure 9 and Figure 10 shown, in cycle 1 or cycle k of the programming operation, the non - selected DSG transistor 112 and non - selected SSG transistor 110 can be turned off during the verification period by the word - line driver 308 of the peripheral circuit 102 applying a ground voltage to the non - selected DSG line 113 (unsel SSG + unsel DSG) and the non - selected SSG line 115 (unsel SSG).

[0109] Method 1200 proceeds to operation 1206, as Figure 12 shown, where during only one of the pre - pulse period or the post - pulse period in the second cycle of the programming operation after the first cycle, turn on the DSG transistor and the SSG transistor in the non - selected memory string. For example, as Figures 1 - 3 , Figure 9 and Figure 10 shown, in cycle n of the programming operation, the non - selected DSG transistor 112 and non - selected SSG transistor 110 can be turned on during the pre - pulse period but not during the post - pulse period ( Figure 9 ) or during the post - pulse period but not during the pre - pulse period ( Figure 10 ) by the word - line driver 308 of the peripheral circuit 102 applying a positive voltage to the non - selected DSG line 113 (unsel SSG + unsel DSG) and the non - selected SSG line 115 (unsel SSG), so that during the pre - pulse period but not during the post - pulse period ( Figure 9 ) or during the post - pulse period but not during the pre - pulse period ( Figure 10 ).

[0110] Method 1200 proceeds to operation 1208, as Figure 12 shown, where during the verification period between the pre - pulse period and the post - pulse period in the second cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non - selected memory string. For example, as Figures 1 - 3 , Figure 9 and Figure 10As shown, in cycle n of the programming operation, the ground voltage can be applied to the unselected DSG line 113 (unsel SSG + unsel DSG) and the unselected SSG line 115 (unsel SSG) by the word line driver 308 of the peripheral circuit 102 during the verification period, so as to turn off the unselected DSG transistor 112 and the unselected SSG transistor 110 during the verification period.

[0111] Figure 13 FIG. shows a block diagram of a system 1300 having a storage device according to some aspects of the present disclosure. The system 1300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As Figure 13 shown, the system 1300 may include a host 1308 and a memory system 1302 having one or more storage devices 100 ( Figure 1 as shown) and a memory controller 1306. The host 1308 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1308 may be configured to: send data to the storage device 100 or receive data from the storage device 404.

[0112] The storage device 100 can be any storage device disclosed in the present disclosure. According to some embodiments, the memory controller 1306 is coupled to the storage device 100 and the host 1308, and is configured to control the storage device 100. The memory controller 1306 can manage the data stored in the storage device 100 and communicate with the host 1308. In some embodiments, the memory controller 1306 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1306 is designed to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC) for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 1306 can be configured to control the operations of the storage device 100, such as read, erase, and program operations. The memory controller 1306 can also be configured to manage various functions regarding the data stored in or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 1306 is further configured to: process error correction codes (ECC) for data read from or written to the storage device 100. Any other suitable functions can also be performed by the memory controller 1306, for example, formatting the storage device 100. The memory controller 1306 can communicate with external devices (such as the host 1308) according to a specific communication protocol. For example, the memory controller 1306 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0113] The memory controller 1306 and one or more storage devices 100 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 1302 can be implemented and packaged into different types of terminal electronic products. In as Figure 14AIn one example shown, the memory controller 1306 and a single storage device 100 can be integrated into a memory card 1402. The memory card 1402 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1402 can also include a memory card connector 1404 that couples the memory card 1402 to a host (e.g., the host 1308 in FIG. 14). In Figure 14B In another example shown, the memory controller 1306 and multiple storage devices 100 can be integrated into an SSD 1406. The SSD 1406 can also include an SSD connector 1408 that couples the SSD 1406 to a host (e.g., Figure 13 the host 1308 in FIG. 14). In some embodiments, the storage capacity and / or operating speed of the SSD 1406 are greater than those of the memory card 1402.

[0114] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Accordingly, based on the teachings and guidance presented herein, these adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments.

[0115] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

[0116] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. In addition, the inventive subject matter described herein can also be used in a variety of other applications. The functional and structural features described in the present disclosure can be combined, adjusted, modified, and rearranged in a manner consistent with the scope of the present disclosure.

Claims

1. A storage device, comprising: a plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; and a peripheral circuit coupled to the plurality of memory strings and configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings and inhibit non-selected memory cells in non-selected memory strings among the plurality of memory strings, wherein the peripheral circuit includes: a word line driver configured to: turn off the DSG transistors in the non-selected memory strings during a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn on the DSG transistors in the non-selected memory strings during at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle.

2. The storage device according to claim 1, wherein, The programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are the start cycle and the end cycle of the ISPP, respectively.

3. The storage device according to claim 1 or 2, wherein The word line driver is further configured to: turn off the SSG transistors in the non-selected memory strings during a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn on the SSG transistors in the non-selected memory strings during at least one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation.

4. The storage device according to claim 3, wherein, The word line driver is further configured to: turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation; and turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation.

5. The storage device according to claim 3 or 4, wherein The word line driver is further configured to: turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a pre-pulse period in a second cycle of the programming operation; and turn on the DSG transistors and the SSG transistors in the non-selected memory strings during a post-pulse period in a second cycle of the programming operation.

6. The storage device according to claim 3 or 4, wherein, The word line driver is further configured to: turn on the DSG transistors and the SSG transistors in the non-selected memory strings during a pre-pulse period in a second cycle of the programming operation; and turn off the DSG transistors and the SSG transistors in the non-selected memory strings during a post-pulse period in a second cycle of the programming operation.

7. The storage device according to any one of claims 1-6, wherein, The DSG transistors in the selected memory string are electrically separated from the DSG transistors in the non-selected memory strings.

8. A method for operating a storage device, the storage device including a plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor, the method comprising: During the pre-pulse period and the post-pulse period in the first cycle of the programming operation, turn off the DSG transistors in the unselected memory strings among the multiple memory strings; And During at least one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation after the first cycle, turn on the DSG transistors in the unselected memory strings.

9. The method according to claim 8, wherein The programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are respectively the start cycle and the end cycle of the ISPP.

10. The method according to claim 8 or 9, further comprising: During the pre-pulse period and the post-pulse period in the first cycle of the programming operation, turn off the SSG transistors in the unselected memory strings; And During at least one of the pre-pulse period or the post-pulse period in the second cycle of the programming operation, turn on the SSG transistors in the unselected memory strings.

11. The method according to claim 10, further comprising: During the verification period between the pre-pulse period and the post-pulse period in the first cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the unselected memory strings; And During the verification period between the pre-pulse period and the post-pulse period in the second cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the unselected memory strings.

12. The method according to claim 10 or 11, further comprising: During the pre-pulse period in the second cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the unselected memory strings; And During the post-pulse period in the second cycle of the programming operation, turn on the DSG transistors and the SSG transistors in the unselected memory strings.

13. The method according to claim 10 or 11, further comprising: During the pre-pulse period in the second cycle of the programming operation, turn on the DSG transistors and the SSG transistors in the unselected memory strings; And During the post-pulse period in the second cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the unselected memory strings.

14. The method according to any one of claims 8 - 13, wherein, The DSG transistors in the selected memory strings are electrically separated from the DSG transistors in the unselected memory strings.

15. A system, comprising: A storage device configured to store data, the storage device including multiple memory strings, each of the multiple memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; And A peripheral circuit coupled to the multiple memory strings and configured to: in a programming operation, program a selected memory cell in a selected memory string among the multiple memory strings and inhibit unselected memory cells in unselected memory strings among the multiple memory strings, wherein the peripheral circuit includes: A word line driver configured to: During the pre-pulse period and the post-pulse period in the first cycle of the programming operation, turn off the DSG transistors in the unselected memory strings; and During at least one of a pre - pulse period or a post - pulse period in a second cycle of the programming operation after the first cycle, turn on the DSG transistors in the non - selected memory strings; and A memory controller, the memory controller being coupled to the storage device and configured to control the storage device.

16. The system according to claim 15, wherein The programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are respectively the start cycle and the end cycle of the ISPP.

17. The system according to claim 15 or 16, wherein, The word line driver is further configured to: During a pre - pulse period and a post - pulse period in a first cycle of the programming operation, turn off the SSG transistors in the non - selected memory strings; And During at least one of a pre - pulse period or a post - pulse period in a second cycle of the programming operation, turn on the SSG transistors in the non - selected memory strings.

18. The system according to claim 17, wherein, The word line driver is further configured to: During a verification period between a pre - pulse period and a post - pulse period in a first cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the non - selected memory strings; And During a verification period between a pre - pulse period and a post - pulse period in a second cycle of the programming operation, turn off the DSG transistors and the SSG transistors in the non - selected memory strings.

19. The system according to any one of claims 15 - 18, wherein, The DSG transistors in the selected memory strings are electrically separated from the DSG transistors in the non - selected memory strings.

20. The system according to any one of claims 15 - 19, wherein, The storage device is a NAND flash memory device.

21. A storage device, comprising: A plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; And Peripheral circuitry, the peripheral circuitry being coupled to the plurality of memory strings and configured to: in a programming operation, program selected memory cells in the selected memory strings among the plurality of memory strings and inhibit non - selected memory cells in the non - selected memory strings among the plurality of memory strings, wherein the peripheral circuitry includes: A word line driver, the word line driver being configured to: During only one of a pre - pulse period or a post - pulse period in a first cycle of the programming operation, turn on the DSG transistors in the non - selected memory strings; and During only one of a pre - pulse period or a post - pulse period in a second cycle of the programming operation after the first cycle, turn on the DSG transistors in the non - selected memory strings.

22. The storage device according to claim 21, wherein, The programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are respectively the start cycle and the end cycle of the ISPP.

23. The storage device according to claim 21 or 22, wherein, The word line driver is further configured to: During only one of a pre - pulse period or a post - pulse period in a first cycle of the programming operation, turn on the SSG transistors in the non - selected memory strings; and During only one of a pre - pulse period or a post - pulse period in a second cycle of the programming operation, turn on the SSG transistors in the non - selected memory strings.

24. The storage device according to claim 23, wherein, The word line driver is further configured to: During a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string; And During a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string.

25. The storage device according to claim 23 or 24, wherein, The word line driver is further configured to: During the pre-pulse period but not during the post-pulse period in the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string; And During the pre-pulse period but not during the post-pulse period in the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string.

26. The storage device according to claim 23 or 24, wherein, The word line driver is further configured to: During the post-pulse period but not during the pre-pulse period in the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string; And During the post-pulse period but not during the pre-pulse period in the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the non-selected memory string.

27. The storage device according to any one of claims 21-26, wherein, The DSG transistor in the selected memory string is electrically isolated from the DSG transistor in the non-selected memory string.

28. A method for operating a memory device, the memory device including a plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor, the method comprising: During only one of a pre-pulse period or a post-pulse period in a first cycle of a programming operation, turn on the DSG transistor in the non-selected memory string among the plurality of memory strings; And During only one of a pre-pulse period or a post-pulse period in a second cycle of the programming operation after the first cycle, turn on the DSG transistor in the non-selected memory string.

29. The method according to claim 28, wherein The programming operation is incremental step pulse programming (ISPP), and the first cycle and the second cycle are respectively the start cycle and the end cycle of the ISPP.

30. The method according to claim 28 or 29, further comprising: During only one of a pre-pulse period or a post-pulse period in the first cycle of the programming operation, turn on the SSG transistor in the non-selected memory string; And During only one of a pre-pulse period or a post-pulse period in the second cycle of the programming operation, turn on the SSG transistor in the non-selected memory string.

31. The method according to claim 30, further comprising: During a verification period between a pre-pulse period and a post-pulse period in the first cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string; And During a verification period between a pre-pulse period and a post-pulse period in the second cycle of the programming operation, turn off the DSG transistor and the SSG transistor in the non-selected memory string.

32. The method according to claim 30 or 31, further comprising: During the pre-pulse period but not during the post-pulse period of the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the unselected memory string; And During the pre-pulse period but not during the post-pulse period of the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the unselected memory string.

33. The method according to claim 30 or 31, further comprising: During the post-pulse period but not during the pre-pulse period of the first cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the unselected memory string; And During the post-pulse period but not during the pre-pulse period of the second cycle of the programming operation, turn on the DSG transistor and the SSG transistor in the unselected memory string.

34. The method according to any one of claims 28-33, wherein The DSG transistor in the selected memory string is electrically isolated from the DSG transistor in the unselected memory string.

35. A system, comprising: A storage device, comprising: A plurality of memory strings, each of the memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; and Peripheral circuitry coupled to the plurality of memory strings and configured to: in a programming operation, program a selected memory cell in a selected memory string among the plurality of memory strings and inhibit an unselected memory cell in an unselected memory string among the plurality of memory strings, wherein the peripheral circuitry includes: A word line driver configured to: Turn on the DSG transistor in the unselected memory string in only one of the pre-pulse period or the post-pulse period of the first cycle of the programming operation; and Turn on the DSG transistor in the unselected memory string in only one of the pre-pulse period or the post-pulse period of the second cycle of the programming operation after the first cycle; and A memory controller coupled to the storage device and configured to control the storage device.

36. A storage device, comprising: A plurality of memory strings, each of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; And Peripheral circuitry coupled to the plurality of memory strings and configured to, in a programming operation: During the pre-pulse period and the post-pulse period of the first cycle of the programming operation, apply a select voltage to a first DSG transistor in a first memory string among the plurality of memory strings and apply a deselect voltage to a second DSG transistor in a second memory string among the plurality of memory strings; And During at least one of the pre-pulse period or the post-pulse period of the second cycle of the programming operation after the first cycle, apply the select voltage to the first DSG transistor in the first memory string and apply the deselect voltage to the second DSG transistor in the second memory string.

37. The storage device according to claim 36, wherein, The peripheral circuitry is further configured to: During a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation, a select voltage is applied to a first SSG transistor in the first memory string, and a deselect voltage is applied to a second SSG transistor in the second memory string; And During a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation, a select voltage is applied to a first SSG transistor in the first memory string, and a deselect voltage is applied to a second SSG transistor in the second memory string.

38. The storage device according to claim 36 or 37, wherein, The select voltage is a positive voltage, and the deselect voltage is a ground voltage.

39. A memory device, comprising: A plurality of memory strings, each memory string of the plurality of memory strings including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor; And Peripheral circuitry coupled to the plurality of memory strings and configured to, in a programming operation: During a pre-pulse period and a post-pulse period in a first cycle of the programming operation, apply a select voltage to a first DSG transistor in a first memory string of the plurality of memory strings; During one of the pre-pulse period or the post-pulse period in a first cycle of the programming operation, apply a deselect voltage to a second DSG transistor in a second memory string of the plurality of memory strings; During a pre-pulse period and a post-pulse period in a second cycle of the programming operation after the first cycle, apply the select voltage to the first DSG transistor in the first memory string; And During one of the pre-pulse period or the post-pulse period in a second cycle of the programming operation, apply the deselect voltage to the second DSG transistor in the second memory string.

40. The storage device according to claim 39, wherein, The peripheral circuitry is further configured to: During a verification period between a pre-pulse period and a post-pulse period in a first cycle of the programming operation, apply the select voltage to a first SSG transistor in the first memory string, and apply the deselect voltage to a second SSG transistor in the second memory string; And During a verification period between a pre-pulse period and a post-pulse period in a second cycle of the programming operation, apply the select voltage to a first SSG transistor in the first memory string, and apply the deselect voltage to a second SSG transistor in the second memory string.

41. The storage device according to claim 39 or 40, wherein, The select voltage is a positive voltage, and the deselect voltage is a ground voltage.

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