Inspection system

Abstract

This inspection system is provided with: a semiconductor substrate on which a first inspection circuit and a second inspection circuit are formed; a measurement unit that measures predetermined characteristics in each of the first inspection circuit and the second inspection circuit; and an estimation unit that estimates the first inspection circuit and the second inspection circuit on the basis of a first measurement result obtained by measuring the first inspection circuit by the measurement unit and a second measurement result obtained by measuring the second inspection circuit by the measurement unit. The process variation is estimated when the first inspection circuit and the second inspection circuit are formed on the semiconductor substrate. The size of the variation in the characteristic with respect to the process variation in the second inspection circuit is different from the size of the variation in the characteristic with respect to the process variation in the first inspection circuit.

Description

Technical Field

[0001] The present invention relates to an inspection system. Background Art

[0002] In order to evaluate a semiconductor process or component, a TEG (Test Element Group) formed on a semiconductor substrate is used. Patent Document 1 discloses a semiconductor device in which a plurality of TEGs are arranged in a scribe region. Patent Document 2 discloses a test circuit in which a plurality of monitor TEGs are mixed and mounted together with a semiconductor device on the same chip and are dispersedly arranged at arbitrary positions within the chip.

[0003] <Prior Art Documents>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-217258

[0006] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-012639 Summary of the Invention

[0007] <Problems to be Solved by the Invention>

[0008] The present invention provides a technique for estimating process variations in a semiconductor process.

[0009] <Means for Solving the Problems>

[0010] According to one aspect of the present invention, there is provided an inspection system including: a semiconductor substrate on which a first inspection circuit and a second inspection circuit are formed; a measurement unit that measures predetermined characteristics in each of the first inspection circuit and the second inspection circuit; and an estimation unit that estimates process variations when the first inspection circuit and the second inspection circuit are formed on the semiconductor substrate, based on a first measurement result obtained by the measurement unit measuring the first inspection circuit and a second measurement result obtained by the measurement unit measuring the second inspection circuit, wherein a magnitude of a variation in the characteristic with respect to the process variation in the second inspection circuit is different from a magnitude of a variation in the characteristic with respect to the process variation in the first inspection circuit.

[0011] <Effects of the Invention>

[0012] The present invention provides a technique for estimating process variations in a semiconductor process. Brief Description of the Drawings

[0013] Figure 1 is a diagram showing an overall configuration of an inspection system according to a first embodiment.

[0014] Figure 2 It is a diagram of the semiconductor substrate of the inspection system according to the first embodiment.

[0015] Figure 3 It is a flowchart illustrating the inspection method using the inspection system according to the first embodiment.

[0016] Figure 4 It is a diagram showing the overall structure of the inspection system according to the second embodiment.

[0017] Figure 5 It is a diagram for explaining the inspection circuit of the inspection system according to the second embodiment.

[0018] Figure 6 It is a diagram for explaining the inspection circuit of the inspection system according to the second embodiment.

[0019] Figure 7 It is a circuit diagram showing the element circuits constituting the inspection circuit of the inspection system according to the third embodiment.

[0020] Figure 8 It is a circuit diagram showing the element circuits constituting the inspection circuit of the inspection system according to the third embodiment.

[0021] Figure 9 It is a circuit diagram showing the element circuits constituting the inspection circuit of the inspection system according to the third embodiment.

[0022] Figure 10 It is a circuit diagram showing the element circuits constituting the inspection circuit of the inspection system according to the fourth embodiment.

[0023] Figure 11 It is a circuit diagram showing the element circuits constituting the inspection circuit of the inspection system according to the fourth embodiment.

[0024] Figure 12 It is a diagram showing the structure of the element circuits constituting the inspection circuit of the inspection system according to the fifth embodiment.

[0025] Figure 13 It is a diagram showing the structure of the element circuits constituting the inspection circuit of the inspection system according to the fifth embodiment.

[0026] Figure 14 It is a diagram showing the structure of the element circuits constituting the inspection circuit of the inspection system according to the fifth embodiment.

[0027] Figure 15 It is a diagram showing the structure of the element circuits constituting the inspection circuit of the inspection system according to the fifth embodiment.

[0028] Figure 16 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0029] Figure 17 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0030] Figure 18 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0031] Figure 19 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0032] Figure 20 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0033] Figure 21 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0034] Figure 22 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0035] Figure 23 This is a diagram showing the structure of the element circuit of the inspection circuit that constitutes the inspection system according to the fifth embodiment.

[0036] Figure 24 This is a diagram showing the overall structure of the inspection system according to the sixth embodiment.

[0037] Figure 25 This is a diagram showing the overall structure of the inspection system according to the seventh embodiment.

[0038] Figure 26 This is a diagram for explaining the inspection circuit of the inspection system according to the seventh embodiment.

[0039] Figure 27 This is a diagram for explaining an operation example of the inspection system according to the present embodiment.

[0040] Figure 28 This is a diagram for explaining an operation example of the inspection system according to the present embodiment.

[0041] Figure 29 This is a diagram for explaining an operation example of the inspection system according to the present embodiment.

[0042] Figure 30This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0043] Figure 31 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0044] Figure 32 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0045] Figure 33 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0046] Figure 34 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0047] Figure 35 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0048] Figure 36 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0049] Figure 37 This is a diagram for explaining an operation example of the inspection system according to this embodiment.

[0050] Figure 38 This is a circuit diagram for explaining a modified example of an element circuit of an inspection circuit constituting the inspection system according to this embodiment.

[0051] Figure 39 This is a circuit diagram for explaining a modified example of an element circuit of an inspection circuit constituting the inspection system according to this embodiment.

[0052] Figure 40 This is a circuit diagram for explaining a modified example of an element circuit of an inspection circuit constituting the inspection system according to this embodiment.

[0053] Figure 41 This is a circuit diagram for explaining a modified example of an element circuit of an inspection circuit constituting the inspection system according to this embodiment. Detailed Embodiment

[0054] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, the present invention is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0055] In addition, regarding the descriptions in the specifications and drawings related to the respective embodiments, for components having substantially the same or corresponding functional structures, duplicate descriptions are sometimes omitted by assigning the same or corresponding reference numerals. Also, for ease of understanding, the scales of the respective parts in the drawings are sometimes different from the actual ones.

[0056] <<First Embodiment>>

[0057] The inspection system according to the first embodiment will be described. The inspection system according to the first embodiment estimates process variations when forming the first inspection circuit and the second inspection circuit on a semiconductor substrate on which the first inspection circuit and the second inspection circuit are formed. The inspection system according to the first embodiment estimates process variations by measuring characteristics in the first inspection circuit and the second inspection circuit whose variations with respect to process variations are different.

[0058] <<Inspection System>>

[0059] Figure 1 FIG. is a diagram showing the overall structure of an inspection system 1 as an example of the inspection system according to the first embodiment. Taking the inspection system 1 as an example, the inspection system according to the first embodiment will be described.

[0060] The inspection system 1 includes a semiconductor substrate 10 and an inspection device 20.

[0061] [[Semiconductor Substrate 10]]

[0062] The semiconductor substrate 10 is a substrate on which wirings and circuit elements are formed. The semiconductor substrate 10 forms wirings and circuit elements by performing a plurality of processes on a silicon substrate.

[0063] In addition, the semiconductor substrate 10 is not limited to a silicon substrate, and may be, for example, a silicon carbide substrate or a gallium arsenide substrate.

[0064] The structure of the semiconductor substrate 10 will be described. Figure 2 FIG. is a diagram for explaining the semiconductor substrate 10 of the inspection system 1 which is an example of the inspection system according to the present embodiment. The semiconductor substrate 10 has a substantially circular shape in plan view.

[0065] The semiconductor substrate 10 has a plurality of chips 11. Each of the plurality of chips 11 includes required circuits. Each of the plurality of chips 11 operates through the required circuits to achieve required functions.

[0066] In addition, the semiconductor substrate 10 includes a plurality of TEGs 12 and a plurality of TEGs 13 for evaluating processes and components. The TEG 12 is used to evaluate process variations. The TEG 12 includes an inspection circuit for evaluating process variations. The TEG 13 is used to evaluate components. The TEG 13 is used for electrical measurements such as the threshold voltage of transistors performed during WAT (Wafer Acceptance Test).

[0067] The plurality of TEGs 12 are respectively disposed near any one of the plurality of chips 11. Similarly, the plurality of TEGs 13 are respectively disposed near any one of the plurality of chips 11. By inspecting the TEG 12 and the TEG 13 respectively, the states of the chips 11 located near the TEG 12 and the TEG 13 can be inspected.

[0068] The semiconductor substrate 10 has a plurality of chip formation regions 14 in which the plurality of chips 11 are respectively formed. After forming the plurality of chips 11, the semiconductor substrate 10 is cut into individual chips 11 by a dicing machine. The semiconductor substrate 10 has a cutting region 15, which is a region for cutting the plurality of chips 11 respectively, between adjacent chip formation regions 14.

[0069] The TEG 12 and the TEG 13 are respectively formed in the cutting region 15. In addition, either one of the TEG 12 and the TEG 13 may be formed in the chip formation region 14.

[0070] Details of the TEG 12 will be described. The TEG 12 has a plurality of inspection circuits with different variations in given characteristics with respect to a given process variation when processing the semiconductor substrate 10. The TEG 12 has an inspection circuit 12a and an inspection circuit 12b.

[0071] Regarding the process variations in the case of processing the semiconductor substrate 10, for example, there are variations in the ion concentration doped in the semiconductor layer and variations in the oxide film thickness. When the ion concentration and the oxide film thickness change, for example, the threshold voltage in a MOS (Metal-Oxide-Semiconductor) transistor changes. Regarding the inspection circuit 12a, when there is a process variation, a given characteristic changes. Similarly, regarding the inspection circuit 12b, when there is a process variation, a given characteristic changes. As the characteristic value, for example, it is frequency, voltage, current, etc.

[0072] Regarding the inspection circuit 12a and the inspection circuit 12b, the sensitivities to a given characteristic with respect to process variations are different. In other words, the magnitude of the variation in the characteristic with respect to process variations in either the inspection circuit 12a or the inspection circuit 12b is different from the magnitude of the variation in the characteristic value with respect to process variations in the other of the inspection circuit 12a and the inspection circuit 12b.

[0073] For example, the variation in the characteristic with respect to process variations in the inspection circuit 12b is made greater than the variation in the characteristic with respect to process variations in the inspection circuit 12a. By making the variation in the characteristic with respect to process variations in the inspection circuit 12b greater than the variation in the characteristic with respect to process variations in the inspection circuit 12a, it is possible to detect process variations that cannot be detected by the inspection result of the inspection circuit 12a.

[0074] [Inspection device 20]

[0075] The inspection device 20 measures the characteristics in each of the inspection circuit 12a and the inspection circuit 12b. In addition, the inspection device 20 estimates the process variations when the inspection circuit 12a and the inspection circuit 12b are respectively formed based on the characteristics in the inspection circuit 12a and the inspection circuit 12b that have been measured.

[0076] The inspection device 20 includes a measurement unit 21 and an estimation unit 22.

[0077] (Measurement unit 21)

[0078] The measurement unit 21 measures the characteristics in each of the inspection circuit 12a and the inspection circuit 12b. The measurement unit 21 is connected to the inspection circuit 12a and the inspection circuit 12b in any one of the plurality of TEGs 12 through the wiring Lm.

[0079] The measurement unit 21 supplies power to the inspection circuit 12a to be measured and detects the signal SIGa output from the inspection circuit 12a. Then, the measurement unit 21 measures a predetermined characteristic based on the signal SIGa. In addition, the measurement unit 21 supplies power to the inspection circuit 12b to be measured and detects the signal SIGb output from the inspection circuit 12b. Then, the measurement unit 21 measures a predetermined characteristic based on the signal SIGb.

[0080] The measurement unit 21 outputs the measurement result Ra of the predetermined characteristic measured in the inspection circuit 12a and the measurement result Rb of the predetermined characteristic measured in the inspection circuit 12b to the estimation unit 22.

[0081] The predetermined characteristic measured by the measurement unit 21 is, for example, frequency, voltage, current, etc.

[0082] (Estimation unit 22)

[0083] The estimation unit 22 estimates the process variations when the inspection circuits 12a and 12b are respectively formed. The estimation unit 22 estimates the process variations based on the measurement results Ra and Rb measured by the measurement unit 21.

[0084] For example, the estimation unit 22 estimates the variations in ion concentration and oxide film thickness in the semiconductor process based on the measurement result Ra and the measurement result Rb.

[0085] <Inspection method>

[0086] An inspection method using the inspection system according to the first embodiment will be described. Figure 3 It is a flowchart for explaining the inspection method of the inspection system 1 which is an example of the inspection system according to the first embodiment. Each process of the inspection method will be described.

[0087] (Step S10)

[0088] First, the inspection system 1 measures the predetermined characteristics of each of the inspection circuits 12a and 12b formed on the semiconductor substrate 10. More specifically, the measurement unit 21 measures the predetermined characteristics of each of the inspection circuits 12a and 12b formed on the semiconductor substrate 10.

[0089] The measurement unit 21 is connected to the inspection circuits 12a and 12b included in the TEG 12 to be inspected among the plurality of TEGs 12 formed on the semiconductor substrate 10 via the wiring Lm. Then, the measurement unit 21 measures the predetermined characteristics of the connected inspection circuits 12a and 12b.

[0090] (Step S11)

[0091] First, the measurement unit 21 measures the characteristics of the inspection circuit 12a. The measurement unit 21 supplies the power required to operate the inspection circuit 12a to the inspection circuit 12a. The measurement unit 21 detects the signal SIGa of the inspection circuit 12a. Then, the measurement unit 21 measures the predetermined characteristics based on the signal SIGa. The measurement unit 21 outputs the result Ra obtained by measuring the predetermined characteristics to the estimation unit 22. After the measurement of the inspection circuit 12a by the measurement unit 21 is completed, the supply of power to the inspection circuit 12a is stopped.

[0092] (Step S12)

[0093] Next, the measurement unit 21 measures the characteristics of the inspection circuit 12b. The measurement unit 21 supplies the power required to operate the inspection circuit 12b to the inspection circuit 12b. The measurement unit 21 detects the signal SIGb of the inspection circuit 12b. Then, the measurement unit 21 measures the predetermined characteristics based on the signal SIGb. The measurement unit 21 outputs the measurement result Rb obtained by measuring the predetermined characteristics to the estimation unit 22. After the measurement of the inspection circuit 12b by the measurement unit 21 is completed, the power supply to the inspection circuit 12b is stopped.

[0094] In addition, in the above description, after the measurement of the inspection circuit is completed, the power supply to the inspection circuit is stopped, but another power supply may be connected to the inspection circuit, and the power supply to the inspection circuit may be continued even when the inspection circuit is not being measured.

[0095] (Step S20)

[0096] Next, the inspection system 1 estimates process variations based on the measurement result Ra obtained by measuring the inspection circuit 12a and the measurement result Rb obtained by measuring the inspection circuit 12b. More specifically, the estimation unit 22 estimates the process variations when forming the inspection circuit 12a and the inspection circuit 12b on the semiconductor substrate 10 based on the measurement result Ra and the measurement result Rb.

[0097] The estimation unit 22 acquires the measurement result Ra obtained by measuring the inspection circuit 12a from the measurement unit 21. In addition, the estimation unit 22 acquires the measurement result Rb obtained by measuring the inspection circuit 12b from the measurement unit 21.

[0098] The inspection circuit 12a and the inspection circuit 12b have different magnitudes of variation in the predetermined characteristics with respect to a specific process variation in the plurality of processes for processing the semiconductor substrate 10. Therefore, if the measurement result Ra and the measurement result Rb are compared, the variation can be emphasized and observed for a specific process variation. By emphasizing and observing the variation for a specific process variation, the existence of a specific process variation can be estimated.

[0099] (Step S30)

[0100] Next, the inspection system 1 determines whether to end the process. More specifically, the estimation unit 22 determines whether to end the process. In the case of ending the process (Yes in Step S30), the estimation unit 22 ends the process. In the case of not ending the process, in other words, in the case of continuing the process (No in Step S30), the estimation unit 22 returns to Step S10 and repeats the process. For example, the inspection system 1 inspects a plurality of TEGs 12 in the semiconductor substrate 10 by repeating the process.

[0101] <Summary>

[0102] According to the inspection system related to the first embodiment, process variations in a semiconductor process can be estimated.

[0103] In addition, the inspection circuit 12a is an example of a first inspection circuit, and the inspection circuit 12b is an example of a second inspection circuit. The measurement result Ra is an example of a first measurement result, and the measurement result Rb is an example of a second measurement result.

[0104] <Second Embodiment>

[0105] An inspection system related to the second embodiment will be described. The inspection system related to the second embodiment estimates process variations when forming a first inspection circuit and a second inspection circuit on a semiconductor substrate for the semiconductor substrate on which the first inspection circuit and the second inspection circuit are formed. The inspection system related to the second embodiment estimates process variations by measuring characteristics in the first inspection circuit and the second inspection circuit, which have different variations in characteristics with respect to process variations.

[0106] <Inspection System>

[0107] Figure 4 FIG. shows the overall structure of an inspection system 2 as an example of the inspection system related to the second embodiment. Taking the inspection system 2 as an example, the inspection system related to the second embodiment will be described.

[0108] The inspection system 2 includes a semiconductor substrate 110 and an inspection device 120.

[0109] [Semiconductor Substrate 110]

[0110] The semiconductor substrate 110 is a substrate on which wirings and circuit elements are formed. The semiconductor substrate 110 includes a TEG 112 instead of the TEG 12 in the semiconductor substrate 10. For details of the semiconductor substrate 110 other than the TEG 112, refer to the description of the semiconductor substrate 10, and details of the TEG 112 will be described here.

[0111] The TEG 112 has a plurality of inspection circuits with different variations in given characteristics with respect to a given process variation when the semiconductor substrate 110 is processed. The TEG 112 has an inspection circuit 112a and an inspection circuit 112b.

[0112] The inspection circuit 112a and the inspection circuit 112b will be described separately. Figure 5 FIG. is a diagram for explaining the inspection circuit 112a of the inspection system 2 as an example of the inspection system related to the second embodiment. Figure 6 FIG. is a diagram for explaining the inspection circuit 112b of the inspection system 2 as an example of the inspection system related to the second embodiment.

[0113] The inspection circuit 112a includes a plurality of element circuits 112A. The inspection circuit 112a includes an odd number of element circuits 112A. The plurality of element circuits 112A are connected in series.

[0114] The plurality of element circuits 112A are respectively circuits of an inverted logic. The inspection circuit 112a inputs the output of the last-stage element circuit 112A among the odd number of element circuits 112A to the first-stage element circuit 112A. The inspection circuit 112a is a feedback-type oscillation circuit. The inspection circuit 112a is a so-called ring oscillator (ring oscillation circuit). When power is supplied to the inspection circuit 112a, it outputs an AC signal, i.e., signal OSCa, having a frequency caused by the delay in each element circuit 112A.

[0115] The inspection circuit 112b includes a plurality of element circuits 112B. The inspection circuit 112b includes an odd number of element circuits 112B. The plurality of element circuits 112B are connected in series.

[0116] The plurality of element circuits 112B are respectively circuits of an inverted logic. The inspection circuit 112b inputs the output of the last element circuit 112B among the odd number of element circuits 112B to the starting element circuit 112B. The inspection circuit 112b is a feedback-type oscillation circuit. The inspection circuit 112b is a so-called ring oscillator (ring oscillation circuit). When power is supplied to the inspection circuit 112b, it outputs an AC signal, i.e., signal OSCb, having a frequency caused by the delay in each element circuit 112B.

[0117] The influence degrees of the frequency variations corresponding to the process variations in the substrate processing process when forming the semiconductor substrate 110 for the element circuit 112A and the element circuit 112B are different.

[0118] [Inspection device 120]

[0119] The inspection device 120 measures a predetermined characteristic, i.e., the frequency, in each of the inspection circuit 112a and the inspection circuit 112b. In addition, the inspection device 120 estimates the process variations when forming each of the inspection circuit 112a and the inspection circuit 112b based on the characteristics measured in the inspection circuit 112a and the inspection circuit 112b.

[0120] The inspection device 120 includes a measurement unit 121 and an estimation unit 122.

[0121] (Measurement unit 121)

[0122] The measurement unit 121 measures the characteristics in each of the inspection circuits 112a and 112b. The measurement unit 121 is respectively connected in series with the inspection circuit 112a and the inspection circuit 112b in any one of the plurality of TEGs 112 through the wiring Lm.

[0123] The measurement unit 121 supplies power to the inspection circuit 112a to be measured and detects the signal OSCa output from the inspection circuit 112a. Then, the measurement unit 121 measures a predetermined characteristic based on the signal OSCa. The measurement unit 121 measures the frequency of the signal OSCa as a predetermined characteristic.

[0124] In addition, the measurement unit 121 supplies power to the inspection circuit 112b to be measured and detects the signal OSCb output from the inspection circuit 112b. Then, the measurement unit 121 measures a predetermined characteristic based on the signal OSCb. The measurement unit 121 measures the frequency of the signal OSCb as a predetermined characteristic.

[0125] The measurement unit 121 outputs the measurement result Rfa obtained by measuring the frequency of the signal OSCa, which is the predetermined characteristic in the inspection circuit 112a, and the measurement result Rfb obtained by measuring the frequency of the signal OSCb, which is the predetermined characteristic in the inspection circuit 12b, to the estimation unit 122.

[0126] (Estimation unit 122)

[0127] The estimation unit 122 estimates the process variations in the formation of each of the inspection circuits 112a and 112b. The estimation unit 122 estimates the process variations based on the measurement result Rfa and the measurement result Rfb measured by the measurement unit 121.

[0128] <Summary>

[0129] According to the inspection system according to the second embodiment, it is possible to estimate process variations in the semiconductor process.

[0130] In addition, the plurality of element circuits 112A is an example of a plurality of first element circuits, the element circuit 112A is an example of a first element circuit, and the inspection circuit 112a is an example of a first inspection circuit. The plurality of element circuits 112B is an example of a plurality of second element circuits, the element circuit 112B is an example of a second element circuit, and the inspection circuit 112b is an example of a second inspection circuit.

[0131] <<Third Embodiment>

[0132] Next, the inspection system according to the third embodiment will be described. The inspection system according to the third embodiment is an inspection system having a further limited structure for the element circuits 112A and 112B in the inspection system according to the second embodiment. The element circuits 112A and 112B are selected such that the inspection circuit 112a having the element circuit 112A and the inspection circuit 112b having the inspection circuit 112b have different sensitivities to process variations. In the inspection system according to the third embodiment, the circuit functions and structures of the element circuits 112A and 112B are different.

[0133] <Element circuit>

[0134] The element circuits constituting the element circuits 112A and 112B respectively will be described. As the element circuits, a NOT circuit (inverter circuit), a NAND circuit (NAND gate circuit), and a NOR circuit (NOR gate circuit) will be described respectively.

[0135] [NOT circuit]

[0136] The NOT circuit is a logic negation circuit. The NOT circuit is a so-called inverter. Figure 7 It is a circuit diagram for explaining a NOT circuit 112i which is an example of an element circuit of an inspection circuit constituting the inspection system according to the third embodiment.

[0137] In addition, in the present invention, a p-type MOSFET (Metal-Oxide Semiconductor Field Effect Transitor) having a p-channel is referred to as a PMOS transistor. In addition, an n-type MOSFET having an n-channel is referred to as an NMOS transistor.

[0138] The NOT circuit 112i is a NOT circuit. The NOT circuit 112i has a PMOS transistor 112p1 and an NMOS transistor 112n1.

[0139] Either the source or the drain of the PMOS transistor 112p1 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p1 is connected to either the source or the drain of the NMOS transistor 112n1 and is connected to the output Out of the NOT circuit 112i. The other of the source and the drain of the NMOS transistor 112n1 is connected to the common potential Vss.

[0140] The gate of the PMOS transistor 112p1 and the gate of the NMOS transistor 112n1 are connected to the input In of the NOT circuit 112i.

[0141] [NAND Circuit]

[0142] The NAND circuit is a negative logic product circuit. Figure 8 It is a circuit diagram for explaining the NAND circuit 112nd, which is an example of an element circuit of the inspection circuit constituting the inspection system according to the third embodiment.

[0143] The NAND circuit 112nd is a NAND circuit. The NAND circuit 112nd includes a PMOS transistor 112p2, a PMOS transistor 112p3, an NMOS transistor 112n2, and an NMOS transistor 112n3.

[0144] Either the source and drain of the PMOS transistor 112p2 and the PMOS transistor 112p3 are connected to the power supply potential Vdd. The other of the source and drain of the PMOS transistor 112p2 and the PMOS transistor 112p3 is connected to either the source and drain of the NMOS transistor 112n2 and is also connected to the output Out of the NAND circuit 112nd.

[0145] The other of the source and drain of the NMOS transistor 112n2 is connected to either the source and drain of the NMOS transistor 112n3.

[0146] The other of the source and drain of the NMOS transistor 112n3 is connected to the common potential Vss. The gate of the PMOS transistor 112p2 and the gate of the NMOS transistor 112n3 are connected to the input In of the NAND circuit 112nd. The gate of the PMOS transistor 112p3 is connected to the gate of the NMOS transistor 112n2 and is also connected to the power supply potential Vdd.

[0147] The NAND circuit 112nd, which is a NAND circuit, includes the NMOS transistor 112n2 and the NMOS transistor 112n3 connected in series between the power supply potential Vdd and the common potential Vss. Therefore, the NAND circuit 112nd strongly exhibits the influence of the n-channel possessed by the NMOS transistor 112n2 and the NMOS transistor 112n3. Since the NAND circuit 112nd strongly exhibits the influence of the n-channel, it will strongly exhibit an influence in the case of a change in the ion concentration of the n-channel. Therefore, by adopting the NAND circuit 112nd in either the inspection circuit 112a or the inspection circuit 112b, it is possible to detect a change in the ion concentration of the n-channel as a process variation.

[0148] [NOR Circuit]

[0149] The NOR circuit is a negative logic sum circuit.Figure 9 This is a circuit diagram for explaining an example of an element circuit, the NOR circuit 112nr, which is a component of the inspection circuit constituting the third embodiment of the inspection system.

[0150] The NOR circuit 112nr is a NOR circuit. The NOR circuit 112nr includes a PMOS transistor 112p4, a PMOS transistor 112p5, an NMOS transistor 112n4, and an NMOS transistor 112n5.

[0151] Either the source or the drain of the PMOS transistor 112p4 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p4 is connected to either the source or the drain of the PMOS transistor 112p5. The other of the source and the drain of the PMOS transistor 112p5 is connected to either the source or the drain of each of the NMOS transistor 112n4 and the NMOS transistor 112n5, and is also connected to the output Out of the NOR circuit 112nr.

[0152] The other of the source and the drain of each of the NMOS transistor 112n4 and the NMOS transistor 112n5 is connected to the common potential Vss. The gates of the PMOS transistor 112p4 and the NMOS transistor 112n4 are connected to the input In of the NOR circuit 112nr. The gate of the PMOS transistor 112p5 is connected to the gate of the NMOS transistor 112n5 and is also connected to the common potential Vss.

[0153] The NOR circuit 112nr, as a NOR circuit, includes the PMOS transistor 112p4 and the PMOS transistor 112p5 connected in series between the power supply potential Vdd and the common potential Vss. Therefore, the NOR circuit 112nr strongly exhibits the influence of the p-channel characteristics of the PMOS transistor 112p4 and the PMOS transistor 112p5. Since the NOR circuit 112nr strongly exhibits the influence of the p-channel, in the case of a change in the ion concentration of the p-channel, the influence will be strongly manifested. Therefore, by adopting the NOR circuit 112nr in either the inspection circuit 112a or the inspection circuit 112b, as a process variation, it is possible to detect a change in the ion concentration of the p-channel.

[0154] <Combination examples of the element circuit 112A and the element circuit 112B>

[0155] (First combination example)

[0156] The inspection circuit 112a includes a NOT circuit 112i as a NOT circuit, and is an element circuit 112A. In addition, the inspection circuit 112b includes a NAND circuit 112nd as a NAND circuit, and is an element circuit 112B.

[0157] (Second combination example)

[0158] The inspection circuit 112a includes a NOT circuit 112i as a NOT circuit, and is an element circuit 112A. In addition, the inspection circuit 112b includes a NOR circuit 112nr as a NOR circuit, and is an element circuit 112B.

[0159] (Third combination example)

[0160] The inspection circuit 112a includes a NAND circuit 112nd as a NAND circuit, and is an element circuit 112A. In addition, the inspection circuit 112b includes a NOR circuit 112nr as a NOR circuit, and is an element circuit 112B.

[0161] In addition, in the above examples, the circuit of the element circuit 112A and the circuit of the element circuit 112B may be replaced with each other.

[0162] <Summary>

[0163] According to the inspection system according to the third embodiment, process variations in the semiconductor process can be estimated. According to the inspection system according to the third embodiment, variations in ion concentration can be estimated in the case where there are variations in ion concentration.

[0164] In addition, an example in which the NOT circuit 112i is the first element circuit and the NAND circuit 112nd is the second element circuit will be described. The PMOS transistor 112p1 is an example of the first PMOS transistor, and the NMOS transistor 112n1 is an example of the first NMOS transistor. In addition, the PMOS transistor 112p2 is an example of the second PMOS transistor, and the PMOS transistor 112p3 is an example of the third PMOS transistor. The NMOS transistor 112n2 is an example of the second NMOS transistor, and the NMOS transistor 112n3 is an example of the third NMOS transistor.

[0165] Next, a case where the NOT circuit 112i is an example of the first element circuit and the NOR circuit 112nr is an example of the second element circuit will be described. The PMOS transistor 112p1 is an example of the first PMOS transistor, and the NMOS transistor 112n1 is an example of the first NMOS transistor. Further, the PMOS transistor 112p4 is an example of the fourth PMOS transistor, and the PMOS transistor 112p5 is an example of the fifth PMOS transistor. The NMOS transistor 112n4 is an example of the fourth NMOS transistor, and the NMOS transistor 112n5 is an example of the fifth NMOS transistor.

[0166] <<Fourth Embodiment>>

[0167] Next, the inspection system according to the fourth embodiment will be described. The inspection system according to the fourth embodiment is an inspection system having a more restricted structure with respect to the element circuits 112A and 112B in the inspection system according to the second embodiment. The element circuits 112A and 112B are selected such that the inspection circuit 112a having the element circuit 112A and the inspection circuit 112b having the inspection circuit 112b have different sensitivities to process variations. In the inspection system according to the fourth embodiment, the element circuits 112A and 112B have the same function but different circuit structures.

[0168] <<Element Circuit>>

[0169] The element circuits constituting the element circuits 112A and 112B will be described. As the element circuits, a NOT circuit (a NOT circuit with dummy circuits) connected to dummy circuits and a NOT circuit (a NOT circuit with dummy wirings) connected to dummy wirings will be described respectively.

[0170] [NOT Circuit with Dummy Circuits]

[0171] The NOT circuit with dummy circuits includes a NOT circuit and two dummy NOT circuits that are connected to the input but not to the output. In other words, the NOT circuit with dummy circuits includes a NOT circuit and two dummy NOT circuits that are connected to the input but have no output destination. By dividing the input into multiple parts and connecting them to multiple NOT circuits, the NOT circuit with dummy circuits can increase the apparent size of the gate capacitance in the element circuit. By increasing the gate capacitance in the element circuit, variations in the insulating film thickness can be estimated.

[0172] Regarding the NOT circuit with dummy circuits, Figure 10 will be used for the description. Figure 10This is a circuit diagram for explaining an example of an element circuit of an inspection circuit that constitutes the inspection system according to the fourth embodiment, namely, the NOT circuit 112i2.

[0173] The NOT circuit 112i2 includes a NOT circuit 112t1, a dummy NOT circuit 112t2, and a dummy NOT circuit 112t3.

[0174] The NOT circuit 112t1 is a NOT circuit. The NOT circuit 112t1 has a PMOS transistor 112p6 and an NMOS transistor 112n6.

[0175] Either the source or the drain of the PMOS transistor 112p6 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p6 is connected to either the source or the drain of the NMOS transistor 112n6, and is also connected to the output Out of the NOT circuit 112i2. The other of the source and the drain of the NMOS transistor 112n6 is connected to the common potential Vss. The gates of the PMOS transistor 112p6 and the NMOS transistor 112n6 are connected to the input In of the NOT circuit 112i2.

[0176] The dummy NOT circuit 112t2 is a NOT circuit. Here, the dummy NOT circuit 112t2 is connected to the input In of the NOT circuit 112i2, but not connected to the output Out of the NOT circuit 112i2. In other words, the dummy NOT circuit 112t2 is a circuit without an output destination. The dummy NOT circuit 112t2 has a PMOS transistor 112p7 and an NMOS transistor 112n7.

[0177] Either the source or the drain of the PMOS transistor 112p7 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p7 is connected to either the source or the drain of the NMOS transistor 112n7. The other of the source and the drain of the NMOS transistor 112n7 is connected to the common potential Vss. The gates of the PMOS transistor 112p7 and the NMOS transistor 112n7 are connected to the input In of the NOT circuit 112i2.

[0178] The dummy NOT circuit 112t3 is a NOT circuit. Here, the dummy NOT circuit 112t3 is connected to the input In of the NOT circuit 112i2, but not connected to the output Out of the NOT circuit 112i2. In other words, the dummy NOT circuit 112t3 is a circuit without an output destination. The dummy NOT circuit 112t3 has a PMOS transistor 112p8 and an NMOS transistor 112n8.

[0179] Either the source or the drain of the PMOS transistor 112p8 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p8 is connected to either the source or the drain of the NMOS transistor 112n8. The other of the source and the drain of the NMOS transistor 112n8 is connected to the common potential Vss. The gates of the PMOS transistor 112p8 and the NMOS transistor 112n8 are connected to the input In of the NOT circuit 112i2.

[0180] [NOT circuit with dummy wiring]

[0181] The NOT circuit with dummy wiring includes a NOT circuit and a wiring connected to the gate of the NOT circuit. The NOT circuit with dummy wiring is a circuit for eliminating the influence of the wiring in the NOT circuit with dummy circuit.

[0182] Regarding the NOT circuit with dummy wiring, Figure 11 an explanation will be given. Figure 11 FIG. is a circuit diagram for explaining the NOT circuit 112i3, which is an example of an element circuit of the inspection circuit constituting the inspection system according to the fourth embodiment.

[0183] The NOT circuit 112i3 includes a NOT circuit 112t4, a dummy wiring 112w1, and a dummy wiring 112w2.

[0184] The NOT circuit 112t4 is a NOT circuit. The NOT circuit 112t4 includes a PMOS transistor 112p9 and an NMOS transistor 112n9.

[0185] Either the source or the drain of the PMOS transistor 112p9 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p9 is connected to either the source or the drain of the NMOS transistor 112n9 and is connected to the output Out of the NOT circuit 112i3. The other of the source and the drain of the NMOS transistor 112n9 is connected to the common potential Vss. The gates of the PMOS transistor 112p9 and the NMOS transistor 112n9 are connected to the input In of the NOT circuit 112i3.

[0186] The dummy wiring 112w1 is a wiring having the same structure as the wiring from the input In to the dummy NOT circuit 112t2 in the NOT circuit 112i2.

[0187] The dummy wiring 112w2 is a wiring having the same structure as the wiring from the input In to the dummy NOT circuit 112t3 in the NOT circuit 112i2.

[0188] <Combined examples of element circuit 112A and element circuit 112B>

[0189] (First combined example)

[0190] The inspection circuit 112a includes a dummy circuit - equipped NOT circuit 112i2 as the element circuit 112A. Additionally, the inspection circuit 112b includes a dummy wiring - equipped NOT circuit 112i3 as the element circuit 112B.

[0191] (Second combined example)

[0192] The inspection circuit 112a includes a dummy circuit - equipped NOT circuit 112i2 as the element circuit 112A. Additionally, the inspection circuit 112b includes a NOT circuit 112i as the element circuit 112B.

[0193] Furthermore, in the above examples, the circuits constituting the element circuit 112A and the circuits constituting the element circuit 112B can also be interchanged with each other.

[0194] <Summary>

[0195] According to the inspection system related to the fourth embodiment, process variations in the semiconductor process can be estimated. According to the inspection system related to the fourth embodiment, in the case of variations in the insulating film thickness, the variations in the insulating film thickness can be estimated.

[0196] In addition, a case where the NOT circuit 112i2 is an example of the first element circuit and the NOT circuit 112i3 is an example of the second element circuit is described. The dummy NOT circuit 112t2 is an example of the first dummy NOT circuit, and the dummy NOT circuit 112t3 is an example of the second dummy NOT circuit. The dummy wiring 112w1 is an example of the first dummy wiring, and the dummy wiring 112w2 is an example of the second dummy wiring.

[0197] The PMOS transistor 112p6 is an example of the sixth PMOS transistor, and the NMOS transistor 112n6 is an example of the sixth NMOS transistor. Additionally, the PMOS transistor 112p7 is an example of the seventh PMOS transistor, the PMOS transistor 112p8 is an example of the eighth PMOS transistor, and the PMOS transistor 112p9 is an example of the ninth PMOS transistor. The NMOS transistor 112n7 is an example of the seventh NMOS transistor, the NMOS transistor 112n8 is an example of the eighth NMOS transistor, and the NMOS transistor 112n9 is an example of the ninth NMOS transistor.

[0198] In addition, in the above examples, although NOT circuits are used to form the element circuits, NAND circuits or NOR circuits can be used instead of NOT circuits.

[0199] Fifth Embodiment

[0200] Next, the inspection system according to the fifth embodiment will be described. The inspection system according to the fifth embodiment is an inspection system having a further limited structure for the element circuits 112A and 112B in the inspection system according to the second embodiment. The element circuits 112A and 112B are selected such that the inspection circuit 112a having the element circuit 112A and the inspection circuit 112b having the inspection circuit 112b have different sensitivities to process variations. In the inspection system according to the fifth embodiment, with respect to the element circuits 112A and 112B, the functions and circuit structures are the same, but the shapes of the circuits are different.

[0201] <Element Circuit>

[0202] The element circuits constituting the element circuits 112A and 112B respectively will be described. As the element circuits, the NOT circuit, the NAND circuit, and the NOR circuit will be described respectively.

[0203] [NOT Circuit]

[0204] As the element circuits constituting the element circuits 112A and 112B respectively, the case of using a NOT circuit will be described. The NOT circuit is selected from four types of NOT circuits having different sizes of MOS transistors constituting them, as any one of the element circuits 112A and 112B. The element circuits 112A and 112B are selected as different types of NOT circuits.

[0205] Figure 12 FIG. is a diagram for explaining the structure of the NOT circuit 112m1 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 13 FIG. is a diagram for explaining the structure of the NOT circuit 112m2 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 14 FIG. is a diagram for explaining the structure of the NOT circuit 112m3 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 15 FIG. is a diagram for explaining the structure of the NOT circuit 112m4 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment.

[0206] In addition, in Figures 12 to 15 each of the figures, with respect to the gate electrode and the semiconductor layer in the MOS transistor, a view from above the layer is shown. In Figures 12 to 15In the respective figures, electrical connections are represented by dotted lines. In addition, in Figures 12 to 15 In the respective figures, regarding the semiconductor layer, the semiconductor layers forming the source and drain of the MOS transistor around the gate electrode are shown, and the illustration of other semiconductor layers is omitted.

[0207] NOT circuits 112m1, 112m2, 112m3, and 112m4 each have the same element structure as the Figure 7 shown NOT circuit 112i. The gate widths of the PMOS transistors 112p1 or NMOS transistors 112n1 in NOT circuits 112m1, 112m2, 112m3, and 112m4 are different from each other.

[0208] (NOT circuit 112m1)

[0209] NOT circuit 112m1 includes a gate electrode GT. The gate electrode GT is provided across the PMOS transistor 112p1 and the NMOS transistor 112n1. The dimension L of the gate electrode GT corresponds to the gate length of each of the PMOS transistor 112p1 and the NMOS transistor 112n1. The dimension W1 corresponds to the gate width of each of the PMOS transistor 112p1 and the NMOS transistor 112n1.

[0210] The semiconductor layer PW1 is a semiconductor layer that becomes either the source or the drain of the PMOS transistor 112p1. The semiconductor layer PW2 is a semiconductor layer that becomes the other of the source and the drain of the PMOS transistor 112p1. The semiconductor layer NW1 is a semiconductor layer that becomes either the source or the drain of the NMOS transistor 112n1. The semiconductor layer NW2 is a semiconductor layer that becomes the other of the source and the drain of the NMOS transistor 112n1.

[0211] (NOT circuit 112m2)

[0212] NOT circuit 112m2 is different from NOT circuit 112m1 in that the gate width of the NMOS transistor 112n1 is dimension W2. In other words, the gate width of the NMOS transistor 112n1 in NOT circuit 112m2 is different from the gate width of the NMOS transistor 112n1 in NOT circuit 112m1.

[0213] (NOT circuit 112m3)

[0214] The NOT circuit 112m3 differs from the NOT circuit 112m1 in that the gate width of the PMOS transistor 112p1 is dimension W2. In other words, the gate width of the PMOS transistor 112p1 in the NOT circuit 112m3 is different from the gate width of the PMOS transistor 112p1 in the NOT circuit 112m1.

[0215] (NOT circuit 112m4)

[0216] The NOT circuit 112m4 differs from the NOT circuit 112m1 in that the gate widths of the NMOS transistor 112n1 and the PMOS transistor 112p1 are both dimension W2. In other words, the gate width of the NMOS transistor 112n1 in the NOT circuit 112m4 is different from the gate width of the NMOS transistor 112n1 in the NOT circuit 112m1. Additionally, the gate width of the PMOS transistor 112p1 in the NOT circuit 112m4 is different from the gate width of the PMOS transistor 112p1 in the NOT circuit 112m1.

[0217] As a variable that determines the driving ability of a MOS transistor, there is a drain current Id. The drain current Id is proportional to the gate oxide capacitance Cox per unit area. The drain current Id in the linear region of the MOS transistor is shown in Equation 1. The drain current Id in the saturation region of the MOS transistor is shown in Equation 2.

[0218]

Equation 1

[0219]

[0220]

Equation 2

[0221]

[0222] Here, Lg is the gate length, Wg is the gate width, μ is the mobility of electrons or holes, Vg is the gate-source voltage, Vd is the drain-source voltage, and Vt is the threshold voltage.

[0223] Therefore, by changing the dimension of the gate width Wg, for example, it is possible to make the variation of the gate oxide capacitance Cox different during the process variation.

[0224] The gate length Lg is a parameter that is particularly important for the structure of the transistor and is a dimension that is strictly managed. Therefore, it is usually difficult to change the strictly dimension-managed gate length Lg. Therefore, in the inspection device according to the present embodiment, by changing the gate width Wg, the variation of the characteristics with respect to the process variation is made different.

[0225] <Combination examples of the element circuits 112A and 112B>

[0226] (First combination example)

[0227] The inspection circuit 112a includes a NOT circuit 112m1 as the element circuit 112A. In addition, the inspection circuit 112b includes a NOT circuit 112m2 as the element circuit 112B.

[0228] (Second combination example)

[0229] The inspection circuit 112a includes a NOT circuit 112m1 as the element circuit 112A. In addition, the inspection circuit 112b includes a NOT circuit 112m3 as the element circuit 112B.

[0230] (Third combination example)

[0231] The inspection circuit 112a includes a NOT circuit 112m1 as the element circuit 112A. In addition, the inspection circuit 112b includes a NOT circuit 112m4 as the element circuit 112B.

[0232] (Other combination examples)

[0233] In addition, regarding the combination of the element circuit 112A and the element circuit 112B, it is not limited to the above examples, and two circuits can be appropriately selected from the NOT circuit 112m1, the NOT circuit 112m2, the NOT circuit 112m3, and the NOT circuit 112m4. In addition, in the above examples, the circuit constituting the element circuit 112A and the circuit constituting the element circuit 112B can also be interchanged with each other.

[0234] [NAND circuit]

[0235] As the element circuits respectively constituting the element circuit 112A and the element circuit 112B, the case of using a NAND circuit will be described. The NAND circuit is selected from four types of NAND circuits having different MOS transistor sizes as any one of the element circuit 112A and the element circuit 112B. The element circuit 112A and the element circuit 112B are selected as different types of NAND circuits.

[0236] Figure 16 FIG. is a diagram for explaining the structure of a NAND circuit 112d1 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 17 FIG. is a diagram for explaining the structure of a NAND circuit 112d2 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 18 FIG. is a diagram for explaining the structure of a NAND circuit 112d3 which is an example of the element circuit of the inspection circuit constituting the inspection system according to the fifth embodiment. Figure 19FIG. is a diagram for explaining the structure of a NAND circuit 112d4, which is an example of an element circuit of an inspection circuit constituting the inspection system according to the fifth embodiment.

[0237] In addition, in each of the Figures 16 to 19 figures, for the gate electrode and the semiconductor layer in the MOS transistor, a view from above the layer is shown. In each of the Figures 16 to 19 figures, electrical connection is indicated by a dotted line. In addition, in each of the Figures 16 to 19 figures, for the semiconductor layer, the semiconductor layers (diffusion layers) forming the source and drain of the MOS transistor around the gate electrode are shown, and illustration of other semiconductor layers is omitted.

[0238] The NAND circuit 112d1, the NAND circuit 112d2, the NAND circuit 112d3, and the NAND circuit 112d4 each have the same element structure as the Figure 8 shown NAND circuit 112nd. The gate widths of the PMOS transistors, which are p-type transistors, or the NMOS transistors, which are n-type transistors, in the NAND circuit 112d1, the NAND circuit 112d2, the NAND circuit 112d3, and the NAND circuit 112d4 are different from each other.

[0239] (NAND circuit 112d1)

[0240] The NAND circuit 112d1 includes a gate electrode GT1 and a gate electrode GT2. The gate electrode GT1 is provided across the PMOS transistor 112p2 and the NMOS transistor 112n3. The gate electrode GT2 is provided across the PMOS transistor 112p3 and the NMOS transistor 112n2. The size L of the gate electrode GT1 and the gate electrode GT2 corresponds to the gate length of each of the PMOS transistor 112p2, the PMOS transistor 112p3, the NMOS transistor 112n2, and the NMOS transistor 112n3. The size W3 corresponds to the gate width of each of the PMOS transistor 112p2, the PMOS transistor 112p3, the NMOS transistor 112n2, and the NMOS transistor 112n3.

[0241] The semiconductor layer PW3 is a semiconductor layer that becomes either the source or the drain of the PMOS transistor 112p2. The semiconductor layer PW4 is a semiconductor layer that becomes either the source or the drain of the PMOS transistor 112p3. The semiconductor layer PW5 is a semiconductor layer that becomes the other of the source and the drain of the PMOS transistor 112p2 and the other of the source and the drain of the PMOS transistor 112p3.

[0242] The semiconductor layer NW3 is a semiconductor layer that serves as either the source or the drain of the NMOS transistor 112n2. The semiconductor layer NW4 is a semiconductor layer that serves as the other of the source and the drain of the NMOS transistor 112n2 and either the source or the drain of the NMOS transistor 112n3. The semiconductor layer NW5 is a semiconductor layer that serves as the other of the source and the drain of the NMOS transistor 112n3.

[0243] (NAND circuit 112d2)

[0244] The NAND circuit 112d2 is different from the NAND circuit 112d1 in that the gate widths of the NMOS transistor 112n2 and the NMOS transistor 112n3 are each of the size W4. In other words, the gate width of the NMOS transistor 112n2 in the NAND circuit 112d2 is different from the gate width of the NMOS transistor 112n2 in the NAND circuit 112d1. Additionally, the gate width of the NMOS transistor 112n3 in the NAND circuit 112d2 is different from the gate width of the NMOS transistor 112n3 in the NAND circuit 112d1.

[0245] (NAND circuit 112d3)

[0246] The NAND circuit 112d3 is different from the NAND circuit 112d1 in that the gate widths of the PMOS transistor 112p2 and the PMOS transistor 112p3 are each of the size W4. In other words, the gate width of the PMOS transistor 112p2 in the NAND circuit 112d3 is different from the gate width of the PMOS transistor 112p2 in the NAND circuit 112d1. Additionally, the gate width of the PMOS transistor 112p3 in the NAND circuit 112d3 is different from the gate width of the PMOS transistor 112p3 in the NAND circuit 112d1.

[0247] (NAND circuit 112d4)

[0248] The NAND circuit 112d4 is different from the NAND circuit 112d1 in that the gate widths of the NMOS transistor 112n2 and the NMOS transistor 112n3 are each of the size W4. Additionally, the NAND circuit 112d4 is different from the NAND circuit 112d1 in that the gate widths of the PMOS transistor 112p2 and the PMOS transistor 112p3 are each of the size W4.

[0249] In other words, the gate width of the NMOS transistor 112n2 in the NAND circuit 112d4 is different from that of the NMOS transistor 112n2 in the NAND circuit 112d1. Additionally, the gate width of the NMOS transistor 112n3 in the NAND circuit 112d4 is different from that of the NMOS transistor 112n3 in the NAND circuit 112d1.

[0250] Moreover, the gate width of the PMOS transistor 112p2 in the NAND circuit 112d4 is different from that of the PMOS transistor 112p2 in the NAND circuit 112d1. The gate width of the PMOS transistor 112p3 in the NAND circuit 112d4 is different from that of the PMOS transistor 112p3 in the NAND circuit 112d1.

[0251] <Combination examples of the element circuits 112A and 112B>

[0252] (First combination example)

[0253] The inspection circuit 112a includes the NAND circuit 112d1 as the element circuit 112A. Additionally, the inspection circuit 112b includes the NAND circuit 112d2 as the element circuit 112B.

[0254] (Second combination example)

[0255] The inspection circuit 112a includes the NAND circuit 112d1 as the element circuit 112A. Additionally, the inspection circuit 112b includes the NAND circuit 112d3 as the element circuit 112B.

[0256] (Third combination example)

[0257] The inspection circuit 112a includes the NAND circuit 112d1 as the element circuit 112A. Additionally, the inspection circuit 112b includes the NAND circuit 112d4 as the element circuit 112B.

[0258] (Other combination examples)

[0259] Furthermore, regarding the combination of the element circuits 112A and 112B, it is not limited to the above examples, and two circuits can be appropriately selected from the NAND circuit 112d1, the NAND circuit 112d2, the NAND circuit 112d3, and the NAND circuit 112d4. Additionally, in the above examples, the circuit constituting the element circuit 112A and the circuit constituting the element circuit 112B can also be interchanged.

[0260] [NOR circuit]

[0261] As element circuits that respectively constitute element circuit 112A and element circuit 112B, the case of using a NOR circuit will be described. The NOR circuit is selected from four types of NOR circuits with different sizes of MOS transistors constituting it, and is used as either element circuit 112A or element circuit 112B. Element circuit 112A and element circuit 112B are selected in such a way that they are different types of NOR circuits.

[0262] Figure 20 A diagram for explaining the structure of NOR circuit 112r1, which is an example of an element circuit of an inspection circuit constituting the inspection system according to the fifth embodiment. Figure 21 A diagram for explaining the structure of NOR circuit 112r2, which is an example of an element circuit of an inspection circuit constituting the inspection system according to the fifth embodiment. Figure 22 A diagram for explaining the structure of NOR circuit 112r3, which is an example of an element circuit of an inspection circuit constituting the inspection system according to the fifth embodiment. Figure 23 A diagram for explaining the structure of NOR circuit 112r4, which is an example of an element circuit of an inspection circuit constituting the inspection system according to the fifth embodiment.

[0263] In addition, in Figures 20 to 23 each of the figures, for the gate electrode and the semiconductor layer in the MOS transistor, a view from above the layer is shown. Also, in Figures 20 to 23 each of the figures, electrical connection is indicated by a dotted line. And, in Figures 20 to 23 each of the figures, regarding the semiconductor layer, the semiconductor layers constituting the source and drain of the MOS transistor around the gate electrode are shown, and the illustration of other semiconductor layers is omitted.

[0264] NOR circuit 112r1, NOR circuit 112r2, NOR circuit 112r3, and NOR circuit 112r4 each have the same element structure as the Figure 9 shown NOR circuit 112nr. The gate widths of the PMOS transistors, which are p-type transistors, or the NMOS transistors, which are n-type transistors, in NOR circuit 112r1, NOR circuit 112r2, NOR circuit 112r3, and NOR circuit 112r4 are different from each other.

[0265] (NOR circuit 112r1)

[0266] The NOR circuit 112r1 includes a gate electrode GT3 and a gate electrode GT4. The gate electrode GT3 is disposed across the PMOS transistor 112p4 and the NMOS transistor 112n4. The gate electrode GT4 is disposed across the PMOS transistor 112p5 and the NMOS transistor 112n5. The dimension L of the gate electrode GT3 and the gate electrode GT4 corresponds to the gate length of each of the PMOS transistor 112p4, the PMOS transistor 112p5, the NMOS transistor 112n4, and the NMOS transistor 112n5. The dimension W5 corresponds to the gate width of each of the PMOS transistor 112p4, the PMOS transistor 112p5, the NMOS transistor 112n4, and the NMOS transistor 112n5.

[0267] The semiconductor layer PW6 is a semiconductor layer that serves as either the source or the drain of the PMOS transistor 112p4. The semiconductor layer PW7 is a semiconductor layer that serves as the other of the source and the drain of the PMOS transistor 112p4 and either the source or the drain of the PMOS transistor 112p5. The semiconductor layer PW8 is a semiconductor layer that serves as the other of the source and the drain of the PMOS transistor 112p5.

[0268] The semiconductor layer NW6 is a semiconductor layer that serves as either the source or the drain of the NMOS transistor 112n4 and either the source or the drain of the NMOS transistor 112n4. The semiconductor layer NW7 is a semiconductor layer that serves as the other of the source and the drain of the NMOS transistor 112n4. The semiconductor layer NW8 is a semiconductor layer that serves as the other of the source and the drain of the NMOS transistor 112n5.

[0269] (NOR circuit 112r2)

[0270] The NOR circuit 112r2 is different from the NOR circuit 112r1 in that the gate width of each of the NMOS transistor 112n4 and the NMOS transistor 112n5 is the dimension W6. In other words, the gate width of the NMOS transistor 112n4 in the NOR circuit 112r2 is different from the gate width of the NMOS transistor 112n4 in the NOR circuit 112r1. In addition, the gate width of the NMOS transistor 112n5 in the NOR circuit 112r2 is different from the gate width of the NMOS transistor 112n5 in the NOR circuit 112r1.

[0271] (NOR circuit 112r3)

[0272] The NOR circuit 112r3 is different from the NOR circuit 112r1 in that the gate widths of the PMOS transistors 112p4 and 112p5 are each of size W6. In other words, the gate width of the PMOS transistor 112p4 in the NOR circuit 112r3 is different from the gate width of the PMOS transistor 112p4 in the NOR circuit 112r1. Additionally, the gate width of the PMOS transistor 112p5 in the NOR circuit 112r3 is different from the gate width of the PMOS transistor 112p5 in the NOR circuit 112r1.

[0273] (NOR circuit 112r4)

[0274] The NOR circuit 112r4 is different from the NOR circuit 112r1 in that the gate widths of the NMOS transistors 112n4 and 112n5 are each of size W6. Additionally, the NOR circuit 112r4 is different from the NOR circuit 112r1 in that the gate widths of the PMOS transistors 112p4 and 112p5 are each of size W6.

[0275] In other words, the gate width of the NMOS transistor 112n4 in the NOR circuit 112r4 is different from the gate width of the NMOS transistor 112n4 in the NOR circuit 112r1. Additionally, the gate width of the NMOS transistor 112n5 in the NOR circuit 112r4 is different from the gate width of the NMOS transistor 112n5 in the NOR circuit 112r1.

[0276] Moreover, the gate width of the PMOS transistor 112p4 in the NOR circuit 112r4 is different from the gate width of the PMOS transistor 112p4 in the NOR circuit 112r1. Additionally, the gate width of the PMOS transistor 112p5 in the NOR circuit 112r4 is different from the gate width of the PMOS transistor 112p5 in the NOR circuit 112r1.

[0277] <Combination examples of the element circuits 112A and 112B>

[0278] (First combination example)

[0279] The inspection circuit 112a includes the NOR circuit 112r1 as the element circuit 112A. Additionally, the inspection circuit 112b includes the NOR circuit 112r2 as the element circuit 112B.

[0280] (Second combination example)

[0281] The inspection circuit 112a includes the NOR circuit 112r1 as the element circuit 112A. Additionally, the inspection circuit 112b includes the NOR circuit 112r3 as the element circuit 112B.

[0282] (Third combination example)

[0283] The inspection circuit 112a includes a NOR circuit 112r1 as an element circuit 112A. In addition, the inspection circuit 112b includes a NOR circuit 112r4 as an element circuit 112B.

[0284] (Other combination examples)

[0285] In addition, for the combination of the element circuit 112A and the element circuit 112B, it is not limited to the above examples, and two circuits can be appropriately selected from the NOR circuit 112r1, the NOR circuit 112r2, the NOR circuit 112r3, and the NOR circuit 112r4. In addition, in the above examples, the circuit constituting the element circuit 112A and the circuit constituting the element circuit 112B can also be interchanged with each other.

[0286] <Summary>

[0287] According to the inspection system according to the fifth embodiment, process variations in the semiconductor process can be estimated. According to the inspection system according to the fifth embodiment, in the case of a variation in the insulation film thickness, the variation in the insulation film thickness can be estimated.

[0288] In addition, the case where the NOT circuit 112m1 is an example of the first element circuit and the NOT circuit 112m2 is an example of the second element circuit will be described. The PMOS transistor 112p1 in the NOT circuit 112m1 is an example of the tenth PMOS transistor, and the NMOS transistor 112n1 is an example of the tenth NMOS transistor. In addition, the PMOS transistor 112p1 in the NOT circuit 112m2 is an example of the eleventh PMOS transistor, and the NMOS transistor 112n1 is an example of the eleventh NMOS transistor.

[0289] <Sixth Embodiment>

[0290] Next, the inspection system according to the sixth embodiment will be described. The inspection system according to the sixth embodiment includes three types of inspection circuits in the TEG on the semiconductor substrate.

[0291] <Inspection system>

[0292] Here, regarding the inspection system according to the sixth embodiment, the differences from the inspection system according to the first embodiment will be described. Figure 24 FIG. is a diagram showing the overall structure of an inspection system 3 which is an example of the inspection system according to the sixth embodiment. Taking the inspection system 3 as an example, the inspection system according to the sixth embodiment will be described.

[0293] The inspection system 3 includes a semiconductor substrate 210 and an inspection device 220.

[0294] [Semiconductor substrate 210]

[0295] The semiconductor substrate 210 has a TEG 212 instead of the TEG 12 of the semiconductor substrate 10. The TEG 212 has an inspection circuit 12a, an inspection circuit 12b, and an inspection circuit 12c.

[0296] The sensitivities of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c to a given characteristic value with respect to process variations are different from each other. In other words, the variation of the characteristic value with respect to process variations in any one of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c is different from the variation of the characteristic with respect to process variations in inspection circuits other than the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c.

[0297] [Inspection device 220]

[0298] The inspection device 220 measures the characteristics in each of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c. In addition, the inspection device 220 estimates the process variations when each of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c is formed, based on the characteristics measured in each of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c.

[0299] The inspection device 220 includes a measurement unit 221 and an estimation unit 222.

[0300] (Measurement unit 221)

[0301] The measurement unit 221 measures the characteristics in each of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c. The measurement unit 221 is connected to the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c in any one of the plurality of TEGs 212 through the wiring Lm, respectively.

[0302] The measurement unit 221 supplies power to the inspection circuit 12a to be measured and detects the signal SIGa output from the inspection circuit 12a. Then, the measurement unit 221 measures a predetermined characteristic based on the signal SIGa. In addition, the measurement unit 221 supplies power to the inspection circuit 12b to be measured and detects the signal SIGb output from the inspection circuit 12b. Then, the measurement unit 221 measures a predetermined characteristic based on the signal SIGb. In addition, the measurement unit 221 supplies power to the inspection circuit 12c to be measured and detects the signal SIGc output from the inspection circuit 12c. Then, the measurement unit 221 measures a predetermined characteristic based on the signal SIGc.

[0303] The measurement unit 221 outputs the measurement result Ra obtained by measuring a predetermined characteristic in the inspection circuit 12a, the measurement result Rb obtained by measuring a predetermined characteristic in the inspection circuit 12b, and the measurement result Rc obtained by measuring a predetermined characteristic in the inspection circuit 12c to the estimation unit 222.

[0304] (Estimation unit 222)

[0305] The estimation unit 222 estimates the process variations during the formation of the inspection circuit 12a, the inspection circuit 12b, and the inspection circuit 12c, respectively. The estimation unit 222 estimates the process variations based on the measurement result Ra, the measurement result Rb, and the measurement result Rc measured by the measurement unit 221.

[0306] <Summary>

[0307] According to the inspection system according to the sixth embodiment, it is possible to estimate process variations in the semiconductor process.

[0308] In addition, the inspection circuit 12a is an example of the first inspection circuit, the inspection circuit 12b is an example of the second inspection circuit, and the inspection circuit 12c is an example of the third inspection circuit. The measurement result Ra is an example of the first measurement result, the measurement result Rb is an example of the second measurement result, and the measurement result Rc is an example of the third measurement result.

[0309] In addition, in the above example, a semiconductor substrate having three inspection circuits with different characteristics has been described, but the number of inspection circuits is not limited to the above, and it may have four or more inspection circuits with different characteristics.

[0310] <<Seventh Embodiment>>

[0311] An inspection system according to the seventh embodiment will be described. The inspection system according to the seventh embodiment estimates process variations during the formation of the first inspection circuit, the second inspection circuit, and the third inspection circuit on a semiconductor substrate having the first inspection circuit, the second inspection circuit, and the third inspection circuit formed thereon. The inspection system according to the seventh embodiment estimates process variations by measuring characteristics in the first inspection circuit, the second inspection circuit, and the third inspection circuit, which have different variations in characteristics with respect to process variations.

[0312] <Inspection System>

[0313] Figure 25 FIG. is a diagram showing the overall structure of an inspection system 4 as an example of the inspection system according to the seventh embodiment. Taking the inspection system 4 as an example, the inspection system according to the seventh embodiment will be described.

[0314] The inspection system 4 includes a semiconductor substrate 310 and an inspection device 320.

[0315] [Semiconductor substrate 310]

[0316] The semiconductor substrate 310 is a substrate on which wirings and circuit elements are formed. The semiconductor substrate 310 includes a TEG 312 in place of the TEG 212 on the semiconductor substrate 210. For details of the semiconductor substrate 310 other than the TEG 312, refer to the description of the semiconductor substrate 210. Here, details of the TEG 312 will be described.

[0317] The TEG 312 has a plurality of inspection circuits with different variations in given characteristics with respect to a given process variation when the semiconductor substrate 310 is processed. The TEG 312 has an inspection circuit 112a, an inspection circuit 112b, and an inspection circuit 112c.

[0318] For each of the inspection circuit 112a and the inspection circuit 112b, refer to the description of the inspection system according to the second embodiment. Here, the inspection circuit 112c will be described. Figure 26 FIG. is a diagram for explaining the inspection circuit 112c of the inspection system 4 which is an example of the inspection system according to the seventh embodiment.

[0319] The inspection circuit 112c includes a plurality of element circuits 112C. The inspection circuit 112c includes an odd number of element circuits 112C. The plurality of element circuits 112C are connected in series.

[0320] The plurality of element circuits 112C are each a circuit of an inversion logic. The inspection circuit 112c inputs the output of the element circuit 112C at the final stage among the odd number of element circuits 112C to the element circuit 112C at the foremost stage. The inspection circuit 112c is a feedback type oscillation circuit. The inspection circuit 112c is a so-called ring oscillator (ring oscillation circuit). When power is supplied to the inspection circuit 112c, it outputs an AC signal, i.e., a signal OSCc, having a frequency caused by the delay in each element circuit 112C.

[0321] [Inspection device 320]

[0322] The inspection device 320 measures predetermined characteristics in each of the inspection circuit 112a, the inspection circuit 112b, and the inspection circuit 112c. In addition, the inspection device 320 estimates process variations when each of the inspection circuit 112a, the inspection circuit 112b, and the inspection circuit 112c is formed based on the measured characteristics in the inspection circuit 112a, the inspection circuit 112b, and the inspection circuit 112c.

[0323] The inspection device 320 includes a measurement unit 321 and an estimation unit 322.

[0324] (Measurement unit 321)

[0325] The measurement unit 321 measures the characteristics in each of the inspection circuits 112a, 112b, and 112c. The measurement unit 321 is respectively connected to the inspection circuits 112a, 112b, and 112c in any one of the plurality of TEGs 312 through the wiring Lm.

[0326] For the inspection circuits 112a and 112b, the measurement unit 321 performs the same processing as the inspection system 2 which is an example of the inspection system according to the second embodiment. In addition, the measurement unit 321 supplies power to the inspection circuit 112c to be measured, and detects the signal OSCc output from the inspection circuit 112c. Then, the measurement unit 321 measures a predetermined characteristic based on the signal OSCc. As the predetermined characteristic, the measurement unit 321 measures the frequency of the signal OSCc.

[0327] The measurement unit 321 outputs the measurement result Rfa obtained by measuring the frequency of the signal OSCa which is the predetermined characteristic in the inspection circuit 112a, and the measurement result Rfb obtained by measuring the frequency of the signal OSCb which is the predetermined characteristic in the inspection circuit 112b to the estimation unit 322. In addition, the measurement unit 321 outputs the measurement result Rfc obtained by measuring the frequency of the signal OSCc which is the predetermined characteristic in the inspection circuit 112c to the estimation unit 322.

[0328] (Estimation unit 322)

[0329] The estimation unit 322 estimates the process variations when each of the inspection circuits 112a, 112b, and 112c is formed. The estimation unit 322 estimates the process variations based on the measurement results Rfa, Rfb, and Rfc measured by the measurement unit 321.

[0330] <Combination examples of the element circuits 112A, 112B, and 112C>

[0331] (First combination example)

[0332] The inspection circuit 112a includes the NOT circuit 112i as the element circuit 112A. In addition, the inspection circuit 112b includes the NAND circuit 112nd as the element circuit 112B. In addition, the inspection circuit 112c includes the NOR circuit 112nr as the element circuit 112C.

[0333] (Second combination example)

[0334] The inspection circuit 112a includes a NOT circuit 112i as an element circuit 112A. Further, the inspection circuit 112b includes a NOT circuit 112i2 as an element circuit 112B. Further, the inspection circuit 112c includes a NOT circuit 112i3 as an element circuit 112C.

[0335] (Third combination example)

[0336] The inspection circuit 112a includes a NOT circuit 112m1 as an element circuit 112A. Further, the inspection circuit 112b includes a NOT circuit 112m2 as an element circuit 112B. Further, the inspection circuit 112c includes a NOT circuit 112m3 as an element circuit 112C.

[0337] (Other combination examples)

[0338] In addition, for the combination of the element circuit 112A, the element circuit 112B, and the element circuit 112C, it is not limited to the above examples. For example, three circuits can be appropriately selected from the NOT circuits 112m1, NOT circuits 112m2, NOT circuits 112m3, and NOT circuits 112m4. In addition, for the combination of the element circuit 112A, the element circuit 112B, and the element circuit 112C, three circuits can be appropriately selected from the NAND circuits 112d1, NAND circuits 112d2, NAND circuits 112d3, and NAND circuits 112d4. In addition, for the combination of the element circuit 112A, the element circuit 112B, and the element circuit 112C, three circuits can be appropriately selected from the NOR circuits 112r1, NOR circuits 112r2, NOR circuits 112r3, and NOR circuits 112r4.

[0339] In addition, in the above examples, the circuits constituting the element circuit 112A, the circuits constituting the element circuit 112B, and the circuits constituting the element circuit 112C can also be mutually replaced.

[0340] <Summary>

[0341] According to the inspection system according to the seventh embodiment, process variations in the semiconductor process can be estimated.

[0342] In addition, the plurality of element circuits 112A are an example of a plurality of first element circuits, the element circuit 112A is an example of a first element circuit, and the inspection circuit 112a is an example of a first inspection circuit. The plurality of element circuits 112B are an example of a plurality of second element circuits, the element circuit 112B is an example of a second element circuit, and the inspection circuit 112b is an example of a second inspection circuit. The plurality of element circuits 112C are an example of a plurality of third element circuits, the element circuit 112C is an example of a third element circuit, and the inspection circuit 112c is an example of a third inspection circuit.

[0343] <Operation Example 1>

[0344] Shows Operation Example 1 when the inspection device according to the present embodiment is operating. Specifically, in the seventh embodiment, the case where the NOT circuit 112i, the NAND circuit 112nd, and the NOR circuit 112nr are respectively provided as the element circuits 112A, 112B, and 112C will be described.

[0345] Figure 27 , Figure 28 , Figure 29 , Figure 30 Shows the results of measuring the output frequencies in the inspection circuits 112a, 112b, and 112c for the reference sample, sample A, sample B, and sample C, respectively. Figure 27 , Figure 28 , Figure 29 and Figure 30 The horizontal axis of each represents the measurement result (frequency) in the inspection circuit 112a. Figure 27 , Figure 28 , Figure 29 and Figure 30 The vertical axis of each represents the measurement results in the inspection circuits 112a, 112b, and 112c, respectively. In addition, the unit of frequency is expressed in arbitrary units. Figure 27 , Figure 28 , Figure 29 and Figure 30 The points in each represent the results of measuring the inspection circuits 112a, 112b, and 112c respectively for the multiple TEGs 312 on one semiconductor substrate 310.

[0346] In Figure 27 , Figure 28 , Figure 29 and Figure 30 In each of the figures, the data N-N represents the measurement result of the inspection circuit 112a. In addition, the data D-N represents the measurement result of the inspection circuit 112b. Furthermore, the data R-N represents the measurement result of the inspection circuit 112c.

[0347] The reference sample is a semiconductor substrate 310 fabricated under normal process conditions. Sample A is a semiconductor substrate 310 fabricated under the same conditions as the reference sample. Sample B is a semiconductor substrate 310 fabricated under conditions where the threshold voltage of the NMOS transistor is set lower and the threshold voltage of the PMOS transistor is set higher. Sample C is a semiconductor substrate 310 fabricated under conditions where the threshold voltage of the NMOS transistor is set higher and the threshold voltage of the PMOS transistor is set lower. In other words, Sample A, Sample B, and Sample C are samples in which the process conditions are modulated with respect to the reference sample regarding ion concentration, respectively.

[0348] In addition, regarding the above measurement results, the differences in the average frequencies between inspection circuit 112a and inspection circuit 112b, between inspection circuit 112a and inspection circuit 112c, and between inspection circuit 112b and inspection circuit 112c are summarized in Table 1. In addition, the average frequency is the average of the frequencies measured in multiple TEGs 312 in one semiconductor substrate 310. In Table 1, inspection circuit 112a, inspection circuit 112b, and inspection circuit 112c are represented as inspection circuit a, inspection circuit b, and inspection circuit c, respectively.

[0349] According to Figure 27 and Figure 28 and Table 1, the same results were obtained for the reference sample and Sample A. Therefore, results with good reproducibility were obtained when fabricated under the same conditions.

[0350]

Table 1

[0351]

[0352] [Comparison between NOT Circuit and NAND Circuit]

[0353] The difference in the average frequencies (difference ΔF1) between inspection circuit 112a with element circuit 112A being a NOT circuit and inspection circuit 112b with element circuit 112B being a NAND circuit is compared. The difference ΔF1 for the reference sample and Sample A is approximately equal. On the other hand, the difference ΔF1 for Sample B becomes smaller compared to the reference sample. A smaller difference ΔF1 means that the frequency of Sample B is higher, that is, the threshold voltage is lower. In addition, the difference ΔF1 for Sample C becomes larger compared to the reference sample. A larger difference ΔF1 means that the frequency of Sample C is lower, that is, the threshold voltage is higher.

[0354] That is, by comparing the difference in the average frequencies (difference ΔF1) between inspection circuit 112a with element circuit 112A being a NOT circuit and inspection circuit 112b with element circuit 112B being a NAND circuit, the variation in the ion concentration of the n-channel can be inferred.

[0355] [Comparison between NOT Circuit and NOR Circuit]

[0356] The difference (difference ΔF2) in the average frequency between the inspection circuit 112a with the element circuit 112A being a NOT circuit and the inspection circuit 112c with the element circuit 112C being a NOR circuit is compared. The difference ΔF2 between the reference sample and sample A is approximately equal. On the other hand, the difference ΔF2 of sample B becomes larger compared to the reference sample. A large difference ΔF2 means that the frequency of sample B becomes lower, that is, the threshold voltage becomes higher. In addition, the difference ΔF2 of sample C becomes smaller compared to the reference sample. A small difference ΔF2 means that the frequency of sample C becomes higher, that is, the threshold voltage becomes lower.

[0357] That is, by comparing the difference (difference ΔF2) in the average frequency between the inspection circuit 112a with the element circuit 112A being a NOT circuit and the inspection circuit 112c with the element circuit 112C being a NOR circuit, the variation in the ion concentration of the p-channel can be estimated.

[0358] [Comparison between NAND Circuit and NOR Circuit]

[0359] The difference (difference ΔF3) in the average frequency between the inspection circuit 112b with the element circuit 112B being a NAND circuit and the inspection circuit 112c with the element circuit 112C being a NOR circuit is compared. The difference ΔF3 between the reference sample and sample A is approximately equal. On the other hand, the difference ΔF3 of sample B becomes smaller compared to the reference sample. In addition, the difference ΔF3 of sample C becomes larger compared to the reference sample. Therefore, by comparing the difference (difference ΔF3) in the average frequency between the inspection circuit 112b with the element circuit 112B being a NAND circuit and the inspection circuit 112c with the element circuit 112C being a NOR circuit, the variation in the ion concentration of the n-channel and p-channel can be further emphasized.

[0360] In addition, in the above example, the inspection system according to the seventh embodiment is taken as an example for illustration, but the inspection systems according to the second or third embodiment using two inspection circuits are the same.

[0361] [Operation Example 2]

[0362] An operation example 2 when the inspection system according to the present embodiment is operated is shown. Specifically, in the seventh embodiment, the case where the NOT circuit 112i2, the NOT circuit 112i3, and the NOT circuit 112i are respectively provided as the element circuit 112A, the element circuit 112B, and the element circuit 112C is described.

[0363] Figure 31The results of simulations are shown for a total of five conditions: the standard film thickness, the standard film thickness ± 5%, and the standard film thickness ± 10%, with the insulating film thickness changed. Figure 31 The horizontal axis represents the measurement result (frequency) in the inspection circuit 112c. Figure 31 The vertical axis represents the differential frequency of the measurement results (frequency) in the inspection circuit 112a and the inspection circuit 112b. Additionally, the unit of frequency is expressed in arbitrary units.

[0364] Line Lp10 represents the result for the standard film thickness + 10%, line Lp05 represents the result for the standard film thickness + 5%, line Ltyp represents the result for the standard film thickness, line Pm05 represents the result for the standard film thickness - 5%, and line Pm10 represents the result for the standard film thickness - 10%. According to Figure 31 the results, with the inspection system according to the present embodiment, it is possible to detect variations in the film thickness of the insulating film.

[0365] The results of measurements using an actual substrate are described. Figure 32 These are the results of measurements for the cases where the insulating film thickness is 0.757 nm and 0.620 nm. Figure 31 The horizontal axis represents the measurement result (frequency) in the inspection circuit 112c. Figure 31 The vertical axis represents the delay times in the inspection circuit 112a and the inspection circuit 112b. Additionally, the units of frequency and time are expressed in arbitrary units.

[0366] Point S1 represents the result for the case where the insulating film thickness is 0.620 nm, and point S2 represents the result for the case where the insulating film thickness is 0.757 nm. According to Figure 32 the results, with the inspection system according to the present embodiment, it is possible to detect variations in the film thickness of the insulating film.

[0367] <Operation Example 3>

[0368] Operation Example 3 when the inspection system according to the present embodiment is operated is shown. Specifically, the case is described where in the seventh embodiment, the NOT circuit 112m1, the NOT circuit 112m2, and the NOT circuit 112m3 are respectively provided as the element circuit 112A, the element circuit 112B, and the element circuit 112C. More specifically, the element circuit 112A is the NOT circuit 112m1 in which the gate width of the NMOS transistor 112n1 is equal to the gate width of the PMOS transistor 112p1. Additionally, the element circuit 112B is the NOT circuit 112m2 in which the gate width of the NMOS transistor 112n1 is shorter than the gate width of the PMOS transistor 112p1. Further, the element circuit 112C is the NOT circuit 112m3 in which the gate width of the PMOS transistor 112p1 is shorter than the gate width of the NMOS transistor 112n1.

[0369] Figure 33 , Figure 34 , Figure 35 show the results of measuring the frequencies of the outputs in the inspection circuits 112a, 112b, and 112c for the reference sample 2, sample A2, and sample B2, respectively. Figure 33 , Figure 34 and Figure 35 The horizontal axis of each represents the measurement result (frequency) in the inspection circuit 112a as a reference. Figure 33 , Figure 34 and Figure 35 The vertical axis of each represents the measurement results in the inspection circuits 112b and 112c, respectively. In addition, the unit of frequency is expressed in arbitrary units. Figure 33 , Figure 34 and Figure 35 The points in each of the diagrams of , , and are the results of measuring the inspection circuits 112a, 112b, and 112c, respectively, of the multiple TEGs 312 on a single semiconductor substrate 310.

[0370] In Figure 33 , Figure 34 and Figure 35 In each of the diagrams of , , and , the data PS represents the measurement result of the inspection circuit 112c. In addition, the data NS represents the measurement result of the inspection circuit 112b.

[0371] The reference sample 2 is a semiconductor substrate 310 fabricated under normal process conditions. Sample A2 is a semiconductor substrate 310 fabricated under conditions where the threshold voltage of the NMOS transistor is set low and the threshold voltage of the PMOS transistor is set high. Sample B2 is a semiconductor substrate 310 fabricated under conditions where the threshold voltage of the NMOS transistor is set high and the threshold voltage of the PMOS transistor is set low. In other words, sample A2 and sample B2 are samples in which the process conditions are modulated with respect to the reference sample 2 regarding the ion concentration.

[0372] In addition, regarding the above measurement results, the differences in the average frequencies between the inspection circuit 112a and the inspection circuit 112b, between the inspection circuit 112a and the inspection circuit 112c, and between the inspection circuit 112b and the inspection circuit 112c are summarized in Table 2. In addition, the average frequency is the average of the frequencies measured in multiple TEGs 312 in one semiconductor substrate 310. In Table 2, the inspection circuit 112a, the inspection circuit 112b, and the inspection circuit 112c are represented as inspection circuit a, inspection circuit b, and inspection circuit c, respectively. In addition, the difference in the average frequencies between the inspection circuit 112a and the inspection circuit 112b is set as the difference ΔF11, the difference in the average frequencies between the inspection circuit 112a and the inspection circuit 112c is set as the difference ΔF12, and the difference in the average frequencies between the inspection circuit 112b and the inspection circuit 112c is set as the difference ΔF13.

[0373] The difference ΔF11 and the difference ΔF12 represent the differences in the frequencies of the inspection circuit a (ring oscillator) with the NOT circuit 112m1 having the same gate width of the PMOS transistor 112p1 and the NMOS transistor 112n1 as the element circuit. The frequency of the inspection circuit a is higher than the frequencies of the inspection circuit b and the inspection circuit c respectively, so the higher the frequency, the smaller the difference.

[0374]

Table 2

[0375]

[0376] According to Figure 33 、 Figure 34 and Figure 35 and Table 2, the difference in the average frequencies between the inspection circuit a and the inspection circuit b (difference ΔF11) mainly shows the threshold characteristics of the p-channel in the PMOS transistor. In addition, the difference in the average frequencies between the inspection circuit a and the inspection circuit c (difference ΔF12) mainly shows the threshold characteristics of the n-channel in the NMOS transistor. In addition, the difference in the average frequencies between the inspection circuit b and the inspection circuit c (difference ΔF13) shows the threshold characteristics of the p-channel in the PMOS transistor and the threshold characteristics of the n-channel in the NMOS transistor.

[0377] In addition, Figure 36 shows the results of simulations performed by changing the manufacturing conditions for the case where the manufacturing conditions are standard and the case where the thresholds of the n-channel and p-channel are changed (a total of 8 conditions).

[0378] Figure 36The horizontal axis represents manufacturing conditions. "F" represents manufacturing conditions where the threshold is changed for high-speed operation, and "S" represents manufacturing conditions where the threshold is changed for low-speed operation. The "F" or "S" on the left represents the manufacturing conditions for the n-channel, and the "F" or "S" on the right represents the manufacturing conditions for the p-channel. Additionally, when "m" is given, for each of "F" and "S", it represents the standard condition and the intermediate condition.

[0379] Figure 36 The vertical axis represents the difference in output between the inspection circuit with the NOT circuit 112m1 as the element circuit and the inspection circuit with the NOT circuit 112m2 or NOT circuit 112m3 as the element circuit. The unit of frequency is expressed in arbitrary units. The upper section (data PS) is the result of the inspection circuit with the NOT circuit 112m3 as the element circuit. The lower section (data NS) is the result of the inspection circuit with the NOT circuit 112m2 as the element circuit.

[0380] Line Lps represents the simulation results under each condition for the inspection circuit with the NOT circuit 112m3 as the element circuit. Line Lpavg represents the average value obtained by summarizing the results under each condition for the inspection circuit with the NOT circuit 112m3 as the element circuit. Line Lns represents the simulation results under each condition for the inspection circuit with the NOT circuit 112m2 as the element circuit. Line Lnavg represents the average value obtained by summarizing the results under each condition for the inspection circuit with the NOT circuit 112m3 as the element circuit.

[0381] According to Figure 36 the results, for PS, according to the characteristics of the p-channel, in the case of the S characteristic, the result is greater than the average, and in the case of the F characteristic, the result is less than the average. According to Figure 36 the results, it can be seen that for NS, according to the characteristics of the n-channel, in the case of the S characteristic, the result is greater than the average, and in the case of the F characteristic, the result is less than the average.

[0382] As described above, according to the inspection system according to the present embodiment, it is possible to strongly detect variations in the n-channel or p-channel.

[0383] <Operation Example 4>

[0384] Shows Operation Example 4 when the inspection system according to the present embodiment is operated. Specifically, the case where the NAND circuit 112nd and the NOR circuit 112nr are respectively provided as the element circuit 112A and the element circuit 112B in the third embodiment will be described.

[0385] Figure 37 Shows the results of measurements made by changing the manufacturing conditions when using the NAND circuit and the NOR circuit as the element circuits.

[0386] Figure 37 The horizontal axis of Figure 37 represents the result of using the NAND circuit 112nd as the inspection circuit 112a of the element circuit 112A. Figure 37 The vertical axis of Figure 37 represents the result of using the NOR circuit 112nr as the inspection circuit 112b of the element circuit 112B.

[0387] In addition, Figure 37 The data TT1 and data TT2 in Figure 37 represent the data in the samples fabricated under standard manufacturing conditions. Figure 37 The data FS1 in Figure 37 represents the data in the samples fabricated under manufacturing conditions where the threshold is such that the N-channel is fast acting and the P-channel is slow acting. Figure 37 The data SF1 in Figure 37 represents the data in the samples fabricated under manufacturing conditions where the threshold is such that the N-channel is slow acting and the P-channel is fast acting.

[0388] As Figure 37 shown, in the case of manufacturing conditions where the n-channel is fast and the p-channel is slow, the inspection circuit 112a having the NAND circuit 112nd as the element circuit is faster. On the other hand, in the case of manufacturing conditions where the n-channel is slow and the p-channel is fast, the inspection circuit 112b having the NOR circuit 112nr as the element circuit is faster.

[0389] As described above, by combining the NAND circuit and the NOR circuit as the element circuits, the state of the process can be estimated based on the frequency characteristics.

[0390] <Modification Example 1>

[0391] Describe Modification Example 1 of the NAND circuit and the NOR circuit constituting the element circuit. In the third embodiment, the NAND circuit and the NOR circuit are described separately, but the NAND circuit and the NOR circuit are not limited to the examples described in the third embodiment. In Modification Example 1, examples where the internal connections of the NAND circuit and the NOR circuit are different are described.

[0392] (Modification Example of NAND Circuit)

[0393] Figure 38 It is a circuit diagram showing a modification example of the NAND circuit 112nd, which is an example of the element circuit of the inspection circuit constituting the inspection system according to the present embodiment. Specifically, Figure 38 It is a diagram showing the NAND circuit 112nd2 as a modification example of the NAND circuit 112nd.

[0394] In Figure 8In the NAND circuit 112nd, the NMOS transistor 112n3 is connected to the input In, while in the NAND circuit 112nd2, the NMOS transistor 112n2 is connected to the input In.

[0395] The NAND circuit 112nd2 is a NAND circuit. The NAND circuit 112nd2 includes a PMOS transistor 112p2, a PMOS transistor 112p3, an NMOS transistor 112n2, and an NMOS transistor 112n3.

[0396] Either the source or the drain of each of the PMOS transistor 112p2 and the PMOS transistor 112p3 is connected to the power supply potential Vdd. The other of the source and the drain of each of the PMOS transistor 112p2 and the PMOS transistor 112p3 is connected to either the source or the drain of the NMOS transistor 112n2 and is connected to the output Out of the NAND circuit 112nd2.

[0397] The other of the source and the drain of the NMOS transistor 112n2 is connected to either the source or the drain of the NMOS transistor 112n3.

[0398] The other of the source and the drain of the NMOS transistor 112n3 is connected to the common potential Vss. The gates of the PMOS transistor 112p2 and the NMOS transistor 112n2 are connected to the input In of the NAND circuit 112nd2. The gate of the PMOS transistor 112p3 is connected to the gate of the NMOS transistor 112n3 and is connected to the power supply potential Vdd.

[0399] The NAND circuit 112nd2, which is a NAND circuit, includes the NMOS transistor 112n2 and the NMOS transistor 112n3 connected in series between the power supply potential Vdd and the common potential Vss. Therefore, the NAND circuit 112nd2 strongly exhibits the influence of the n-channel possessed by the NMOS transistor 112n2 and the NMOS transistor 112n3. Since the NAND circuit 112nd2 strongly exhibits the influence of the n-channel, in the case of a change in the ion concentration of the n-channel, the influence will be strongly exhibited. Therefore, by adopting the NAND circuit 112nd2 as an element circuit of any one of the inspection circuits 112a, the inspection circuit 112b, and the inspection circuit 112c, it is possible to detect a change in the ion concentration of the n-channel as a process variation.

[0400] In addition, in the NAND circuit 112nd2, since the gate of the NMOS transistor 112n3 is connected to the power supply potential Vdd, the potential is determined. Therefore, the NMOS transistor 112n3 can be regarded as a fixed resistance component. As a result, compared with the NAND circuit 112nd, the influence of the variation caused by the ion concentration in the n-channel of the NAND circuit 112nd2 is different from that of the NAND circuit 112nd. Therefore, the NAND circuit 112nd2 can investigate the influence of the variation caused by the ion concentration in the n-channel with characteristics different from those of the NAND circuit 112nd.

[0401] (Modification example of NOR circuit)

[0402] Figure 39 The figure is a circuit diagram illustrating a modification example of the NOR circuit 112nr, which is an element circuit of the inspection circuit constituting the inspection system according to the present embodiment. Specifically, Figure 39 The figure is a diagram illustrating the NOR circuit 112nr2 as a modification example of the NOR circuit 112nr.

[0403] In Figure 9 In the NOR circuit 112nr, the PMOS transistor 112p4 is connected to the input In, while in the NOR circuit 112nr2, the PMOS transistor 112p5 is connected to the input In.

[0404] The NOR circuit 112nr2 is a NOR circuit. The NOR circuit 112nr2 includes the PMOS transistor 112p4, the PMOS transistor 112p5, the NMOS transistor 112n4, and the NMOS transistor 112n5.

[0405] Either the source or the drain of the PMOS transistor 112p4 is connected to the power supply potential Vdd. The other of the source and the drain of the PMOS transistor 112p4 is connected to either the source or the drain of the PMOS transistor 112p5. The other of the source and the drain of the PMOS transistor 112p5 is connected to either the source or the drain of each of the NMOS transistor 112n4 and the NMOS transistor 112n5 and is connected to the output Out of the NOR circuit 112nr2.

[0406] The other of the source and the drain of each of the NMOS transistor 112n4 and the NMOS transistor 112n5 is connected to the common potential Vss. The gate of the PMOS transistor 112p5 and the gate of the NMOS transistor 112n4 are connected to the input In of the NOR circuit 112nr2. The gate of the PMOS transistor 112p4 is connected to the gate of the NMOS transistor 112n5 and is connected to the common potential Vss.

[0407] The NOR circuit 112nr2, which is a NOR circuit, includes a PMOS transistor 112p4 and a PMOS transistor 112p5 connected in series between the power supply potential Vdd and the common potential Vss. Therefore, the NOR circuit 112nr2 strongly exhibits the influence of the p-channel of the PMOS transistor 112p4 and the PMOS transistor 112p5. Since the NOR circuit 112nr2 strongly exhibits the influence of the p-channel, it will strongly exhibit the influence in the case of changes in the ion concentration of the p-channel. Therefore, by adopting the NOR circuit 112nr2 as an element circuit of any one of the inspection circuits 112a, 112b, and 112c, the change in the ion concentration of the p-channel can be detected as a process variation.

[0408] In addition, since the gate of the PMOS transistor 112p4 of the NOR circuit 112nr2 is connected to the common potential Vss, the potential is determined. Therefore, the PMOS transistor 112p4 can be regarded as a constant resistance component. Therefore, compared with the NOR circuit 112nr, the influence of the change caused by the ion concentration of the p-channel in the NOR circuit 112nr2 is different from that in the NOR circuit 112nr. Therefore, the NOR circuit 112nr2 can investigate the influence of the change caused by the ion concentration of the p-channel with characteristics different from those of the NOR circuit 112nr.

[0409] <Modification Example 2>

[0410] Describe Modification Example 2 of the NAND circuit and NOR circuit that make up the element circuit. In the third embodiment, the NAND circuit and NOR circuit are described separately, but the NAND circuit and NOR circuit are not limited to the examples described in the third embodiment. In Modification Example 2, examples with different numbers of inputs are described for the NAND circuit and NOR circuit, respectively.

[0411] (Modification Example of NAND Circuit)

[0412] Figure 40 This is a circuit diagram for describing a modification example of the NAND circuit 112nd, which is an example of an element circuit of the inspection circuit constituting the inspection system according to the present embodiment. Specifically, Figure 40 This is a diagram for describing the NAND circuit 112nd3, which is a modification example of the NAND circuit 112nd.

[0413] Figure 8 In the NAND circuit 112nd in , it is a 2-input NAND circuit, while the NAND circuit 112nd3 is a 3-input NAND circuit.

[0414] The NAND circuit 112nd3 is a 3-input NAND circuit. Based on the structure of the NAND circuit 112nd, the NAND circuit 112nd3 further includes a PMOS transistor 112p31 and an NMOS transistor 112n21.

[0415] The PMOS transistor 112p31 is arranged in parallel with the PMOS transistor 112p3. In addition, the NMOS transistor 112n21 is serially arranged between the NMOS transistor 112n2 and the NMOS transistor 112n3.

[0416] In the NAND circuit 112nd, two n-channel transistors are serially connected between the power supply potential Vdd and the common potential Vss. The load seen from the n-channel transistor that conducts and blocks can see a resistive load (n-channel transistor) and a capacitive load (the next-stage p-channel and n-channel transistors). The load seen from the p-channel transistor that conducts and blocks is only a capacitive load (the next-stage p-channel and n-channel transistors). Therefore, the NAND circuit 112nd becomes a circuit sensitive to changes in the n-channel.

[0417] In addition, in the NAND circuit 112nd3 which is a 3-input NAND circuit, the load seen from the n-channel transistor that conducts and blocks can see two n-channel transistors as a series resistive load. On the other hand, the load seen from the p-channel transistor that conducts and blocks, similar to the NAND circuit 112nd which is a 2-input NAND circuit, has no series resistive load. Therefore, by using a 3-input NAND circuit, it becomes more sensitive to changes in the n-channel.

[0418] (Modification example of NOR circuit)

[0419] Figure 41 It is a circuit diagram showing a modification example of the NOR circuit 112nr which is an example of an element circuit of the inspection circuit constituting the inspection system according to the present embodiment. Specifically, Figure 41 It is a diagram for explaining the NOR circuit 112nr3 which is a modification example of the NOR circuit 112nr.

[0420] Figure 9 The NOR circuit 112nr in [[ ]] is a 2-input NOR circuit, and the NOR circuit 112nr3 is a 3-input NOR circuit.

[0421] The NOR circuit 112nr3 is a 3-input NOR circuit. Based on the structure of the NOR circuit 112nr, the NOR circuit 112nr3 further includes a PMOS transistor 112p51 and an NMOS transistor 112n51.

[0422] The PMOS transistor 112p51 is serially disposed between the PMOS transistor 112p4 and the PMOS transistor 112p5. Additionally, the NMOS transistor 112n51 is disposed in parallel with the NMOS transistor 112n5.

[0423] In the NOR circuit 112nr, two p-channel transistors are serially connected between the power supply potential Vdd and the common potential Vss. The load seen from the p-channel transistor that performs switching can see a resistive load (p-channel transistor) and a capacitive load (the p-channel and n-channel transistors in the next stage). The load seen from the p-channel transistor that performs switching is only a capacitive load (the p-channel and n-channel transistors in the next stage). Therefore, the NOR circuit 112nr is a circuit sensitive to variations in the p-channel.

[0424] Additionally, in the NOR circuit 112nr3 which is a 3-input NOR circuit, the load seen from the p-channel transistor that performs switching can see two p-channel transistors as a serially connected resistive load. On the other hand, the load seen from the n-channel transistor that performs switching, similar to the NOR circuit 112nr which is a 2-input NOR circuit, does not have a serially connected resistive load. Therefore, by using a 3-input NOR circuit, it becomes more sensitive to variations in the p-channel.

[0425] Additionally, in the above description, a 3-input NAND circuit or NOR circuit has been described, but the input can also be 4 inputs or more. Additionally, similar to Modification 1, the transistors connected to the inputs of each circuit can be changed, and the number of transistors that fix the gate potential can also be changed.

[0426] It should be understood that the inspection system and inspection method according to the present embodiment disclosed herein are illustrative in all respects and not restrictive. The above embodiment can be modified and improved in various ways without departing from the claims and their gist. The matters described in the above multiple embodiments can also adopt other structures within a non-contradictory range, and in addition, can be combined within a non-contradictory range.

[0427] This application claims the priority of the basic patent application No. 2022-208570 filed with the Japan Patent Office on December 26, 2022, and incorporates the entire content thereof by reference.

[0428] Reference Numeral Explanation

[0429] 1, 2, 3, 4: Inspection System

[0430] 10, 110, 210, 310: Semiconductor Substrate

[0431] 11: Chip

[0432] 12a, 12b, 12c: Inspection circuit

[0433] 14: Chip formation area

[0434] 15: Cutting area

[0435] 20, 120, 220, 320: Inspection device

[0436] 21, 121, 221, 321: Measurement unit

[0437] 22, 122, 222, 322: Estimation unit

[0438] 112a, 112b, 112c: Inspection circuit

[0439] 112A, 112B, 112C: Element circuit

[0440] 112i, 112i2, 112i3: NOT circuit

[0441] 112t1, 112t4: NOT circuit

[0442] 112t2, 112t3: dummy NOT circuit

[0443] 112w1, 112w2: dummy wiring

[0444] 112m1, 112m2, 112m3, 112m4: NOT circuit

[0445] 112nd, 112nd2, 112nd3, 112d1, 112d2, 112d3, 112d4: NAND circuit

[0446] 112nr, 112nr2, 112nr3, 112r1, 112r2, 112r3, 112r4: NOR circuit

[0447] 112n1, 112n2, 112n3, 112n4, 112n5, 112n6, 112n7, 112n8, 112n9: NMOS transistor

[0448] 112p1, 112p2, 112p3, 112p4, 112p5, 112p6, 112p7, 112p8, 112p9: PMOS transistor

[0449] GT, GT1, GT2, GT3, GT4: Gate electrode

[0450] NW1, NW2, NW3, NW4, NW5, NW6, NW7, NW8: Semiconductor layer

[0451] PW1, PW2, PW3, PW4, PW5, PW6, PW7, PW8: Semiconductor layer

[0452] OSCa, OSCb, OSCc, SIGa, SIGb, SIGc: Signals

[0453] Ra, Rb, Rc, Rfa, Rfb, Rfc: Measurement results.

Claims

1. An inspection system comprising: A semiconductor substrate on which a first inspection circuit and a second inspection circuit are formed; A measurement unit that measures predetermined characteristics in each of the first inspection circuit and the second inspection circuit; and An estimation unit that estimates process variations when forming the first inspection circuit and the second inspection circuit on the semiconductor substrate based on a first measurement result obtained by the measurement unit measuring the first inspection circuit and a second measurement result obtained by the measurement unit measuring the second inspection circuit, wherein the magnitude of the variation in the characteristics of the second inspection circuit with respect to the process variations is different from the magnitude of the variation in the characteristics of the first inspection circuit with respect to the process variations.

2. The inspection system according to claim 1, wherein the first inspection circuit is a ring oscillator circuit in which a plurality of first element circuits are connected in series and the output of the last stage is input to the first stage, the second inspection circuit is a ring oscillator circuit in which a plurality of second element circuits are connected in series and the output of the last stage is input to the first stage, and the characteristic is frequency.

3. The inspection system according to claim 2, wherein the first element circuit is a NOT circuit, and the second element circuit is a NAND circuit.

4. The inspection system according to claim 3, wherein the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel, either the source or the drain of the first PMOS transistor is connected to a power supply potential, the other of the source and the drain of the first PMOS transistor is connected to either the source or the drain of the first NMOS transistor and is connected to the output of the first element circuit, the other of the source and the drain of the first NMOS transistor is connected to a common potential, the gates of the first PMOS transistor and the first NMOS transistor are connected to the input of the first element circuit, the second element circuit includes a second PMOS transistor and a third PMOS transistor having p-channels and a second NMOS transistor and a third NMOS transistor having n-channels, either the source or the drain of each of the second PMOS transistor and the third PMOS transistor is connected to the power supply potential, the other of the source and the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either the source or the drain of the second NMOS transistor and is connected to the output of the second element circuit, the other of the source and the drain of the second NMOS transistor is connected to either the source or the drain of the third NMOS transistor, the other of the source and the drain of the third NMOS transistor is connected to the common potential, and the gates of the second PMOS transistor and the third NMOS transistor are connected to the input of the second element circuit. The gate of the third PMOS transistor is connected to the gate of the second NMOS transistor and is connected to the power supply potential.

5. The inspection system according to claim 2, wherein the first element circuit is a NOT circuit, the second element circuit is a NOR circuit.

6. The inspection system according to claim 5, wherein the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel, either the source or the drain of the first PMOS transistor is connected to the power supply potential, the other of the source and the drain of the first PMOS transistor is connected to either the source or the drain of the first NMOS transistor and is connected to the output of the first element circuit, the other of the source and the drain of the first NMOS transistor is connected to the common potential, the gates of the first PMOS transistor and the first NMOS transistor are connected to the input of the first element circuit, the second element circuit includes a fourth PMOS transistor and a fifth PMOS transistor having p-channels, and a fourth NMOS transistor and a fifth NMOS transistor having n-channels, either the source or the drain of the fourth PMOS transistor is connected to the power supply potential, the other of the source and the drain of the fourth PMOS transistor is connected to either the source or the drain of the fifth PMOS transistor, the other of the source and the drain of the fifth PMOS transistor is connected to either the source or the drain of the fourth NMOS transistor and the fifth NMOS transistor and is connected to the output of the second element circuit, the other of the source and the drain of the fourth NMOS transistor and the fifth NMOS transistor is connected to the common potential, the gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input of the second element circuit, the gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the common potential.

7. The inspection system according to claim 2, wherein the first element circuit is a NAND circuit, the second element circuit is a NOR circuit.

8. The inspection system according to claim 7, wherein the first element circuit includes a second PMOS transistor and a third PMOS transistor having p-channels, and a second NMOS transistor and a third NMOS transistor having n-channels, either the source or the drain of each of the second PMOS transistor and the third PMOS transistor is connected to the power supply potential, the other of the source and the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either the source or the drain of the second NMOS transistor and is connected to the output of the second element circuit, The other of the source and the drain of the second NMOS transistor is connected to any one of the source and the drain of the third NMOS transistor. The other of the source and the drain of the third NMOS transistor is connected to a common potential. The gates of the second PMOS transistor and the third NMOS transistor are connected to the input of the second element circuit. The gate of the third PMOS transistor is connected to the gate of the second NMOS transistor and is connected to the power supply potential. The second element circuit includes a fourth PMOS transistor and a fifth PMOS transistor having p-channels, and a fourth NMOS transistor and a fifth NMOS transistor having n-channels. Any one of the source and the drain of the fourth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the fourth PMOS transistor is connected to any one of the source and the drain of the fifth PMOS transistor. The other of the source and the drain of the fifth PMOS transistor is connected to any one of the source and the drain of the fourth NMOS transistor and the fifth NMOS transistor, and is connected to the output of the second element circuit. The other of the source and the drain of the fourth NMOS transistor and the fifth NMOS transistor is connected to the common potential. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input of the second element circuit. The gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the common potential.

9. The inspection system according to claim 2, wherein The first element circuit includes a plurality of NOT circuits, and the inputs of the plurality of NOT circuits are connected to the input of the first element circuit. The second element circuit is a NOT circuit.

10. The inspection system according to claim 9, wherein The first element circuit has: A NOT circuit including a sixth PMOS transistor having a p-channel and a sixth NMOS transistor having an n-channel; A first dummy NOT circuit including a seventh PMOS transistor having a p-channel and a seventh NMOS transistor having an n-channel; And A second dummy NOT circuit including an eighth PMOS transistor having a p-channel and an eighth NMOS transistor having an n-channel. Any one of the source and the drain of the sixth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the sixth PMOS transistor is connected to any one of the source and the drain of the sixth NMOS transistor and is connected to the output of the first element circuit. The other of the source and the drain of the sixth NMOS transistor is connected to the common potential. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input of the first element circuit. Any one of the source and the drain of the seventh PMOS transistor is connected to the power supply potential. The other of the source and the drain of the seventh PMOS transistor is connected to any one of the source and the drain of the seventh NMOS transistor, The other of the source and the drain of the seventh NMOS transistor is connected to the common potential, The gates of the seventh PMOS transistor and the seventh NMOS transistor are connected to the input of the first element circuit, Any one of the source and the drain of the eighth PMOS transistor is connected to the power supply potential, The other of the source and the drain of the eighth PMOS transistor is connected to any one of the source and the drain of the eighth NMOS transistor, The other of the source and the drain of the eighth NMOS transistor is connected to the common potential, The gates of the eighth PMOS transistor and the eighth NMOS transistor are connected to the input of the first element circuit, The second element circuit includes a ninth PMOS transistor having a p-channel, a ninth NMOS transistor having an n-channel, a first dummy wiring, and a second dummy wiring, Any one of the source and the drain of the ninth PMOS transistor is connected to the power supply potential, The other of the source and the drain of the ninth PMOS transistor is connected to any one of the source and the drain of the ninth NMOS transistor and is connected to the output of the second element circuit, The other of the source and the drain of the ninth NMOS transistor is connected to the common potential, The gates of the ninth PMOS transistor and the ninth NMOS transistor are connected to the input of the second element circuit, The first dummy wiring is a wiring having the same structure as the wiring from the input of the first element circuit to the first dummy NOT circuit, The second dummy wiring is a wiring having the same structure as the wiring from the input of the first element circuit to the second dummy NOT circuit.

11. The inspection system according to claim 2, wherein The second element circuit has the same circuit structure as the first element circuit, The gate widths of the transistors constituting the second element circuit are different from the gate widths of the transistors constituting the first element circuit corresponding to the transistors.

12. The inspection system according to claim 11, wherein The first element circuit and the second element circuit are any one of a NOT circuit, a NAND circuit, and a NOR circuit.

13. The inspection system according to claim 11, wherein The first element circuit is a NOT circuit including a tenth PMOS transistor having a p-channel and a tenth NMOS transistor having an n-channel, Any one of the source and the drain of the tenth PMOS transistor is connected to the power supply potential, The other of the source and the drain of the tenth PMOS transistor is connected to any one of the source and the drain of the tenth NMOS transistor and is connected to the output of the first element circuit, The other of the source and the drain of the tenth NMOS transistor is connected to the common potential, The gates of the tenth PMOS transistor and the tenth NMOS transistor are connected to the input of the first element circuit. The second element circuit is a NOT circuit including an eleventh PMOS transistor having a p-channel and an eleventh NMOS transistor having an n-channel. Either the source or the drain of the eleventh PMOS transistor is connected to the power supply potential. The other of the source and the drain of the eleventh PMOS transistor is connected to either the source or the drain of the eleventh NMOS transistor and is connected to the output of the second element circuit. The other of the source and the drain of the eleventh NMOS transistor is connected to the common potential. The gates of the eleventh PMOS transistor and the eleventh NMOS transistor are connected to the input of the second element circuit. The gate width of the eleventh PMOS transistor is different from the gate width of the tenth PMOS transistor, or the gate width of the eleventh NMOS transistor is different from the gate width of the tenth NMOS transistor.

14. The inspection system according to claim 1, wherein the semiconductor substrate further has a third inspection circuit. The measurement unit measures the characteristics in the third inspection circuit. The estimation unit estimates the process variation when forming the first inspection circuit, the second inspection circuit, and the third inspection circuit on the semiconductor substrate based on the first measurement result, the second measurement result, and the third measurement result obtained by the measurement unit measuring the third inspection circuit. The magnitude of the variation of the characteristics in the third inspection circuit with respect to the process variation is different from the magnitude of the variation of the characteristics in each of the first inspection circuit and the second inspection circuit with respect to the process variation.

15. The inspection system according to claim 14, wherein the first inspection circuit is a ring oscillator circuit in which a plurality of first element circuits are connected in series and the output of the final stage is input to the first stage. The second inspection circuit is a ring oscillator circuit in which a plurality of second element circuits are connected in series and the output of the final stage is input to the first stage. The third inspection circuit is a ring oscillator circuit in which a plurality of third element circuits are connected in series and the output of the final stage is input to the first stage. The characteristic is frequency.

16. The inspection system according to claim 15, wherein the first element circuit is a NOT circuit. the second element circuit is a NAND circuit. the third element circuit is a NOR circuit.

17. The inspection system according to claim 16, wherein the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel. Either the source or the drain of the first PMOS transistor is connected to the power supply potential. The other of the source and the drain of the first PMOS transistor is connected to either the source or the drain of the first NMOS transistor and is connected to the output of the first element circuit. The other of the source and the drain of the first NMOS transistor is connected to a common potential. The gates of the first PMOS transistor and the first NMOS transistor are connected to the input of the first element circuit. The second element circuit includes a second PMOS transistor and a third PMOS transistor having p-channels, and a second NMOS transistor and a third NMOS transistor having n-channels. Either of the source and the drain of each of the second PMOS transistor and the third PMOS transistor is connected to the power supply potential. The other of the source and the drain of each of the second PMOS transistor and the third PMOS transistor is connected to either of the source and the drain of the second NMOS transistor, and is connected to the output of the second element circuit. The other of the source and the drain of the second NMOS transistor is connected to either of the source and the drain of the third NMOS transistor. The other of the source and the drain of the third NMOS transistor is connected to the common potential. The gates of the second PMOS transistor and the third NMOS transistor are connected to the input of the second element circuit. The gate of the third PMOS transistor is connected to the gate of the second NMOS transistor and is connected to the power supply potential. The third element circuit includes a fourth PMOS transistor and a fifth PMOS transistor having p-channels, and a fourth NMOS transistor and a fifth NMOS transistor having n-channels. Either of the source and the drain of the fourth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the fourth PMOS transistor is connected to either of the source and the drain of the fifth PMOS transistor. The other of the source and the drain of the fifth PMOS transistor is connected to either of the source and the drain of each of the fourth NMOS transistor and the fifth NMOS transistor, and is connected to the output of the third element circuit. The other of the source and the drain of each of the fourth NMOS transistor and the fifth NMOS transistor is connected to the common potential. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input of the third element circuit. The gate of the fifth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the common potential.

18. The inspection system according to claim 15, wherein the first element circuit is a NOT circuit. the second element circuit includes a plurality of NOT circuits, and the inputs of the plurality of NOT circuits are connected to the input of the second element circuit. the third element circuit is a NOT circuit including dummy wirings.

19. The inspection system according to claim 18, wherein the first element circuit includes a first PMOS transistor having a p-channel and a first NMOS transistor having an n-channel. Either the source or the drain of the first PMOS transistor is connected to the power supply potential. The other of the source and the drain of the first PMOS transistor is connected to either the source or the drain of the first NMOS transistor and is connected to the output of the first element circuit. The other of the source and the drain of the first NMOS transistor is connected to the common potential. The gates of the first PMOS transistor and the first NMOS transistor are connected to the input of the first element circuit. The second element circuit includes: A NOT circuit including a sixth PMOS transistor having a p-channel and a sixth NMOS transistor having an n-channel. A first dummy NOT circuit including a seventh PMOS transistor having a p-channel and a seventh NMOS transistor having an n-channel. And A second dummy NOT circuit including an eighth PMOS transistor having a p-channel and an eighth NMOS transistor having an n-channel. Either the source or the drain of the sixth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the sixth PMOS transistor is connected to either the source or the drain of the sixth NMOS transistor and is connected to the output of the second element circuit. The other of the source and the drain of the sixth NMOS transistor is connected to the common potential. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input of the second element circuit. Either the source or the drain of the seventh PMOS transistor is connected to the power supply potential. The other of the source and the drain of the seventh PMOS transistor is connected to either the source or the drain of the seventh NMOS transistor. The other of the source and the drain of the seventh NMOS transistor is connected to the common potential. The gates of the seventh PMOS transistor and the seventh NMOS transistor are connected to the input of the second element circuit. Either the source or the drain of the eighth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the eighth PMOS transistor is connected to either the source or the drain of the eighth NMOS transistor. The other of the source and the drain of the eighth NMOS transistor is connected to the common potential. The gates of the eighth PMOS transistor and the eighth NMOS transistor are connected to the input of the second element circuit. The third element circuit includes a ninth PMOS transistor having a p-channel, a ninth NMOS transistor having an n-channel, a first dummy wiring, and a second dummy wiring. Either the source or the drain of the ninth PMOS transistor is connected to the power supply potential. The other of the source and the drain of the ninth PMOS transistor is connected to either the source or the drain of the ninth NMOS transistor and is connected to the output of the third element circuit. The other of the source and the drain of the ninth NMOS transistor is connected to the common potential, the gates of the ninth PMOS transistor and the ninth NMOS transistor are connected to the input of the third element circuit, the first dummy wiring is a wiring having the same structure as the wiring from the input of the second element circuit to the first dummy NOT circuit, the second dummy wiring is a wiring having the same structure as the wiring from the input of the second element circuit to the second dummy NOT circuit.

20. The inspection system according to any one of claims 14 to 19, wherein, the semiconductor substrate has a plurality of chip formation regions and a cutting region for cutting the plurality of chip formation regions into respective chip formation regions, the first inspection circuit, the second inspection circuit, and the third inspection circuit are respectively formed in the cutting region.

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