A novel by-wire EMB system architecture and method

Abstract

The application discloses a novel drive-by-wire EMB system architecture and method, which comprises a controller PCBA, the controller PCBA comprises three microprocessor modules, a plurality of bus switches and a plurality of bus drivers, the microprocessor modules are connected with the bus switches through bus signals 1, a watchdog module is further arranged between the microprocessor modules and the bus switches, the watchdog module transmits an enable signal to the redundant bus switches to control the opening or closing of the bus switches, the bus switches are connected with the bus drivers to ensure communication, the novel drive-by-wire EMB system architecture and method improve the compactness of design, meanwhile, three microprocessor modules are used as redundant backup, two microprocessor modules control two wheel-side brake motors along diagonal lines, and the other microprocessor module is used as a backup module after a conventional microprocessor module fails, so that the safety redundancy of design is greatly improved, and the safety of driving is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of chassis brake-by-wire EMB, and particularly relates to a novel brake-by-wire EMB system architecture and method. BACKGROUND

[0002] The traditional EMB system usually contains four sets of brake wheel edge controller electrical systems and two sets of brake domain controller electrical systems. Although this design can provide sufficient redundancy, the system structure is complex, the number of components is large, which leads to great difficulty in system integration, and due to the large number of components, the number of fault points also increases, which greatly affects the reliability and stability of the system.

[0003] At the same time, for the design of a large number of brake wheel edge controllers and brake domain controllers but lacking sufficient redundancy, once a controller fails, it may cause the entire brake system to fail, thereby endangering driving safety.

[0004] In addition, under complex road conditions or emergency braking conditions, the traditional EMB system may cause unstable braking effect due to controller failure or uneven brake force distribution, thereby affecting driving safety.

[0005] Therefore, the above problems need to be solved. SUMMARY

[0006] The purpose of the application is to overcome the above shortcomings, and the purpose of the application is to provide a novel brake-by-wire EMB system architecture and method, which proposes a new EMB architecture that a centralized control unit controls four wheel edge brake motors to realize brake-by-wire, which improves the compactness of the design; At the same time, three microprocessor modules are used as redundant backups, two of which control two wheel edge brake motors on the diagonal, and the other microprocessor module is used as a backup module after the failure of the regular microprocessor module, which greatly improves the safety redundancy of the design and improves the safety of driving.

[0007] Technical scheme: In order to realize the above-mentioned purpose, the application provides a novel drive-by-wire EMB system architecture, which comprises a controller PCBA, the controller PCBA comprises a first microprocessor module, a second microprocessor module, a third microprocessor module, a first bus switch, a second bus switch, a third bus switch, a fourth bus switch, a first bus driver and a second bus driver; the first microprocessor module is connected with the first bus switch through a bus signal 1; the third microprocessor module is connected with the second bus switch through a bus signal 2; the second microprocessor module is connected with the fourth bus switch through a bus signal 3; and the third microprocessor module is connected with the fourth bus switch through a bus signal 4. By connecting different microprocessor modules with different bus switches and bus drivers, the system can continue to run through other paths when a certain microprocessor module or bus switch fails, thereby improving the fault tolerance and reliability of the system; meanwhile, three microprocessor modules are used as redundant backups, two of which realize control, and the other one is used as a backup module after the failure of the conventional microprocessor module, which greatly improves the safety redundancy of the design and the safety of driving.

[0008] Further, a first watchdog module is arranged between the first microprocessor module and the second bus switch, and the first watchdog module transmits an enable signal 1 to the second bus switch for controlling the opening or closing of the second bus switch; a second watchdog module is arranged between the third microprocessor module and the first bus switch, and the second watchdog module transmits an enable signal 2 to the first bus switch for controlling the opening or closing of the first bus switch; a third watchdog module is arranged between the second microprocessor module and the third bus switch, and the third watchdog module transmits an enable signal 3 to the third bus switch for controlling the opening or closing of the third bus switch; and a fourth watchdog module is arranged between the third microprocessor module and the fourth bus switch, and the fourth watchdog module transmits an enable signal 4 to the fourth bus switch for controlling the opening or closing of the fourth bus switch. The watchdog module is independent of the microprocessor module and can monitor the running state of the microprocessor in real time; if the microprocessor appears in a dead loop, is stuck or has other abnormal conditions, the watchdog module can timely trigger a reset operation to restore the normal operation of the system; and the bus switch is controlled by the watchdog module, and once an abnormality is detected, the communication link of the faulty module can be quickly cut off to prevent the spread of the fault; meanwhile, the multiple watchdog modules monitor different microprocessor modules and bus switches, thereby further enhancing the redundancy of the system

[0009] Further, the first bus switch and the second bus switch are connected with the first bus driver to ensure the realization of communication; and the third bus switch and the fourth bus switch are connected with the second bus driver to ensure the realization of communication. The bus switch can realize the shortest propagation delay, ensure the rapid transmission of signals on the bus and improve the response speed of the system.

[0010] Further, the controller PCBA further comprises a first PMSM motor pre-driver, a second PMSM motor pre-driver, a third PMSM motor pre-driver, a fourth PMSM motor pre-driver, a first MOS three-phase bridge, a second MOS three-phase bridge, a third MOS three-phase bridge, and a fourth MOS three-phase bridge; the first PMSM motor pre-driver and the second PMSM motor pre-driver are connected with the first bus driver; the third PMSM motor pre-driver and the fourth PMSM motor pre-driver are connected with the second bus driver; the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge, and the fourth MOS three-phase bridge are connected with the first PMSM motor pre-driver, the second PMSM motor pre-driver, the third PMSM motor pre-driver, and the fourth PMSM motor pre-driver respectively. The PMSM motor pre-driver has an energy conversion efficiency of more than 95%, high efficiency and high power density, improves the space utilization of limited space and other application scenarios, optimizes the dynamic response and efficiency of the motor; by connecting several PMSM motor pre-drivers with different bus drivers, the system realizes redundancy design, even if a pre-driver module fails, other modules can still work normally, improving the reliability and safety of the system; at the same time, the MOS three-phase bridge has high reliability and low failure rate in the three-phase power converter, further enhancing the stability of the system.

[0011] Further, it further comprises a right front brake motor, a left rear brake motor, a left front brake motor, and a right rear brake motor; the right front brake motor, the left rear brake motor, the left front brake motor, and the right rear brake motor are connected with the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge, and the fourth MOS three-phase bridge through a wire harness; the wire harness contains U, V, W three-phase drive signals and motor position sensor signals. The right front, left rear, left front, and right rear four brake motors are controlled by independent MOS three-phase bridges, realizing accurate control of the braking force of each wheel, and by connecting the brake motor with different three-phase bridges, realizing the diagonal control logic; at the same time, the risk of single-point failure is reduced, and if a three-phase bridge fails, the braking function of other motors can still work normally, thereby improving the overall reliability of the system.

[0012] Further, the controller PCBA further comprises a first CAN transceiver, a second CAN transceiver, a third CAN transceiver, a fourth CAN transceiver, a first power management PMIC and 4 wheel speed signal processing module, a second power management PMIC and 4 wheel speed signal processing module, and a wheel speed current signal 4-to-8 processing module; the first CAN transceiver and the second CAN transceiver are connected with the first microprocessor module; the second CAN transceiver and the third CAN transceiver are connected with the second microprocessor module; the wheel speed current signal 4-to-8 processing module is connected with the first microprocessor module and the second microprocessor module through the first power management PMIC and 4 wheel speed signal processing module and the second power management PMIC and 4 wheel speed signal processing module, respectively. By configuring multiple CAN transceivers and connecting them to different microprocessor modules, communication redundancy of the system is achieved, effectively preventing communication interruption caused by failure of a single CAN transceiver, and enhancing the fault tolerance of the system; at the same time, through the wheel speed current signal 4-to-8 processing module, the system efficiently processes and converts the signals of the four wheel speed sensors, providing more accurate wheel speed information for the microprocessor module, greatly improving the anti-interference ability and precision of the signals, and thus enhancing the braking control performance of the vehicle.

[0013] Further, it further comprises a connector module; the first CAN transceiver, the second CAN transceiver, the third CAN transceiver, the fourth CAN transceiver, the first microprocessor module, and the second microprocessor module are connected with the connector module. By centrally managing communication and power connection through the connector module, the complexity and cost of wiring are reduced; at the same time, as the connection center, the connector module enables the CAN transceivers and the microprocessor modules to be quickly connected and replaced, facilitating system integration and maintenance.

[0014] Further, the controller PCBA further comprises a power supply switching switch, a first redundant power supply switching logic module, and a second redundant power supply switching logic module; the first redundant power supply switching logic module and the second redundant power supply switching logic module are connected with the first microprocessor module and the second microprocessor module, respectively; the power supply switching switch is connected with the power supply switching switch; the power supply switching switch is connected with the first MOS three-phase bridge, the second MOS three-phase bridge, the third MOS three-phase bridge, and the fourth MOS three-phase bridge, respectively. By setting two redundant power supply switching logic modules and connecting them with two microprocessor modules, respectively, it is ensured that the backup module can seamlessly take over in the event of failure of the main power module, thereby improving the reliability of the system; at the same time, the power supply switching switch can realize efficient power switching, reduce energy loss during power switching, and ensure efficient operation of the system in low-power mode.

[0015] Further, the connector module further comprises power supply 1 and power supply 2; the power supply 1 and the power supply 2 are connected with the power supply switching switch. By designing two independent power supply inputs, the design of the redundant power supply is perfected, even if one of the power supplies fails, the other power supply can continue to power the system, significantly improving the reliability of the system.

[0016] Further, the connector module further comprises pedal signal 1 and pedal signal 2; the pedal signal 1 and the pedal signal 2 are connected with the first microprocessor module and the second microprocessor module through the heterogeneous pedal signal 1 and the heterogeneous pedal signal 2. The heterogeneous pedal signal 1 and the heterogeneous pedal signal 2 adopt different encoding modes, which enhances the fault tolerance of the system, that is, even if one kind of signal is subjected to a specific type of interference, the other signal can still work normally, reducing the risk of a single failure point.

[0017] Further, the first microprocessor module, the second microprocessor module and the third microprocessor module are further connected with each other through an information interaction channel. The information interaction channel supports data sharing and synchronization between the microprocessor modules, ensures that the design of the redundant module has high responsiveness, and improves the cooperative working ability of the system.

[0018] The application also provides a novel drive-by-wire EMB method for realizing the novel drive-by-wire EMB system architecture provided by the application, comprising:

[0019] S1): the first bus switch, the second bus switch, the third bus switch and the fourth bus switch are in a normally open mode, and are turned off when an enable signal is input; the bus switch is in a normally open mode by default, and is turned off only when an enable signal is received. This design ensures that the bus switch is in a safe default state when the system is started or reset, avoiding communication failure caused by accidental signals;

[0020] S2): when the first microprocessor module works normally, the first microprocessor module provides an enable signal through the first watchdog module to turn off the second bus switch, and the third microprocessor module does not provide a watchdog signal, at this time, the first bus switch is normally turned on, the first microprocessor module communicates with the first PMSM motor pre-driver and the second PMSM motor pre-driver through the first bus switch and the first bus driver, and realizes motor driving; the first microprocessor module controls the turning off of the second bus switch through the first watchdog module, ensuring the independent control of the first microprocessor module on the first bus switch, and providing a redundant mechanism for the system, even if the second bus switch fails, the first bus switch can still work normally;

[0021] S3): when the second microprocessor module works normally, the second microprocessor module provides an enable signal through the third watchdog module to make the third bus switch off, the third microprocessor module does not provide a watchdog signal, at this time, the fourth bus switch is normally open, the second microprocessor module communicates with the third PMSM motor pre-driver and the fourth PMSM motor pre-driver through the fourth bus switch and the second bus driver, and motor driving is realized; the second microprocessor module controls the third bus switch to be off through the third watchdog module, which ensures the independent control of the second microprocessor module on the fourth bus switch, and provides a redundancy mechanism for the system, so that even if the third bus switch fails, the fourth bus switch can still work normally;

[0022] S4): when the first microprocessor module fails or works abnormally, the watchdog signal is interrupted, the first watchdog module stops working, at this time, the second bus switch is open, the third microprocessor module starts to intervene, replaces the first microprocessor module to provide the watchdog signal, makes the first bus switch off through the enable signal provided by the second watchdog module, and communicates with the first PMSM motor pre-driver and the second PMSM motor pre-driver through the first bus driver, and motor driving is realized; when the first microprocessor module fails or abnormally, the first watchdog module stops working, and the second bus switch is automatically open; after the system detects the fault, the backup module is switched quickly, and the influence of the fault on the system operation is reduced;

[0023] S5): when the second microprocessor module fails or works abnormally, the watchdog signal is interrupted, the third watchdog module stops working, at this time, the third bus switch is open, the third microprocessor module starts to intervene, replaces the second microprocessor module to provide the watchdog signal, makes the fourth bus switch off through the enable signal provided by the fourth watchdog module, and communicates with the third PMSM motor pre-driver and the fourth PMSM motor pre-driver through the second bus driver, and motor driving is realized; when the second microprocessor module fails or abnormally, the third watchdog module stops working, and the third bus switch is automatically open; after the system detects the fault, the backup module is switched quickly, and the influence of the fault on the system operation is reduced.

[0024] The above technical scheme can be seen that the present application has the following beneficial effects:

[0025] 1. The novel drive-by-wire EMB system architecture and method, a new EMB architecture for realizing drive-by-wire braking by a centralized control unit controlling four wheel edge brake motors is proposed, and the compactness of the design is improved;

[0026] 2. The novel drive-by-wire EMB system architecture and method of the application uses three microprocessor modules as redundant backups, two of which control two diagonal wheel-side brake motors, and the other serves as a backup module after the failure of the conventional microprocessor module, greatly improving the safety redundancy of the design and the safety of driving. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The overall schematic diagram of the novel drive-by-wire EMB system architecture and method of the application;

[0028] In the figure:

[0029] 1000 - connector module; 1001 - 4-wheel speed current signal processing module; 1002 - first CAN transceiver; 1003 - second CAN transceiver; 1004 - third CAN transceiver; 1005 - fourth CAN transceiver; 1006 - first power management PMIC and 4-wheel speed signal processing module; 1007 - second power management PMIC and 4-wheel speed signal processing module; 1008 - first microprocessor module; 1009 - second microprocessor module; 1010 - power supply switching switch; 1011 - first PMSM motor pre-driver; 1012 - second PMSM motor pre-driver; 1013 - third PMSM motor pre-driver; 1014 - fourth PMSM motor pre-driver; 1015 - first MOS three-phase bridge; 1016 - second MOS three-phase bridge; 1017 - third MOS three-phase bridge; 1018 - fourth MOS three-phase bridge; 1019 - right front brake motor; 1020 - left rear brake motor; 1021 - left front brake motor; 1022 - right rear brake motor; 1023 - third microprocessor module; 1024 - first bus switch; 1025 - second bus switch; 1026 - first bus driver; 1027 - third bus switch; 1028 - fourth bus switch; 1029 - second bus driver; 1030 - first watchdog module; 1031 - second watchdog module; 1032 - fourth watchdog module; 1033 - third watchdog module; 1035 - first redundant power supply switching logic module; 1036 - second redundant power supply switching logic module; 1100 - controller PCBA;

[0030] 1: 1010 - power supply switching switch;

[0031] 2: 1035 - first redundant power supply switching logic module;

[0032] 3: 1036 - second redundant power supply switching logic module. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described below in the detailed description and illustrated in the accompanying drawings by using examples, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application. Embodiments

[0034] In this embodiment, as Figure 1 , the present application discloses a new drive-by-wire EMB system architecture, comprising: a controller PCBA 1100, the controller PCBA 1100 comprises a first microprocessor module 1008, a second microprocessor module 1009, a third microprocessor module 1023, a first bus switch 1024, a second bus switch 1025, a third bus switch 1027, a fourth bus switch 1028, a first bus driver 1026 and a second bus driver 1029; the first microprocessor module 1008 is connected with the first bus switch 1024 through bus signal 1; the third microprocessor module 1023 is connected with the second bus switch 1025 through bus signal 2; the second microprocessor module 1009 is connected with the fourth bus switch 1028 through bus signal 3; the third microprocessor module 1023 is connected with the fourth bus switch 1028 through bus signal 4.

[0035] Specifically, the first microprocessor module 1008, the second microprocessor module 1009 and the third microprocessor module 1023 can integrate real-time monitoring and diagnosis functions as a preferred, through the first bus driver 1026 and the second bus driver 1029 to monitor the running state of the system in real time, and timely discover and handle the fault.

[0036] In this embodiment, as Figure 1 , the first microprocessor module 1008 and the second bus switch 1025 are further provided with a first watchdog module 1030, and the first watchdog module 1030 transmits enable signal 1 to the second bus switch 1025 for controlling its opening or closing; the third microprocessor module 1023 and the first bus switch 1024 are further provided with a second watchdog module 1031, and the second watchdog module 1031 transmits enable signal 2 to the first bus switch 1024 for controlling its opening or closing; the second microprocessor module 1009 and the third bus switch 1027 are further provided with a third watchdog module 1033, and the third watchdog module 1033 transmits enable signal 3 to the third bus switch 1027 for controlling its opening or closing; the third microprocessor module 1023 and the fourth bus switch 1028 are further provided with a fourth watchdog module 1032, and the fourth watchdog module 1032 transmits enable signal 4 to the fourth bus switch 1028 for controlling its opening or closing.

[0037] Specifically, the first microprocessor module 1008, the second microprocessor module 1009, and the third microprocessor module 1023 work independently as triple-redundancy backup microprocessor modules and interact information through buses. The third microprocessor module 1023 is a backup microprocessor module of the first microprocessor module 1008 and the second microprocessor module 1009. When the first microprocessor module 1008 or the second microprocessor module 1009 fails, the system sends fault information and the third microprocessor module 1023 takes over, which can greatly ensure driving safety.

[0038] In the embodiment, the first bus switch 1024 and the second bus switch 1025 are connected with the first bus driver 1026 to ensure communication, and the third bus switch 1027 and the fourth bus switch 1028 are connected with the second bus driver 1029 to ensure communication. Figure 1

[0039] Specifically, the first bus driver 1026 and the second bus driver 1029 can be preferably selected as designs supporting multiple communication protocols, such as CANopen, EtherCAT, Modbus, etc.

[0040] In the embodiment, the controller PCBA 1100 further includes a first PMSM motor pre-driver 1011, a second PMSM motor pre-driver 1012, a third PMSM motor pre-driver 1013, a fourth PMSM motor pre-driver 1014, a first MOS three-phase bridge 1015, a second MOS three-phase bridge 1016, a third MOS three-phase bridge 1017, and a fourth MOS three-phase bridge 1018. Figure 1

[0041] Specifically, the PMSM motor pre-driver can process control signals such as PWM signals from the microprocessor module to control the speed and direction of the motor.

[0042] ​​In particular, in order to avoid the up and down bridge arm through, need to configure dead time, select the carrier frequency at 15KHz~20KHz, the initial value of the dead time is set to 4us as a preferred.

[0043] Specifically, each PMSM motor pre-driver selects a model integrated with overcurrent protection, short circuit protection and other functions as a preferred to prevent motor or driver damage.

[0044] In the embodiment, as Figure 1 It also includes right front brake motor 1019, left rear brake motor 1020, left front brake motor 1021 and right rear brake motor 1022; the right front brake motor 1019, left rear brake motor 1020, left front brake motor 1021, right rear brake motor 1022 are connected with the first MOS three-phase bridge 1015, second MOS three-phase bridge 1016, third MOS three-phase bridge 1017, fourth MOS three-phase bridge 1018 through the wire harness; the wire harness contains U, V, W three-phase drive signal and motor position sensor signal.

[0045] Specifically, each MOS three-phase bridge contains at least three upper bridge MOS tubes and three lower bridge MOS tubes, which control the U / V / W three-phase of the motor respectively; according to the received control signal, the upper bridge and lower bridge MOS tubes corresponding to the phase of the motor rotation are turned on with the power supply.

[0046] Specifically, the wire harness selects twisted pair, shielded wire and the like as an exemplary preferred, the design should be easy to assemble, and the interference should be considered to reduce from the wire harness layout.

[0047] In the embodiment, as Figure 1 The controller PCBA 1100 also includes a first CAN transceiver 1002, a second CAN transceiver 1003, a third CAN transceiver 1004, a fourth CAN transceiver 1005, a first power management PMIC and 4 wheel speed signal processing module 1006, a second power management PMIC and 4 wheel speed signal processing module 1007 and a wheel speed current signal 4 to 8 processing module 1001; the first CAN transceiver 1002 and the second CAN transceiver 1003 are connected with the first microprocessor module 1008; the second CAN transceiver 1003 and the third CAN transceiver 1004 are connected with the second microprocessor module 1009; the wheel speed current signal 4 to 8 processing module 1001 is connected with the first microprocessor module 1008 and the second microprocessor module 1009 through the first power management PMIC and 4 wheel speed signal processing module 1006 and the second power management PMIC and 4 wheel speed signal processing module 1007 respectively.

[0048] Specifically, two vehicle CAN signals are used as communication redundancy backup, and are communicated with the first microprocessor module 1008 through the first CAN transceiver 1002 and the second CAN transceiver 1003 respectively.

[0049] Specifically, two vehicle CAN signals are used as communication redundancy backup, and are communicated with the second microprocessor module 1009 through the third CAN transceiver 1004 and the fourth CAN transceiver 1005 respectively.

[0050] Specifically, a double-channel CAN transceiver can be used as a preferred embodiment. The double-channel CAN transceiver is composed of two completely independent transceivers, which can provide two interfaces between the controller area network (CAN) protocol controller and the physical double-wire CAN bus, realize high-speed communication, and have low-power mode and silent mode at the same time.

[0051] In the embodiment, the controller PCBA 1100 further includes a power supply switch 1010, a first redundant power supply switching logic module 1035, and a second redundant power supply switching logic module 1036. Figure 1 The first CAN transceiver 1002, the second CAN transceiver 1003, the third CAN transceiver 1004, the fourth CAN transceiver 1005, the first microprocessor module 1008, and the second microprocessor module 1009 are connected with the connector module 1000.

[0052] Specifically, each microprocessor module can independently monitor the corresponding CAN transceiver and trigger the corresponding switching mechanism when an abnormality is detected.

[0053] Specifically, each microprocessor module can integrate real-time monitoring and diagnosis functions, monitor the running state of the system in real time through each CAN transceiver, and timely discover and handle faults.

[0054] In the embodiment, the controller PCBA 1100 further includes a power supply switch 1010, a first redundant power supply switching logic module 1035, and a second redundant power supply switching logic module 1036. Figure 1 The first redundant power supply switching logic module 1035 and the second redundant power supply switching logic module 1036 are connected with the first microprocessor module 1008 and the second microprocessor module 1009 respectively. The power supply switch 1010 is connected with the first MOS three-phase bridge 1015, the second MOS three-phase bridge 1016, the third MOS three-phase bridge 1017, and the fourth MOS three-phase bridge 1018 respectively.

[0055] Specifically, each redundant power supply switching logic module can independently monitor the corresponding microprocessor module and trigger the power supply switch 1010 to switch the power supply when an abnormality is detected.

[0056] Specifically, the first redundant power supply switching logic module 1035 and the second redundant power supply switching logic module 1036 can integrate a fault detection function, which can not only trigger switching when detecting power supply abnormalities, but also send an alarm signal to remind maintenance personnel to check.

[0057] In the embodiment, the plug-in module 1000 further comprises a power supply 1 and a power supply 2, and the power supply 1 and the power supply 2 are connected with the power supply switching switch 1010. Figure 1

[0058] Specifically, the power supply switching switch 1010 can monitor the state of the two power supplies in real time and automatically switch to the standby power supply when detecting a main power supply failure. This seamless switching mechanism ensures that the system can still operate normally when the power supply fails, avoiding system failure caused by power supply interruption.

[0059] In the embodiment, the plug-in module 1000 further comprises a pedal signal 1 and a pedal signal 2, and the pedal signal 1 and the pedal signal 2 are connected with the first microprocessor module 1008 and the second microprocessor module 1009 through the heterogeneous pedal signal 1 and the heterogeneous pedal signal 2, respectively. Figure 1

[0060] Specifically, the two microprocessor modules 1008 and 1009 process different pedal signals respectively, such as one microprocessor can focus on real-time signal processing, and the other can be used for signal verification and fault diagnosis, so as to realize more accurate signal processing and analysis.

[0061] In the embodiment, the first microprocessor module 1008 and the second microprocessor module 1009 are further connected with each other through an information interaction channel. Figure 1

[0062] Specifically, each microprocessor module can monitor the state of other microprocessor modules in real time through the information interaction channel, and once a fault is detected, the system can quickly switch to a standby module to reduce system failure caused by single-point failure.

[0063] In the embodiment, the application further discloses a novel drive-by-wire EMB method for realizing the novel drive-by-wire EMB system architecture disclosed by the application, comprising:

[0064] ​​​S1): the first bus switch 1024, the second bus switch 1025, the third bus switch 1027 and the fourth bus switch 1028 are in the open mode, and the switches are turned off when the input enable signal is input; in particular, the first bus switch 1024, the second bus switch 1025 and the third bus switch 1027 can be remotely controlled and the state thereof can be monitored by using a network interface such as an Ethernet or a CAN bus, so as to facilitate system maintenance and troubleshooting;

[0065] S2): when the first microprocessor module 1008 normally works, the first microprocessor module 1008 provides an enable signal to the second bus switch 1025 through the first watchdog module 1030 to turn off the second bus switch 1025, and the third microprocessor module 1023 does not provide a watchdog signal, at this time, the first bus switch 1024 is normally turned on, the first microprocessor module 1008 communicates with the first PMSM motor pre-driver 1011 and the second PMSM motor pre-driver 1012 through the first bus switch 1024 and the first bus driver 1026 to realize motor driving; in particular, in the communication process, the data can be encrypted in real time as an optimization to ensure the security and integrity of the data and prevent the data from being tampered with;

[0066] S3): when the second microprocessor module 1009 normally works, the second microprocessor module 1009 provides an enable signal to the third bus switch 1027 through the third watchdog module 1033 to turn off the third bus switch 1027, and the third microprocessor module 1023 does not provide a watchdog signal, at this time, the fourth bus switch 1028 is normally turned on, the second microprocessor module 1009 communicates with the third PMSM motor pre-driver 1013 and the fourth PMSM motor pre-driver 1014 through the fourth bus switch 1028 and the second bus driver 1029 to realize motor driving; in particular, when the second microprocessor module 1009 normally works, intelligent load balancing is realized through the bus driver 1029 to dynamically adjust the allocation of communication tasks according to the system load;

[0067] S4): when the first microprocessor module 1008 fails or works abnormally, the output watchdog signal is interrupted, the first watchdog module 1030 stops working, at this time, the second bus switch 1025 is turned on, the third microprocessor module 1023 starts to intervene to replace the first microprocessor module 1008 to provide a watchdog signal, the first bus switch 1024 is turned off through the second watchdog module 1031 to provide an enable signal, and the first PMSM motor pre-driver 1011 and the second PMSM motor pre-driver 1012 are communicated through the first bus driver 1026 to realize motor driving; in particular, the third microprocessor module 1023 can integrate an adaptive switching strategy to adaptively select a switching strategy such as rapid switching or gradual switching according to the severity of the fault and the system state;

[0068] S5): when the second microprocessor module 1009 appears failure or abnormal work, the watchdog signal interruption is output, the third watchdog module 1033 stops working, at this time the third bus switch 1027 is opened, the third microprocessor module 1023 starts to intervene, instead of the second microprocessor module 1009 to provide the watchdog signal, through the fourth watchdog module 1032 to provide the enable signal to make the fourth bus switch 1028 off, and through the second bus driver 1029 and the third PMSM motor pre-driver 1013, the fourth PMSM motor pre-driver 1014 communication, realize motor drive;Specifically, the third microprocessor module 1023 can integrate the fault isolation mechanism, when detecting the failure of the second microprocessor module 1009, the fault isolation mechanism is started immediately, the connection of the fault module and the system is cut off, and the fault diffusion is prevented.

[0069] The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements can be made, and these improvements should be considered as the protection scope of the present application.

Claims

1. A novel drive-by-wire EMB system architecture characterized by: Comprising: A controller PCBA (1100) comprising a first microprocessor module (1008), a second microprocessor module (1009), a third microprocessor module (1023), a first bus switch (1024), a second bus switch (1025), a third bus switch (1027), a fourth bus switch (1028), a first bus driver (1026), and a second bus driver (1029); The first microprocessor module (1008) is connected with the first bus switch (1024) through bus signal 1; the third microprocessor module (1023) is connected with the second bus switch (1025) through bus signal 2; the second microprocessor module (1009) is connected with the fourth bus switch (1028) through bus signal 3; the third microprocessor module (1023) is connected with the fourth bus switch (1028) through bus signal 4; A first watchdog module (1030) is further arranged between the first microprocessor module (1008) and the second bus switch (1025), and the first watchdog module (1030) transmits enable signal 1 to the second bus switch (1025) for controlling the opening or closing thereof; A second watchdog module (1031) is further arranged between the third microprocessor module (1023) and the first bus switch (1024), and the second watchdog module (1031) transmits enable signal 2 to the first bus switch (1024) for controlling the opening or closing thereof; A third watchdog module (1033) is further arranged between the second microprocessor module (1009) and the third bus switch (1027), and the third watchdog module (1033) transmits enable signal 3 to the third bus switch (1027) for controlling the opening or closing thereof; A fourth watchdog module (1032) is further arranged between the third microprocessor module (1023) and the fourth bus switch (1028), and the fourth watchdog module (1032) transmits enable signal 4 to the fourth bus switch (1028) for controlling the opening or closing thereof; The first bus switch (1024) and the second bus switch (1025) are connected with the first bus driver (1026), ensuring the realization of communication; The third bus switch (1027) and the fourth bus switch (1028) are connected with the second bus driver (1029), ensuring the realization of communication; The controller PCBA (1100) further comprises a first PMSM motor pre-driver (1011), a second PMSM motor pre-driver (1012), a third PMSM motor pre-driver (1013), a fourth PMSM motor pre-driver (1014), a first MOS three-phase bridge (1015), a second MOS three-phase bridge (1016), a third MOS three-phase bridge (1017), and a fourth MOS three-phase bridge (1018). The first PMSM motor pre-driver (1011) and the second PMSM motor pre-driver (1012) are connected with the first bus driver (1026); the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) are connected with the second bus driver (1029); the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017) and the fourth MOS three-phase bridge (1018) are connected with the first PMSM motor pre-driver (1011), the second PMSM motor pre-driver (1012), the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) respectively; The system architecture further comprises a right front brake motor (1019), a left rear brake motor (1020), a left front brake motor (1021) and a right rear brake motor (1022); the right front brake motor (1019), the left rear brake motor (1020), the left front brake motor (1021) and the right rear brake motor (1022) are connected with the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017) and the fourth MOS three-phase bridge (1018) through a wire harness; the wire harness contains U, V, W three-phase driving signals and motor position sensor signals.

2. The novel drive-by-wire EMB system architecture of claim 1, wherein: The controller PCBA (1100) further comprises a first CAN transceiver (1002), a second CAN transceiver (1003), a third CAN transceiver (1004), a fourth CAN transceiver (1005), a first power management PMIC and 4 wheel speed signal processing module (1006), a second power management PMIC and 4 wheel speed signal processing module (1007) and a wheel speed current signal 4-to-8 processing module (1001); The first CAN transceiver (1002) and the second CAN transceiver (1003) are connected with the first microprocessor module (1008); the second CAN transceiver (1003) and the third CAN transceiver (1004) are connected with the second microprocessor module (1009); the wheel speed current signal 4-to-8 processing module (1001) is connected with the first microprocessor module (1008) and the second microprocessor module (1009) through the first power management PMIC and 4 wheel speed signal processing module (1006) and the second power management PMIC and 4 wheel speed signal processing module (1007) respectively.

3. The novel drive-by-wire EMB system architecture of claim 2, wherein: The connector module (1000) is further included; the first CAN transceiver (1002), the second CAN transceiver (1003), the third CAN transceiver (1004), the fourth CAN transceiver (1005), the first microprocessor module (1008) and the second microprocessor module (1009) are connected with the connector module (1000).

4. The novel brake-by-wire EMB system architecture of claim 3, wherein: The controller PCBA (1100) further comprises a power supply switch (1010), a first redundant power supply switch logic module (1035) and a second redundant power supply switch logic module (1036); The first redundant power supply switch logic module (1035) and the second redundant power supply switch logic module (1036) are connected with the first microprocessor module (1008) and the second microprocessor module (1009) respectively; the power supply switch (1010) is connected with the power supply switch (1010); the power supply switch (1010) is connected with the first MOS three-phase bridge (1015), the second MOS three-phase bridge (1016), the third MOS three-phase bridge (1017) and the fourth MOS three-phase bridge (1018) respectively.

5. The novel brake-by-wire EMB system architecture of claim 4, wherein: The connector module (1000) further comprises a power supply 1 and a power supply 2; the power supply 1 and the power supply 2 are connected with the power supply switch (1010).

6. The novel brake-by-wire EMB system architecture of claim 3, wherein: The connector module (1000) further comprises a pedal signal 1 and a pedal signal 2; the pedal signal 1 and the pedal signal 2 are connected with the first microprocessor module (1008) and the second microprocessor module (1009) through the heterogeneous pedal signal 1 and the heterogeneous pedal signal 2 respectively.

7. The novel drive-by-wire EMB system architecture of claim 1, wherein: The first microprocessor module (1008), the second microprocessor module (1009) and the third microprocessor module (1023) are further connected through an information interaction channel.

8. A control method of a new type of brake-by-wire EMB, applied to the new type of brake-by-wire EMB system architecture of any one of claims 1-7, characterized in that: Comprise: S1): the first bus switch (1024), the second bus switch (1025), the third bus switch (1027) and the fourth bus switch (1028) are in the open mode, and the switch is turned off when the input enable signal is input; S2): when the first microprocessor module (1008) works normally, the first microprocessor module (1008) provides an enable signal through the first watchdog module (1030) to make the second bus switch (1025) off, and the third microprocessor module (1023) does not provide a watchdog signal, at this time, the first bus switch (1024) is normally turned on, the first microprocessor module (1008) communicates with the first PMSM motor pre-driver (1011) and the second PMSM motor pre-driver (1012) through the first bus switch (1024) and the first bus driver (1026), and motor driving is realized; S3): when the second microprocessor module (1009) works normally, the second microprocessor module (1009) provides an enable signal through the third watchdog module (1033) to make the third bus switch (1027) off, and the third microprocessor module (1023) does not provide a watchdog signal, at this time, the fourth bus switch (1028) is normally turned on, the second microprocessor module (1009) communicates with the third PMSM motor pre-driver (1013) and the fourth PMSM motor pre-driver (1014) through the fourth bus switch (1028) and the second bus driver (1029), and motor driving is realized; S4): When the first microprocessor module (1008) fails or works abnormally, the watchdog signal is interrupted, the first watchdog module (1030) stops working, at this time the second bus switch (1025) is opened, the third microprocessor module (1023) starts to intervene, instead of the first microprocessor module (1008) to provide the watchdog signal, through the second watchdog module (1031) to provide the enable signal to make the first bus switch (1024) off, and through the first bus driver (1026) to communicate with the first PMSM motor pre-driver (1011), the second PMSM motor pre-driver (1012), realize motor driving; S5): When the second microprocessor module (1009) fails or works abnormally, the watchdog signal is interrupted, the third watchdog module (1033) stops working, at this time the third bus switch (1027) is opened, the third microprocessor module (1023) starts to intervene, instead of the second microprocessor module (1009) to provide the watchdog signal, through the fourth watchdog module (1032) to provide the enable signal to make the fourth bus switch (1028) off, and through the second bus driver (1029) to communicate with the third PMSM motor pre-driver (1013), the fourth PMSM motor pre-driver (1014), realize motor driving.

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