Chip interconnection metal layer planarization electrochemical polishing device and method
Through the combination of porous ceramic plates and electrochemical polishing devices, the problem of excessive removal and scratching of copper materials in the surface planarization of the chip interconnect layer is solved, and efficient and stress-free polishing is achieved, which improves processing accuracy and stability.
Patent Information
- Application Number
- CN202510499036.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-08-01
AI Technical Summary
The prior art has problems of excessive removal, scratches and uneven removal of copper materials during the planarization of the chip interconnect metal layer, resulting in defects in the surface of the interconnect layer and affecting circuit performance.
A planarization electrochemical polishing device and method of chip interconnect metal layer is adopted, and the silicon wafer rotation-revolution composite motion is achieved by using porous ceramic plates and industrial robots, and polishing is combined with electrolyte and electrochemical reactions to avoid mechanical stress and achieve uniform anode dissolution.
The surface planarity and processing accuracy of the interconnected metal layer are improved, scratches of copper materials and low dielectric constant materials are avoided, and polishing efficiency and stability are improved.
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Figure CN120400970A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of surface treatment of metal materials, and particularly relates to an electrochemical polishing device and method for planarizing a chip interconnect metal layer. Background Art
[0002] Since the Moore's law was proposed, the process complexity and integration level of chips have been increasing generation by generation. The number of interconnect wiring layers has been increasing continuously, and the interconnect wiring signals within the chip have become increasingly complex, posing higher requirements for the global flatness of the surface of the interconnect layer materials. Continuing to deposit a thin film in the case of insufficient flatness of the interconnect layer will cause the uneven topographical features to be retained in the next interconnect layer. With the superposition of the number of interconnect layers, the uneven topographical features will cause lithography pattern deviation, thereby affecting subsequent processes, and ultimately resulting in the failure of some electrical parameters of the chip or circuit failure. After the chemical mechanical polishing (CMP) technology was proposed, it has been widely used in the field of planarizing chip interconnect metal layers. However, due to the differences in the physical and chemical properties of different materials, such as the high hardness and poor activity of the barrier layer metal, while the copper has low hardness and good activity, under the dual action of the polishing head downward pressure and abrasive, it is extremely easy to cause excessive removal of the copper material and scratches on the copper surface during the process of removing the high-hardness barrier layer. The excessive removal of the copper material will generate "butterfly pits" and "etch pits" on the interconnect layer. Too deep "butterfly pits" and "etch pits" will cause the loss of copper interconnect lines in thinner areas, resulting in circuit RC delay, and even the complete loss of copper interconnect lines, leading to problems such as circuit open circuit. The scratches on the copper surface will cause irreversible defects on the surface. In the context of the continuous reduction of the feature size of the interconnect layer, more stringent requirements are also put forward for the control of various defect sizes of the interconnect layer. How to control defects such as "butterfly pits", "etch pits", and "scratches" on the surface of the interconnect layer while ensuring the polishing efficiency is an urgent problem to be solved.
[0003] The stress-free polishing (SFP) technology for the metal of the chip interconnect layer is a planarization technology developed based on the electrolytic polishing technology. Compared with traditional planarization processing, the SFP process will not cause cracks or delamination in the copper interconnect layer during planarization processing, and no "scratch" defects will be generated on the surface of the copper interconnect layer and low dielectric constant materials. However, due to the uneven distribution of the electroplated copper layer, there is a potential difference at different positions on the surface of the silicon wafer. The potential difference will cause inconsistent material removal efficiency during processing, making it difficult to achieve planarization. Therefore, during the planarization processing of the SFP process, it is necessary to minimize the potential difference on the surface of the silicon wafer during each processing according to the current density effect. At the same time, to reduce the shape error of the "butterfly pit", only one concentric ring can be processed at a time, and the surface of the copper interconnect layer can be finally planarized by processing several concentric rings. Although the SFP technology can effectively improve problems such as "scratches" and "butterfly pits" on the surface of the interconnect layer, this is achieved by sacrificing the processing efficiency to improve the surface quality.
[0004] In summary, in the field of planarization processing of chip interconnect metal layers, a new planarization processing solution is needed to solve the above problems. Summary of the Invention
[0005] The object of the present invention is to provide a planarization electrochemical polishing device and method for chip interconnect metal layers to solve the problems existing in the above-mentioned prior art.
[0006] To achieve the above object, the present invention provides a planarization electrochemical polishing device for chip interconnect metal layers, including a housing. The housing is a cylinder with an open top. At the central position of the inner bottom end of the housing, an auxiliary electrode layer is installed. Above the auxiliary electrode, a porous ceramic plate is provided. The centers of the auxiliary electrode layer and the porous ceramic plate are on the same straight line, and the diameters of the auxiliary electrode layer and the porous ceramic plate are the same. An electrolyte is filled between the outer side wall of the porous ceramic plate and the inner side wall of the housing. A silicon wafer to be polished is provided on the porous ceramic plate. The silicon wafer to be polished can be installed at the end of an industrial robot, and the industrial robot realizes the compound movement of the silicon wafer's self-rotation and revolution.
[0007] Optionally, a conductive ring plate is installed around the outer side wall of the housing. The porous ceramic plate is connected to the positive electrode of the power supply through a wire based on the principle of sliding contact between the brush and the conductive ring, and the auxiliary electrode layer is connected to the negative electrode of the power supply through a wire.
[0008] Optionally, a wire fixing device is provided at the bottom of the auxiliary electrode layer.
[0009] Optionally, an insulating layer is provided between the porous ceramic plate and the auxiliary electrode layer.
[0010] Optionally, the silicon wafer to be polished is installed at the end of the industrial robot through a fixture.
[0011] A planarization electrochemical polishing method for chip interconnect metal layers, applied to the planarization electrochemical polishing device for chip interconnect metal layers, includes:
[0012] Immerse the porous ceramic plate in the electrolyte for exhaust treatment. After the treatment is completed, load the electrolyte and the porous ceramic plate into the polishing device, and adjust the electrolyte based on a preset height and a preset temperature;
[0013] Install the silicon wafer to be polished at the end of the industrial robot through a fixture. The industrial robot realizes the compound movement of the silicon wafer's self-rotation and revolution, and makes the silicon wafer to be polished contact the upper surface of the porous ceramic plate;
[0014] Based on the principle of sliding contact between the brush and the conductive ring, connect the porous ceramic plate to the positive electrode of the power supply through a wire, and connect the auxiliary electrode in the polishing device to the negative electrode of the power supply;
[0015] Start the industrial robot for polishing processing, so that the silicon wafer to be processed moves in a circular motion at a preset frequency to complete the planarization processing of the interconnect structure on the silicon wafer surface.
[0016] Optionally, the exhaust treatment of the porous ceramic plate by dipping it into the electrolyte specifically includes:
[0017] Dip the porous ceramic plate into the electrolyte, and use an ultrasonic vibration device to remove the air in the pores of the porous ceramic plate, so that the porous ceramic plate adsorbs and stores the electrolyte;
[0018] After the exhaust treatment is completed, take out the porous ceramic plate and drain the excess electrolyte until there is no liquid film residue on its surface.
[0019] Optionally, the regulation of the electrolyte based on the preset height and preset temperature specifically includes:
[0020] Control the temperature of the electrolyte at the preset temperature;
[0021] Control the liquid level height of the electrolyte according to the preset height: immerse the main area in the thickness direction of the porous ceramic plate in the electrolyte, and keep the liquid level of the electrolyte about 2 mm below the top of the porous ceramic plate.
[0022] Optionally, during the polishing process, the connected network structure inside the porous ceramic plate forms a capillary effect, sucking the electrolyte from the immersed part to the processing position of the non-immersed part.
[0023] Optionally, measure the electrochemical parameters in the electrolyte within a preset time, and obtain the performance and condition of the electrolyte based on the electrochemical parameters.
[0024] The technical effects of the present invention are as follows:
[0025] 1. The porous ceramic plate of the present invention has a higher surface flatness compared with the traditional polishing pad, and the surface flatness of the interconnect metal layer after polishing is better.
[0026] 2. The porous ceramic plate of the present invention has high mechanical strength, and does not need to be replaced or trimmed during the polishing process, and can realize efficient synchronous polishing of the entire surface of the workpiece.
[0027] 3. The present invention is a polishing method based on the principle of electrolyte-constrained electrochemical polishing. After being energized, the material of the chip interconnect layer undergoes uniform anodic dissolution, and no mechanical stress is generated during the polishing process.
[0028] 4. The present invention not only has the advantages of low surface roughness and high polishing efficiency of the chemical mechanical polishing method, but also has the advantages of the stress-free polishing method to avoid surface scratches of copper materials and low dielectric constant materials, and is expected to become an important way for the planarization processing of chip interconnect layer materials. Description of the Drawings
[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.
[0030] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application. In the accompanying drawings:
[0031] Figure 1 is the implementation flowchart in the embodiments of the present invention;
[0032] Figure 2 is the schematic diagram of the device structure in the embodiments of the present invention;
[0033] Label description: 1. Conductive ring plate; 2. Housing; 3. Electrolyte; 4. Auxiliary electrode; 5. Insulating layer; 6. Porous ceramic plate; 7. Wire fixing device; 8. Silicon wafer to be polished; 9. Fixture. Detailed implementation manners
[0034] Now, various exemplary implementation manners of the present invention will be described in detail. This detailed description should not be considered as a limitation to the present invention, but rather as a more detailed description of certain aspects, characteristics, and implementation schemes of the present invention.
[0035] It should be understood that the terms described in the present invention are only for describing specific implementation manners and are not used to limit the present invention. Additionally, for the numerical ranges in the present invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Each intermediate value within any stated value or stated range, as well as each smaller range between any other stated value or intermediate value within the stated range, is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded from the range.
[0036] Without departing from the scope or spirit of the present invention, various improvements and changes can be made to the specific implementation manners of the description of the present invention, which are obvious to those skilled in the art. Other implementation manners obtained from the description of the present invention are obvious to those skilled in the art. The description and embodiments of this application are only exemplary.
[0037] Regarding the terms "comprising", "including", "having", "containing", etc. used herein, they are all open-ended terms, that is, they are intended to mean including but not limited to.
[0038] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0039] As Figure 1 - Figure 2 shown, in this embodiment, an electrochemical polishing device for planarizing a chip interconnect metal layer is provided, which includes a housing 2. The housing 2 is a cylinder with an open top. At the central position of the inner bottom end of the housing 2, an auxiliary electrode 4 layer is installed. Above the auxiliary electrode 4, a porous ceramic plate 6 is provided. The centers of the auxiliary electrode 4 layer and the porous ceramic plate 6 are located on the same straight line, and the diameters of the auxiliary electrode 4 layer and the porous ceramic plate 6 are the same. An electrolyte 3 is filled between the outer side wall of the porous ceramic plate 6 and the inner side wall of the housing 2; a silicon wafer 8 to be polished is provided on the porous ceramic plate 6. The silicon wafer 8 to be polished can be installed at the end of an industrial robot, and the industrial robot realizes the compound movement of the silicon wafer's self-rotation and revolution.
[0040] A conductive ring plate 1 is installed around the outer side wall of the housing 2. The porous ceramic plate 6 is connected to the positive electrode of the power supply through a wire based on the principle of sliding contact between a brush and a conductive ring. The auxiliary electrode 4 layer is connected to the negative electrode of the power supply through a wire. A wire fixing device 7 is provided at the bottom of the auxiliary electrode 4 layer. An insulating layer 5 is provided between the porous ceramic plate 6 and the auxiliary electrode 4 layer. The silicon wafer 8 to be polished is installed at the end of the industrial robot through a fixture 9.
[0041] An electrochemical polishing method for planarizing a chip interconnect metal layer, which is applied to the above-mentioned electrochemical polishing device for planarizing a chip interconnect metal layer, includes:
[0042] Immerse the porous ceramic plate 6 in the electrolyte 3 for degassing treatment. After the treatment is completed, load the electrolyte 3 and the porous ceramic plate 6 into the polishing device, and adjust the electrolyte 3 based on a preset height and a preset temperature;
[0043] Install the silicon wafer 8 to be polished at the end of the industrial robot through the fixture 9. The industrial robot realizes the compound movement of the silicon wafer's self-rotation and revolution, and makes the silicon wafer 8 to be polished contact the upper surface of the porous ceramic plate 6;
[0044] Based on the principle of sliding contact between a brush and a conductive ring, connect the porous ceramic plate 6 to the positive electrode of the power supply through a wire, and connect the auxiliary electrode 4 in the polishing device to the negative electrode of the power supply;
[0045] Start the industrial robot for polishing processing, so that the silicon wafer to be processed performs circular motion at a preset frequency, and complete the planarization processing of the interconnect structure on the silicon wafer surface.
[0046] The porous ceramic plate 6 used in this embodiment has significant advantages. Compared with traditional polishing pads, the porous ceramic plate 6 has a higher surface flatness, which can make the surface flatness of the polished interconnect metal layer better, thereby improving the processing accuracy of the chip interconnect layer material. In addition, the porous ceramic plate 6 has high mechanical strength and does not need to be replaced or trimmed during the polishing process, and can achieve efficient synchronous polishing of the entire surface area of the workpiece, greatly improving the processing efficiency and stability. During the polishing process, after being energized, the chip interconnect layer material will undergo uniform anodic dissolution. Since there is no mechanical contact, no mechanical stress will be generated, effectively avoiding scratching the surfaces of copper materials and low dielectric constant materials. This embodiment not only has the advantages of low surface roughness and high polishing efficiency of the chemical mechanical polishing method, but also has the advantage of avoiding scratching the material surface of the stress-free polishing method, and is expected to become an important way for the planarization processing of chip interconnect layer materials.
[0047] The specific implementation process of this embodiment is as follows:
[0048] Immerse the porous ceramic plate 6 in the pre-prepared electrolyte 3, and use an ultrasonic vibration device to remove the air in the pores of the porous ceramic plate 6, so that the porous ceramic plate 6 adsorbs and stores the electrolyte 3, and drain the excess electrolyte 3 until there is no liquid film on the surface;
[0049] Load the pre-prepared electrolyte 3 and the porous ceramic plate 6 into the polishing device, and control the temperature of the electrolyte 3 at the preset temperature;
[0050] Install the silicon wafer to be processed on the end of the industrial robot through the fixture 9, and the industrial robot realizes the combined rotation-revolution movement of the silicon wafer, and makes the silicon wafer 8 to be polished contact the upper surface of the porous ceramic plate 6;
[0051] Connect the porous ceramic plate 6 to the positive pole of the power supply, and connect the auxiliary electrode 4 in the polishing device to the negative pole of the power supply, and apply a voltage between the positive pole and the negative pole to cause ionization and chemical reactions in the electrolyte 3;
[0052] The silicon wafer to be processed moves in a circular motion at a certain frequency in the polishing device, so that the silicon wafer to be processed and the porous ceramic plate 6 after adsorbing the electrolyte 3 generate relative motion, thereby completing the planarization processing of the interconnect structure on the silicon wafer surface.
[0053] Optionally, after the electrolyte 3 and the porous ceramic plate 6 are loaded into the polishing device, control the liquid level height of the electrolyte 3 so that 2 / 3 of the porous ceramic plate 6 in the thickness direction is immersed in the electrolyte 3 and 1 / 3 is not immersed in the electrolyte 3.
[0054] Optionally, the pre-prepared electrolyte 3 is formulated based on the interconnect material of the silicon wafer to be processed.
[0055] Optionally, the porous ceramic plate 6 is connected to the positive pole of the power supply through a wire based on the sliding contact principle of the carbon brush and the slip ring.
[0056] It is feasible that during processing, the silicon wafer to be processed utilizes a large number of interconnected network structures inside the porous ceramic plate 6 to form a capillary effect, thereby achieving the goal of sucking the electrolyte 3 to the processing position.
[0057] It is feasible to apply voltage between the processing anode and the processing cathode through an adjustable DC power supply, and the voltage is adjusted according to processing efficiency, processing quality and processing material requirements.
[0058] Optionally, this embodiment further includes: measuring electrochemical parameters in the electrolyte 3 in real time or within a preset time, and obtaining the performance and status of the electrolyte 3 based on the electrochemical parameters.
[0059] In summary, this embodiment provides a method for flattening the surface interconnect structure of a silicon wafer based on electrolyte-constrained electrochemical polishing. First, the porous ceramic plate 6 is immersed in a pre-configured electrolyte 3. The air in the pores is removed by an ultrasonic vibration device, so that the ceramic plate absorbs and stores the electrolyte 3. The excess electrolyte 3 is then drained until there is no liquid film on the surface. Next, the electrolyte 3 and the porous ceramic plate 6 are placed in a polishing device, the temperature of the electrolyte 3 is controlled at a preset value, and the liquid level is adjusted so that the main area of the porous ceramic plate in the thickness direction is immersed in the electrolyte, and the liquid level of the electrolyte is maintained at about 2 mm below the top of the porous ceramic plate. The silicon wafer to be processed is mounted on the end of the industrial robot through a fixture 9, realizing a rotation-revolution compound motion and contacting the upper surface of the porous ceramic plate 6. Through the principle of sliding contact between the brush and the conductive ring, the porous ceramic plate 6 is connected to the positive pole of the power supply, the auxiliary electrode 4 in the polishing device is connected to the negative pole of the power supply, and a voltage is applied using an adjustable DC power supply to induce ionization and chemical reaction in the electrolyte 3. During the polishing process, the silicon wafer performs a circular motion at a constant frequency, creating relative motion with the porous ceramic plate 6, which absorbs the electrolyte 3, completing the planarization process. Simultaneously, the capillary effect of the interconnected network structure within the porous ceramic plate 6 enables continuous pumping and supply of the electrolyte 3. Furthermore, by measuring the electrochemical parameters of the electrolyte 3 in real time or within a preset timeframe, the performance and condition of the electrolyte 3 can be dynamically monitored to optimize the polishing effect.
[0060] Compared with traditional polishing pads, the porous ceramic plate 6 of this embodiment has higher surface flatness and mechanical strength, and can achieve full-area efficient synchronous polishing without the need for replacement or trimming. During the polishing process, power is turned on to cause uniform anodic dissolution of the interconnection layer material, without mechanical stress, to avoid scratches. This method combines the high efficiency and low roughness of chemical mechanical polishing with the anti-scratch advantages of stress-free polishing, and is an important way to planarize the chip interconnection layer.
[0061] As described above, it is only the preferred specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. An electrochemical polishing device for planarizing a chip interconnect metal layer, characterized in that It includes a housing (2), the housing (2) being a cylinder with an open top. At the central position of the inner bottom end of the housing (2), an auxiliary electrode (4) layer is installed. Above the auxiliary electrode (4), a porous ceramic plate (6) is provided. The centers of the auxiliary electrode (4) layer and the porous ceramic plate (6) are on the same straight line, and the diameters of the auxiliary electrode (4) layer and the porous ceramic plate (6) are the same. An electrolyte (3) is filled between the outer sidewall of the porous ceramic plate (6) and the inner sidewall of the housing (2); a silicon wafer to be polished (8) is provided on the porous ceramic plate (6), and the silicon wafer to be polished (8) can be installed at the end of an industrial robot, and the industrial robot realizes the compound rotation-revolution movement of the silicon wafer.
2. The electrochemical polishing device for planarizing a chip interconnect metal layer according to claim 1, characterized in that, A conductive ring plate (1) is installed around the outer sidewall of the housing (2). Based on the principle of sliding contact between a brush and a conductive ring, the porous ceramic plate (6) is connected to the positive pole of a power supply through a wire, and the auxiliary electrode (4) layer is connected to the negative pole of the power supply through a wire.
3. The electrochemical polishing device for planarizing a chip interconnect metal layer according to claim 2, characterized in that, A wire fixing device (7) is provided at the bottom of the auxiliary electrode (4) layer.
4. The electrochemical polishing device for planarizing a chip interconnect metal layer according to claim 1, characterized in that, An insulating layer (5) is provided between the porous ceramic plate (6) and the auxiliary electrode (4) layer.
5. An electrochemical polishing device for planarizing a chip interconnect metal layer according to claim 1, wherein, The silicon wafer to be polished (8) is installed at the end of an industrial robot through a fixture (9).
6. A method for electrochemical polishing of a chip interconnect metal layer planarization, which is applied to a chip interconnect metal layer planarization electrochemical polishing device described in claims 1-5, characterized in that, It includes: Immerse the porous ceramic plate (6) in the electrolyte (3) for degassing treatment. After the treatment is completed, load the electrolyte (3) and the porous ceramic plate (6) into the polishing device, and regulate the electrolyte (3) based on a preset height and a preset temperature; Install the silicon wafer to be polished (8) at the end of an industrial robot through a fixture (9), and the industrial robot realizes the compound rotation-revolution movement of the silicon wafer, and makes the silicon wafer to be polished (8) contact the upper surface of the porous ceramic plate (6); Based on the principle of sliding contact between a brush and a conductive ring, connect the porous ceramic plate (6) to the positive pole of the power supply through a wire, and connect the auxiliary electrode (4) in the polishing device to the negative pole of the power supply; Start the industrial robot for polishing, and make the silicon wafer to be processed perform circular motion at a preset frequency to complete the planarization processing of the interconnect structure on the surface of the silicon wafer.
7. A method for electrochemical polishing of a chip interconnect metal layer planarization according to claim 6, characterized in that, The immersing the porous ceramic plate (6) in the electrolyte (3) for degassing treatment specifically includes: Immerse the porous ceramic plate (6) in the electrolyte (3), and use an ultrasonic vibration device to remove the air in the pores of the porous ceramic plate (6) so that the porous ceramic plate (6) adsorbs and stores the electrolyte (3); After the degassing treatment is completed, take out the porous ceramic plate (6) and drain the excess electrolyte (3) until there is no liquid film residue on its surface.
8. The electrochemical polishing method for planarizing a chip interconnect metal layer according to claim 6, characterized in that, The regulating the electrolyte (3) based on a preset height and a preset temperature specifically includes: Control the temperature of the electrolyte (3) at the preset temperature; Control the liquid level height of the electrolyte (3) according to the preset height: immerse the main area in the thickness direction of the porous ceramic plate (6) in the electrolyte (3), and keep the liquid level of the electrolyte (3) about 2 mm below the top of the porous ceramic plate.
9. The electrochemical polishing method for planarizing a chip interconnect metal layer according to claim 6, wherein During the polishing process, the connected network structure inside the porous ceramic plate (6) forms a capillary effect, sucking the electrolyte (3) from the immersed part to the processing position of the non-immersed part.
10. A method for electrochemical polishing of a chip interconnect metal layer planarization according to claim 6, characterized in that, Measure the electrochemical parameters in the electrolyte (3) within a preset time, and obtain the performance and condition of the electrolyte (3) based on the electrochemical parameters.