Power semiconductor device test system and method

Abstract

According to the power semiconductor device test system and method provided by the invention, the gate signal of the device to be tested under the actual working condition can be simulated through the signal generation module. The clamp module can be connected with the to-be-tested device and the performance test module, and in order to avoid the influence of parasitic parameters of the clamp on electric heat balance, device seats in the clamp module can be symmetrically distributed, so that the parasitic parameters of the clamp on each parallel branch can be the same, and errors introduced by the clamp module are eliminated. Besides, the performance test module is used for simulating the working condition of the to-be-tested device connected with the clamp module, and the monitoring control module is used for collecting the device temperature and voltage and current signals of the to-be-tested device in the performance test module, and monitoring and recording the voltage and current signals according to the device temperature to determine a test result. Monitoring and recording of voltage and current signals are automatically triggered through the numerical value of the temperature of the device, so that the accuracy of a test result can be improved while the labor cost is reduced.

Description

Technical Field

[0001] This application relates to the technical field of performance testing, and particularly to a power semiconductor device testing system and method. Background Art

[0002] As silicon-based semiconductor technology approaches its limit, silicon carbide materials have become a new choice for improving the performance of power converters due to their excellent electrical properties, such as high blocking voltage, low on-resistance, and high switching speed. Against the backdrop of pursuing "carbon peak" and "carbon neutrality", the demand for high-performance and low-energy-consuming power semiconductor modules has surged, especially in the fields of new energy vehicles and renewable energy. Therefore, it has become crucial to develop a test platform that can simulate actual working conditions and test the dynamic performance of silicon carbide devices at high temperatures.

[0003] Currently, the buck converter platform has received attention because it can simulate the continuous operating state and test the performance of devices at high temperatures. This platform inputs a gate drive signal to the device under test to simulate the continuous operating state of the device under test in actual working conditions. During continuous switching, due to the effects of switching losses and conduction losses, the chip junction temperature in the device under test will increase, and relevant data is recorded to evaluate the performance of the device under test.

[0004] However, currently during the testing process, it is necessary to manually monitor the experimental state in real time and continuously pay attention to the temperature rise, which easily affects the accuracy of the test results. Moreover, the test results are difficult to accurately reflect the electrothermal imbalance caused by different device parameters, thereby affecting the test accuracy. Therefore, the existing test platforms have problems with poor accuracy during the testing of power semiconductor devices. Summary of the Invention

[0005] The purpose of this application aims to solve at least one of the above technical defects, especially the technical defect of poor accuracy in the existing test platforms during the testing of power semiconductor devices.

[0006] In a first aspect, this application provides a power semiconductor device testing system, which includes a signal generation module, a monitoring and control module, a performance testing module, and a fixture module;

[0007] The signal generation module is connected to the performance testing module. The signal generation module is used to simulate the gate signal of the device under test under actual working conditions and amplify and input the simulated gate signal to the performance testing module;

[0008] The fixture module is used to connect the device under test and the performance testing module; the distribution of the device seats in the fixture module is arranged in a symmetric layout;

[0009] The performance test module is connected to the monitoring and control module. The performance test module is used to simulate the working conditions of the device under test connected to the fixture module. The monitoring and control module is used to collect the device temperature and voltage and current signals of the device under test in the performance test module, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test based on the recorded information.

[0010] In one embodiment, the signal generation module includes a pulse signal generator and a drive circuit;

[0011] The pulse signal generator is connected to the drive circuit. The pulse signal generator is used to generate a PWM signal and a dual-pulse drive signal;

[0012] The drive circuit is connected to the performance test module. The drive circuit is used to receive and amplify the PWM signal and the dual-pulse drive signal and then input them into the performance test module to simulate the gate signal of the device under test under actual working conditions.

[0013] In one embodiment, the process that the monitoring and control module is used to monitor and record the voltage and current signals according to the device temperature and determine the test result of the device under test based on the recorded information includes:

[0014] The monitoring and control module obtains a temperature threshold, and when the device temperature reaches the temperature threshold, records the waveform of the voltage and current signals to obtain a recording result;

[0015] The monitoring and control module evaluates the conduction loss, switching loss, and thermal stability of the device under test based on the recording result to generate the test result of the device under test.

[0016] In one embodiment, the performance test module includes a busbar DC power supply, a busbar capacitor, a load inductor, a load capacitor, a load resistor, a freewheeling diode, and a drive resistor;

[0017] The busbar DC power supply is connected in parallel with the busbar capacitor. The first end of the busbar capacitor is connected to the negative electrode of the freewheeling diode, and the second end is connected to the negative terminal of the fixture module and grounded at the second end;

[0018] The positive electrode of the freewheeling diode is connected to the positive terminal of the fixture module. The gate terminal of the fixture module is connected to one end of the drive resistor, and the other end of the drive resistor serves as the input end of the performance test module;

[0019] The first end of the load capacitor is connected to the first end of the load inductor, and the second end of the load inductor is connected to the negative electrode of the freewheeling diode;

[0020] The second end of the load capacitor is connected to the positive electrode of the freewheeling diode, and the load resistor is connected in parallel with the load capacitor.

[0021] In one embodiment, the fixture module includes a four-layer PCB circuit board, a plurality of device sockets, a positive terminal, a negative terminal, a gate terminal, and a Kelvin source terminal;

[0022] The PCB circuit boards are arranged in the fixture module from top to bottom in sequence. Insulating materials are filled between each layer of PCB circuit boards, and conductive materials are laid on the first-layer PCB circuit board and the fourth-layer PCB circuit board;

[0023] The positive terminal is arranged at the center of the first-layer PCB circuit board, and the negative terminal is arranged at the center of the fourth-layer PCB circuit board;

[0024] The gate terminal and the Kelvin source terminal are coaxially arranged near the center of the third-layer PCB circuit board and are led out from the fourth-layer PCB circuit board;

[0025] The device sockets are used to connect the device under test and are arranged on the front of the fixture module in a symmetric layout form.

[0026] In one embodiment, the drain of the device socket is connected to the first-layer PCB circuit board, the source is connected to the fourth-layer PCB circuit board, and the Kelvin source and the gate are connected to the third-layer PCB circuit board.

[0027] In one embodiment, the included angle between the connection line of each device socket and the center position of the fixture module is equal to the quotient of 360 degrees divided by the number of device sockets.

[0028] In one embodiment, the monitoring and control module includes a temperature measurement device, a voltage and current acquisition device, an oscilloscope, and a control device;

[0029] The temperature measurement device is used to collect the device temperature of the device under test in the performance test module, and the voltage and current acquisition device is used to collect the voltage and current signals of the device under test in the performance test module;

[0030] The oscilloscope is used to display and record the waveform of the voltage and current signals, and the control device is used to receive the user's instructions and start the test process.

[0031] In one embodiment, the voltage and current acquisition device includes a voltage probe and a current clamp; the voltage probe is used to collect voltage signals, and the current clamp is used to collect current signals.

[0032] Second aspect, the present application provides a method for testing a power semiconductor device, which is applied to the power semiconductor device testing system described in any one of the above embodiments. The system includes a signal generation module, a monitoring and control module, a performance testing module, and a fixture module. The method includes:

[0033] When starting the test, receive the temperature threshold input by the user, and trigger the signal generation module to generate a PWM signal and a double-pulse drive signal to test the device under test connected to the fixture module in the performance testing module;

[0034] During the test, trigger the temperature measurement device in the monitoring and control module to perform real-time temperature detection on the device under test;

[0035] When it is detected that the device temperature of the device under test reaches the temperature threshold, collect the voltage and current of the device under test based on the voltage and current acquisition device in the monitoring and control module, and record and display them through the oscilloscope in the monitoring and control module.

[0036] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0037] The power semiconductor device testing system and method provided by the present application. The system includes a signal generation module, a monitoring and control module, a performance testing module, and a fixture module. The signal generation module is connected to the performance testing module. Through the signal generation module, the gate signal of the device under test under actual working conditions can be simulated, and the simulated gate signal is amplified and input to the performance testing module. The fixture module can connect the device under test and the performance testing module. Since both the parasitic parameters of the fixture and the parasitic parameters of the device can affect the electrothermal balance, in order to avoid the influence of the parasitic parameters of the fixture on the electrothermal balance, the distribution of the device seats in the fixture module can be set to a symmetric layout, so that the parasitic parameters of each parallel branch are the same, thereby reflecting the influence of devices with different parameters on the electrothermal balance, eliminating the error introduced by the fixture module, and improving the test accuracy. In addition, the performance testing module is connected to the monitoring and control module. The performance testing module is used to simulate the working conditions of the device under test connected to the fixture module. The monitoring and control module is used to collect the device temperature and voltage and current signals of the device under test in the performance testing module, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test according to the recorded information. The monitoring and recording of the voltage and current signals are automatically triggered by the value of the device temperature, which can achieve automatic testing, reduce labor costs, and improve the accuracy of the test results at the same time. Description of the Drawings

[0038] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0039] Figure 1 Schematic diagram of the structure of a power semiconductor device test system provided by an embodiment of the present application;

[0040] Figure 2 Circuit structure diagram of a multi-device parallel BUCK experiment provided by an embodiment of the present application;

[0041] Figure 3 Schematic diagram of the structure of a fixture module provided by an embodiment of the present application;

[0042] Figure 4 Circuit structure diagram of a performance test module provided by an embodiment of the present application;

[0043] Figure 5 Schematic diagram of a PCB circuit board provided by an embodiment of the present application;

[0044] Figure 6 Schematic diagram of the flow of a power semiconductor device test method provided by an embodiment of the present application. Detailed implementation manners

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0046] The existing power semiconductor test platform lacks a control feedback system and requires manual real-time monitoring of the experimental status. During the test, researchers need to continuously monitor the temperature rise and manually adjust the oscilloscope to record waveforms at the required moments. In some cases, the device under test heats up relatively quickly (about 0.5°C / s to 0.8°C / s under air-cooled heat dissipation conditions), and there are many waveforms to be recorded during the heating process. Often, the recording time given to the experimenter is only dozens of seconds. For example, under air-cooled heat dissipation conditions, it takes 2 to 3 minutes for the device to heat up to 100°C. If waveforms at 6 temperatures need to be collected during this period, the average collection time for each temperature is only 20 to 30 seconds. Therefore, it not only consumes labor costs but also easily affects the accuracy of the test results due to recording errors. Secondly, the existing test platform fails to consider the fixture layout. Due to the asymmetric layout of the fixtures, the test results cannot reflect the electrothermal imbalance caused by the parameter imbalance of the device. Based on this, as Figure 1 shown, the present application provides a power semiconductor device test system, which includes a signal generation module 110, a monitoring and control module 120, a performance test module 130, and a fixture module 140.

[0047] The signal generation module 110 is connected to the performance test module 130. The signal generation module 110 is used to simulate the gate signal of the device under test under actual working conditions and amplify the simulated gate signal and input it to the performance test module 130.

[0048] The fixture module 140 is used to connect the device under test and the performance test module 130. The distribution of the device seats in the fixture module 140 is set to be symmetrically arranged.

[0049] The performance test module 130 is connected to the monitoring and control module **********120. The performance test module 130 is used to simulate the working conditions of the device under test connected by the fixture module 140. The monitoring and control module 120 is used to collect the device temperature and voltage and current signals of the device under test in the performance test module 130, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test according to the recorded information.

[0050] Among them, the device under test refers to the power semiconductor device to be tested. The gate signal refers to the electrical signal used to control the conduction and cutoff of the device under test.

[0051] In this embodiment, the signal generation module 110 first generates gate signals that simulate the actual working conditions of the device under test. These signals reflect various operating conditions that the device may encounter in actual applications, such as load changes, temperature fluctuations, etc. The signal generation module 110 also amplifies the generated signals to ensure sufficient driving ability. Then, the signals output by the signal generation module are input into the performance test module 130, where the performance test module 130 can simulate the working conditions of the device under test connected to the fixture module 140, including applying voltage, current, and possible environmental stresses, etc. The fixture module 140 uses a device seat with a symmetric layout to ensure that the parasitic parameters of the fixtures in each parallel branch are consistent, thereby eliminating errors introduced by the test system and accurately evaluating the device performance. The monitoring and control module 120 is responsible for real-time collecting the device temperature and voltage and current signals of the device under test, and automatically triggering the oscilloscope to record key waveforms according to the temperature threshold. Finally, the performance of the device under test is evaluated based on the recorded information to obtain the test results.

[0052] Specifically, the signal generation module 110 can receive relevant instructions to generate signals that meet the corresponding requirements, and these signals can be designed according to the expected performance of the device under test under actual working conditions. Subsequently, the signals generated by the signal generation module 110 can be amplified through a specific drive circuit. Then, the processed signals are input into the performance test module 130 to simulate the gate signals of the device under test under actual working conditions, so that the thermal stability and other indicators of the device under test can be tested in the performance test module 130. Then, the accuracy of the test is improved through two measures. On the one hand, the monitoring and control module 120 automatically records the waveforms of the voltage and current signals when the device temperature reaches the temperature threshold, which can ensure the correctness of the signal recording.

[0053] On the other hand, in the fixture module 140, the parasitic parameters on each parallel branch are different, resulting in different magnitudes of current flowing through each branch, then different amounts of heat generated, and finally different temperatures. Therefore, one way to achieve thermal equilibrium is to minimize the differences in parasitic parameters of each parallel branch. The parasitic parameters in the circuit can be divided into package parasitic parameters (which can be understood as fixture parasitic parameters in this solution) and device parasitic parameters. If an asymmetrically arranged fixture module is used, then the currents and temperatures flowing through the parallel DUTs obtained finally are different, and this difference here is caused by the combined effects of fixture parasitic parameter differences and device parasitic parameter differences. If a symmetrically arranged fixture module is used, it can ensure that the fixture parasitic parameter differences are very small. At this time, the current and temperature differences of the parallel DUTs obtained can be entirely attributed to device parameter differences. Based on this, the device seats in the fixture module 140 are arranged symmetrically, making the fixture parasitic parameters on each parallel branch the same, that is, the fixture parasitic parameter difference is zero, thereby reflecting the influence of devices with different parameters on thermal equilibrium, eliminating the errors introduced by the fixture module, and improving the test accuracy.

[0054] As Figure 2 shown, in the multi-device parallel BUCK experiment, the devices need to be paralleled through an external circuit such as a circuit board or wires. Figure 2 Taking the parallel connection of three DUTs as an example, where Qn (n = x~z) are the DUTs, L QnD 、L QnS 、L QnKS are the drain, source, and Kelvin source parasitic inductances generated by the device itself respectively, and L QnDP 、L QnSP are the drain and source parasitic inductances of the package (i.e., the external circuit, such as a PCB board and wires, etc.). When the device is turned on, the current flow direction (taking Qx as an example): DC+ — load — L QxDP — L QxD — Qx — L QxS — L QxSP — DC-, and the test circuit consists of three such parallel branches. The differences in parasitic inductances on each parallel branch will cause different drain currents for each device during the switching process, that is, the so-called dynamic current imbalance, and this imbalance will cause different thermal losses for each device. In the traditional layout, the package parasitic inductances on each parallel branch are not guaranteed to be the same, and the thermal imbalance of the devices is caused by the combined effects of package inductance differences and device inductance differences, and the influence of device inductance differences on thermal imbalance cannot be studied separately.

[0055] To study the influence of device parasitic inductance on thermal equilibrium, it is necessary to ensure that the package parasitic inductances on each parallel branch are the same, that is, make L QxDP = LQyDP = L QzDP ,L QxSP = L QySP = L QzSP 。In this way, it can be considered that the electrothermal imbalance phenomenon of the device is caused by the parameter imbalance of the device. According to the partial inductance theory, the inductance of a conductor is related to the length and cross-section of the conductor, and the mutual inductance between two conductors is related to the distance and angle between the conductors. In order to make the package inductance of each parallel branch consistent, a regular polygon layout is adopted, aiming to ensure that the conductor length, cross-section, angle, and distance are all the same. For easy understanding, please refer to Figure 5 , Figure 5 -a, Figure 5 -b are the power loop traces. Set the device sockets in the figure as x, y, z (corresponding to Figure 2 the three parallel devices under test in Figure 5 -a) from top to bottom in a clockwise direction. In QxDP = L QyDP = L QzDP , the drain lead conductors of the devices under test x, y, z need to meet the above requirements, that is, the lengths, cross-sections, angles, and distances of the traces x1-5, y1-5, z1-5 are all consistent. Among them, x1, y1, z1 respectively represent Figure 5 the x, y, z device sockets in

[0056] -a, 1 represents the drain terminal of the device socket, and 5 represents the positive connection terminal of the fixture module. Figure 5 Similarly, in QxSP = L QySP = L QzSP , the source lead conductors of the devices under test x, y, z need to meet the above requirements, that is, the lengths, cross-sections, angles, and distances of the traces x2-6, y2-6, z2-6 are all consistent. Among them, x2, y2, z2 respectively represent Figure 5 the x, y, z device sockets in

[0057] -b, 2 represents the source terminal of the device socket, and 6 represents the positive connection terminal of the fixture module.

[0058] In the above embodiments, the signal generation module is connected to the performance test module. Through the signal generation module, the gate signal of the device under test under actual working conditions can be simulated, and the simulated gate signal is amplified and input into the performance test module. The fixture module can connect the device under test and the performance test module. Since both the parasitic parameters of the fixture and the parasitic parameters of the device can affect the electrothermal equilibrium, in order to avoid the influence of the parasitic parameters of the fixture on the electrothermal equilibrium, the distribution of the device seats in the fixture module can be set to a symmetric layout, so that the parasitic parameters of the fixtures on each parallel branch are the same, thereby reflecting the influence of devices with different parameters on the electrothermal equilibrium, eliminating the errors introduced by the fixture module, and improving the test accuracy. In addition, the performance test module is connected to the monitoring and control module. The performance test module is used to simulate the working conditions of the device under test connected by the fixture module. The monitoring and control module is used to collect the device temperature and voltage and current signals of the device under test in the performance test module, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test according to the recorded information. The monitoring and recording of the voltage and current signals are automatically triggered by the value of the device temperature, so that automatic testing can be achieved, reducing the labor cost and improving the accuracy of the test result at the same time.

[0059] As Figure 1 shown, in one of the embodiments, the signal generation module 110 includes a pulse signal generator 111 and a drive circuit 112.

[0060] The pulse signal generator 111 is connected to the drive circuit 112. The pulse signal generator 111 is used to generate a PWM signal and a dual-pulse drive signal.

[0061] The drive circuit 112 is connected to the performance test module 130. The drive circuit 112 is used to receive and amplify the PWM signal and the dual-pulse drive signal and then input them into the performance test module 130 to simulate the gate signal of the device under test under actual working conditions.

[0062] Among them, the PWM signal refers to a pulse width modulation signal. The PWM signal is a modulation method that controls the average power of the signal by changing the pulse duration. The dual-pulse drive signal is a signal that continuously generates two pulses within a short period of time.

[0063] In this embodiment, the pulse signal generator 111 can generate PWM signals and dual-pulse drive signals. These signals simulate the switching operations of the device under test in actual applications. For example, in testing a semiconductor transistor for motor control applications, the PWM signal can be used to simulate the speed regulation process of the motor, while the dual-pulse drive signal can be used to evaluate the performance of the semiconductor transistor under fast and continuous switching operations. Then the signals generated by the pulse signal generator 111 are received and amplified by the drive circuit 112 to ensure that the signals have sufficient power and the correct waveform to drive the device under test in the performance test module 130.

[0064] In one embodiment, the monitoring and control module is used for the process of monitoring and recording voltage and current signals according to the device temperature and determining the test results of the device under test based on the recorded information, including:

[0065] The monitoring and control module obtains the temperature threshold, and when the device temperature reaches the temperature threshold, records the waveform of the voltage and current signals to obtain a recording result.

[0066] The monitoring and control module evaluates the conduction loss, switching loss, and thermal stability of the device under test based on the recording result to generate the test results of the device under test.

[0067] Among them, the conduction loss refers to the electrical energy consumed due to the resistance of the device itself when the device under test is in the conducting state. The switching loss refers to the loss generated due to the changes in current and voltage during the switching process of the device under test. The thermal stability refers to the ability of the device under test to maintain its performance without significant changes during long-term operation or under extreme temperature conditions.

[0068] In this embodiment, the monitoring and control module is responsible for real-time monitoring of the device temperature of the device under test, and when the preset temperature threshold is reached, automatically triggers the recording of the voltage and current waveforms. Then, using these waveform data, the conduction loss of the device under test can be calculated, that is, the electrical energy consumed due to the internal resistance when the device is in the conducting state. At the same time, by analyzing the waveforms during the switching process of the device under test, the switching loss can be evaluated, that is, the energy loss generated due to the changes in current and voltage during the switching operation of the device. In addition, by monitoring the temperature change of the device under test after continuous operation, its thermal stability can be evaluated. Finally, the test results are generated based on the evaluation results of the conduction loss, switching loss, and thermal stability of the device under test.

[0069] Exemplarily, when evaluating the performance of the device under test A in a power converter, the monitoring and control module records the voltage and current waveforms of the device under test A when it reaches a specific operating temperature. Based on these recording results, the conduction loss and switching loss of the device under test A, as well as its thermal stability at high temperatures, can be evaluated.

[0070] Specifically, when the device temperature reaches the temperature threshold, the monitoring and control module automatically records the waveforms of voltage and current signals, which can ensure the correctness of signal recording, improve the accuracy of testing, and comprehensively evaluate the performance of the device under test by evaluating its performance in multiple dimensions, thereby improving the reliability of testing.

[0071] As Figure 3 shown, in one embodiment, the performance test module includes a busbar DC power supply , a busbar capacitor , a load inductor , a load capacitor , a load resistor , a freewheeling diode D, and a driving resistor .

[0072] The busbar DC power supply is connected in parallel with the busbar capacitor . The first end of the busbar capacitor is connected to the negative electrode of the freewheeling diode D, and the second end is connected to the negative terminal s of the fixture module Q and grounded at the second end. The positive electrode of the freewheeling diode D is connected to the positive terminal d of the fixture module Q. The gate terminal g of the fixture module Q is connected to one end of the driving resistor , and the other end of the driving resistor is grounded. The gate terminal g of the fixture module Q serves as the input of the performance test module. The first end of the load capacitor is connected to the first end of the load inductor . The second end of the load inductor is connected to the negative electrode of the freewheeling diode D. The second end of the load capacitor is connected to the positive electrode of the freewheeling diode D. The load resistor is connected in parallel with the load capacitor .

[0073] In this embodiment, in the performance test module, the current path is divided into two cases: when the device under test is turned on and when it is turned off. When the device under test is turned on, the current flows out from the positive electrode of the busbar DC power supply , passes through the load branch (the branch composed of the load inductor , the load capacitor , and the load resistor ), then passes through the device under test and returns to the negative electrode of the busbar DC power supply . When the device under test is turned off, the device under test is in the off state and no current can flow through it. At this time, the load branch and the freewheeling diode D form a freewheeling circuit. The current direction of the load inductor remains unchanged. The current flows out from the load inductor , passes through the load capacitor and the load resistor , it flows back to the load inductor through the freewheeling diode D to the negative pole. In other words, when the device under test is turned on, the current directly passes through the device under test, and at this time, the performance of the device in the conduction state can be measured and evaluated. When the device under test is turned off, the function of the freewheeling diode D is to provide an alternative path for the current to continue flowing around the turned-off device under test, thereby avoiding voltage spikes or other circuit damages that may be caused by a sudden interruption of the current. Through such a circuit configuration, the continuous working and intermittent working states that the device under test may encounter in actual applications can be simulated, so as to evaluate its performance in different working modes.

[0074] In Figure 3 , represents the driving voltage generated by the signal input by the signal generation module.

[0075] As Figure 4 shown, in one embodiment, the fixture module includes four layers of PCB circuit boards (10, 11, 12, the second layer of PCB circuit board is not labeled), a plurality of device sockets 17, a positive terminal 13, a negative terminal 14, a gate terminal 16, and a Kelvin source terminal 15.

[0076] The PCB circuit boards are arranged in the fixture module from top to bottom in sequence, and insulating materials are filled between each layer of PCB circuit board. Conductive materials are laid on the first layer of PCB circuit board 10 and the fourth layer of PCB circuit board 12. The positive terminal 13 is arranged at the center of the first layer of PCB circuit board 10, and the negative terminal 14 is arranged at the center of the fourth layer of PCB circuit board 12. The gate terminal 16 and the Kelvin source terminal 15 are coaxially arranged near the center of the third layer of PCB circuit board 11, and are led out from the fourth layer of PCB circuit board 12. The device sockets 17 are used to connect the device under test and are arranged on the front of the fixture module in a symmetric layout form.

[0077] It can be understood that Figure 4 only describes one device socket, but in actual applications, there are generally multiple device sockets. In one example, the conductive material can be a copper layer.

[0078] Specifically, in order to facilitate testing the influence of device parameter mismatch on the electrothermal equilibrium performance under actual working conditions, the overall fixture module adopts a symmetric layout form to eliminate the influence of package mismatch. Since the number of devices under test needs to be determined according to actual requirements, for the sake of generality, this application will use the number of devices under test as n (n≥2) for description:

[0079] When the number of devices under test is n, the fixture module should be arranged as a regular n-sided polygon. The n device seats 17 are arranged at the vertices of the regular n-sided polygon. The included angles between the lines connecting each device seat 17 and the center point of the PCB circuit board or the center position of the fixture module satisfy 360° / n. The positive terminal 13 is arranged at the center of the regular n-sided polygon and leads out from the first-layer PCB circuit board 10. To take into account the insulation requirements for measuring high-voltage devices and ensure safe electrical clearances and creepage distances, the negative terminal 14 is arranged at the center of the regular n-sided polygon and leads out from the fourth-layer PCB circuit board 12. The gate terminal 16 and the Kelvin source terminal 15 are in the form of coaxial terminals, arranged near the center of the regular n-sided polygon and lead out from the fourth-layer PCB circuit board 12. The "nearby" here can be understood as giving priority to arranging the source terminal near the center of the regular n-sided polygon and arranging it nearby in accordance with the process requirements. The drains, sources, gates, and Kelvin sources of the n device seats 17 are electrically connected to the positive terminal 13, negative terminal 14, gate terminal 16, and Kelvin source terminal 15 respectively through large-area copper plating.

[0080] In this embodiment, since both the fixture parasitic parameters and the device parasitic parameters can affect the electrothermal balance, in order to avoid the influence of the fixture parasitic parameters on the electrothermal balance, the distribution of the device seats in the fixture module can be set as a symmetric layout. This can make the fixture parasitic parameters on each parallel branch the same, thereby reflecting the influence of devices with different parameters on the electrothermal balance, eliminating the error introduced by the fixture module, and improving the test accuracy.

[0081] As Figure 4 shown, in one of the embodiments, the drain 18 of the device seat 17 is connected to the first-layer PCB circuit board 10, the source 19 is connected to the fourth-layer PCB circuit board 12, and the Kelvin source 20 and the gate 21 are connected to the third-layer PCB circuit board 11.

[0082] In Figure 4 , 10, 11, 12 respectively represent the first-layer, third-layer, and fourth-layer PCB circuit boards. The traces of the first-layer and fourth-layer PCB circuit boards are connected by large-area copper plating. That is, the first-layer PCB circuit board is used as the high-voltage layer, and a whole piece of copper plating is used to connect the drains 18 of each device seat. The fourth-layer PCB circuit board is used as the low-voltage layer, and a whole piece of copper plating is used to connect the sources 19 of each device seat. The third-layer PCB circuit board is used as the driving signal trace layer, and a wiring method is adopted. The wiring path is as Figure 5As shown in -c. Since only even-numbered layers can be processed during PCB manufacturing, a four-layer circuit board must be used when three signal layers are required, and the second-layer PCB circuit board has no obvious function in this solution. 13 to 16 represent the positive terminal, negative terminal, Kelvin source terminal, and gate terminal respectively, 17 is the device socket, and 18 to 21 are the drain, source, Kelvin source, and gate of the device socket respectively. In terms of insulation, since the drain of the device socket bears high voltage while the source, Kelvin source, and gate bear low voltage, creepage distance and clearance should be designed between the drain and the source, Kelvin source, and gate of adjacent device sockets according to GB / T16935. At the same time, the positive terminal of the fixture module is connected to the DC power supply of the busbar. The negative terminal, Kelvin source terminal, and gate terminal are connected to a low potential, and the creepage distance and clearance between the positive terminal and the negative terminal, Kelvin source terminal, and gate terminal may be designed according to GB / T16935.

[0083] In one example, as Figure 5 shown, Figure 5 -a represents the front side of the first-layer PCB circuit board, Figure 5 -b represents the back side of the fourth-layer PCB circuit board, Figure 5 -c represents the traces of the third-layer PCB circuit board. In Figure 5 , 9 is the device socket, 1 to 4 are the drain, source, Kelvin source, and gate of the device socket respectively, 5 is the positive terminal, 6 is the negative terminal, 7 is the Kelvin source terminal, and 8 is the gate terminal. The dashed lines represent electrical connections. Among them, since the second-layer PCB circuit board does not play an obvious role, the front image of the second-layer PCB circuit board is not shown in Figure 5 .

[0084] In one of the embodiments, the included angle between the connection line of each device socket and the center position of the fixture module is equal to the quotient of 360 degrees divided by the number of device sockets.

[0085] In this embodiment, the distribution of the device sockets in the fixture module is set as a symmetric layout, which can make the parasitic parameters of the fixtures on each parallel branch the same, thus reflecting the influence of devices with different parameters on electrothermal equilibrium, eliminating the parameter differences introduced by the fixture module, and improving the test accuracy.

[0086] As Figure 1 shown, in one of the embodiments, the monitoring and control module 120 includes a temperature measurement device 121, a voltage and current acquisition device 122, an oscilloscope 123, and a control device 124.

[0087] The temperature measurement device 121 is used to collect the device temperature of the device under test in the performance test module 130, and the voltage and current acquisition device 122 is used to collect the voltage and current signals of the device under test in the performance test module.

[0088] The oscilloscope 123 is used to display and record the waveforms of the voltage and current signals, and the control device 124 is used to receive the user's instructions and start the test process.

[0089] In this embodiment, the device temperature is detected by the temperature measurement device 121, and the monitoring and recording of the voltage and current signals are automatically triggered according to the value of the device temperature, so as to realize automatic testing, reduce labor costs and improve the accuracy of the test results at the same time.

[0090] In one example, the temperature measurement device can use an infrared temperature sensor, and the control device can use a microcontroller device with peripherals such as a display screen and keys. The infrared temperature sensor is used to collect the device temperature of the device under test in the performance test module, and is converted into a digital signal through an analog-to-digital converter and output to the control device, where the I2C communication protocol is adopted. The control device can use an STM32 single-chip microcomputer as the control core to process data and realize the working mode switching by controlling the relay. The keys and the display screen communicate with the control device through GPIO for human-computer interaction to realize functions such as threshold setting and temperature display. The oscilloscope is used to monitor the current and voltage waveforms of the device under test, such as drain-source voltage, gate voltage, drain current, etc., and the control device realizes the control of the oscilloscope through a serial communication interface.

[0091] In one of the embodiments, the voltage and current acquisition device includes a voltage probe and a current clamp; the voltage probe is used to collect voltage signals, and the current clamp is used to collect current signals.

[0092] In one embodiment, a Pearson coil can also be used to collect current signals.

[0093] The power semiconductor device test method provided by the embodiments of the present application will be described below. The power semiconductor device test method described below can be correspondingly referred to the power semiconductor device test system described above.

[0094] As Figure 6 shown, the present application provides a power semiconductor device test method, which is applied to the power semiconductor device test system in any one of the above embodiments. The system includes a signal generation module, a monitoring and control module, a performance test module, and a fixture module. The method includes:

[0095] S201: When starting the test, receive the temperature threshold input by the user, and trigger the signal generation module to generate a PWM signal and a double-pulse drive signal to test the device under test connected to the fixture module in the performance test module.

[0096] S202: During the test process, trigger the temperature measurement device in the monitoring and control module to perform real-time temperature detection on the device under test.

[0097] S203: When it is detected that the device temperature of the device under test reaches the temperature threshold, collect the voltage and current of the device under test based on the voltage and current acquisition device in the monitoring and control module, and record and display them through the oscilloscope in the monitoring and control module.

[0098] In this embodiment, the user can input one or more temperature thresholds. The power semiconductor device test system sends a signal to activate the temperature measurement device for real-time temperature monitoring, and at the same time makes the relay act and connect the modulated drive signal to the performance test circuit. The device under test is triggered by continuous pulses. Due to the conduction loss and switching loss, the temperature of the device under test continues to rise. Whenever the temperature measurement device detects that the device temperature reaches the above temperature threshold, the system can let the oscilloscope record the waveform of the voltage and current signals until the waveforms at all temperature thresholds are recorded and then the relay acts to disconnect, and the system returns to the initial state.

[0099] In the above embodiment, the signal generation module is connected to the performance test module. Through the signal generation module, the gate signal of the device under test under actual working conditions can be simulated and the simulated gate signal can be amplified and input to the performance test module. The fixture module can connect the device under test and the performance test module. Since both the fixture parasitic parameters and the device parasitic parameters can affect the electro-thermal equilibrium, in order to avoid the influence of the fixture parasitic parameters on the electro-thermal equilibrium, the distribution of the device seats in the fixture module can be set to a symmetric layout, so that the fixture parasitic parameters on each parallel branch are the same, thereby reflecting the influence of devices with different parameters on the electro-thermal equilibrium, eliminating the error introduced by the fixture module, and improving the test accuracy. In addition, the performance test module is connected to the monitoring and control module. The performance test module is used to simulate the working conditions of the device under test connected by the fixture module, and the monitoring and control module is used to collect the device temperature and voltage and current signals of the device under test in the performance test module, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test according to the recorded information. The monitoring and recording of the voltage and current signals are automatically triggered by the value of the device temperature, so that automatic testing can be realized, reducing the labor cost and improving the accuracy of the test result at the same time.

[0100] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0101] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, for the "connection" in the above embodiments, if there is a transmission of electrical signals or data between the connected objects, it should be understood as "electrical connection", "communication connection", etc.

[0102] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element. In this article, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "including / comprising" or "having" etc. specify the existence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the existence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0103] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0104] The foregoing description of the disclosed embodiments enables those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power semiconductor device testing system, characterized in that, The system includes a signal generation module, a monitoring and control module, a performance testing module, and a fixture module; The signal generation module is connected to the performance testing module. The signal generation module is used to simulate the gate signal of the device under test under actual working conditions and amplify the simulated gate signal and input it into the performance testing module; The fixture module is used to connect the device under test and the performance testing module; the distribution of the device seats in the fixture module is arranged in a symmetric layout; The performance testing module is connected to the monitoring and control module. The performance testing module is used to simulate the working conditions of the device under test connected by the fixture module. The monitoring and control module is used to collect the device temperature and voltage and current signals of the device under test in the performance testing module, monitor and record the voltage and current signals according to the device temperature, and determine the test result of the device under test according to the recorded information.

2. The power semiconductor device testing system according to claim 1, characterized in that The signal generation module includes a pulse signal generator and a drive circuit; The pulse signal generator is connected to the drive circuit. The pulse signal generator is used to generate a PWM signal and a double-pulse drive signal; The drive circuit is connected to the performance testing module. The drive circuit is used to receive and amplify the PWM signal and the double-pulse drive signal and then input them into the performance testing module to simulate the gate signal of the device under test under actual working conditions.

3. The power semiconductor device testing system according to claim 1, wherein The process that the monitoring and control module is used to monitor and record the voltage and current signals according to the device temperature and determine the test result of the device under test according to the recorded information includes: The monitoring and control module obtains a temperature threshold, and when the device temperature reaches the temperature threshold, records the waveform of the voltage and current signals to obtain a recording result; The monitoring and control module evaluates the conduction loss, switching loss, and thermal stability of the device under test based on the recording result to generate the test result of the device under test.

4. The power semiconductor device testing system according to claim 1, characterized in that, The performance testing module includes a busbar DC power supply, a busbar capacitor, a load inductor, a load capacitor, a load resistor, a freewheeling diode, and a drive resistor; The busbar DC power supply is connected in parallel with the busbar capacitor. The first end of the busbar capacitor is connected to the negative electrode of the freewheeling diode, and the second end is connected to the negative terminal of the fixture module and is grounded at the second end; The positive electrode of the freewheeling diode is connected to the positive terminal of the fixture module. The gate terminal of the fixture module is connected to one end of the drive resistor, and the other end of the drive resistor is used as the input end of the performance testing module; The first end of the load capacitor is connected to the first end of the load inductor, and the second end of the load inductor is connected to the negative electrode of the freewheeling diode; The second end of the load capacitor is connected to the positive electrode of the freewheeling diode, and the load resistor is connected in parallel with the load capacitor.

5. The power semiconductor device testing system according to claim 1, characterized in that The fixture module includes a four-layer PCB circuit board, a plurality of device seats, a positive terminal, a negative terminal, a gate terminal, and a Kelvin source terminal; The PCB circuit boards are arranged from top to bottom in the fixture module, and insulating materials are filled between each layer of PCB circuit boards. Conductive materials are laid on the first-layer PCB circuit board and the fourth-layer PCB circuit board; The positive terminal is arranged at the center of the first-layer PCB circuit board, and the negative terminal is arranged at the center of the fourth-layer PCB circuit board; The gate terminal and the Kelvin source terminal are coaxially arranged near the center of the third-layer PCB circuit board and are led out from the fourth-layer PCB circuit board; The device socket is used to connect the device under test and is arranged on the front of the fixture module in a symmetric layout form.

6. The power semiconductor device testing system according to claim 5, wherein The drain of the device socket is connected to the first-layer PCB circuit board, the source is connected to the fourth-layer PCB circuit board, and the Kelvin source and the gate are connected to the third-layer PCB circuit board.

7. The power semiconductor device testing system according to any one of claims 1 to 6, characterized in that, The included angle between the connection line of each device socket and the center position of the fixture module is equal to the quotient of 360 degrees divided by the number of device sockets.

8. The power semiconductor device test system according to claim 1, wherein The monitoring and control module includes a temperature measurement device, a voltage and current acquisition device, an oscilloscope, and a control device; The temperature measurement device is used to collect the device temperature of the device under test in the performance test module, and the voltage and current acquisition device is used to collect the voltage and current signals of the device under test in the performance test module; The oscilloscope is used to display and record the waveforms of the voltage and current signals, and the control device is used to receive the user's instructions and start the test process.

9. The power semiconductor device testing system according to claim 8, characterized in that, The voltage and current acquisition device includes a voltage probe and a current clamp; the voltage probe is used to collect voltage signals, and the current clamp is used to collect current signals.

10. A method for testing a power semiconductor device, characterized in that, Applied to the power semiconductor device test system according to any one of claims 1 to 9, the system includes a signal generation module, a monitoring and control module, a performance test module, and a fixture module. The method includes: When the test is started, receive the temperature threshold input by the user, and trigger the signal generation module to generate a PWM signal and a double-pulse drive signal to test the device under test connected to the fixture module in the performance test module; During the test process, trigger the temperature measurement device in the monitoring and control module to perform real-time temperature detection on the device under test; When it is detected that the device temperature of the device under test reaches the temperature threshold, collect the voltage and current of the device under test based on the voltage and current acquisition device in the monitoring and control module, and record and display them through the oscilloscope in the monitoring and control module.

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