Online measurement circuit, SiC MOSFET gate oxide layer degradation monitoring method based on drain-source voltage surge characteristics and SiC MOSFET gate oxide layer degradation monitoring system based on drain-source voltage surge characteristics

Abstract

The invention provides an on-line measurement circuit and a SiC MOSFET gate oxide layer degradation monitoring method and monitoring system based on drain-source voltage surge characteristics, and the on-line measurement circuit comprises a waveform extraction circuit which is used for extracting a voltage waveform signal between a Kelvin source electrode and a power source electrode of a measured SiC MOSFET and carrying out voltage division output; and the envelope extraction circuit is used for extracting an envelope line of the voltage waveform signal output by the waveform extraction circuit and outputting the envelope line, and the peak value of the envelope line is used for representing the degradation degree of the gate oxide layer of the tested SiC MOSFET. According to the technical scheme, on-line measurement is carried out on the amplitude change condition of the surge signal superposed in the drain-source voltage of the SiC MOSFET, and the degradation degree of the gate oxide layer of the SiC MOSFET can be accurately monitored in the working process of the SiC MOSFET.

Description

Technical Field

[0001] This application belongs to the field of new energy technologies. Further, it relates to the field of power device monitoring technologies in new energy equipment, and specifically provides an on-line measurement circuit, a monitoring method and a monitoring system for SiC MOSFET gate oxide layer degradation based on drain-source voltage surge characteristics. Background Art

[0002] SiC MOSFET is a new type of power device, and has currently been widely applied in new energy equipment (such as electric vehicle inverters, photovoltaic inverters, and wind power converters). Since its gate oxide layer is thinner than that of Si MOSFET, its performance is more vulnerable to gate oxide layer degradation under high-voltage and high-frequency operating conditions. Therefore, on-line monitoring of the degradation degree of the SiC MOSFET gate oxide layer is of great significance for ensuring the safe operation of the system.

[0003] However, the existing schemes for evaluating the gate oxide layer state based on the measurement results of conventional electrical parameters such as threshold voltage drift or gate leakage current generally have limitations of high hardware requirements and difficulty in on-line experiments of inverters, and it is difficult to achieve real-time monitoring under the operating state of the inverter.

[0004] Therefore, there is a need to provide a new scheme that simultaneously meets the requirements of low hardware cost and high measurement accuracy, and does not require interrupting the device operation, and can realize real-time monitoring of the degradation degree of the SiC MOSFET gate oxide layer under the operating conditions of the inverter. Summary of the Invention

[0005] The first aspect of this application provides an on-line measurement circuit for on-line measurement of the SiC MOSFET to be measured in a SiC inverter during the operation of the SiC inverter. The on-line measurement circuit includes:

[0006] A waveform extraction circuit for extracting the voltage waveform signal between the Kelvin source and the power source of the SiC MOSFET to be measured and performing voltage division output;

[0007] An envelope extraction circuit for extracting the envelope of the voltage waveform signal output by the waveform extraction circuit and outputting it. The peak value of the envelope is used to characterize the degradation degree of the gate oxide layer of the SiC MOSFET to be measured.

[0008] Further, the waveform extraction circuit includes a first resistor and a second resistor connected in series;

[0009] The first end of the first resistor is electrically connected to the Kelvin source of the SiC MOSFET under test, and the second end is electrically connected to the first end of the second resistor and serves as the output end of the waveform extraction circuit. The second end of the second resistor is electrically connected to the power source of the SiC MOSFET under test and the ground terminal.

[0010] Preferably, the ratio of the resistance value of the first resistor to that of the second resistor is greater than or equal to 2.

[0011] Further, the envelope extraction circuit includes a first operational amplifier, a second operational amplifier, a first switching device, a second switching device, a first capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a positive power supply, and a negative power supply. The positive input terminal of the first operational amplifier is electrically connected to the output end of the waveform extraction circuit through the fourth resistor, the negative input terminal is electrically connected to the negative power supply through the fifth resistor, and the output end is electrically connected to the control terminals of the first switching device and the second switching device. The input terminal of the first switching device is electrically connected to the positive power supply through the sixth resistor, and the output end is electrically connected to the negative input terminal of the first operational amplifier. The input terminal of the second switching device is electrically connected to the positive power supply through the seventh resistor, and the output end is electrically connected to the positive input terminal of the second operational amplifier. The negative input terminal of the second operational amplifier is electrically connected to the ground terminal, and the output end is used to output the envelope line and is electrically connected to the ground terminal through the eighth resistor. Both ends of the first capacitor and both ends of the third resistor are connected between the positive input terminal of the second operational amplifier and the ground terminal.

[0012] Further, both the first switching device and the second switching device are NPN bipolar junction transistors. The NPN bipolar junction transistor uses the base as the control terminal, the collector as the input terminal, and the emitter as the output terminal.

[0013] Preferably, the resistance value r3 of the third resistor and the capacitance value c of the first capacitor E satisfy the following formula:

[0014]

[0015] where f SW is the switching frequency of the SiC MOSFET under test, and K is the discharge coefficient.

[0016] Preferably, the maximum operating frequencies of both the first operational amplifier and the second operational amplifier are not lower than 100Mhz, and the slew rates are not lower than 3.14V / ns.

[0017] The second aspect of the present application provides a method for monitoring the degradation of the gate oxide layer of a SiC MOSFET based on the drain-source voltage surge characteristic, including:

[0018] During the operation of the SiC inverter, the peak value of the envelope of the V S waveform signal of the SiC MOSFET under test is measured online, and the drain-source current of the SiC MOSFET under test in the on state is measured online, where V S is the voltage between the Kelvin source and the power source of the SiC MOSFET under test;

[0019] Using the pre-calibrated gate oxide layer degradation degree estimation model and the online measurement results of the SiC MOSFET under test, the degradation degree of the gate oxide layer of the SiC MOSFET under test is monitored.

[0020] Furthermore, the gate oxide layer degradation degree estimation model includes an undegraded fitting curve, and the undegraded fitting curve is obtained through the following steps:

[0021] Perform offline measurement on the first calibrated SiC MOSFET to obtain the drain-source current and the peak value of the envelope of the V S waveform signal in the on state when it is in several different working conditions. The first calibrated SiC MOSFET is a SiC MOSFET of the same model as the SiC MOSFET under test and not degraded.

[0022] Perform curve fitting on the offline measurement results of the first calibrated SiC MOSFET to obtain the undegraded fitting curve.

[0023] Preferably, the gate oxide layer degradation degree estimation model further includes a degradation degree tolerance table, and the degradation degree tolerance table is obtained through the following steps:

[0024] Perform offline measurement on several different second calibrated SiC MOSFETs to obtain the drain-source current and the peak value of the envelope of the V S waveform signal in the on state when each second calibrated SiC MOSFET is in several different working conditions. The several different second calibrated SiC MOSFETs are SiC MOSFETs of the same model as the SiC MOSFET under test and in different degradation degrees;

[0025] Based on the offline measurement results of several different second calibrated SiC MOSFETs and the undegraded fitting curve, obtain the degradation degree tolerance table.

[0026] The third aspect of the present application provides a SiC MOSFET gate oxide layer degradation monitoring system based on the drain-source voltage surge characteristic, including:

[0027] The aforementioned on-line measurement circuit is used to on-line measure the peak value of the envelope of the V S waveform signal of the measured SiC MOSFET during the operation of the SiC inverter;

[0028] A current measurement module is used to on-line measure the drain-source current of the measured SiC MOSFET in the on state during the operation of the SiC inverter;

[0029] A monitoring module uses the pre-calibrated gate oxide layer degradation degree estimation model and the on-line measurement results of the measured SiC MOSFET to monitor the degradation degree of the gate oxide layer of the measured SiC MOSFET.

[0030] The on-line measurement circuit provided by the embodiments of the present application adopts a non-intrusive on-line monitoring method. By monitoring the self-inductance voltage of the inherent parasitic inductance between the Kelvin source and the power source, a surge voltage signal that can reflect the degradation degree of the gate oxide layer can be monitored. There is no need to externally connect sensors or interrupt the device operation, realizing real-time status monitoring under inverter working conditions; the hardware requirements and cost of this on-line measurement circuit are low. The hardware cost is reduced by multiplexing the parasitic inductance, and the ADC sampling rate requirement is reduced by the peak holding method.

[0031] In addition, the parameters collected by this on-line measurement circuit are decoupled from temperature, with high anti-temperature interference ability. The output result is hardly affected by temperature under a specific driving resistance, and the output result is sensitive to the degradation of the gate oxide layer, showing obvious changes in the early stage of aging. It has strong universality and compatibility, and the detection module can be directly integrated into a commercial SiC MOSFET system using a 4-pin package. Description of the Drawings

[0032] Figure 1 is a circuit diagram of a SiC inverter;

[0033] Figure 2 is a schematic diagram of the on-line measurement circuit provided by the embodiments of the present application;

[0034] Figure 3 is a pin diagram of a SiC MOSFET using a 4-pin package method;

[0035] Figure 4 is for Figure 3 equivalent circuit diagram for driving the SiC MOSFET;

[0036] Figure 5 is a schematic diagram of the voltage waveform signal and its envelope between the S pole and the S' pole of the SiC MOSFET in a specific embodiment;

[0037] Figure 6Schematic diagram of the degradation mechanism of the gate oxide layer of SiC MOSFET;

[0038] Figure 7 I-V characteristics of SiC MOSFET during the turn-off process;

[0039] Figure 8 Schematic diagram of the drain-source voltage waveforms and PWM drive signals of three SiC MOSFETs on the upper bridge of a SiC inverter;

[0040] Figure 9 For Figure 8 Schematic diagram of the equivalent circuit of stage A where Q1 generates a surge voltage in

[0041] Figure 10 For Figure 8 Schematic diagram of the equivalent circuit of stage C where Q1 generates a surge voltage in

[0042] Figure 11 Physical diagram of the on-line measurement circuit provided according to an embodiment of the present application;

[0043] Figure 12 Flow chart of the SiC MOSFET gate oxide layer degradation monitoring method based on drain-source surge characteristics provided according to an embodiment of the present application;

[0044] Figure 13 Schematic diagram of the circuit of the calibration test equipment provided according to an embodiment of the present application;

[0045] Figure 14 Physical diagram of the calibration test equipment provided according to an embodiment of the present application;

[0046] Figure 15 Schematic diagram of the results of the calibration experiment on a fresh SiC MOSFET;

[0047] Figure 16 For the fresh SiC MOSFET's V surge_C 、I D_ON Relationship schematic diagram;

[0048] Figure 17 Schematic diagram of the equipment for aging the second calibrated SiC MOSFET;

[0049] Figure 18 Schematic diagram of the state change of the second calibrated SiC MOSFET after different aging times;

[0050] Figure 19 For the second calibrated SiC MOSFET's V surge_C 、I D_ON Relationship schematic diagram;

[0051] Figure 20 Flow chart of the SiC MOSFET gate oxide layer degradation monitoring method based on drain-source surge characteristics provided by an embodiment of the present application;

[0052] Figure 21 Schematic diagram of the measured experimental platform under the actual operating conditions of a real SiC inverter provided by an embodiment of the present application;

[0053] Figure 22 Schematic diagram of some experimental data collected from the measured experiment;

[0054] Figure 23 Schematic diagram of the monitoring results of a healthy SiC MOSFET;

[0055] Figure 24 Schematic diagram of the monitoring results of an aged SiC MOSFET;

[0056] Figure 25 Schematic diagram of the architecture of the SiC MOSFET gate oxide layer degradation monitoring system based on drain-source surge characteristics provided by an embodiment of the present application. Detailed implementation manners

[0057] Hereinafter, the present application will be further described based on preferred implementation manners with reference to the accompanying drawings.

[0058] In the description of the embodiments of the present application, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the products of the embodiments of the present application are usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, in the description of the present application, in order to distinguish different units, terms such as first and second are used in this specification, but these are not limited by the manufacturing sequence and should not be construed as indicating or implying relative importance. On the detailed description and claims of the present application, their names may be different. In addition, for the convenience of understanding, various components in the drawings are enlarged or reduced, but this approach is not intended to limit the protection scope of the present application.

[0059] The terms used in this specification are for the purpose of describing the embodiments of the present application, but are not intended to limit the present application. It should also be noted that unless otherwise clearly specified and defined, the terms "arranged", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, a direct connection, or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those skilled in the art, the specific meanings of the above terms in the present application can be specifically understood.

[0060] Figure 1 It is a circuit diagram of a SiC inverter constructed by SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors). Among them, Q1 to Q6 are six SiC MOSFETs respectively, L1 to L6 are the parasitic inductances of Q1 to Q6, C1 to C6 are the equivalent output capacitances of Q1 to Q6, S1 to S6 are the gate drive signals of Q1 to Q6, and M is the load motor.

[0061] During the operation of this SiC inverter, due to the relatively thin gate oxide layer of the SiC MOSFET, it is easier to generate the problem of gate oxide layer degradation. And this kind of gate oxide layer degradation has become one of the key problems affecting the reliability of SiC MOSFETs and severely restricts the wide application of SiC MOSFETs. Therefore, during the operation of the SiC inverter, it is necessary to measure and evaluate the gate oxide layer degradation of each SiC MOSFET in the SiC inverter conveniently, efficiently and accurately.

[0062] Although various methods for estimating the degradation degree of the gate oxide layer of SiC MOSFETs have been disclosed currently, some of the existing methods have a high requirement for the temperature stability of the measurement environment because the measurement results are coupled with the junction temperature of the power device; some need to add an additional temperature acquisition module to achieve the decoupling operation of the measurement result and temperature, resulting in the introduction of new parasitic parameters and affecting the performance of the drive circuit; and some solutions need a sampling circuit with an extremely high sampling rate to meet the requirements of sampling accuracy, thus greatly increasing the cost and difficulty of hardware implementation. Therefore, the current solutions for measuring and estimating the degradation degree of the gate oxide layer of SiC MOSFETs generally have limitations such as high hardware requirements and difficulty in on-line experiments of the inverter.

[0063] To solve the above problems, as Figure 2As shown, this application provides an on-line measurement circuit 1 through an embodiment, which is used to perform on-line measurement on the SiC MOSFET to be measured in the SiC inverter during the operation of the SiC inverter, and the obtained measurement results can be used to characterize the degradation degree of the gate oxide layer of the SiC MOSFET to be measured.

[0064] As Figure 2 shown, this on-line measurement circuit 1 can be connected to the bridge arm circuit 2 of the inverter Figure 1 when the shown SiC inverter is in a normal working state ( Figure 2 the middle bridge arm circuit 2 is composed of SiC MOSFETs Q1 and Q2), and perform on-line measurement on the SiC MOSFET Q1 to be measured on the bridge arm circuit 2. In the embodiment of this application, the SiC MOSFET used for on-line measurement and obtaining the aging degree of its gate oxide layer is called the SiC MOSFET to be measured. For example, Figure 2 Q1 in Figure 1 is the SiC MOSFET to be measured. Obviously, in other embodiments, this on-line measurement circuit can also be used to perform on-line measurement on

[0065] As Figure 2 shown, this on-line measurement circuit 1 is composed of a waveform extraction circuit 11 and an envelope extraction circuit 12. Specifically, the waveform extraction circuit 11 is used to extract the voltage waveform signal between the Kelvin source S' and the power source S of the SiC MOSFET to be measured (i.e., Q1) and perform voltage division output; the envelope extraction circuit 12 is used to extract the envelope of the voltage waveform signal output by the waveform extraction circuit 11 and perform output. Among them, the peak value of the extracted and output envelope is used to characterize the degradation degree of the gate oxide layer of Q1.

[0066] Figure 3 shows the pin diagram of a SiC MOSFET using a 4-pin package method. Figure 4 shows the equivalent circuit diagram for driving it. This type of 4-pin package SiC MOSFET has been widely used in application fields such as new energy vehicle motor inverters and photovoltaic inverters. As shown in the figure, in addition to the G pole (gate pole), D pole (drain pole) and S pole that are the same as the 3-pin package method, an S' pole pin is also led out. In order to distinguish it from the S pole, for the 4-pin package SiC MOSFET, its S pole is called the power source pole, and the S' pole is called the Kelvin source pole.

[0067] The Kelvin source electrode is constructed by separately dividing a part of the source electrode during metallization and leading it out through a pin. When driving the SiC MOSFET, by connecting the S' electrode to the G electrode, the lead-out parts of the gate-source loop and the drain-source loop are separated, thus avoiding the influence of the reverse voltage generated by the parasitic inductance on the drain-source loop due to the rapid flow of a large current during turn-on on the gate-source loop.

[0068] Correspondingly, an inductance L will be induced between the S electrode and the S' electrode. S , L S The existence of L causes a changing voltage waveform during the switching process of the SiC MOSFET. The on-line measurement circuit provided in this application is used to extract and output the envelope of the voltage waveform between the S electrode and the S' electrode.

[0069] Figure 5 Shows the voltage waveform signal (after voltage division) between the S electrode and the S' electrode and its envelope in a specific embodiment. In the subsequent monitoring method, the peak value of this envelope is used to monitor the degradation degree of the gate oxide layer of the SiC MOSFET.

[0070] It should be noted that the essence of the Kelvin source electrode is to separately lead out a loop connecting the gate on the source electrode of the SiC MOSFET chip. Even for a SiC MOSFET without a separate S' pin, the S' electrode can still be autonomously led out through adaptive transformation.

[0071] The following specifically explains the mechanism of collecting the envelope of the voltage waveform signal between the S electrode and the S' electrode through the relationship between the degradation of the gate oxide layer of the SiC MOSFET and the corresponding changes in various electrical parameters during the turn-off process of the SiC MOSFET.

[0072] I. Relationship between the degradation degree of the gate oxide layer of the SiC MOSFET and the change amounts of related electrical parameters

[0073] Figure 6 Shows the degradation mechanism of the gate oxide layer of the SiC MOSFET. According to Figure 6 the structure of the N-channel power SiC MOSFET shown in part (a) in, under the long-term action of high junction temperature and high electrical field stress, the defects at the SiC / SiO2 interface in the gate oxide layer will increase. When the SiC MOSFET is conducting, the drain-source current I D The path is as shown by the blue arrow. When the current path is close to the gate oxide layer interface, as Figure 6As shown in part (b), more electrons will be trapped here by the defects, and this phenomenon increases the accumulated charge density Nt at the SiC / SiO2 interface.

[0074] The gate threshold voltage V of the SiC MOSFET TH satisfies Equation (1). From Equation (1), it can be seen that the degradation of the gate oxide layer will cause V TH to increase.

[0075]

[0076] The Miller plateau voltage V GP satisfies Equation (2):

[0077]

[0078] where L CH is the channel length, W CH is the channel width, μ is the carrier migration velocity, C ox is the gate oxide capacitance, I D is the stable value of the drain-source current before the SiC MOSFET turns off (its amplitude is I D_on ), and the relationship between μ and Nt satisfies Equation (3):

[0079]

[0080] Taking the derivative of Equation (3) gives Equation (4):

[0081]

[0082] Observing Equation (4), it can be seen that the degradation of the gate oxide layer will cause V GP to increase.

[0083] The equivalent circuit of the SiC MOSFET is as shown in part (c) of Figure 6 , and its I-V characteristics during the turn-off process are shown in Figure 7 . Combining the above figure, during the Miller plateau stage (t1 to t2), the drain-source voltage V DS gradually increases, and the gate-source voltage V GS is maintained at the Miller voltage V GP unchanged. The drive current I G is generated by the discharge of the gate-drain capacitance C GD , and I G satisfies Equation (5), where t off represents the time variable during the turn-off stage.

[0084] At this time, V GP can be obtained from Equation (6):

[0085]

[0086] V GP = V EE + I G R G (6),

[0087] Among them, R G is the gate drive resistance, V EE is the gate turn-off drive voltage. Combining equations (5) and (6), it can be seen that the rate of change of the drain-source voltage dV DS / dt satisfies equation (7):

[0088]

[0089] Combining equations (2) and (4), it can be seen that when I D remains unchanged, if the gate oxide layer degrades and V GP increases, it will cause an increase in dV DS / dt during the turn-off process of the SiC MOSFET.

[0090] During the current decay period (t2~t3), the drain-source current I D gradually decreases from the load current to 0, and the gate-source voltage V GS satisfies equation (8):

[0091]

[0092] Among them, C GS is the gate-source capacitance. In the actual operation of the SiC MOSFET, the current decay period is extremely short, and the time t - t2 can be treated as a constant B.

[0093] The transconductance g m of the SiC MOSFET satisfies equation (9):

[0094]

[0095] Combining equation (8), it can be seen that the rate of change of the drain-source current satisfies equation (10):

[0096]

[0097] Combining equations (3) and (4), it can be seen that when I D remains unchanged, if the gate oxide layer degrades and V GP and μ change, it will cause a change in dI D / dt during the turn-off process of the SiC MOSFET.

[0098] Through the above analysis, it can be seen that dI D / dt during the turn-off process of the SiC MOSFET can be used as a characterization parameter for the degradation of its gate oxide layer.

[0099] 2. Voltage Surge Phenomenon and Mechanism Analysis in SiC MOSFET

[0100] SiC inverters have various parasitic parameters in their actual operation, such as Figure 1 The SiC inverter shown in the figure is generally equipped with a heat sink for heat dissipation, thereby introducing a parasitic capacitance C between the heat sink and each bridge arm. su , C sv , C sw , and introduce parasitic capacitance C between the heat sink and the busbar sn 、C sp Due to the presence of parasitic parameters, dV DS / dt and dI D / dt will cause a surge in the drain-source voltage of the SiC MOSFET.

[0101] The following uses the upper bridge as an example to illustrate the surge characteristics of the drain-source voltage in the working state of the SiC inverter. Figure 8 The drain-source voltage waveforms and PWM drive signals of the three SiC MOSFETs Q1, Q3, and Q5 on the upper bridge are shown from top to bottom. As shown in the figure, three surge voltages A, B, and C are generated on the drain-source voltage of each SiC MOSFET during the turn-off process of its switching cycle.

[0102] The mechanism of surge voltage A is as follows: the switching state of the SiC MOSFET in the current bridge arm remains unchanged, while the SiC MOSFETs in other bridge arms are turned off. The dV generated by the SiC MOSFETs in other bridge arms is DS / dt generates a surge current through the output capacitor, which flows through the parasitic capacitance path, causing the drain-source voltage of the current bridge arm SiC MOSFET to generate a surge voltage A.

[0103] Taking the surge voltage A of Q1 as an example, deduce its amplitude V surge_A The expression, Figure 9 This is the equivalent circuit of the surge voltage stage A generated by Q1. The current path is shown by the red arrow in the figure. Since Q1 and Q3 are in the on state, their on resistance is R on , at the moment Q5 turns off, the output capacitor C5 discharges, and we can get equation (11), as well as equations (12) and (13) satisfied by the voltage of U1:

[0104]

[0105] Combining equations (11) to (13) yields equation (14), and ultimately, equation (15) yields the amplitude expression for the Q1 surge voltage A:

[0106]

[0107] V surge_A =I surge_A ×R on (15).

[0108] The mechanism of surge voltage B is similar to that of A. It is also caused by the shutdown of SiC MOSFETs in other bridge arms, which generates a surge in the drain-source voltage of the SiC MOSFET in the current bridge arm. For example, surge voltage B of Q1 is caused by the shutdown of Q3.

[0109] The generation mechanism of surge voltage C is different from that of surge voltage A and surge voltage B. It is due to the change of the switching state of the SiCMOSFET in the current bridge arm, which generates dI D / dt is generated on the drain-source voltage of the SiC MOSFET in the current bridge arm through parasitic inductance. Taking Q1 as an example, the equivalent circuit when it generates surge voltage C is as follows Figure 10 As shown, during the off period of Q1, I D When the current becomes 0, the expression of the surge voltage C satisfies equation (16):

[0110]

[0111] 3. Characteristics Analysis of Surge Voltages A, B, and C

[0112] From equations (14) and (15), we can see that for SiC MOSFET Q1, its V surge_A The value of parasitic inductance L1, L5, parasitic capacitance C SW 、C SU , on-state resistance R on and V DS Of the above variables, only R on Will be affected by gate oxide degradation, but due to R on It will also change with the junction temperature. Therefore, if you want to surge_A To determine the degree of gate oxide degradation, additional junction temperature information is required. Based on the same analysis, if you want to use V surge_B To determine the degree of gate oxide degradation, it is also necessary to obtain junction temperature information. However, in SiC inverters, the junction temperature and R on The acquisition method is complex, which will undoubtedly increase the complexity of the measurement circuit.

[0113] In addition, when the inverter working condition changes, the duty cycle changes will cause V surge_A Superimposed on different gate-source voltage waveforms, for example, Figure 8 In the embodiment shown, Q1's V surge_A Superimposed on the on-state voltage V on On the other hand, the V of Q3 and Q5surge_A is superimposed on the DC bus voltage V BUS on, and V surge_B also has the above characteristics. Therefore, if V surge_A or V surge_B is used as the measurement item, it is also necessary to consider the bridge arm where the measured SiC MOSFET is located to ensure acquisition at different times, or to design a measurement circuit separately for different bridge arms, which will also cause difficulties in the design of the measurement circuit.

[0114] According to equation (16), for SiC MOSFET Q1, the value of V surge_C is related to the parasitic inductance L1 and dI D / dt. Generally, the parasitic inductance L1 does not change with temperature or service life. Therefore, under the operating conditions of the SiC inverter, by collecting I D and V surge_C the degradation degree of the gate oxide layer can be reflected.

[0115] Based on the above analysis, V surge_C should be used as the parameter to characterize the degradation degree of the SiC MOSFET, and a measurement circuit capable of collecting V surge_C (or capable of collecting an electrical parameter that is linearly proportional to V surge_C and is easy to measure) should be designed.

[0116] IV. Select appropriate measurement electrical parameters

[0117] According to the foregoing analysis, V surge_C can characterize the degradation of the gate oxide layer of the SiC MOSFET, but the V surge_C signal is superimposed on the gate-source voltage with an amplitude equal to V BUS . The amplitude of V BUS is large and has nothing to do with the degradation of the gate oxide layer. If the gate-source voltage is used as the measurement item, it is necessary to greatly improve the sensitivity of the measurement circuit to ensure that a small surge amplitude on the high V BUS amplitude can be obtained. Therefore, compared with directly measuring the gate-source voltage and separating the surge voltage C in it, using dI D / dt to reflect V surge_C is a more reasonable choice.

[0118] According to Figure 8 it can be known that when the switching state of the inverter changes, V surge_A and V surge_B will also be superimposed on V BUS . It can be found from Figure 8 that V surge_C has the highest amplitude among the three surge voltages. Therefore, the peak value of V surge_C can be highlighted by extracting the envelope and excluding Vsurge_A and V surge_B influence.

[0119] Adopt an envelope line to obtain the peak value of V surge_C can also effectively reduce the hardware cost. The reason is that in an actual inverter, the dI of the SiC MOSFET D / dt is about 5 A / ns, and the rate of change of the V surge_C signal is approximately the same as it. If the complete V surge_C signal is collected, it will lead to an overly expensive hardware cost. In contrast, the method of extracting the envelope line can reduce the ADC resolution requirement on the basis of maintaining the peak information, thereby achieving a reduction in hardware cost.

[0120] Furthermore, it can be seen from equation (17) that the voltage across the two ends of L S is in a proportional relationship with dI D / dt:

[0121]

[0122] Combined with equation (16), the linear proportional relationship between Vs and V surge_C as shown in equation (18) can be obtained:

[0123]

[0124] It can be seen that V surge_C can be measured by the change of V S . The online measurement circuit 1 provided in this application precisely measures the voltage V S across the two ends of the inductor L S between the S pole and the S' pole to reflect the change information of V surge_C . Based on the above analysis, in the subsequent gate oxide layer degradation monitoring method, the above measurement results will be used for the estimation of the gate oxide layer degradation of the SiC MOSFET, and in the following description, V surge_C can be used to replace V S .

[0125] V. Specific implementation manner of the online measurement circuit3]

[0126] In the embodiment of this application, as Figure 2 shown, the waveform extraction circuit 11 includes a first resistor R1 and a second resistor R2 connected in series. Among them, the first end of the first resistor R1 is electrically connected to the Kelvin source electrode S' of the SiC MOSFET to be measured, the second end is electrically connected to the first end of the second resistor R2 and serves as the output end of the waveform extraction circuit 11, and the second end of the second resistor R2 is electrically connected to the power source electrode S of the SiC MOSFET to be measured and the ground terminal. The voltage V is realized through the first resistor R1 and the second resistor R2S Extraction of the voltage waveform and voltage division output.

[0127] Preferably, the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is greater than or equal to 2. For example, in a specific embodiment, R1 is 1 kΩ and R2 is 470 Ω. By reasonably setting the resistance values of the two resistors R1 and R2, it can be ensured that the output voltage amplitude meets the range requirements of the subsequent processing circuit.

[0128] In the embodiment of the present application, as Figure 2 shown, the envelope extraction circuit 12 includes a first operational amplifier U1, a second operational amplifier U2, a first switching device q1, a second switching device q2, a first capacitor C E , a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a positive power supply, and a negative power supply. Among them, the positive power supply and the negative power supply are both DC power supplies, and the voltage values are V CC and -V CC respectively, and their specific values can be determined according to the positive and negative withstand voltages of the operational amplifier. For example, V CC is selected as 5 V or 3.3 V (correspondingly, -V CC is -5 V or -3.3 V).

[0129] Further, the positive input terminal of the first operational amplifier U1 is electrically connected to the output terminal of the waveform extraction circuit 11 through the fourth resistor R4, the negative input terminal is electrically connected to the negative power supply (-V CC ) through the fifth resistor R5, and the output terminal is electrically connected to the control terminals of the first switching device q1 and the second switching device q2 at the same time; the input terminal of the first switching device q1 is electrically connected to the positive power supply (V CC ) through the sixth resistor R6, and the output terminal is electrically connected to the negative input terminal of the first operational amplifier U1; the input terminal of the second switching device q2 is electrically connected to the positive power supply (V CC ) through the seventh resistor R7, and the output terminal is electrically connected to the positive input terminal of the second operational amplifier U2; the negative input terminal of the second operational amplifier U2 is electrically connected to the ground terminal, the output terminal is used to output the envelope line (Vout), and is electrically connected to the ground terminal through the eighth resistor R8 at the same time; one end of the first capacitor C E is electrically connected to the positive input terminal of the second operational amplifier U2, and the other end is electrically connected to the ground terminal; similarly, one end of the third resistor R3 is electrically connected to the positive input terminal of the second operational amplifier U2, and the other end is electrically connected to the ground terminal.

[0130] The waveform of the Vout signal output by the envelope extraction circuit 12 is the Figure 5 envelope line in, and the working principle of this envelope extraction circuit 12 is:

[0131] At Vsurge_C During the rapid rise stage, the Vs (equivalent to V surge_C ) after voltage division enters the positive input terminal of the first operational amplifier U1 and is compared with -V CC . After comparison, the output voltage signal will simultaneously control the first switching device q1 and the second switching device q2 to maintain a continuous on state, so that the first capacitor C E is charged until it reaches the peak value of V surge_C . At the same time, the V out output by the second operational amplifier U2 rapidly rises to the peak value of V surge_C ;

[0132] When V surge_C starts to decline after passing through its peak point, the voltage signal output by the first operational amplifier U1 is inverted, and the first switching device q1 and the second switching device q2 are turned off. After that, the first capacitor C E enters the discharge state. During this process, since other surge voltages A, B, etc. cannot exceed the potential of the capacitor C E , the V out output by the operational amplifier U2 slowly declines until the surge voltage C in the next cycle triggers the first switching device q1 and the second switching device q2 to conduct again.

[0133] An AD converter that meets the requirements of sampling rate speed and accuracy can be used for analog-to-digital conversion and then further digital signal processing operations. It can be found that by outputting a signal in the form of an envelope, while retaining the peak value of the surge voltage C, it can effectively filter out the voltage fluctuations caused by other surge voltages and effectively reduce the accuracy requirements for AD conversion and data processing. In some specific embodiments, for example, AD9248 can be used as the AD converter, with a measurement range of ±12V and an accuracy higher than 5mV.

[0134] In some preferred embodiments, both the first switching device q1 and the second switching device q2 are NPN bipolar junction transistors, with their bases as the control terminals, collectors as the input terminals, and emitters as the output terminals. Using NPN bipolar junction transistors to construct switching devices can effectively improve the response speed of the circuit.

[0135] The first operational amplifier U1 and the second operational amplifier U2 can be constructed using operational amplifiers with suitable parameters. Their bandwidth and slew rate have an important impact on the accuracy of envelope extraction. Specifically, the slew rate and bandwidth calculation of the operational amplifier satisfy equation (19),

[0136]

[0137] where SR is the slew rate of the operational amplifier, V m is the maximum output voltage of the operational amplifier, and fmax is the maximum operating frequency of the circuit. Since the switching speed of the SiC MOSFET is about 5 A / ns, in the inverter operating condition, the switching duration of the SiC MOSFET is about 30 ns. Therefore, f max is preferably not less than 100 MHz. In order to make full use of the ADC accuracy and not exceed the ADC range, at V m with a value of 5 V, it can be calculated that SR is at least 3.14 V / ns.

[0138] In a specific embodiment, U1 and U2 can use an operational amplifier of model LM7171, whose bandwidth is 200 MHz and slew rate is 4.1 V / ns.

[0139] Combined with Figure 5 and the previous analysis, it can be seen that the generation of the envelope can be divided into a charging stage and a discharging stage. The duration of the charging stage is generally relatively short, much shorter than the switching process of the SiC MOSFET; the shape of the envelope in the discharging stage is related to the values of R3 and C E . Between two V surge_C peaks, the values of R3 and C E should satisfy equation (20) to minimize the voltage drop of C E as much as possible:

[0140]

[0141] where f sw is the switching frequency of the SiC MOSFET, and K is the discharging coefficient.

[0142] The ranges of the above parameters can be reasonably set according to the specific operating conditions of the SiC inverter and the requirements for data acquisition accuracy. For example, in a specific embodiment, K = 5, the switching frequency of the SiC inverter is 20 kHz, R3 is 47 k, and C E is 10 nF. In other embodiments, the parameter values of the above components can also be reasonably set according to the specific parameters of the measured SiC MOSFET.

[0143] Similarly, although Figure 2 the optional resistance values of resistors R4 to R8 are given in the shown embodiment, in other embodiments, the resistance values of the above resistors can also be flexibly adjusted according to the specifications of the measured SiC MOSFET, and comprehensively considering the range, accuracy, and speed characteristics of the operational amplifier and switching devices.

[0144] Figure 11 The shown embodiment shows the physical diagram of the on-line measurement circuit 1 manufactured according to the Figure 2 circuit schematic diagram.

[0145] VI. Online Monitoring of Degradation Degree of SiC MOSFET Gate Oxide Layer

[0146] Some embodiments of the present application provide a method for monitoring the degradation of the SiC MOSFET gate oxide layer based on the drain-source surge characteristics. The method includes:

[0147] During the operation of the SiC inverter, online measurement of the peak value of the envelope of the V S waveform signal is performed, and online measurement of the drain-source current I D_ON of the SiC MOSFET under test in the on state is performed. Here, V S is the voltage between the Kelvin source and the power source of the SiC MOSFET under test;

[0148] Using the pre-calibrated gate oxide layer degradation degree estimation model and the online measurement results of the SiC MOSFET under test, the degradation degree of the gate oxide layer of the SiC MOSFET under test is monitored.

[0149] Figure 12 shows a specific embodiment of the method. Referring to Figure 12 , during the operation of the SiC inverter, after determining the SiC MOSFET under test, the envelope of V S can be obtained through the aforementioned online measurement circuit, and the drain-source current in the on state can be measured by devices such as current probes. The measurement results can be digitized using a dual-channel AD converter such as the aforementioned AD9248, and the envelope peak information can be extracted. Then, the envelope peak and I D_ON are compared with the preset gate oxide layer degradation degree estimation model to obtain an estimation result of the degradation degree of the gate oxide layer of the SiC MOSFET under test. In addition, after completing the monitoring of one SiC MOSFET under test, the SiC MOSFET under test can be replaced and the above measurement and comparison process can be repeated.

[0150] During the process of monitoring the SiC MOSFET under test, it is necessary to measure I S while collecting the envelope information of V D_ON because, as can be seen from equations (2) and (10), V surge_C is affected by the stable value of the drain-source current I D before turn-off (i.e., I D_on ). Since the I D_on of the SiC inverter is different under different operating conditions, when comparing the measurement results with the gate oxide layer degradation degree model, it should be performed for the same I D_on .

[0151] VII. Establishing an Estimation Model for the Degradation Degree of the SiC MOSFET Gate Oxide Layer

[0152] The estimation model for the degradation degree of the SiC MOSFET gate oxide layer is used to reflect the drain-source voltage surge C of the non-degraded SiC MOSFET under various working conditions (with different I D_on ), as analyzed above, the peak value of the V S envelope can be used for characterization. Generally, it can be represented by a function curve in the form of V surge_C_fresh = f(I D ). The establishment of this function curve can be achieved through offline measurement using the calibration experimental equipment shown in Figure 13 . The experimental principle is similar to the double-pulse test. Here, both Q and DUT are fresh and non-degraded SiC MOSFETs. V1 is a constant voltage source that provides a small constant voltage (such as 4V) to keep Q normally closed. L is the load inductor, and its inductance value can be determined according to the SiC MOSFET specifications (for example, an inductor with an inductance value of 100uH is selected). The data acquisition part includes a measurement circuit and a current probe. Among them, the measurement circuit is the aforementioned online measurement circuit for outputting the VS waveform envelope.

[0153] Figure 14 The embodiment of shows the physical diagram of this calibration experimental equipment. As shown in the figure, the controller is used to generate the drive signal for the DUT, and the DC Bus Capacitor is used to stabilize the voltage so that the voltage of V BUS is maintained at a set value (such as 300V). The Driver generates N gate pulses with a high-level time of t high and a low-level time of t low , so that the values of each group of I D increase successively as shown in Equation (21):

[0154]

[0155] By using the measurement circuit and the current probe, N groups of I D and V surge_C can be continuously measured.

[0156] Table 1 shows the specific experimental parameters of this calibration experimental equipment in a certain calibration experiment:

[0157] Table 1

[0158]

[0159]

[0160] Since the maximum continuous current of the DUT is 25A, according to Equation (21), N is taken as 8, and thigh It takes 1.4 μs. Calibration experiments are carried out using fresh SiC MOSFETs. The drain-source voltage V of the DUT is collected through an oscilloscope. DS , the surge voltage V surge_C and the drain-source current I D . The waveforms are as shown in part (a) of Figure 15 . As I increases, V D gradually increases. After I surge_C exceeds 22.4 A, since the absolute value of dI D / dt no longer increases, R3 and C D in the measurement circuit form a discharge loop, causing the V E curve to show a downward trend. Therefore, the surge voltage C is related to the current, which is consistent with the previous analysis. According to the curve in part (b) of surge_C Figure 15 , after I D exceeds 22.4 A, the absolute value of dI D / dt is maintained at 77.1 A / μs, so V surge_C no longer increases. Further, at a bus voltage of 300 V with the gate drive parameters unchanged, the relationship between V surge_C and I D is as shown in Figure 16 . The relationship curve between V surge_C and I D can be obtained by fitting the measurement results. For example, fitting the data in Figure 16 gives the non-degraded fitting curve shown in equation (22) (i.e., the gate oxide degradation degree estimation model of the SiC MOSFET of the DUT model):

[0161]

[0162]

[0163] Figure 13 After obtaining the above non-degraded fitting curve, during the operation of the SiC inverter, the peak value of the V S envelope (in this application, this measured value is denoted as V surge_C_real ) and the corresponding I D_on of each measured SiC MOSFET during its turn-off process can be obtained in real time. Then, using this non-degraded fitting curve, the deviation degree between V D and V surge_C_real is evaluated under the same I surge_C_fresh condition, so as to estimate the degradation degree of the measured SiC MOSFET.

[0163] In some preferred embodiments, Figure 13 and Figure 14 can also be used.Experimental equipment is used to perform offline measurements on several SiC MOSFETs with different degrees of gate oxide layer degradation. The offline measurement results are combined with the non-degraded fitting curve corresponding to a fresh SiC MOSFET to obtain a degradation tolerance table T ol = TABLE(I D ). In the embodiments of the present application, to clearly distinguish between the fresh SiC MOSFET used to establish the non-degraded fitting curve V surge_C_fresh = f(I D ) and the SiC MOSFETs with different degradation degrees used to generate the degradation tolerance table T ol = TABLE(I D ), the former is called the first calibrated SiC MOSFET, and the latter is called the second calibrated SiC MOSFET.

[0164] Obviously, the second calibrated SiC MOSFET needs to be aged to different degrees in advance while monitoring its aging degree. This operation can be achieved by the equipment shown in Figure 17 . The (a) part in Figure 17 is the circuit schematic diagram. Among them, SMU1 is used to apply a high electrical field Stress to the gate of the DUT (i.e., the second calibrated SiC MOSFET). At the same time, SMU1 and SMU2 can be used to measure the V TH of the DUT. When SMU1 scans the voltage of the gate-source, the drain-source voltage provided by SMU2 remains unchanged. When I D exceeds the threshold current I th , the gate-source voltage is V TH , as shown in the physical diagram of the (b) part. The temperature chamber is used to provide a high-temperature test environment. The ambient temperature is set to 150°C, and the V TH value of the DUT is detected regularly to evaluate the aging degree of the DUT. The aging strategy for the second calibrated SiC MOSFET is shown in Table 2.

[0165] Table 2

[0166]

[0167]

[0168] Figure 18 The (a) part of surge_C shows the change of V surge_C at the instant of turn-off of the second calibrated SiC MOSFE after different aging times. The results show that the V surge_C_Fresh value of the aged second calibrated SiC MOSFET is greater than that of the fresh first calibrated SiCMOSFET. Figure 18Part (b) can be used to explain the above results.

[0169] Figure 18 Part (b) shows the I at the instant of turn-off D changes occurring with the increase of the aging duration. In the time interval of t1 - t2, when the aging duration is less than 48H, |dI D / dt| increases with the increase of the duration, and V surge_C also increases; when the aging duration is greater than 48H and less than 72H, |dI D / dt| decreases with the increase of the aging duration, and V surge_C also decreases accordingly; when the aging duration is greater than 72H, |dI D / dt| increases again with the increase of, and V surge_C also increases, but is always greater than the V surge_C and |dI D / dt| of the fresh SiC MOSFET, which is consistent with the previous analysis of the change of dI D / dt with aging at the instant of turn-off.

[0170] The relationship between V surge_C and I D of the second calibrated SiC MOSFE at the instant of turn-off under different aging durations is as shown in Figure 19 . It can be seen that the V D value at the same I surge_C changes with the change of the aging degree.

[0171] The difference in the peak V D voltage (ΔV surge_C ) between the aged SiC MOSFET (second calibrated SiC MOSFET) and the fresh SiC MOSFET (first calibrated SiC MOSFET) at the same I surge_C can be used to characterize the degradation of the gate oxide layer.

[0172] ΔV surge_C = V surge_C_Aged - V surge_C_Fresh (23),

[0173] The V surge_C when the SiC MOSFET just starts to age can be called V surge_C_D . The difference between V surge_C_D and V surge_C_fresh is the tolerance value T ol . If ΔV surge_CIf the value exceeds the tolerance, it is considered that the gate oxide layer of the SiC MOSFET has aged at this time. Otherwise, the SiC MOSFET is considered healthy. The minimum ΔV in the conducted experiments can be taken surge_C as the tolerance value, as shown in Figure 19 by the yellow area in

[0174] Table 3 records the specific tolerance values T D corresponding to each I ol . Using this degradation degree tolerance table, T ol and I D can establish a look-up relationship T ol =TABLE(I D ).

[0175] Table 3

[0176] <![CDATA[I D (A)]]> <![CDATA[T ol (mV)]]> 2.8 202 5.6 118 8.4 75 11.2 113 14 140 16.8 87 19.6 73 22.4 74

[0177] Figure 20 The embodiment of shows the complete process of monitoring the degradation degree of the gate oxide layer of each measured SiC MOSFET in a working SiC inverter. The gate oxide layer degradation degree estimation model used therein consists of the fitting curve V surge_C_fresh =f(I D ) and the degradation degree tolerance table T ol =TABLE(I D ). The implementation manners of each step of this embodiment have been described in detail above.

[0178] VIII. Experimental Verification

[0179] To verify the effectiveness of the gate oxide layer degradation monitoring method provided in this application, in a specific embodiment, a three-phase six-bridge-arm power topology structure as shown in Figure 21 was built to conduct measured experiments under the working conditions of a real SiC inverter, where parts (a) and (b) are the circuit schematic diagram and the physical diagram respectively. The specific parameter settings of the measured experimental platform are shown in Table 4.

[0180] This verification experiment collects V DS of the measured SiC MOSFET, phase current I A , I D and V surge_C (obtained by collecting V S information) through an oscilloscope. Some experimental data are as shown in Figure 22 . Under the target Q-axis current, the phase current is stable, there is a surge phenomenon in the phase voltage, the peak envelope extraction value is stable, and V surge_C increases as the absolute value of the drain current increases, which is consistent with the previous analysis and meets the expectations.

[0181] Table 4

[0182] Experimental setup parameters Value Switching frequency 20Khz Q-axis target current 23A LOAD SIC MOSFET Cree C3M0016120K LOAD L 200uL V mcu 300V V motor 300V NI FPGA PXIe-7822

[0183] Verification experiments were respectively carried out on healthy and aged SiC MOSFETs. At the operating point with I D_on being 19.6 A and substituting V surge_C_fresh = f(I D ), the obtained V surge_C_fresh and the V ol obtained by looking up the table T D = TABLE(I ol ) were used for data comparison.

[0184] Figure 23 shows the experimental results of healthy SiC MOSFETs. The results show that when I D_on = 19.6 A, the difference between the experimentally measured V surge_C_Healthy value and V surge_C_fresh is 35 mV, which is less than the tolerance value T ol obtained by looking up the table. It can be considered that the health state of its gate oxide layer has not changed, and it belongs to a healthy SiC MOSFET.

[0185] Figure 24 shows the experimental results of aged SiC MOSFETs. The results show that when I D_on = 19.6 A, the difference between the experimentally measured V surge_C_Aged value and V surge_C_fresh is 92 mV, which exceeds the tolerance value T ol obtained by looking up the table. It can be considered that the health state of its gate oxide layer has changed significantly, and this SiC MOSFET is an aged SiC MOSFET.

[0186] Some embodiments of the present application also provide a SiC MOSFET gate oxide layer degradation monitoring system based on the drain-source voltage surge characteristic. As shown in Figure 25 , this monitoring system includes:

[0187] The aforementioned on-line measurement circuit is used to on-line measure the peak value of the envelope of the V S waveform signal of the SiC MOSFET to be measured during the operation of the SiC inverter;

[0188] The current measurement module is used to on-line measure the drain-source current of the SiC MOSFET to be measured in the on state during the operation of the SiC inverter;

[0189] The monitoring module uses the pre-calibrated gate oxide layer degradation degree estimation model and the online measurement results of the SiC MOSFET to be measured to monitor the degradation degree of the gate oxide layer of the SiC MOSFET to be measured.

[0190] The specific implementation manners of the online measurement circuit and the current measurement module have been introduced above. In some specific embodiments, the monitoring module can be implemented in a manner known to those skilled in the art. For example, devices including but not limited to digital signal processors (DSPs), microcontroller units (MCUs), field programmable gate arrays (FPGAs), and embedded systems based on Linux or RTOS can pre-store the gate oxide layer degradation degree estimation model through built-in or external storage units, and can perform the comparison operation of the measurement data and the degradation degree estimation model through a pre-embedded executable program. In addition, the system can also be equipped with a display device and an interactive operation interface to realize functions such as real-time display of monitoring results, switching of the power device to be measured, and parameter adjustment.

[0191] The specific implementation manners of the present application have been described in detail above. For those skilled in the art of this technology, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An on-line measurement circuit is used to perform on-line measurement on the SiC MOSFET to be measured in the SiC inverter during the operation of the SiC inverter, and is characterized in that, Including: A waveform extraction circuit, configured to extract a voltage waveform signal between the Kelvin source and the power source of the SiC MOSFET under test and perform voltage division output; An envelope extraction circuit, configured to extract the envelope of the voltage waveform signal output by the waveform extraction circuit and output it, and the peak value of the envelope is used to characterize the degradation degree of the gate oxide layer of the SiC MOSFET under test.

2. The on-line measurement circuit according to claim 1, wherein The waveform extraction circuit includes a first resistor and a second resistor connected in series; The first end of the first resistor is electrically connected to the Kelvin source of the SiC MOSFET under test, the second end is electrically connected to the first end of the second resistor and serves as the output end of the waveform extraction circuit, and the second end of the second resistor is electrically connected to the power source and the ground terminal of the SiC MOSFET under test.

3. The on-line measurement circuit according to claim 2, wherein The ratio of the resistance value of the first resistor to the resistance value of the second resistor is greater than or equal to 2.

4. The on-line measurement circuit according to claim 1, wherein The envelope extraction circuit includes a first operational amplifier, a second operational amplifier, a first switching device, a second switching device, a first capacitor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a positive power supply and a negative power supply; The positive input terminal of the first operational amplifier is electrically connected to the output terminal of the waveform extraction circuit through the fourth resistor, the negative input terminal is electrically connected to the negative power supply through the fifth resistor, and the output terminal is electrically connected to the control terminals of the first switching device and the second switching device; The input terminal of the first switching device is electrically connected to the positive power supply through the sixth resistor, and the output terminal is electrically connected to the negative input terminal of the first operational amplifier; The input terminal of the second switching device is electrically connected to the positive power supply through the seventh resistor, and the output terminal is electrically connected to the positive input terminal of the second operational amplifier; The negative input terminal of the second operational amplifier is electrically connected to the ground terminal, and the output terminal is used to output the envelope and is electrically connected to the ground terminal through the eighth resistor; Both ends of the first capacitor and both ends of the third resistor are connected between the positive input terminal of the second operational amplifier and the ground terminal.

5. The on-line measurement circuit according to claim 4, wherein 6. The on-line measurement circuit according to claim 4, characterized in that, The resistance value r3 of the third resistor and the capacitance value c of the first capacitor E Satisfy the following formula: where f SW is the switching frequency of the SiC MOSFET under test, and K is the discharge coefficient. Both the first switching device and the second switching device are NPN bipolar junction transistors, the NPN bipolar junction transistor uses the base as the control terminal, the collector as the input terminal, and the emitter as the output terminal.

7. The on-line measurement circuit according to claim 4, wherein 8. A method for monitoring the degradation of the gate oxide layer of a SiC MOSFET based on the drain-source voltage surge characteristics, characterized in that, The maximum operating frequencies of the first operational amplifier and the second operational amplifier are both not lower than 100Mhz, and the slew rates are both not lower than 3.14V / ns. During the operation of the SiC inverter, the peak value of the envelope of the V S waveform signal of the SiC MOSFET under test is measured online, and the drain-source current of the SiC MOSFET under test in the on state is measured online, where V S is the voltage between the Kelvin source and the power source of the SiC MOSFET under test; Including: Using the pre-calibrated gate oxide layer degradation degree estimation model and the on-line measurement results of the SiC MOSFET under test, monitor the degradation degree of the gate oxide layer of the SiC MOSFET under test.

9. The method for monitoring the degradation of the gate oxide layer of a SiC MOSFET based on the drain-source voltage surge characteristics according to claim 8, wherein The gate oxide layer degradation degree estimation model includes an undegraded fitting curve, and the undegraded fitting curve is obtained through the following steps: Perform offline measurements on the first calibrated SiC MOSFET to obtain the drain-source current and the peak value of the envelope of the V S waveform signal when it is in several different working conditions. Here, the first calibrated SiC MOSFET is a SiC MOSFET of the same model as the SiC MOSFET under test and has not degraded; Curve fitting is performed on the offline measurement results of the first calibrated SiC MOSFET to obtain the undegraded fitting curve.

10. The method for monitoring the degradation of the gate oxide layer of a SiC MOSFET based on the drain-source voltage surge characteristics according to claim 9, characterized in that, The gate oxide layer degradation degree estimation model further includes a degradation degree tolerance table, and the degradation degree tolerance table is obtained through the following steps: Offline measurements are performed on a number of different second-calibrated SiC MOSFETs to obtain the drain-source current and the peak value of the envelope of the V S waveform signal in the on state when each second-calibrated SiC MOSFET is in a number of different operating conditions, where the number of different second-calibrated SiC MOSFETs are SiC MOSFETs of the same model as the SiC MOSFET under test and in different degrees of degradation; Based on the offline measurement results of several different second calibrated SiC MOSFETs and the undegraded fitting curve, a degradation degree tolerance table is obtained.

11. A monitoring system for the degradation of the gate oxide layer of a SiC MOSFET based on the drain-source voltage surge characteristics, characterized in that, It includes: The on-line measurement circuit as claimed in claim 1 is used to on-line measure the peak value of the envelope of the V S waveform signal during the operation of the SiC inverter; A current measurement module for online measuring the drain-source current of the SiC MOSFET under test in the on state during the operation of the SiC inverter; A monitoring module for monitoring the degradation degree of the gate oxide layer of the SiC MOSFET under test by using the gate oxide layer degradation degree estimation model obtained by pre-calibration and the online measurement results of the SiC MOSFET under test.

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