Optimal selection method and measurement method of electrical parameters and estimation method of degradation condition of gate oxide layer of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention provides an optimal selection method and a measurement method of electrical parameters and an estimation method of the degradation condition of a gate oxide layer of a SiC MOSFET, and the optimal selection method comprises the following steps: determining a relation model between a plurality of electrical parameters and the degradation degree of the gate oxide layer in a turn-off process in combination with a gate oxide layer degradation model of the SiC MOSFET and the I-V characteristics of the turn-off process; determining a plurality of alternative electrical parameters in combination with the relation model and the actual working characteristics of the SiC inverter; on the basis of the equivalent circuit model of each alternative electrical parameter, evaluating the online measurement difficulty of each alternative electrical parameter and the coupling degree between the alternative electrical parameter and the SiC MOSFET temperature, and determining a preferred electrical parameter according to an evaluation result; and determining a mapping electrical parameter for joint measurement with the preferred electrical parameter. By deeply exploring the relationship between the aging of the gate oxide layer and each electrical parameter, the electrical parameter suitable for online monitoring of the degradation degree of the gate oxide layer of the SiC MOSFET can be preferably selected.

Description

Technical Field

[0001] This application belongs to the field of new energy technologies, and relates to the power device performance monitoring technology of inverters applied to new energy equipment. Specifically, it provides an optimization method and a measurement method for electrical parameters, as well as an estimation method for the degradation of the gate oxide layer of SiC MOSFETs. Background Art

[0002] In recent years, with the rapid development of clean energy technologies represented by photovoltaic power generation, wind power, new energy vehicles, etc., higher requirements have been put forward for power devices. The silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) is gradually replacing the silicon metal-oxide-semiconductor field-effect transistor (Si MOSFET) due to its advantages such as faster switching speed, higher blocking voltage, higher temperature tolerance, lower on-resistance, and lower switching losses, and has become an indispensable part of fields such as energy conversion, aerospace, and electric vehicles.

[0003] Because the SiC MOSFET has a thinner gate oxide layer, lower channel electron mobility, and higher SiC / SiO2 interface trap density, which reduces the barrier height between SiC / SiO2 and exacerbates the Fowler-Nordheim tunneling effect, making it more vulnerable to gate oxide layer degradation than Si MOSFETs and having a shorter working life. It can be seen that gate oxide layer degradation has become one of the key reliability issues of SiC MOSFETs, seriously restricting the wide application of SiC MOSFETs. Therefore, studying an effective method for monitoring the degradation of the gate oxide layer of SiC MOSFETs is of great significance for its life prediction and reliability assessment.

[0004] The electrical parameter method is widely used in the monitoring of the degradation degree of different positions (including the gate oxide layer) of power devices. Currently, a variety of methods for monitoring the degradation of the gate oxide layer using the electrical parameter method have been proposed. However, in various known technical solutions, either the selected measured electrical parameter is coupled with the junction temperature of the power device, resulting in a high requirement for the temperature stability of the measurement environment; or an additional temperature acquisition module is added to decouple the measured electrical parameter from the temperature, resulting in the introduction of new parasitic parameters and affecting the performance of the drive circuit; or a sampling circuit with an extremely high sampling rate is required to meet the requirements of sampling accuracy, thus greatly increasing the cost and difficulty of hardware implementation. Therefore, the above-mentioned existing technologies are not suitable for online monitoring of the degradation degree of the gate oxide layer of SiC MOSFETs during the continuous switching operation of SiC inverters. Summary of the Invention

[0005] The first aspect of the present application provides a method for optimizing electrical parameters. The electrical parameters optimized by this method can effectively characterize the aging degree of the gate oxide layer in SiC MOSFETs, and have low difficulty, low cost, and high accuracy in online measurement during the operation of SiC inverters, and can effectively realize the online monitoring of the performance of SiC inverters. The method includes the following steps:

[0006] Combined with the gate oxide layer degradation model of SiC MOSFETs and the I-V characteristics during the turn-off process, determine the relationship model between several electrical parameters and the degradation degree of the gate oxide layer during the turn-off process of SiC MOSFETs;

[0007] Combined with the relationship model and the actual working characteristics of SiC inverters, determine several alternative electrical parameters, where the alternative electrical parameters are caused by parasitic parameters during the operation of SiC inverters, and the parameter values change with the change of the degradation of the gate oxide layer of SiC MOSFETs;

[0008] Based on the equivalent circuit models of each alternative electrical parameter, evaluate the online measurement difficulty of each alternative electrical parameter and its coupling degree with the temperature of SiC MOSFETs, and determine the optimized electrical parameter according to the evaluation results;

[0009] Determine the mapping electrical parameter for joint measurement with the optimized electrical parameter.

[0010] The second aspect of the present application provides a method for measuring electrical parameters, which is used for online measurement of the measured electrical parameters of the measured SiC MOSFETs in SiC inverters during the operation of SiC inverters, where the measured electrical parameters are linearly related to the optimized electrical parameters determined by the aforementioned method for optimizing electrical parameters.

[0011] Preferably, the on-line measurement of the electrical parameters to be measured is carried out by accessing a measurement circuit during the operation of the SiC inverter, and the access mode of the measurement circuit is set so as not to introduce new parasitic parameters during the measurement of the electrical parameters to be measured.

[0012] The third aspect of the present application provides a method for estimating the degradation of the gate oxide layer of a SiC MOSFET. The method includes the following operations: Based on the results of on-line measurement of the electrical parameters to be measured and the mapped electrical parameters of the SiC MOSFET to be measured during the operation of the SiC inverter, estimate the degradation of the SiC MOSFET to be measured, wherein the on-line measurement of the electrical parameters to be measured is carried out by the aforementioned electrical parameter measurement method.

[0013] Preferably, the estimation of the degradation of the SiC MOSFET to be measured includes:

[0014] Based on the deviation between the on-line measurement results of the electrical parameters to be measured and the mapped electrical parameters of the SiC MOSFET to be measured and the fitting curve of the preferred electrical parameters and the mapped electrical parameters of the same type and non-degraded SiC MOSFET established in advance, evaluate the degradation of the gate oxide layer of the SiC MOSFET to be measured.

[0015] The preferred method for electrical parameters provided by the embodiments of the present application deeply explores the relationship between the aging of the gate oxide layer of the SiC MOSFET and each electrical parameter, aiming to exclude temperature-related factors and other influencing factors introduced by on-line measurement, and selects the optimal electrical parameter that can be used to measure and estimate the degradation degree of the gate oxide layer among various alternative electrical parameters. The electrical parameter selected by this method is suitable for non-invasive on-line monitoring, without external sensors or interrupting device operation, realizing real-time status monitoring under inverter conditions, and at the same time having good high temperature interference resistance. The output result is hardly affected by temperature under a specific driving resistance, and the output result is sensitive to the degradation of the gate oxide layer, and there are obvious changes in the early stage of aging.

[0016] The electrical parameter measurement method provided by the embodiments of the present application designs a reasonable parameter characterization method based on the characteristics of the preferred electrical parameters, determines the signal acquisition method based on this, and the required circuit hardware has low requirements and costs. By multiplexing parasitic inductance, the hardware cost is reduced, and the universality and compatibility are strong. It can be directly integrated into a commercial SiC MOSFET system with a four-pin package. Description of the Drawings

[0017] Figure 1 It is the circuit diagram under the actual working state of a SiC inverter constructed by a SiC MOSFET;

[0018] Figure 2A flowchart of a method for optimizing electrical parameters according to an embodiment of the present application;

[0019] Figure 3 Schematic diagram of a gate oxide layer degradation model of a SiC MOSFET provided according to an embodiment of the present application;

[0020] Figure 4 Based on Figure 3 Schematic diagram of the IV characteristics of the SiC MOSFET turn-off process obtained from the equivalent circuit diagram in;

[0021] Figure 5 This is a schematic diagram of the drain-source voltage and PWM drive signal of the three SiC MOSFETs in the upper bridge when the SiC inverter is in operation;

[0022] Figure 6 This is the equivalent circuit diagram when a surge voltage A is generated on the drain-source voltage of Q1 due to the turn-off of Q5;

[0023] Figure 7 This is the equivalent circuit diagram when Q1 generates surge voltage C;

[0024] Figure 8 A schematic diagram of a measurement circuit according to an embodiment of the present application;

[0025] Figure 9 This is a schematic diagram of the appearance of a SiC MOSFET;

[0026] Figure 10 for Figure 9 Equivalent circuit diagram of SiC MOSFET shown;

[0027] Figure 11 V provided according to the embodiment of the present application surge_C The waveform signal and V surge_C Schematic diagram of the envelope;

[0028] Figure 12 The V of an undegraded SiC MOSFET provided in an embodiment of the present application is measured offline. surge_C_fresh , I D_on Circuit schematic diagram of the experimental system;

[0029] Figure 13 is the V of an undegraded SiC MOSFET surge_C_real , I D_on Schematic diagram of the fitting curve;

[0030] Figure 14 This is a degradation experiment waveform diagram obtained according to the degradation experiment platform provided in an embodiment of the present application;

[0031] Figure 15Schematic diagram of the degradation experiment results of a healthy SiC MOSFET;

[0032] Figure 16 Schematic diagram of the degradation experiment results of an aged SiC MOSFET. Detailed implementation manners

[0033] Hereinafter, the present application will be further described based on preferred implementation manners with reference to the accompanying drawings.

[0034] In the description of the embodiments of the present application, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the products in the embodiments of the present application are usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present application. In addition, in the description of the present application, in order to distinguish different units, the first, second, etc. are used in this specification, but these are not limited by the manufacturing order and cannot be understood as indicating or implying relative importance. In the detailed description and claims of the present application, their names may be different.

[0035] The terms in this specification are used to describe the embodiments of the present application, but are not intended to limit the present application. It should also be noted that unless otherwise clearly defined and limited, if terms such as "set", "connected", "connected to" are used, they should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be specifically understood.

[0036] <Parameter definitions>

[0037] Table 1 shows the definitions of some parameters involved in the specification of the present application.

[0038] Table 1

[0039]

[0040]

[0041] <Introduction to the prior art>

[0042] Figure 1It is a circuit diagram of a SiC inverter constructed using six SiC MOSFETs (Q1 - Q6), where L1 - L6 are the parasitic inductances of Q1 - Q6, C1 - C6 are the equivalent output capacitances of Q1 - Q6, S1 - S6 are the gate drive signals of Q1 - Q6, and M is the load motor. As described in the background art, during the operation of this SiC inverter, the degradation of the gate oxide layer of each SiC MOSFET has become one of the key issues affecting the reliability of SiC MOSFETs and severely restricts the wide application of SiC MOSFETs. However, existing solutions for estimating the degradation degree of the gate oxide layer of SiC MOSFETs by measuring various electrical parameters generally have limitations such as high hardware requirements and difficulty in on-line experiments of the inverter, and it is difficult to achieve real-time monitoring under the operating state of the inverter, etc.

[0043] For example, the on-resistance R on , the gate threshold voltage V TH , the Miller plateau voltage V GP , the Miller plateau duration T GP , the input capacitance C ISS , and the gate leakage current I GSS can be measured. However, among the above electrical parameters, V TH and V GP are coupled with the junction temperature and have high requirements for the temperature stability of the measurement environment. Although the gate oxide layer degradation monitoring technology based on temperature compensation can decouple V TH from the temperature, it requires an additional temperature acquisition module in the gate - source loop, which will introduce gate parasitic inductance and affect the performance of the drive circuit, and is not suitable for application scenarios such as inverters with high requirements for switching frequency; V TH , R on need to measure multiple switching parameters and then be calculated, and the measurement strategy is complex and not suitable for on-line measurement of inverters; T GP , C ISS and I GSS need to acquire complete voltage and current waveforms, have high hardware requirements, and require an nS - level sampling circuit and a uA - level resolution, with too high costs.

[0044] In the currently disclosed technical solutions, there are also some technical solutions for measuring new electrical parameters that can characterize the precursor of gate oxide layer degradation derived from the above electrical parameters. For example, based on the gate electrical parameters, the average value of the gate input voltage can be used to judge the degradation degree of the gate oxide layer. However, a monitoring circuit needs to be added between the gate and the source, which will introduce parasitic parameters and is not suitable for application scenarios such as inverters that have high requirements for switching frequency. Another example is to use the phase current rise delay time and the charging time within a specific gate voltage range as the precursor of gate oxide layer aging. However, an nS-level sampling circuit is required, and there are also problems of high hardware requirements and great measurement difficulty. Another example is to use dI D / dt during the turn-on process of the MOSFET as the electrical parameter for monitoring the precursor of gate oxide layer aging. However, monitoring it requires collecting a complete voltage waveform, which has high requirements for the hardware sampling rate and is not suitable for the application working condition of continuous switching of inverters. In addition, it is also possible to be based on V GP , and use dV DS / dt during the turn-on process of the SiC MOSFET as the gate oxide layer degradation parameter. However, it has not been verified online under the working conditions of the inverter.

[0045] It can be seen that whether it is possible to select the electrical parameter that is most conducive to online measurement from multiple electrical parameters and does not need to consider other influencing factors (such as the measurement result is simultaneously coupled with the temperature dependence, or new parasitic parameters are introduced during the measurement) will determine whether it is possible to conveniently and accurately estimate the degradation degree of the gate oxide layer of the SiC MOSFET.

[0046] <Method for optimizing electrical parameters>

[0047] To achieve the above objective, an embodiment of the present application provides a method for optimizing electrical parameters. Referring to Figure 2 , the optimization method includes the following steps:

[0048] Step 210: Combine the gate oxide layer degradation model of the SiC MOSFET and the I-V characteristics during the turn-off process to determine the relationship model between several electrical parameters and the degradation degree of the gate oxide layer of the SiC MOSFET during the turn-off process;

[0049] Step 220: Combine the relationship model and the actual working characteristics of the SiC inverter to determine several alternative electrical parameters. Among them, the alternative electrical parameters are caused by the parasitic parameters during the working process of the SiC inverter, and the parameter values change with the degradation of the gate oxide layer of the SiC MOSFET;

[0050] Step 230: Evaluate the online measurement difficulty of each alternative electrical parameter and its coupling degree with the temperature of the SiC MOSFET, and determine the optimized electrical parameter according to the evaluation result;

[0051] Step 240: Determine the mapped electrical parameters for joint measurement with the said preferred electrical parameters.

[0052] The implementation methods of each step will be described in detail below in combination with the accompanying drawings and specific embodiments.

[0053] <Mechanism Analysis of Electrical Parameter Changes Caused by Degradation of SiC MOSFET Gate Oxide Layer>

[0054] In step 210, expressions for the numerical values of various electrical parameters during the turn-off process of the SiC MOSFET are calculated through the gate oxide layer degradation model of the SiC MOSFET, thereby conducting a mechanism analysis of the relationship between multiple different electrical parameter values and the degradation degree of the SiC MOSFET gate oxide layer.

[0055] Figure 3 is a schematic diagram of the gate oxide layer degradation model of the SiC MOSFET, refer to Figure 3 , where the simplified structural diagram of the N-channel SiC MOSFET in part (a) is used to describe the internal structure of the SiC MOSFET, the interfacial trap phenomenon diagram after the degradation of the gate oxide layer in part (b) is used to describe the mechanism of gate oxide layer degradation, and part (c) shows the equivalent circuit of the SiC MOSFET. Figure 4 shows the I-V characteristics of the SiC MOSFET during the turn-off process obtained according to the above equivalent circuit diagram.

[0056] As Figure 3 shown in part (a), under the long-term action of high junction temperature and high electrical field stress, it will cause an increase in the defects at the SiC / SiO2 interface in the gate oxide layer. When the SiC MOSFET is conducting, the drain-source current I D The path is as shown by the blue arrow in part (a) of the figure. When the current path is close to the gate oxide layer interface, more electrons will be trapped here by the defects, thus generating Figure 3 The interfacial trap phenomenon shown in part (b) of, this phenomenon causes the cumulative charge density Nt at the SiC / SiO2 interface to increase.

[0057] The gate threshold voltage V TH of the SiC MOSFET satisfies equation (1). From equation (1), it can be seen that the degradation of the gate oxide layer will cause V TH to increase. Since the Miller plateau voltage V GP satisfies equation (2), taking the derivative of equation (2) and combining with the relationship between μ and Nt shown in equation (3), equation (4) can be obtained. From equation (4), it can be seen that the degradation of the gate oxide layer will cause V GP to increase.

[0058]

[0059] As Figure 4 shown, during the Miller plateau stage (t1 - t2) in the turn-off process of the SiC MOSFET, the drain-source voltage V DS gradually increases, and the gate-source voltage V GS is maintained at the Miller voltage V GP unchanged. The drive current I G is generated by the discharge of the gate-drain capacitance C GD , and I G satisfies Equation (5), where the variable t off with a subscript represents the time variable during the turn-off process of the SiC MOSFET. At this time, V GP can be obtained from Equation (6). Combining Equations (5) and (6), the rate of change of the drain-source voltage dV DS / dt as shown in Equation (7) can be obtained.

[0060] During the current decay period (t2 - t3), the drain-source current I D gradually decreases from the load current to 0, and the gate-source voltage V GS satisfies Equation (8), where C GS is the gate-source capacitance. In the actual operation of the SiC MOSFET, the current decay period is extremely short, and the time t - t2 can be treated as a constant B. Since the transconductance g m satisfies Equation (9), combining with Equation (8) shows that the rate of change of the drain-source current I D satisfies Equation (10). Combining Equations (3) and (4) shows that when I D is constant, if the gate oxide layer degrades and V GP and μ change, it will cause a change in dI D / dt during the turn-off process of the SiC MOSFET.

[0061]

[0062] V GP = V EE + I G R G (6),

[0063]

[0064] In this application, Equations (1) to (10) are called the relationship model between the electrical parameters of the SiC MOSFET and the degree of gate oxide layer degradation. By combining different equations among them, the relationship between the values of different electrical parameters and the degree of gate oxide layer degradation during the turn-off process of the SiC MOSFET can be obtained. For example, combining Equation (7) with Equations (2) and (4) shows that when I D is constant, if the gate oxide layer degrades, V GPAn increase will cause an increase in dV during the turn-off process of the SiC MOSFET DS / dt; for another example, by combining Equation (10) with Equations (3) and (4), it can be found that when the gate oxide layer degrades and V GP and μ change accordingly, it will cause a change in dI D / dt during the turn-off process of the SiC MOSFET.

[0065] <Determine alternative electrical parameters>

[0066] Step 220 is used to determine a number of alternative electrical parameters, and its determination steps are implemented by combining the relationship model obtained in the previous step with the actual working characteristics of the SiC inverter.

[0067] Specifically, referring to Figure 1 , during the operation of the SiC inverter, the high-speed switching of each SiC MOSFET will generate a large amount of heat, so heat dissipation needs to be carried out through a radiator, which will inevitably introduce various parasitic capacitances (C su , C sv , C sw , C sn , C sp ) and other parasitic parameters into the inverter circuit. During the operation of the SiC inverter, due to the existence of the above parasitic parameters, dV DS / dt and dI D / dt will generate multiple surges on the drain-source voltage V DS waveform during the turn-off process of each SiC MOSFET, thus forming multiple drain-source surge voltages. Next, combined with Figure 5 , taking the upper bridge of the SiC inverter as an example, the characteristics of each drain-source surge voltage are analyzed.

[0068] Figure 5 shows the drain-source voltage and PWM drive signals of the three SiC MOSFETs (Q1, Q3, Q5) on the upper bridge under the working state of the SiC inverter. Through Figure 5 it can be seen that during the turn-off process of each SiC MOSFET, three pulse-shaped surge voltages A, B, and C will be superimposed on the drain-source voltage.

[0069] Among them, for the SiC MOSFET on each bridge arm (such as Q1), when its switching state remains unchanged and the SiC MOSFETs on other bridge arms (such as Q3, Q5) are in the turn-off process, the dV DS / dt generated by the turn-off generates a surge current through the output capacitance, and the surge current flows through the parasitic capacitance path, causing surge voltages A and B to be generated on the drain-source voltage of the bridge arm SiC MOSFET.

[0070] For example,Figure 6 An equivalent circuit when a surge voltage A is generated on the drain-source voltage of Q1 due to the turn-off of Q5 is shown, where the current path is as Figure 6 shown by the red arrow in, and the specific value V of the surge voltage A surge_A can be obtained by the following equations (11) to (15):

[0071]

[0072] V surge_A = I surge_A × R on (15).

[0073] The mechanism of the surge voltage B superimposed on the drain-source voltage of Q1 during the turn-off process of Q3, and the derivation process of its specific value V surge_B is similar to that of the surge voltage A.

[0074] The generation mechanism of the surge voltage C is different from that of the surge voltages A and B. Specifically, refer to Figure 7 the equivalent circuit diagram when the surge voltage C is generated by Q1 as shown. During the turn-off of Q1, the I D current becomes 0. At this time, the specific value V of the surge voltage C surge_C satisfies equation (16):

[0075]

[0076] The surge voltage C is caused by the change in the switching state of Q1 itself, and the generated dI D / dt is caused by the parasitic inductance.

[0077] It can be seen that for each SiC MOSFET in the upper bridge arm, within each switching cycle, a surge voltage (surge voltage C) caused by its own turn-off process is superimposed on the drain-source voltage waveform, as well as the surge voltages (surge voltage A and surge voltage B) caused by the turn-off processes of the other two SiC MOSFETs in the same upper bridge arm.

[0078] The above analysis is carried out taking each SiC MOSFET in the upper bridge arm as an example. Similarly, for the lower bridge arm, a surge voltage caused by its own turn-off process is also superimposed on the drain-source voltage waveform of each SiC MOSFET (such as Q2), as well as the surge voltages caused by the turn-off processes of the other two SiC MOSFETs (such as Q4 and Q6) in the same lower bridge arm.

[0079] In the embodiments of the present application, the alternative electrical parameters of each SiC MOSFET include V surge_A , V surge_B and V surge_C .

[0080] <Evaluate and optimize the electrical parameters suitable for on-line measurement>

[0081] Step 230 is used to evaluate the processing difficulty of each alternative electrical parameter. Specifically, at least the following factors need to be considered during the evaluation:

[0082] Consideration factor 1: The difficulty of on-line measurement of each alternative electrical parameter of the SiC MOSFET during the operation of the SiC inverter.

[0083] First, since the SiC inverter needs to meet the requirement of long-term stable operation, whether it is measured under actual working conditions or under the working conditions of its aging experiment, it needs to be carried out without affecting its normal operation. If the on-line measurement of the SiC MOSFET generates new parasitic parameters in the SiC inverter circuit, it will not only reduce the credibility of the measurement results, but also require additional correction processing measures and may affect the normal working state of the inverter.

[0084] Second, since the surge voltage is superimposed on the original drain-source voltage waveform of each SiC MOSFET, the difficulty of on-line measurement also needs to be considered from the perspective of whether it is convenient to extract the effective information in the signal. From Figure 5 It can be seen that the amplitudes of surge voltage A and surge voltage B are not only smaller than that of surge voltage C, but also their positions relative to the turn-off moment are uncertain. Therefore, in some cases, surge voltage A and surge voltage B will be superimposed on the drain-source voltage waveform in the on-state, which will undoubtedly increase the processing steps for judging the signal acquisition moment. And if the turn-off moments of each SiC MOSFET are relatively close during the PWM modulation process, the waveforms of surge voltage A and surge voltage B may also be mixed with the rising waveform of the drain-source voltage, and further separation of the effective information of the collected signal is required, which will undoubtedly increase the difficulty of on-line measurement.

[0085] Consideration factor 2: The coupling degree between each alternative electrical parameter and the temperature of the SiC MOSFET.

[0086] If the on-line measurement result of the electrical parameter is not affected by the temperature change of the SiC MOSFET and only reflects the change of the electrical parameter value caused by the degradation of the gate oxide layer, it will undoubtedly improve the credibility of the measurement result and greatly simplify the subsequent data processing operation.

[0087] In step 230, based on the above considerations, the on-line measurement difficulties of surge voltage A, surge voltage B and surge voltage C are evaluated respectively, and the following conclusions can be obtained:

[0088] The surge voltage C is generated during the self-turn-off process of each SiC MOSFET. Its occurrence time is deterministic. Since the generation position of this surge voltage is exactly on the rising step waveform of the drain-source voltage, after being superimposed on the drain-source voltage, it has the highest amplitude on the drain-source voltage waveform.

[0089] In addition, from the expression of the surge voltage V surge_C , it can be seen that the value of V surge_C is related to the parasitic inductance L1 and dI D / dt. Since the parasitic inductance L1 is independent of temperature and the aging degree of the gate oxide layer, it does not change during the long-term operation of the SiC inverter. The value of V surge_C will be determined by dI D / dt. Through the previous analysis, it can be seen that with the degradation of the gate oxide layer, the changes in V GP and μ will cause the change of dI D / dt during the turn-off process of the SiC MOSFET. Therefore, the change of V surge_C can reflect the aging degree of the gate oxide layer.

[0090] At the same time, from equations (2) and (10), it can be seen that the magnitude of dI D / dt also depends on the stable value I D_on of the drain-source current before the SiC MOSFET turns off. For inverters under different working conditions, the steady-state I D_on is different. Obviously, this will make the SiC MOSFET with the same degree of gate oxide layer degradation have different V surge_C under different working conditions of the SiC inverter. Therefore, when estimating the degradation degree of the gate oxide layer of a SiC MOSFET, it is also necessary to measure an electrical parameter related to the specific working condition at the same time, and use this electrical parameter to "map" the measured value of the electrical parameter characterizing the gate oxide layer degradation to the matching specific working condition. In the embodiments of the present application, this electrical parameter used for mapping is called the mapping electrical parameter. For example, when choosing V surge_C as the electrical parameter characterizing the degradation degree of the gate oxide layer, it is necessary to pre-calibrate the V D_on values (which can be expressed as V surge_C ) of the non-degraded SiC MOSFET under different working conditions (i.e., different I surge_C_fresh ), so as to establish the I D_on ~V surge_C_fresh fitting function or fitting curve, and then use the measured I D_on during on-line measurement to map to the plane where the curve is located, and the V surge_C value (which can be expressed as V surge_C_real ) measured under the working condition during on-line measurement can be evaluated and compared with the corresponding V surge_C_freshThe deviation between values is used to estimate the degradation degree of the gate oxide layer.

[0091] The same evaluation method can be used to analyze the measurement difficulty of surge voltage A and surge voltage B. Taking surge voltage A as an example, it can be seen from equations (14) and (15) that the value of surge voltage A is related to parasitic inductances L1 and L5, parasitic capacitances C SW , C SU , on-state resistance R on and V DS . Among the above variables, only R on is affected by the degradation of the gate oxide layer. However, R on varies with the junction temperature. Therefore, if the aging of the gate oxide layer is judged by V surge_A , the junction temperature also needs to be known. Since the acquisition methods of the junction temperature and R on during the operation of the SiC inverter are complex, using V surge_A as the electrical parameter to be measured undoubtedly increases the measurement complexity.

[0092] In addition, when the operating conditions of the inverter change, the change in the duty cycle will cause V surge_A to be superimposed on different voltages. As shown in the above text and Figure 5 , the V surge_A of Q1 is superimposed on the on-state voltage V on , and the V surge_A of Q3 and Q5 is superimposed on the DC bus voltage V BUS . Obviously, this inconsistency will also cause difficulties in the design of the acquisition circuit for V surge_A .

[0093] The evaluation process and method for the measurement difficulty of V surge_B are the same as those for V surge_A , and will not be elaborated here.

[0094] In fact, in each switching cycle of the SiC MOSFET, as Figure 5 shown, in addition to the three surge voltages generated during the turn-off process, three surge voltages also appear during the turn-on process. Since the surge voltages accompanying the turn-on process are superimposed on the conduction voltage V on , the difficulty of measuring it is greater than that of V surge_A and V surge_B . Therefore, the possibility of taking it as the preferred electrical parameter can be directly excluded.

[0095] In some preferred embodiments of the present application, through the above evaluation steps, it can be determined that the surge voltage V surge_C caused by the turn-off process of each SiCMOSFET itself is used as the preferred electrical parameter. It can be seen from the above analysis that V surge_C has at least the following characteristics:

[0096] 1) For each SiC MOSFET, the surge voltage V caused by its own turn-off process surge_C is superimposed on its drain-source voltage V DS and has the highest amplitude on the waveform of its drain-source voltage V DS .

[0097] 2) For each SiC MOSFET, the amplitude of the surge voltage V caused by its own turn-off process surge_C is related to the degradation degree of its gate oxide layer (reflected in dI D / dt) and is independent of its temperature.

[0098] 3) For each SiC MOSFET, the amplitude of the surge voltage V caused by its own turn-off process surge_C is related to the original parasitic parameters of the arm it is in, and the original parasitic parameters of the arm it is in are independent of its temperature (for example, for Q1, its V surge_C is related to the parasitic inductance L1, and L1 is independent of the temperature of Q1).

[0099] <Determine the mapped electrical parameters for combined measurement>

[0100] It can also be known from the above analysis that to accurately estimate the degradation degree of the gate oxide layer of SiC MOSFETs, it is necessary to jointly measure the mapped electrical parameters while measuring the preferred electrical parameters. Therefore, after determining the preferred electrical parameters for on-line measurement, it is also necessary to perform step 240 to determine the mapped electrical parameters that need to be jointly measured on-line with the preferred electrical parameters.

[0101] The specific meaning and function of the mapped electrical parameters have been given above. Obviously, the measurement of the mapped electrical parameters should also be convenient for measurement and should not introduce new influencing factors during the measurement process. In some preferred embodiments, when determining the V of each SiC MOSFET surge_C as the preferred electrical parameter, it can be further determined that the stable value I of the drain-source current before turn-off of each SiC MOSFET D_on is used as the mapped electrical parameter. In fact, since the conduction current itself is used to provide real-time feedback for the control system during the closed-loop feedback control process of the inverter, the on-line measurement method of this parameter value already belongs to the techniques well-known to those skilled in the art.

[0102] <On-line measurement of electrical parameters>

[0103] Some embodiments of the present application also provide a method for measuring electrical parameters, which is used to perform on-line measurement of the measured electrical parameters of the measured SiC MOSFET in the SiC inverter during the operation of the SiC inverter. Among them, the measured electrical parameters are linearly related to the preferred electrical parameters determined by the foregoing preferred method, that is, there is a linear proportional relationship between the two.

[0104] The on-line measurement of the measured electrical parameters can be carried out by connecting a measurement circuit during the operation of the SiC inverter. Preferably, the connection method of the measurement circuit is set so as not to introduce new parasitic parameters during the measurement of the measured electrical parameters.

[0105] Figure 8 The embodiment shown provides a measurement circuit 4 that uses an electrical parameter capable of reflecting the surge voltage V surge_C of the SiC MOSFET as the measured electrical parameter and performs on-line measurement on it. Among them, the SiC MOSFET Q1 on the upper bridge arm in the bridge arm circuit 3 is the measured SiC MOSFET. During the measurement of its V surge_C , the SiC inverter where the bridge arm circuit 3 is located is in a normal working state.

[0106] As Figure 8 shown, the measurement circuit 4 includes a waveform extraction circuit 410 and an envelope extraction circuit 420. Among them, the waveform extraction circuit 410 is used to extract the voltage V S across the parasitic inductance L S between the power source pin S and the Kelvin source pin S' of the measured SiC MOSFET, and perform voltage division output on it.

[0107] According to the previous analysis, the V surge_C signal is superimposed on the bus voltage V BUS , and the amplitude of V BUS is large. V BUS has nothing to do with the degradation of the gate oxide layer. The signal of V BUS is directly measured. Due to the change of V surge_C , the change of V BUS is not significant, that is, V BUS is not sensitive to the change of V surge_C . For the above reasons, in the present application, the waveform extraction circuit 410 reflects the waveform characteristics of V S by collecting the waveform of the voltage difference caused by the parasitic inductance L surge_C between the Kelvin source and the power source of the SiC MOSFET, making it more suitable for on-line measurement. The mechanism is as follows:

[0108] Figure 9 is a schematic diagram of the appearance of a specifically packaged SiC MOSFET using the 4-pin method.Figure 10 The equivalent circuit diagram for driving the SiC MOSFET is shown in the figure. The SiC MOSFET has 4 leads, including the gate (G), the drain (D), and two leads related to the source. Among them, the S pole is called the power source pole and is connected to the power circuit. The S' pole is called the Kelvin source pole. During the operation of the SiC inverter, by connecting it to the drive circuit, the drive circuit and the main power circuit can be decoupled, avoiding the drive circuit from being disturbed by the power circuit, so that the gate can correctly sense the drive voltage.

[0109] There is a parasitic inductance L between the S pole and the S' pole S , as can be seen from equation (17), L S The voltage across both ends is proportional to dI D / dt. Combining with equation (16), the relationship between Vs and V surge_C as shown in equation (18) can be obtained:

[0110]

[0111] It can be seen that V surge_C and V S are in a linear proportional relationship. By monitoring the change of V S , the change information of V surge_C can be equivalently obtained. Therefore, V S or the divided voltage of V S can be regarded as V surge_C .

[0112] Specifically, as Figure 8 shown, in the waveform extraction circuit 410, the series-connected resistors R1 and R2 are used for voltage division. The first end of R1 is connected to the power source pole S, the second end of R1 is connected to the first end of R2, and this connection point serves as the output end of the waveform extraction circuit 410. The second end of R2 is connected to the Kelvin source pole S' and is electrically connected to the ground terminal.

[0113] Preferably, the resistance value of R2 is greater than or equal to twice the resistance value of R1. For example, in a specific embodiment, the value of R1 is 1 kΩ and the value of R2 is 470 Ω.

[0114] The voltage waveform after Vs is divided passes through the output end of the waveform extraction circuit 410 and enters the envelope extraction circuit 420. The envelope extraction circuit 420 extracts the peak value of its envelope line and outputs it as V out .

[0115] The reason for extracting the peak value by obtaining the envelope line can be seen from the previous analysis. When the switching state of the inverter changes, V surge_A and V surge_B will also be superimposed on V BUSAbove, from Figure 5 It can be seen that for each SiC MOSFET, its V surge_C is greater than V surge_A and I surge_B . Therefore, by extracting the envelope, the peak information can be retained while excluding the influence of V surge_A and V surge_B . In addition to the above advantages, in an actual inverter, the dI D / dt of the SiC MOSFET is about 5 A / ns, and the change rate of the V surge_C signal is approximately the same as it. Therefore, the output envelope waveform can also effectively reduce the requirement for the ADC sampling rate and reduce the hardware cost.

[0116] Specifically, the envelope extraction circuit 420 includes two operational amplifiers U1, U2, two switching devices q1, q2, a capacitor C E , and resistors R3 to R8. Their connection relationship and the power supply methods of the positive power supply V CC and the negative power supply -V CC are as shown in Figure 8 . Among them, the specific values of V CC and -V CC can be determined according to the positive and negative withstand voltage limits of the operational amplifier. For example, select positive and negative power supplies of ±5V or ±3.3V.

[0117] Figure 11 shows a schematic diagram of the waveform signal of V surge_C and the envelope of V surge_C output by the envelope extraction circuit 420. The working principle of the envelope extraction circuit 420 is described below in combination with Figure 8 and Figure 11 :

[0118] During the rapid rise stage of V surge_C , the Vs after voltage division (as analyzed before, it can be considered that this voltage signal is equivalent to V surge_C ) enters the positive input terminal of the operational amplifier U1, is compared with -V CC , and then outputs. The output voltage signal will simultaneously control q1 and q2 to maintain a continuous on state, so that the capacitor C E is charged until it reaches the peak of V surge_C . At the same time, the V out output by the operational amplifier U2 rapidly rises to the peak of V surge_C ;

[0119] When V surge_C starts to decline after passing through its peak point, the voltage signal output by the operational amplifier U1 is reversed, and q1 and q2 are turned off. After that, the capacitor C EEnter the discharge state. During this process, since other surge voltages A, B, etc. cannot exceed the potential of capacitor C E , the V output by operational amplifier U2 out slowly decreases until the surge voltage C in the next cycle triggers q1 and q2 to conduct again.

[0120] The V output by U2 out can be subjected to analog-to-digital conversion using an AD converter that meets the sampling rate speed and accuracy requirements, and then further digital signal processing operations can be performed. Through Figure 11 It can be seen that by outputting a signal in the form of an envelope, while retaining the peak value of the surge voltage C, it can effectively filter out the voltage fluctuations caused by other surge voltages, and effectively reduce the accuracy requirements for AD conversion and data processing. In some specific embodiments, for example, AD9248 can be used as the AD converter, with a measurement range of ±12V and an accuracy higher than 5mV.

[0121] In some preferred embodiments, q1 and q2 are NPN bipolar junction transistors BJT, thereby improving the response speed of the circuit.

[0122] The bandwidth and slew rate of operational amplifiers U1 and U2 have an important impact on the extraction accuracy of the envelope. Their slew rate and bandwidth calculations satisfy Equation (19):

[0123]

[0124] Among them, SR is the slew rate of the operational amplifier, V m is the maximum output voltage of the operational amplifier, and f max is the maximum operating frequency of the circuit. Since the switching speed of SiC MOSFET is about 5A / ns, under inverter conditions, the switching duration of SiC MOSFET is about 30ns. Therefore, f max needs to be not less than 100Mhz. In order to make full use of the ADC accuracy and not exceed the ADC measurement range, V m is taken as 5V. After calculation, SR is at least 3.14V / ns. For example, in some limited embodiments, the models of U1 and U2 are LM7171, with a bandwidth of 200Mhz and a slew rate of 4.1V / ns.

[0125] According to Figure 11 and the above analysis, the action time of the surge voltage V surge_C can be divided into the charging interval and the discharging interval of C E . The charging interval is generally relatively short, much shorter than the switching process of SiC MOSFET. The duration of the discharging interval is related to the values of R3 and C E . Since the values of R3 and C[[ID=*43]] E satisfy Equation (20):

[0126]

[0127] where f sw is the switching frequency of the SiC MOSFET, and K is the discharge coefficient. Therefore, by adjusting the values of R3 and C E , it is ensured that the voltage of C surge_C does not drop too much between two V E peaks. In a specific embodiment, the switching frequency of the SiC inverter is 20Khz, the value of K is 5, the value of R3 is 47k, and the value of C E is 10nF. In other embodiments, the parameter values of the above-mentioned various devices can also be reasonably set according to the specific parameters of the SiC MOSFET to be measured.

[0128] Similarly, although Figure 8 the optional resistance values of resistors R4 to R8 are given in the illustrated embodiment, in other embodiments, the resistance values of the above-mentioned various resistors can also be adjusted according to specific measurement requirements.

[0129] <Estimating the Degradation of the Gate Oxide Layer of SiC MOSFET Based on Online Measurement Results>

[0130] Some embodiments of the present application also provide a method for estimating the degradation of the gate oxide layer of a SiC MOSFET, and the method includes the following operations:

[0131] Based on the online measurement results of the measured electrical parameters and mapped electrical parameters of the SiC MOSFET to be measured during the operation of the SiC inverter, estimate the degradation of the SiC MOSFET to be measured.

[0132] Among them, the online measurement of the measured electrical parameters can be carried out by the aforementioned electrical parameter measurement method. The specific steps of the measurement method and the specific implementation manner of the measurement circuit involved have been described in detail above and will not be elaborated here.

[0133] In some preferred embodiments, estimating the degradation of the SiC MOSFET to be measured based on the online measurement results can be achieved through the following steps:

[0134] Based on the deviation between the online measurement results of the measured electrical parameters and mapped electrical parameters of the SiC MOSFET to be measured and the fitting curve of the preferred electrical parameters and mapped electrical parameters of the same type and non-degraded SiC MOSFET established in advance, evaluate the degradation of the gate oxide layer of the SiC MOSFET to be measured.

[0135] The above estimation process will be described in detail below in conjunction with specific embodiments.

[0136] According to the previous analysis, when selecting V surge_C and I D_on as the measured electrical parameter and the mapped electrical parameter respectively, due to the degradation of the gate oxide layer, the same I D_on will cause a change in V surge_C . In addition, since I D_on is also different under different inverter operating conditions, V surge_C will also change. Therefore, it is necessary to first obtain the optimal electrical parameters (which can be defined as V surge_C_fresh ) and the mapped electrical parameter I D_on of the non-degraded SiC MOSFET of the same model, and obtain the fitting curve V surge_C_fresh = f(I D ). Then, according to the measured value of I D_on during on-line measurement, the measured value of V D_on (which can be defined as V surge_C ) under the operating condition of the same I D_on and the deviation of V surge_C_real surge_C_fresh can be obtained. According to the deviation, the degradation degree of the gate oxide layer can be accurately evaluated.

[0137] Figure 12 shows the circuit schematic diagram of the experimental system for off-line measurement of V surge_C_fresh and I D_on of the non-degraded SiC MOSFET. As shown in Figure 12 , the experimental system includes the measurement circuit described above, which is used to off-line collect V surge_C_fresh . The current probe is used to measure and output I D . The acquisition module acquires the V surge_C_fresh output by the measurement circuit and the I D_on output by the current probe.

[0138] The experimental principle of this experimental system is similar to the double-pulse test. Among them, both the SiC MOSFET Q and the SiC MOSFET used for calibration (denoted as DUT in the figure) are fresh MOSFETs. V1 is a constant voltage source with a voltage of 4V, which is used to keep Q normally closed. L is the load inductor, and the preferred value is 100uH. Driver is used to drive the turn-on and turn-off of the DUT. The voltage of V BUS is preferably set to 300V.

[0139] During the experiment, the controller is used to control Driver to generate N gate pulses with a high-level time of t high and a low-level time of t low . Based on Equation (21), each gate pulse will cause a successive increase in the current I D :

[0140]

[0141] By performing N groups of measurements continuously, different values of I can be obtained. D The corresponding V surge_C_fresh value. Figure 13 The figure shows the fitting curve obtained from the above experiment on an undegraded SiC MOSFET. After obtaining the V and I of a SiC MOSFET of the same model in subsequent on-line measurements, the V value corresponding to the same I can be compared with the V value, so as to obtain the evaluation result of the aging degree of the gate oxide layer. surge_C_real 、I D_on After that, the V value corresponding to the same I D_on can be compared with the V surge_C_fresh value, so as to obtain the evaluation result of the aging degree of the gate oxide layer. surge_C_real value, thereby obtaining the evaluation result of the aging degree of the gate oxide layer.

[0142] To verify the effectiveness of the estimation method, in a specific embodiment, a degradation experiment platform with a three-phase six-bridge-arm power topology structure as the core was built to simulate the actual SiC inverter working condition and estimate the degradation degree of the gate oxide layer of the SiC MOSFET in it. The specific parameter settings of the degradation experiment platform are shown in Table 2. During the degradation experiment, the drain voltage V, phase current I, drain current I, and surge voltage V of the DUT were collected through an oscilloscope. The waveform diagram obtained from the degradation experiment is as shown. At the target Q-axis current, the phase current is stable, there is a surge phenomenon in the phase voltage, the peak envelope extraction value is stable, and V increases with the increase of the absolute value of the drain current, which is consistent with the previous analysis and meets the expectation. DS ,phase current I A ,drain current I D and surge voltage V surge_C ,The waveform diagram obtained from the degradation experiment is as Figure 14 shown. At the target Q-axis current, the phase current is stable, there is a surge phenomenon in the phase voltage, the peak envelope extraction value is stable, and V surge_C increases with the increase of the absolute value of the drain current, which is consistent with the previous analysis and meets the expectation.

[0143] Table 2

[0144] Experimental setup parameters Value Switching frequency 20Khz Q-axis target current 23A LOAD SIC MOSFET Cree C3M0016120K LOAD L 200uL V mcu 300V V motor 300V NI FPGA PXIe-7822

[0145] Experiments were carried out on healthy and aged SiC MOSFETs respectively. At the operating point where I is 19.6 A, a comparison and degradation degree estimation were made with the V obtained by substituting V = f(I). D_on At the operating point where I is 19.6 A, a comparison and degradation degree estimation were made with the V obtained by substituting V = f(I). surge_C_fresh =f(I D ) obtained V surge_C_fresh value.

[0146] Figure 15 The degradation experiment results of a certain healthy SiC MOSFET are shown. The results show that when I D_on =19.6 A, the measured V surge_C_Healthy value of this SiC MOSFET and the V D_on value at the same I surge_C_freshThe difference is 35 mV. This difference is within a relatively healthy range, and it can be considered that the health state of its gate oxide layer has not changed, belonging to a healthy SiCMOSFET.

[0147] Figure 16 shows the degradation experimental results of a certain aged SiC MOSFET. The results show that at I D_on = 19.6 A, the difference between its V surge_C_Aged value and V surge_C_fresh is 92 mV, which has exceeded the allowable healthy range. It can be considered that the health state of its gate oxide layer has changed significantly, and this SiC MOSFET is an aged SiC MOSFET.

[0148] The specific embodiments of the present application have been introduced in detail above. For those skilled in the art of this technology, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for optimizing electrical parameters, characterized in that, It includes the following steps: Combining the gate oxide layer degradation model of the SiC MOSFET and the I-V characteristics during the turn-off process, determine the relationship model between several electrical parameters and the degree of gate oxide layer degradation of the SiC MOSFET during the turn-off process; Combining the relationship model and the actual working characteristics of the SiC inverter, determine several alternative electrical parameters, where the alternative electrical parameters are caused by parasitic parameters during the operation of the SiC inverter, and the parameter values change with the degradation of the gate oxide layer of the SiC MOSFET; Based on the equivalent circuit models of the alternative electrical parameters, evaluate the on-line measurement difficulty of each alternative electrical parameter and its coupling degree with the SiC MOSFET temperature, and determine the preferred electrical parameter according to the evaluation results; Determine the mapped electrical parameter for joint measurement with the preferred electrical parameter.

2. The preferred method of the electrical parameters according to claim 1, characterized in that, The relationship model is at least used to characterize the relationship between the following electrical parameters and the degree of degradation of their gate oxide layers during the turn-off process of the SiC MOSET: Miller voltage V GP , drain-source voltage V DS and its rate of change with time dV DS / dt, drain-source current I D and its rate of change with time dI D / dt.

3. The preferred method for electrical parameters according to claim 1, characterized in that The gate oxide layer degradation model of the SiC MOSFET is used to describe the internal structure, gate oxide layer degradation mechanism and equivalent circuit of the SiC MOSFET.

4. The preferred method for electrical parameters according to claim 1, characterized in that, The actual working characteristics of the SiC inverter include: During the operation of the SiC inverter, the drain-source voltage surge phenomenon caused by the turn-off process of each SiC MOSFET.

5. The preferred method for electrical parameters according to claim 4, characterized in that For each SiC MOSFET in the upper bridge arm, the several alternative electrical parameters include the surge voltage caused by its own turn-off process and the surge voltages caused by the turn-off processes of the other two SiC MOSFETs in the same upper bridge arm; For each SiC MOSFET in the lower bridge arm, the several alternative electrical parameters include the surge voltage caused by its own turn-off process and the surge voltages caused by the turn-off processes of the other two SiC MOSFETs in the same lower bridge arm.

6. The preferred method for electrical parameters according to claim 5, characterized in that The preferred electrical parameter is the surge voltage caused by the turn-off process of the SiC MOSFET itself.

7. The preferred method for electrical parameters according to claim 6, characterized in that For each SiC MOSFET, after the surge voltage caused by its own turn-off process is superimposed on its drain-source voltage, it has the highest amplitude on the drain-source voltage waveform.

8. The preferred method for electrical parameters according to claim 6, characterized in that For each SiC MOSFET, the amplitude of the surge voltage caused by its own turn-off process is related to the degree of degradation of its gate oxide layer and has nothing to do with its temperature.

9. The preferred method for electrical parameters according to claim 6, characterized in that For each SiC MOSFET, the amplitude of the surge voltage caused by its own turn-off process is related to the original parasitic parameters of the arm it is in, and the original parasitic parameters of the arm it is in are independent of its temperature.

10. The preferred method for electrical parameters according to any one of claims 6 to 9, characterized in that The mapped electrical parameter is the stable value of the drain-source current before the SiC MOSFET is turned off.

11. A method for measuring electrical parameters, used for on-line measurement of the electrical parameters to be measured of the SiC MOSFET to be measured during the operation of the SiC inverter, characterized in that The electrical parameter to be measured is linearly related to the preferred electrical parameter determined by the method according to claim 1.

12. The method for measuring the electrical parameter according to claim 11, characterized in that, Including the following operations: The on-line measurement of the electrical parameter to be measured is carried out by accessing a measurement circuit during the operation of the SiC inverter, and the access mode of the measurement circuit is set so as not to introduce new parasitic parameters during the measurement of the electrical parameter to be measured.

13. A method for estimating the degradation of the gate oxide layer of a SiC MOSFET, characterized in that, Including the following operations: Based on the results of on-line measurement of the electrical parameter to be measured and the mapped electrical parameter of the SiC MOSFET to be measured during the operation of the SiC inverter, estimate the degradation of the SiC MOSFET to be measured, wherein the on-line measurement of the electrical parameter to be measured is carried out by the method for measuring electrical parameters according to claim 11.

14. The estimation method for the degradation of the gate oxide layer of the SiC MOSFET according to claim 13, wherein The estimation of the degradation of the SiC MOSFET to be measured includes: Based on the deviation between the on-line measurement results of the electrical parameter to be measured and the mapped electrical parameter of the SiC MOSFET to be measured and the fitting curve of the preferred electrical parameter and the mapped electrical parameter of the same type and non-degraded SiC MOSFET established in advance, evaluate the degradation of the gate oxide layer of the SiC MOSFET to be measured.

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