Method and device for testing aliasing chips

Abstract

The invention belongs to the technical field of integrated circuit testing, and particularly relates to an aliasing chip testing method and device. Comprising the steps of generating a chip device defect and failure model classification matrix by constructing a chip internal component model; burning the test vector to a chip test device; performing function and performance parameter testing on the 2.5 D / 3D aliasing chip according to the related information of the chip device defect and failure model classification matrix and the firmware program of the test vector; by constructing the mass production failure early warning model, the yield of the multi-layer aliasing chip is improved. According to the test method, the function and electrical performance parameter test of the multi-layer aliasing chip is realized, the function and parameter verification of the chip is realized, the interconnection fault between the internal components of the chip can be detected, and the yield of the chip is improved by feeding back an engineer according to mass production data.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit testing, and particularly relates to a 2.5D / 3D hybrid chip testing method and testing device based on integrated information processing of navigation, control, and computing, which is applicable to functional verification, electrical performance testing, and mass production yield optimization of such hybrid chips. Background Art

[0002] With the development of integrated circuit testing, the 3D-SiP technology can no longer meet the current application requirements. For example, the invention application with patent application number CN201910024235.7 discloses a testing method for a multi-layer stacked 3D-SIP chip, which proposes a testing method for a multi-layer stacked 3D-SIP chip. By obtaining a fault code custom table and loading a test program into the chip testing device, and then performing functional testing on the multi-layer integrated circuit chip through the fault code custom table in combination with the test program. However, the above technical solution has at least the following problems when in use: The technology process is simple, the internal stacked chips are simple, and it can only analyze simple SIP circuits, and cannot perform functional and parameter test verification on 2.5D / 3D hybrid chips and internal chips.

[0003] Chips based on 2.5D / 3D hybrid technology and using integrated information processing of navigation, control, and computing have emerged. The highly complex integrated chips lead to an increase in testing time and cost. At the same time, the new process also has many uncertain performance manifestations. This also further increases the testing difficulty.

[0004] Therefore, how to provide a 2.5D / 3D hybrid chip testing method based on integrated information processing of navigation, control, and computing has become an urgent technical problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a 2.5D / 3D hybrid chip testing method and testing device based on integrated information processing of navigation, control, and computing. The testing method of the present invention realizes functional and electrical performance parameter testing of multi-layer hybrid chips. This method not only realizes the verification of chip functions and parameters, but also can detect the interconnection faults between internal components of the chip, and feedback to engineers according to mass production data so as to improve the chip yield. This makes the present invention have a wider applicability.

[0006] To solve the above technical problems, the present invention provides a 2.5D / 3D hybrid chip testing method based on integrated information processing of navigation, control, and computing, including: By constructing an internal component model of the chip, generating a classification matrix of chip device defects and failure models; and burning test vectors into the chip testing device; Perform functional and performance parameter tests on the 2.5D / 3D hybrid chip according to the relevant information of the chip device defect and failure model classification matrix and the firmware program of the test vector; that is, obtain the binary classification information of the chip failure model classification matrix through the FPGA port of the 2.5D / 3D hybrid chip, so as to determine whether there are problems with the functional and performance parameters of the 2.5D / 3D hybrid chip; Build a mass production failure warning model to improve the yield of multi-layer hybrid chips.

[0007] Preferably, the building of the internal component model of the chip, that is, building an internal model of the chip composed of an FPGA component, a DSP component, a CIB die module, and an AI module; where the FPGA component is integrated with an FPGA, a FLASH, and a DDR3; the DSP component is integrated with a DSP, a NorFLASH, and a DDR3.

[0008] Preferably, the burning of the test vector to the chip test device, that is, starting the ARM and FPGA projects to the test device for detecting chip defects; including: preloading the FPGA test program, preloading the DSP test program, preloading the CIB test program, and preloading the AI test program to achieve parallel initialization of multi-core test resources.

[0009] Preferably, the functional and electrical performance parameter tests on the 2.5D / 3D hybrid chip include: FPGA component functional test, including FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, and GTH high-speed self-test; FPGA component performance test, that is, output port drive voltage test; CIB functional test, that is, SRIO / SPI / NAND FLASH / PCIe interface functional test; AI functional test, that is, computing power test; DSP component functional test, including floating-point test, EMIF test, and GMAC test; Internal component interconnection and communication test, including DSP and CIB communication, FPGA and CIB communication, and FPGA and DSP communication tests.

[0010] Preferably, the building of the mass production failure warning model includes: Transfer the data of the chip to be tested to the host computer to obtain the current failure data, and compare it with the standard data to determine whether the parameters of the current chip to be tested deviate from the normal range; Record the corresponding failure number F[i] according to the chip device defect and failure model classification matrix, and then build a mass production failure warning model on the host computer; When the ratio of the failure number F[i] to the total number of current tests F is greater than 5%, according to the national standard 548C / 2021, the host computer starts to execute the warning operation; the current failure numbers F[i] are counted, and if the ratio of other failure numbers F[i] to the current failure number F[i] is greater than 95%, it will also be displayed on the host computer; When the host computer is in the warning state, the current failure number F[i] will be displayed on the LED display board of the ARM board. The chip testing device is powered off when it is not operated for a long time. After the engineer confirms the warning state, the total number of tests F is reset passively. At the same time, all the failure comparison information stored in the failure number F[i] is discarded after the chip testing device is powered on, so as to transform into a new mass production failure warning model to meet the subsequent test failure analysis.

[0011] Preferably, the fault state definition of each test in the chip device defect and failure model classification matrix ranges from 10000001 to 10010011 in sequence, and 11111111 means the test passes; 0XXXXXX means the test is in progress, where X represents an uncertain state, and X is 1 or 0.

[0012] The present invention also provides a 2.5D / 3D aliasing chip testing device based on integrated information processing of navigation, control and calculation, which executes a 2.5D / 3D aliasing chip testing method based on integrated information processing of navigation, control and calculation as described above, including: Host computer; Multifunctional integrated processing device, connected to the host computer; Power adapter; Clock adapter; Test chip test board, communicatively connected to the power adapter, the clock adapter and the multifunctional integrated processing device respectively; wherein the test chip test board is used for fixing the test chip and powering on the test chip. The test chip test board is composed of various circuit design hardware, and can complete the test of the test chip under the instruction of the host computer and display the test results on the multifunctional integrated processing device in real time.

[0013] Preferably, before the test program is imported, the construction of the test device needs to be completed, that is: during the test, the power adapter has multiple voltage stabilizing chips built in. After power on, the host computer sends a start instruction to the multifunctional integrated processing device. The multifunctional integrated processing device processes sequentially according to the relevant information of the chip device defect and failure model classification matrix, and tests the functions and performance parameters of the aliasing chip. Finally, the information corresponding to the chip device defect and failure model classification matrix is fed back to the host computer to judge whether the chip is normal, and then the power adapter is powered off and the test ends.

[0014] Preferably, the multifunctional integrated processing device includes: an LED display board, an electronic load, an FPGA hardware board, a CPU hardware board, and an ARM hardware board; the ARM hardware board monitors the tests of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back the port status to the LED display board for displaying the chip device defect and failure model classification matrix information; Among them, the FPGA hardware board is connected to the circuit board of the chip under test through an FPGA interface, and is used for aliasing the function and performance tests of the FPGA components of the chip, the function tests of the DSP components, and the internal component interconnection communication tests; The CPU hardware board is connected to the circuit board of the chip under test through a CPU interface, and is used for aliasing the CIB and AI function tests of the chip; The ARM hardware board is connected to the circuit board of the chip under test through an ARM interface, and is used for aliasing the function tests of the DSP components of the chip; The power adapter is built with a voltage stabilizing chip and is connected to the circuit board of the chip under test for powering on and off the chip; The clock adapter is built with multiple active clocks and is connected to the circuit board of the chip under test for providing a reference clock signal; The FPGA hardware board includes an FPGA processor; the CPU hardware board includes a CPU processor; the ARM hardware board includes an ARM processor.

[0015] Preferably, the test programs loaded on the multifunctional integrated processing device include: Loading the FPGA function test program into the multifunctional integrated processing device; including: Power on the circuit, apply the VIVADO software, select the steps of compilation and debugging, generating the BIT file, and device programming, and complete the program writing; Power on the circuit again, apply the CCS software, import the project engineering, build project for compilation, connect the debugger, and execute the run debug step to complete the writing; Loading the FPGA performance test program into the chip test device; including: Power on the circuit again, apply the VIVADO software, select the Bit file for performance test, and execute the device programming step to complete the program writing; Loading the CIB test program into the chip test device; including: Power on the circuit again, apply the KEIL software, select the corresponding.c project file, connect the debugger, update the internal program of the chip, and power off the chip after completion; Power on the circuit, apply the VIVADO software, select the steps of compilation and debugging, generating the BIT file, and device programming, and complete the program writing; Load the AI test program into the chip test device; including: Re-power the circuit, connect the PCIE interface, select the corresponding Py file through the Pytorch software in the Linux environment, and perform matrix calculations to achieve computing power testing; Load the DSP test program into the chip test device; including: Re-power the circuit, apply the CCS software, import the project engineering, compile the build project, connect the debugger, and execute the run debug step to complete the programming; Power on the circuit, apply the VIVADO software, select the steps of compilation and debugging, generate the BIT file, and device programming to complete the program programming.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The 2.5D / 3D aliasing chip test method for integrated information processing of navigation, control, and computing provided by the present invention realizes the functional and electrical performance parameter testing of multi-layer aliasing chips. This method not only realizes the function and parameter verification of the chip, but also can detect the interconnection faults between the internal components of the chip, and feedback to the engineer according to the mass production data to improve the chip yield. The above advantages indicate that the present invention has a wider applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of the 2.5D / 3D aliasing chip test method for integrated information processing of navigation, control, and computing provided by the present invention.

[0018] Figure 2 It is a schematic structural diagram of the chip test device provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0020] As Figure 1 shown, the embodiment of the present invention specifically provides an aliasing chip test method, including: S110. Analysis of the internal component models of the chip; S120. Generating a classification matrix of chip device defects and failure models; S130. Programming the test vectors into the chip defect detection test platform; S140. FPGA component function testing; S150. FPGA component performance testing; S160, CIB function test; S170, AI function test; S180, DSP component function test; S190, internal component interconnection communication test; S200, feedback the chip device defect and failure model classification matrix and test results to the chip defect detection test platform; S210, mass production failure warning to improve the yield rate.

[0021] The tests include: FPGA component function tests (FLASH self - test, DDR3 1333 / 1600Mbps dual - rate verification, GTH high - speed self - test), FPGA component performance test (output port drive voltage test), CIB function test (SRIO / SPI / NAND FLASH / PCIe interface function), AI function test (computing power test), DSP component function test (floating - point test, EMIF test, GMAC test), internal component interconnection communication test (DSP and CIB communication, FPGA and CIB communication, FPGA and DSP communication).

[0022] The sequential tests on the aliased chips according to the chip device defect and failure model classification matrix and combined with the test program include: FPGA component function tests (FLASH self - test, DDR3 1333 / 1600Mbps dual - rate verification, GTH high - speed self - test), FPGA component performance test (output port drive voltage test), CIB function test (SRIO / SPI / NAND FLASH / PCIe interface function), AI function test (computing power test), DSP component function test (floating - point test, EMIF test, GMAC test), internal component interconnection communication test (DSP and CIB communication, FPGA and CIB communication, FPGA and DSP communication).

[0023] Defining the internal FLASH self - test, internal DDR3 1333Mbps self - test function test, internal DDR3 1600Mbps self - test, and internal GTH high - speed self - test as FPGA component function tests according to the chip device defect and failure model classification matrix.

[0024] Preferably, defining the output port drive voltage test as the FPGA component performance test according to the chip device defect and failure model classification matrix.

[0025] Preferably, the SRIO interface test, SPI interface test, MBIST test, CMU test, NAND FLASH interface function, DDR interface function, and PCIE interface function defined according to the chip device defect and failure model classification matrix are CIB function tests.

[0026] Preferably, the computing power test defined according to the chip device defect and failure model classification matrix is the FPGA component performance test.

[0027] Preferably, the floating-point test, EMIF test, and GMAC test defined according to the chip device defect and failure model classification matrix are DSP component function tests.

[0028] Preferably, the internal DSP and CIB communication test, internal FPGA and CIB communication test, and internal FPGA and DSP communication test defined according to the chip device defect and failure model classification matrix are internal component interconnection communication tests.

[0029] The 2.5D / 3D aliasing chip test method for integrated navigation, control, and computing information processing provided by the present invention realizes the functional and electrical performance parameter tests for multi-layer aliasing chips. This method not only verifies the functions and parameters of the chips, but also detects the interconnection faults between the internal components of the chips, and feeds back to the engineers according to the mass production data, thereby improving the chip yield.

[0030] It should be noted that before importing the test program, it is also necessary to complete the setup of the test device. Specifically, as Figure 2 shown, during the test, the power adapter 410 incorporates multiple voltage regulator chips 400. After power-on, the host computer 10 sends a start command to the multifunctional integrated processing device 15. The multifunctional integrated processing device 15 processes sequentially according to the chip device defect and failure model classification matrix information, and conducts functional and performance tests on the aliasing chip 220. Finally, it feeds back the corresponding chip device defect and failure model classification matrix information to the host computer 10 to determine whether the chip is normal. Then the power adapter 410 is powered off and the test ends.

[0031] Specifically, as Figure 2 shown, the multifunctional integrated processing device 15 is provided with an ARM hardware board 190, which is connected to the circuit board 210 of the chip under test through the ARM interface 170 and is used for the DSP component function test of the aliasing chip. Specifically, as Figure 2As shown, the multifunctional integrated processing device 15 is provided with an LED display board 180, and the FPGA hardware board 100, the CPU hardware board 120 and the ARM hardware board 190 are interconnected through ports and feedback test information. The ARM hardware board 190 monitors the test feedback port status of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back to the LED display board 180 for displaying chip device defect and failure model classification matrix information.

[0032] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is also provided with a CPU hardware board 120, which is connected to the circuit board 210 of the chip under test through the CPU interface 150, and is used for CIB and AI function testing of the aliasing chip. Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is further provided with an FPGA hardware board 100, which is connected to the circuit board 210 of the chip under test via an FPGA interface 130, and is used for FPGA component function and performance testing of the aliasing chip, DSP component function testing, and internal component interconnection and communication testing.

[0033] Specifically, such as Figure 2 As shown, the multifunctional integrated processing device 15 is provided with an LED display board 180, an electronic load 115, an FPGA hardware board 100, a CPU hardware board 120 and an ARM hardware board 190, which are interconnected through ports and feed back test information. The ARM hardware board 190 monitors the test feedback port status of the FPGA hardware board and the CPU hardware board according to the test sequence and feeds it back to the LED display board 180 for displaying chip device defects and failure model classification matrix information.

[0034] Specifically, such as Figure 2 As shown, the aliasing chip 220 is internally composed of multiple components and chips, specifically an FPGA component 240 , a DSP component 260 , a CIB (core particle) module 200 , and an AI module 280 .

[0035] Specifically, such as Figure 2 As shown, the power adapter 410 has a built-in voltage regulator chip 400 and is connected to the circuit board 210 of the chip under test for powering on and off the chip.

[0036] Specifically, such as Figure 2 As shown, the clock adapter 300 has multiple active clocks built in and is connected to the circuit board 210 of the chip under test to provide a reference clock signal.

[0037] The FPGA hardware board 100 includes an FPGA processor 110 , the CPU hardware board 120 includes a CPU processor 140 , and the ARM hardware board 190 includes an ARM processor 160 .

[0038] The ARM interface 170 includes a JTAG debug bus, a UART serial port (expandable to RS-485), and a general signal direct connection channel. The CPU interface 150 provides JTAG and UART dual debug interfaces and a PCIe high-speed channel interface. The FPGA interface 130 integrates a PCIE high-speed interface, a JTAG bus, and a programmable signal direct connection channel interface.

[0039] The central area of the circuit board 210 of the chip under test is designed with an inward concavity for fixing the aliasing chip 220 under test. This PCB is designed as a multi-layer board.

[0040] Specifically, the test programs loaded on the multifunctional integrated processing device include: Loading the FPGA function test program into the multifunctional integrated processing device; Specifically, power on the circuit, apply the VIVADO software, select steps such as compilation and debugging, generating a BIT file, and device programming, and complete the program writing; Specifically, power on the circuit again, apply the CCS software, import the project engineering, build the project for compilation, connect the debugger, and execute steps such as run debug to complete the writing; Loading the FPGA performance test program into the chip test device; Specifically, power on the circuit again, apply the VIVADO software, select the Bit file for performance testing, and execute steps such as device programming to complete the program writing; Loading the CIB test program into the chip test device; Specifically, power on the circuit again, apply the KEIL software, select the corresponding.c project file, connect the debugger, update the internal program of the chip, and power off the chip after completion; Specifically, power on the circuit, apply the VIVADO software, select steps such as compilation and debugging, generating a BIT file, and device programming, and complete the program writing; Loading the AI test program into the chip test device; Specifically, power on the circuit again, connect the PCIE interface, in the Linux environment, through the Pytorch software, select the corresponding Py file, and execute matrix calculations to achieve computing power testing; Loading the DSP test program into the chip test device; Specifically, power on the circuit again, apply the CCS software, import the project engineering, build the project for compilation, connect the debugger, and execute steps such as run debug to complete the writing; Specifically, power on the circuit, apply the VIVADO software, select steps such as compilation and debugging, generating a BIT file, and device programming, and complete the program programming; Preferably, in the chip device defect and failure model classification matrix, each test ranges from 10000001 to 10010011 in sequence, and 11111111 indicates a passed test. 0XXXXXX represents in the test, where X represents uncertainty and can be either 1 or 0.

[0041] Preferably, during the mass production test process, by transmitting the data of the chip under test to the host computer and comparing the current failure data with the standard data, it is determined whether the parameters of the chip under test exceed the normal range. If the parameters of the chip are abnormal, according to the chip device defect and failure model classification matrix, the failure situation of the chip will be recorded as the corresponding failure number F[i], and a mass production failure warning model will be constructed on the host computer. When the ratio of the occurrence times of a certain failure number F[i] to the total number of current tests F exceeds 5%, according to the national standard 548C / 2021, the system will give a warning about the failure defect corresponding to the failure number F[i] on the host computer and display the warning information on the LED display screen of the ARM board. All current failure numbers F[i] are statistically analyzed. If the ratio of other failure numbers F[i] / the current failure number F[i] is greater than 95%, it will also be displayed on the host computer. Once the host computer enters the warning state, the chip defect detection test platform will be powered off when it is not operated for a long time. Only after the engineer confirms the warning state, the total number of tests F will be cleared. At the same time, all recorded failure numbers F[i] and their corresponding failure comparison information will be cleared after the chip defect detection test platform is powered on again, so as to generate a new mass production failure warning model to meet the subsequent test failure analysis requirements.

[0042] The following Table 1 shows the chip device defect and failure model classification matrix information;

[0043] It should be noted that if the internal FLASH self-test, the internal DDR3 1333mbps self-test function test, and the internal DDR3 1600mbps self-test fail, they are located as FLASH defects. If the internal GTH high-speed self-test and the output port drive voltage test fail, they are located as FPGA defects. If the SRIO interface test, the SPI interface test, the MBIST test, the CMU test, the NAND FLASH interface function, the DDR interface function, and the PCIE interface function fail, they are located as CIB defects. If the computing power test fails, it is located as an AI defect. If the floating-point test, the EMIF test, and the GMAC test fail, they are located as DSP defects. If the internal DSP and CIB communication test, the internal FPGA and CIB communication test, and the internal FPGA and DSP communication test fail, they are located as packaging defects.

[0044] The testing of the classification matrix for chip device defects and failure models provided by the present invention will be described in detail below in conjunction with Table 1 above.

[0045] If the test is normal, the LED display board of the ARM will display 11111111. During the test, the LED display board of the ARM will display 0XXXXXX. If there are problems with the chip test, other statuses will be displayed. 1. Internal FLASH self-test Use the FPGA to perform a functional test on the FLASH through the internal interconnection signal. It mainly involves full-address reading and writing of 55AA, AA55, 0000, and 1111, and compare with the data pre-stored in the FPGA. If the data is consistent, the FLASH is normal; otherwise, the internal FLASH self-test fails. The FPGA sends it to the ARM processor 160 through the port signal. The ARM detects the port change, feedbacks 10000001 to the host computer, and at the same time displays the result on the LED display board.

[0046] 2. Internal DDR3 1333mbps self-test Use the FPGA to perform a functional test on the FLASH through the internal interconnection signal. The IP core selects the DDR 1333 rate. It mainly involves full-address reading and writing of 55AA, AA55, 0000, and 1111, and compare with the data pre-stored in the FPGA. If the data is consistent, it indicates that the FLASH is normal; otherwise, the internal FLASH self-test fails. The FPGA sends it to the ARM processor through the port signal. The ARM detects the port change, feedbacks 10000010 to the host computer, and at the same time displays the result on the LED display board.

[0047] 3. Internal DDR3 160mbps self-test Use the FPGA to perform a functional test on the DDR3 through the internal interconnection signal. The IP core selects the DDR 1600 rate. It mainly involves full-address reading and writing of 55AA, AA55, 0000, and 1111, and compare with the data pre-stored in the FPGA. If the data is consistent, the DDR3 is normal; otherwise, the internal FLASH self-test fails. The FPGA sends it to the ARM processor through the port signal. The ARM detects the port change, feedbacks 10000011 to the host computer, and at the same time displays the result on the LED display board.

[0048] 4. Internal GTH high-speed self-test Inside the device, the FPGA runs a high-speed interface test program. A clock signal is given through the reference clock. In the way of signal frequency multiplication, data packets are cyclically sent and read inside the FPGA and counted. When the total count is correct, the test passes. Otherwise, the test fails, the internal GTH high-speed self-test fails, and the FPGA sends it to the ARM processor through the port signal. When the ARM detects the port change, it feeds back 10000100 to the host computer and displays the result on the LED display board at the same time.

[0049] 5. Output port drive voltage test Inside the device, the FPGA runs an output port drive voltage test program. A drive current is applied through the electronic load at the lead-out port of the chip under test. And the signal is sent to the FPGA ADC port of the FPGA hardware board. The FPGA hardware board feeds back the signal to the host computer. If the value ≥ 1.4, the test passes. Otherwise, the test fails, the output port drive voltage test fails, and the ARM processor feeds back 10000101 to the host computer and displays the result on the LED display board at the same time.

[0050] 6. SRIO interface test Configure the SRIO interface rate of the CIB to 5.0Gbps Lane x2 mode. Run the SRIO data write request instruction in the ARM and send 1 write data packet request to the SRIO interface of the CIB. After the CIB chip receives the write request instruction, it performs the data packet exchange operation and returns a write response packet to the FPGA at the end of the exchange. Use the logic analyzer of the FPGA to capture the write instruction and response packet of the SRIO port. Statistically analyze the write / read event delay time series, and take the maximum value in the two series as the final delay time. If the final delay data ≤ 30μs, the test passes. Otherwise, the test fails, the SRIO interface fails, and the ARM processor feeds back 10000110 to the host computer and displays the result on the LED display board at the same time.

[0051] 7. SPI interface test Configure the SPI interface mode of the CIB, send instructions to the registers of the fixed bits of the chip and configure them. The FPGA is responsible for monitoring the SPI interface. If the data is normal, the test passes. Otherwise, the test fails, the SPI interface fails, and the ARM processor feeds back 10000111 to the host computer and displays the result on the LED display board at the same time.

[0052] 8. NAND FLASH interface function Run the test program to perform a full-address test on the Nand Flash through the CIB chip and count the capacity of all Nand Flash storage units. If the total capacity of the Nand Flash ≥ 16 Gb, the test passes; otherwise, the test fails, the SPI interface fails, and the ARM processor feeds back 10001000 to the host computer while displaying the result on the LED display board.

[0053] 9. PCIE Interface Function Configure the PCIE interface rate of the CIB in 5.0 Gbps Lane x2 mode as the EP end; and run the PCIE interface test program on the CPU core board under test, configure the CPU under test as the RC end. The CPU core board uses the PCIE interface to cyclically write and read data packets to / from the EP-end device and complete the verification of the sent and received data packets in the CPU core board. If the data packet transmission verification is error-free, the test passes; otherwise, the test fails, the PCIE interface fails, and the ARM processor feeds back 10001001 to the host computer while displaying the result on the LED display board.

[0054] 10. Computing Power Test For the AI floating-point computing peak performance test program, generate two floating-point matrices of dimensions [m:n] and [n:h], where each matrix element is defined as 1 floating-point number. The program performs the multiplication operation of the above two matrices, so the single operation amount is m * n * h * 2. If the matrix multiplication operation is cycled e times, the total calculation amount is MAI = e * m * n * h * 2. The program uses a timer to obtain the total consumption time T of the above matrix multiplication operation. Then the single-core AI floating-point computing peak power PAI = MAI / T = e * m * n * h * 2 / T, with the unit TFLOPS. If the computing peak power test result ≥ 2.0 TFLOPS, the test passes. Otherwise, the test fails, the computing power test fails, and the ARM processor feeds back 10001010 to the host computer while displaying the result on the LED display board.

[0055] 11. Floating-Point Test Floating-point calculation peak performance test program, which loops through floating-point operations on 8 DSP cores. The number of loops is c, the number of floating-point operations per loop is d, and the floating-point calculation volume of each DSP core is MCORE = c * d. The DSP's timer is used to measure the program running time tREG, and the frequency of the timer is 1 / 6 of the DSP running frequency. Then the total loop time T = tREG * 6 ns. The peak floating-point computing power of a single DSP is PDSP = 8 (cores) * MCORE / T = 8 * c * d / (tREG * 6 * 1000), with the unit of TFLOPS. If the peak computing power test result is correct, the test passes. Otherwise, the test fails, the floating-point test fails, and the ARM processor sends 10001011 to the host computer and displays the result on the LED display board.

[0056] 12. EMIF Test Execute the EMIF interface test program in the internal DSP chip of the device. Configure the EMIF operation data bit width to 32 bits (including all data lines), access the memory on the EMIF interface, and perform multi-address (including all address line transformations) read and write operations on the memory. First, write 0x55AA55AA address by address, read the written data, and compare whether the read and written data are the same. Then write 0xAA55AA55 address by address and compare the read and written data again. If both are the same, the test passes; otherwise, it fails. The EMIF test fails, and the ARM processor sends 10001100 to the host computer and displays the result on the LED display board.

[0057] 13. GMAC Test Connect the Ethernet interface of the DSP to the PC network port through a network cable. Run the Ethernet test program in the DSP, configure the GMAC interface of the DSP to work in 1000 Mbps mode, and at the same time, the test program in the DSP sends the data received by the GMAC port back through the same port. Run the Ethernet test software on the PC. This software sends data packets to the GMAC interface of the DSP and receives the data returned from the DSP GMAC port, and at the same time compares and verifies the sent and received data. If the data transmission is all verified correctly, the test passes; otherwise, the test fails. The GMAC test fails, and the ARM processor sends 10001101 to the host computer and displays the result on the LED display board.

[0058] 14. Internal DSP and CIB Communication Test After the DSP and CIB are loaded, the DSP is interconnected with the CIB through the EMIF interface, and the operating data bit width of the EMIF is configured to 8 bits. Access the CIB on the EMIF interface. If the access is successful, the test passes; otherwise, it fails, and the internal DSP-CIB communication test fails. The ARM processor feeds back 10001110 to the host computer and displays the result on the LED display board at the same time.

[0059] 15. Internal FPGA-CIB Communication Test After the FPGA and CIB are loaded, the FPGA is interconnected with the CIB through the IOB. The CIB feeds back all highs and all lows according to the corresponding ports. If the FPGA can detect the relevant signals, the test passes; otherwise, it fails, and the internal FPGA-CIB communication test fails. The ARM processor feeds back 10001111 to the host computer and displays the result on the LED display board at the same time.

[0060] 16. Internal FPGA-DSP Communication Test After the FPGA and DSP are loaded, the FPGA is interconnected with the DSP through the IOB. The DSP sends data to the FPGA according to the EMIF interface, and the FPGA stores and verifies it. If so, the test passes; otherwise, it fails, and the internal FPGA-DSP communication test fails. The ARM processor feeds back 10010000 to the host computer and displays the result on the LED display board at the same time.

[0061] In summary, a method for testing a 2.5D / 3D aliasing chip based on integrated information processing of navigation, control and computing provided by the present invention not only realizes the function and parameter verification of the chip, but also can detect the interconnection faults between the internal components of the chip, and feedbacks to the engineers according to the mass production data to improve the chip yield.

[0062] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A 2.5D / 3D aliased chip testing method based on integrated information processing of navigation, control and computing, characterized in that, Including: Generating a classification matrix of chip device defects and failure models by constructing an internal component model of the chip; And burning test vectors into the chip test device; Performing functional and performance parameter tests on the 2.5D / 3D hybrid chip according to the relevant information of the chip device defect and failure model classification matrix and the firmware program of the test vector; That is: obtaining the binary classification information of the chip failure model classification matrix through the FPGA port of the 2.5D / 3D hybrid chip, so as to determine whether there are problems with the functional and performance parameters of the 2.5D / 3D hybrid; Constructing a mass production failure warning model to improve the yield of multi-layer hybrid chips.

2. The 2.5D / 3D aliasing chip testing method based on integrated information processing of navigation, control and calculation according to claim 1, characterized in that, The constructing of the internal component model of the chip means constructing an internal model of the chip composed of an FPGA component, a DSP component, a CIB die module, and an AI module; wherein an FPGA, a FLASH, and a DDR3 are integrated on the FPGA component; a DSP, a NorFLASH, and a DDR3 are integrated on the DSP component.

3. A 2.5D / 3D aliased chip testing method based on integrated information processing of navigation, control and computing as claimed in claim 1, characterized in that, The burning of the test vector into the chip test device means starting the ARM and FPGA projects to the test device for detecting chip defects; including: preloading the FPGA test program, preloading the DSP test program, preloading the CIB test program, and preloading the AI test program to achieve parallel initialization of multi-core test resources.

4. A 2.5D / 3D aliasing chip test method based on integrated information processing of navigation, control and computing as claimed in claim 1, characterized in that, The performing of the functional and electrical performance parameter tests on the 2.5D / 3D hybrid chip includes: Functional test of the FPGA component, including FLASH self-test, DDR3 1333 / 1600Mbps dual-rate verification, and GTH high-speed self-test; Performance test of the FPGA component, that is, output port drive voltage test; Functional test of the CIB, that is, SRIO / SPI / NAND FLASH / PCIe interface functional test; Functional test of the AI, that is, computing power test; Functional test of the DSP component, including floating-point test, EMIF test, and GMAC test; Internal component interconnection communication test, including DSP and CIB communication, FPGA and CIB communication, and FPGA and DSP communication tests.

5. A 2.5D / 3D aliasing chip test method based on integrated information processing of navigation, control and calculation as claimed in claim 1, characterized in that, The constructing of the mass production failure warning model includes: Transmitting the data of the chip to be tested to the host computer to obtain the current failure data, and comparing it with the standard data to judge whether the parameters of the current chip to be tested deviate from the normal range; Recording the corresponding failure number F[i] according to the chip device defect and failure model classification matrix, and then constructing a mass production failure warning model on the host computer; When the ratio of the failure number F[i] / the total number of current tests F is greater than 5%, the host computer starts to execute the warning operation; counting all the current failure numbers F[i], if the ratio of other failure numbers F[i] / the current failure number F[i] is greater than 95%, it will also be displayed on the host computer; When the host computer is in the warning state, the current failure number F[i] will be displayed on the LED display board of the ARM board. The chip testing device is in a power-off state when not operated for a long time. After confirming the warning state, the total number of tests F is reset passively. At the same time, all the failure comparison information stored in the failure number F[i] is discarded after the chip testing device is powered on, so as to transform into a new mass production failure warning model to meet the subsequent test failure analysis.

6. A 2.5D / 3D aliasing chip testing method based on integrated information processing of navigation, control, and computing according to claim 1, characterized in that The fault state definitions of each test in the chip device defect and failure model classification matrix range from 10000001 to 10010011 in sequence, and 11111111 indicates that the test passes; 0XXXXXX indicates that the test is in progress, where X represents an uncertain state, and X is either 1 or 0.

7. A 2.5D / 3D aliasing chip test device based on integrated information processing of navigation, control and computing, which executes a 2.5D / 3D aliasing chip test method based on integrated information processing of navigation, control and computing as described in claim 1, characterized in that, Including: Host computer; Multifunctional integrated processing device, connected to the host computer; Power adapter; Clock adapter; Chip under test board, communicatively connected to the power adapter, clock adapter and multifunctional integrated processing device respectively; Among them, the chip under test board is used for fixing the chip under test and powering on the chip under test. The chip under test board is composed of various circuit design hardware, and can complete the test of the chip under test under the instruction of the host computer, and display the test results on the multifunctional integrated processing device in real time.

8. A 2.5D / 3D aliasing chip test device based on integrated information processing of navigation, control and computing as claimed in claim 7, characterized in that, Before importing the test program, it is necessary to complete the setup of the test device, that is: during the test, the power adapter incorporates multiple voltage regulating chips. After power-on, the host computer sends a start instruction to the multifunctional integrated processing device. The multifunctional integrated processing device processes sequentially according to the relevant information of the chip device defect and failure model classification matrix, and conducts functional and performance parameter tests on the aliased chips. Finally, it feeds back the information of the corresponding chip device defect and failure model classification matrix to the host computer to determine whether the chip is normal. Then the power adapter is powered off and the test ends.

9. The 2.5D / 3D aliasing chip test device based on integrated information processing of navigation, control and calculation according to claim 7, wherein, The multifunctional integrated processing device includes: an LED display board, an electronic load, an FPGA hardware board, a CPU hardware board and an ARM hardware board; the ARM hardware board monitors the tests of the FPGA hardware board and the CPU hardware board according to the test sequence, and feeds back the port status to the LED display board for displaying the chip device defect and failure model classification matrix information; Among them, the FPGA hardware board is connected to the circuit board of the chip under test through the FPGA interface, and is used for testing the functions and performance of the FPGA components, DSP components and internal component interconnection communication of the aliased chips; The CPU hardware board is connected to the circuit board of the chip under test through the CPU interface, and is used for testing the CIB and AI functions of the aliased chips; The ARM hardware board is connected to the circuit board of the chip under test through the ARM interface, and is used for testing the DSP component functions of the aliased chips; The power adapter incorporates voltage regulating chips and is connected to the circuit board of the chip under test for powering on and off the chip; The clock adapter incorporates multiple active clocks and is connected to the circuit board of the chip under test for providing a reference clock signal; The FPGA hardware board includes an FPGA processor; the CPU hardware board includes a CPU processor; the ARM hardware board includes an ARM processor.

10. A 2.5D / 3D aliasing chip test device based on integrated information processing of navigation, control and computing as claimed in claim 7, characterized in that The loading of test programs on the multifunctional integrated processing device includes: Loading the FPGA function test program onto the multifunctional integrated processing device; including: Power on the circuit, use the VIVADO software, select the steps of compilation and debugging, generating the BIT file, and device programming, and complete the program writing; Power on the circuit again, use the CCS software, import the project engineering, build the project for compilation, connect the debugger, and execute the run debug step to complete the writing; Loading the FPGA performance test program onto the chip test device; including: Power on the circuit again, use the VIVADO software, select the Bit file for performance test, and execute the device programming step to complete the program writing; Loading the CIB test program onto the chip test device; including: Power on the circuit again, use the KEIL software, select the corresponding.c project file, connect the debugger, update the internal program of the chip, and power off the chip after completion; Power on the circuit, use the VIVADO software, select the steps of compilation and debugging, generating the BIT file, and device programming, and complete the program writing; Loading the AI test program onto the chip test device; including: Power on the circuit again, connect the PCIE interface, in the Linux environment, through the Pytorch software, select the corresponding Py file, and execute matrix calculation to achieve computing power test; Loading the DSP test program onto the chip test device; including: Power on the circuit again, use the CCS software, import the project engineering, compile the engineering, connect the debugger, and execute the run debug step to complete the writing; Power on the circuit, use the VIVADO software, select the steps of compilation and debugging, generating the BIT file, and device programming, and complete the program programming.

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