Differential clock receiving circuit with high slew rate and low delay

Abstract

The invention provides a differential clock receiving circuit with high slew rate and low delay. The differential clock receiving circuit comprises a differential input geminate transistor circuit, a flip voltage follower current mirror biasing circuit, a common-mode level sampling circuit and an active inductor current mirror load circuit. The FVF buffer stage is used as a direct current bias technology. Compared with a traditional tail current source bias method, the method has the advantages that bias current limitation is effectively eliminated, and the slew rate of an output signal is remarkably increased. According to the invention, a negative impedance and active inductor combination technology is used to improve high-frequency impedance. Compared with a traditional resistive load, the technology not only significantly improves the high-frequency output impedance, but also widens the frequency band width.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed integrated circuits, and particularly relates to a differential clock receiving circuit with a high slew rate and low delay. Background Art

[0002] Clock signals have a wide range of applications in the field of integrated circuits. As the "pulse" of the circuit system, they provide an accurate time reference for each functional module. In digital circuits, the execution of processor instructions, the transmission and storage of data, and the synchronous progress of various logical operations all highly depend on the stable rhythm of the clock signal.

[0003] However, due to the attenuation in the clock link, when the signal reaches the chip receiving end, the attenuation of its amplitude will increase with the increase in the clock frequency. If the attenuated clock signal is directly used for sampling in a digital chip, it may lead to misjudgment due to insufficient amplitude, and then cause misoperation. Therefore, the external clock signal must be amplified to a level that can be accurately recognized inside the chip. In terms of interface applications, there are also strict requirements for the jitter and delay of the clock signal. Improving the slew rate of the clock circuit can effectively improve the jitter and delay problems of the clock signal. An increase in the slew rate means that the clock signal changes from low level to high level faster, thereby reducing the amplitude loss caused by attenuation during signal transmission, ensuring that the clock signal can be accurately recognized inside the chip, and reducing the risk of misjudgment and misoperation. This is particularly important for high-speed digital circuit design.

[0004] Currently, there are also some technologies that can reduce the jitter and delay problems generated during the clock signal processing in the circuit and improve the efficiency and accuracy of signal processing. For example, in the field of high-speed clock signal processing, the use of differential amplifiers has become a commonly adopted strategy. Although this technology has achieved remarkable results in improving signal quality, the internal tail current source also brings certain limitations. Its structural schematic diagram is as Figure 1 shown. Specifically, the current value of the tail current source sets an upper limit, which restricts the dynamic response ability of the circuit. When the amplitude of the output signal reaches a relatively high level, the slew rate of the circuit will be inhibited, which will not only introduce unnecessary jitter but also increase the delay during signal transmission. For application scenarios that require high-precision clock synchronization, this increase in delay and jitter is a problem that cannot be ignored. Summary of the Invention

[0005] The purpose of the present invention is to propose a differential clock receiving circuit with a high slew rate and low delay to solve the technical problem of the increase in delay and jitter in the prior art for application scenarios that require high-precision clock synchronization as mentioned in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A differential clock receiving circuit with high slew rate and low delay, comprising a differential input pair transistor circuit, a flip voltage follower current mirror biasing circuit, a common-mode level sampling circuit, and an active inductor current mirror load circuit.

[0008] Further, the differential input pair transistor circuit is composed of two NMOS transistors, and the differential input pair transistor circuit is used to convert the differential clock voltage signal at the input end into a current signal. The flip voltage follower current mirror biasing circuit is composed of two NMOS transistors and an external current source. The common-mode level sampling circuit is composed of a resistor and a capacitor. The active inductor current mirror load circuit is composed of four PMOS transistors and two resistors.

[0009] Further, the differential input pair transistor circuit is two NMOS transistors with the same size.

[0010] Further, the size of the NMOS transistor in the flip voltage follower current mirror biasing circuit connected to the external current source is the same as the size of the differential input pair.

[0011] Specifically, it includes NMOS transistor MN0, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, PMOS transistor MP0, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, resistor R0, resistor R1, resistor R2, resistor R3, and capacitor C0. The drain of NMOS transistor MN0 is connected to the lower end of resistor R2, the drains of PMOS transistors MP0 and MP3, and the voltage signal output terminal VOUTN. The source of NMOS transistor MN0 is connected to the sources of NMOS transistor MN1, the drain of NMOS transistor MN2, and the source of NMOS transistor MN3. The gate of NMOS transistor MN0 is connected to the left end of resistor R0 and the voltage signal input terminal VINP. The right end of resistor R0 is connected to the upper end of capacitor C0, the gate of NMOS transistor MN3, and the left end of resistor R1. The right end of resistor R1 is connected to the gate of NMOS transistor MN1 and the voltage signal input terminal VINN. The lower end of capacitor C0 and the source of NMOS transistor MN2 are grounded respectively. The gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3 and is connected to the power supply Vdd through an external current source Ibias. The drain of NMOS transistor MN1 is connected to the lower end of resistor R3, the drains of PMOS transistors MP1 and MP2, and the voltage signal output terminal VOUTP. The upper end of resistor R2 is connected to the gates of PMOS transistors MP0 and MP2. The upper end of resistor R3 is connected to the gates of PMOS transistors MP1 and MP3. The sources of PMOS transistors MP0, MP1, MP2, and MP3 are connected to the power supply Vdd.

[0012] The present invention has the following beneficial effects:

[0013] The present invention adopts the FVF buffer stage as a DC biasing technique. Compared with the traditional tail current source biasing method, this technique effectively eliminates the biasing current limitation and significantly improves the slew rate of the output signal. The current slew rate of the traditional structure is limited by the tail current source. When the input voltage swing increases, its current will not increase anymore but remain at a fixed value. However, the structure proposed by the present invention can get rid of the limitation of the traditional tail current source, enabling the output current to increase as the input voltage increases. The improvement of the slew rate directly leads to the reduction of jitter and the decrease of transmission delay, which has significant advantages for high-speed signal processing.

[0014] In addition, the present invention uses the combination technique of negative impedance and active inductor to improve the high-frequency impedance. Compared with the traditional resistive load, this technique not only significantly increases the high-frequency output impedance but also broadens the bandwidth. Compared with the inductive load, this technique also has the advantage of saving chip layout area, which is extremely important for modern chip design with continuously increasing integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 Schematic diagram of the clock signal processing circuit structure in the prior art;

[0017] Figure 2 Schematic diagram of the differential clock receiving circuit of the present invention;

[0018] Figure 3 Small-signal equivalent model of the half circuit with an active inductor current mirror load;

[0019] Figure 4 Comparison diagram of the current-voltage characteristics between the present invention and the traditional current. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0021] Refer to Figure 2As shown, a differential clock receiving circuit with a high slew rate and low delay. The circuit structure is mainly divided into three parts, namely, a differential input pair transistor circuit, a flipped voltage follower (FVF) current mirror biasing circuit, and an active inductor current mirror load circuit.

[0022] The differential clock receiving circuit specifically includes NMOS transistors MN0, MN1, MN2, MN3, PMOS transistors MP0, MP1, MP2, MP3, resistors R0, R1, R2, R3, and capacitor C0. The drain of NMOS transistor MN0 is connected to the lower end of resistor R2, the drains of PMOS transistors MP0 and MP3, and the voltage signal output terminal VOUTN. The source of NMOS transistor MN0 is connected to the sources of NMOS transistors MN1, the drain of NMOS transistor MN2, and the sources of NMOS transistors MN3. The gate of NMOS transistor MN0 is connected to the left end of resistor R0 and the voltage signal input terminal VINP. The right end of resistor R0 is connected to the upper end of capacitor C0, the gate of NMOS transistor MN3, and the left end of resistor R1. The right end of resistor R1 is connected to the gate of NMOS transistor MN1 and the voltage signal input terminal VINN. The lower end of capacitor C0 and the source of NMOS transistor MN2 are respectively grounded. The gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3 and is connected to the power supply Vdd through an external current source Ibias. The drain of NMOS transistor MN1 is connected to the lower end of resistor R3, the drains of PMOS transistors MP1 and MP2, and the voltage signal output terminal VOUTP. The upper end of resistor R2 is connected to the gates of PMOS transistors MP0 and MP2. The upper end of resistor R3 is connected to the gates of PMOS transistors MP1 and MP3. The sources of PMOS transistors MP0, MP1, MP2, and MP3 are connected to the power supply Vdd.

[0023] The differential input pair transistor circuit consists of two NMOS transistors MN0 and MN1 with the same size, and their sizes are precisely matched, ensuring the symmetry and balance of the circuit. The main function of the differential input pair transistor is to achieve small-signal transconductance conversion, converting the differential clock voltage signals at the input terminals VINP and VINN into current signals, which is the basis for the operation of the entire circuit.

[0024] The FVF current mirror bias circuit consists of two NMOS transistors MN2 and MN3 and an external current source Ibias. Ibias is the current bias signal provided externally. Among them, the size of MN3 is the same as that of the differential input pair transistors, ensuring that the bias circuit and the input pair transistors are in the same working state. The resistor R0, resistor R1, and capacitor C0 form a common-mode level sampling circuit, whose function is to obtain the common-mode level of the input signal at the gate of MN3 as the DC bias of MN3. Since the input signal is a fully differential signal, theoretically this common-mode level remains unchanged, providing a stable reference point for the circuit. MN2 and MN3 form an FVF buffer stage, which makes the intersection of the source of MN0 and the drain of MN2 a low-resistance node. When the current flowing through MN2 changes, since the gate voltage of MN3 remains unchanged and the current flowing through MN3 also remains unchanged, the voltage value of the above-mentioned low-resistance node remains unchanged, ensuring the stability of the circuit under dynamic conditions.

[0025] The active inductor current mirror load circuit consists of four identical PMOS transistors MP0, MP1, MP2, MP3 and two resistors R2 and R3. This structure can improve the high-frequency impedance of the load and generate a high-frequency response characteristic similar to that of an inductor. MP2 and MP3 are connected in a negative resistance manner, and this structure improves the high-frequency impedance, thereby enhancing the high-frequency gain. When an external differential output signal is applied, the currents flowing through MN0 and MN1 transistors will increase exponentially as their gate voltages increase, without being limited by the tail current source bias of the traditional structure.

[0026] Figure 3The small-signal equivalent model of the half-circuit with an active inductor current mirror load is depicted in detail. In the figure, Vg is the gate voltage, and Vx and -Vx are the voltage signals at different nodes in the circuit; resistors R2 and R3 are ordinary resistor elements that play roles such as voltage division and current limiting in the circuit; ro represents the output resistance of the PMOS transistor, reflecting the impedance characteristics of the transistor at the output; capacitor Cg represents the capacitance related to the gate, and Cds represents the capacitance between the drain and source of the PMOS transistor; current IX is the total current flowing through the half-load; gm0 and gm2 are the transconductances of PMOS transistors MP0 and MP2, which are used to describe the control ability of the gate voltage over the drain current. The transconductance is the ratio of the small change in the drain current (ΔId) caused by a small change in the gate voltage (ΔVg) under certain conditions, and it reflects the control sensitivity of the gate voltage over the drain current. The larger the gm value, the greater the change in the drain current caused by the same change in the gate voltage. -gm2*Vg and gm0*Vg are current sources controlled by Vg; AC ground represents the AC ground, which is the reference potential point for AC signals. In this model, the small-signal impedances of PMOS transistors MP0 and MP2 exhibit opposite polarities. This phenomenon occurs because the polarities of the small-signal voltages at the drains of MP0 and MP2 are exactly opposite. Therefore, the equivalent transconductances (gm) of MP0 and MP2 also show opposite polarities, which results in MP2 exhibiting a negative resistance characteristic, and the overall transconductance is gm0 - gm2. The design of this circuit structure can effectively reduce the equivalent transconductance of the load, thereby achieving a significant increase in gain in circuit design.

[0027] According to Figure 3 Based on the small-signal equivalent model shown, the equivalent impedance of the half-load can be expressed as VX / IX, where IX is the sum of the branch currents of branches ① to ⑤. Among these branches, branches ①, ④, and ⑤ belong to passive RC circuits, and their AC equivalent impedance characteristics remain relatively stable and decrease as the frequency of VX increases. However, the currents in branches ② and ③ are controlled by Vg. Therefore, as the frequency increases, due to the voltage division effect of the resistor and capacitor, the Vg voltage will drop, which causes the currents in branches ② and ③ to decrease, and thus IX decreases. As a result, the value of VX / IX will increase. This phenomenon is consistent with the impedance characteristic of an inductor, that is, the impedance increases as the frequency increases. At the same time, since this circuit is composed of active components, it is also called an active inductor.

[0028] The described active inductor current mirror load circuit can also be replaced by a current mirror load, a resistor load, and an inductor load.

[0029] When the FVF current source structure is jointly applied with the differential input stage of the active inductor high-gain current mirror, due to the high slew rate characteristic of the FVF current source structure itself, this leads to an increase in the load current slew rate, and this increase shows a square-law relationship. This further increases the high-frequency component of its current and indirectly increases the output swing of the active inductor load. Compared with the traditional tail current source differential pair structure, the present invention combined with the active inductor load shows more significant performance improvement. This design enables the circuit to maintain extremely low latency and extremely high slew rate when processing high-speed signals, thus providing users with unprecedented performance improvement in the fields of data transmission and signal processing.

[0030] The present invention significantly enhances the control force of the differential input voltage on the current by precisely controlling the source voltage of the differential pair transistors. Therefore, the current flowing through the input pair transistors is no longer limited by the tail current source, thus greatly increasing the output slew rate. Figure 4 It is a comparison diagram of the current-voltage characteristics of the present invention and the traditional current. In addition, it can effectively reduce the jitter and delay of the output signal, bringing revolutionary progress to the optimization of the performance of electronic devices. In the fields of high-speed signal processing and precision analog circuit design, the present invention undoubtedly opens up new possibilities and provides engineers with a broader innovation space.

[0031] The present invention proposes an innovative circuit design method that combines an active inductor with a negative resistance technology and uses it as the active load of an amplifier. Through this design, the impedance characteristics of the circuit under small-signal conditions are significantly improved, thereby enhancing the gain performance in the high-frequency band. The introduction of the active inductor further strengthens the high-frequency gain, enabling the circuit to perform excellently when processing high-speed signals, thus greatly improving the quality of the output clock signal. Compared with the traditional resistive load, the circuit design proposed by the present invention has obvious advantages in performance. Especially compared with the circuit design using an inductor as the load, the present invention is particularly outstanding in saving precious chip area. Through this innovative circuit design, not only the performance of the circuit is improved, but also a solid foundation is laid for the development of future smaller and more efficient circuit designs.

[0032] The present invention can be widely applied to modern high-speed communication system architectures, including but not limited to serializer / deserializer (Serdes), high-speed analog-to-digital / digital-to-analog converter (AD / DA) chips, and power management integrated circuit (PMIC), and other technical fields. The reception and amplification of clock signals are indispensable in the above fields and are crucial for ensuring the accuracy and stability of data transmission. By optimizing the amplification and processing mechanism of clock signals, the present invention significantly improves the signal integrity and reliability, thereby reducing the error rate and the risk of data loss during high-speed data transmission. In addition, the present invention can also adapt to variable working environments and temperature fluctuations to ensure a stable clock signal under various conditions, which is of great significance for improving the performance and reliability of the entire communication system.

[0033] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well.

Claims

1. A differential clock receiving circuit with high slew rate and low delay, characterized in that, It includes a differential input pair transistor circuit, a flip voltage follower current mirror bias circuit, a common-mode level sampling circuit, and an active inductor current mirror load circuit.

2. The differential clock receiving circuit with high slew rate and low delay according to claim 1, characterized in that, The differential input pair transistor circuit is composed of two NMOS transistors. The differential input pair transistor circuit is used to convert the differential clock voltage signal at the input end into a current signal. The flip voltage follower current mirror bias circuit is composed of two NMOS transistors and an external current source. The common-mode level sampling circuit is composed of a resistor and a capacitor. The active inductor current mirror load circuit is composed of four PMOS transistors and two resistors.

3. The differential clock receiving circuit with high slew rate and low delay according to claim 2, characterized in that The differential input pair transistor circuit is two NMOS transistors with the same size.

4. The differential clock receiving circuit with high slew rate and low delay according to claim 2, wherein The size of the NMOS transistor connected to the external current source in the flip voltage follower current mirror bias circuit is the same as that of the differential input pair transistors.

5. A differential clock receiving circuit with high slew rate and low delay according to claim 2, characterized in that, Specifically, it includes NMOS transistor MN0, NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, PMOS transistor MP0, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, resistor R0, resistor R1, resistor R2, resistor R3, and capacitor C0. The drain of NMOS transistor MN0 is connected to the lower end of resistor R2, the drain of PMOS transistor MP0, the drain of PMOS transistor MP3, and the voltage signal output terminal VOUTN. The source of NMOS transistor MN0 is connected to the source of NMOS transistor MN1, the drain of NMOS transistor MN2, and the source of NMOS transistor MN3. The gate of NMOS transistor MN0 is connected to the left end of resistor R0 and the voltage signal input terminal VINP; the right end of resistor R0 is connected to the upper end of capacitor C0, the gate of NMOS transistor MN3, and the left end of resistor R1; the right end of resistor R1 is connected to the gate of NMOS transistor MN1 and the voltage signal input terminal VINN; the lower end of capacitor C0 and the source of NMOS transistor MN2 are grounded respectively; the gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3 and is connected to the power supply Vdd through the external current source Ibias; the drain of NMOS transistor MN1 is connected to the lower end of resistor R3, the drain of PMOS transistor MP1, the drain of PMOS transistor MP2, and the voltage signal output terminal VOUTP; the upper end of resistor R2 is connected to the gates of PMOS transistor MP0 and PMOS transistor MP2; the upper end of resistor R3 is connected to the gates of PMOS transistor MP1 and PMOS transistor MP3; the sources of PMOS transistor MP0, PMOS transistor MP1, PMOS transistor MP2, and PMOS transistor MP3 are connected to the power supply Vdd.

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