Hypergraph segmentation method considering logic replication under multi-FPGA system

Abstract

The invention discloses a hypergraph segmentation method considering logic replication under a multi-FPGA (Field Programmable Gate Array) system, which provides a staged layout strategy, and firstly segments an original circuit and then reduces cross-FPGA communication delay through logic replication on the premise of ensuring that the limitation of programmable resources of each FPGA is not exceeded. The method specifically comprises a pre-layout stage and a post-layout stage: in the pre-layout stage, a multi-stage division algorithm of a multi-resource weighting strategy is used to obtain a preliminary segmentation result, a multi-dimensional weight superposition strategy is applied to solve various resource constraint problems, and possible resource violations are repaired through a resource fine tuning algorithm; and in the post-layout stage, the logic units are selectively copied based on a simulated annealing algorithm, so that the inter-chip communication overhead is further reduced. By means of the method, the high-quality FPGA segmentation scheme copied through the inter-chip logic can be rapidly generated, and the operation frequency and verification efficiency of a multi-FPGA system are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and more particularly to a hypergraph partitioning method considering logic replication in a multi-FPGA system. Background Art

[0002] The development of VLSI (Very Large Scale Integration) technology has improved the performance of electronic devices in various fields, including smart phones, computers, communication devices, etc., thus enhancing the quality of life, promoting scientific research and economic development. As a key stage in VLSI design, prototype verification ensures the correctness of the design by verifying the functions and performance of the chip, providing guarantee for the successful manufacture of the final product. With the increasing complexity of circuit design, the circuit design needs to be partitioned into a multi-FPGA (Field Programmable Gate Array) system for simulation and verification.

[0003] Traditional graph partitioning algorithms include iterative improvement methods based on movement (such as the KL / FM algorithm) and methods based on multi-level partitioning (such as Metis). Most of the studies on these traditional graph partitioning algorithms focus on balanced partitioning, that is, the partitioning generally requires the scales of each subset to be roughly balanced in order to achieve load balancing. However, in the scenario where the circuit design is allocated to multiple FPGA systems for simulation and verification, the goal is not to achieve load balancing, but to minimize the communication delay as much as possible under the constraint of FPGA capacity. Therefore, there are deficiencies in the prior art. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a hypergraph partitioning method considering logic replication in a multi-FPGA system, which is dedicated to the fusion partitioning of a multi-FPGA system and the partitioning layout of inter-chip logic replication. It can automatically explore the lowest communication delay partitioning method deployed in a multi-FPGA system for digital circuits containing a large number of logic units under various resource constraints of the on-site FPGA by using the method of logic replication.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides a hypergraph partitioning method considering logic replication in a multi-FPGA system, including:

[0007] Partition a plurality of logic units in the hypergraph to be partitioned into a plurality of FPGAs, and form a first corresponding relationship between each FPGA and each logic unit currently corresponding to the configuration;

[0008] Perform the first iterative operation, where the first iterative operation includes randomly selecting an FPGA and a logic unit, looking up the first correspondence of the logic unit, where the randomly selected FPGA and the randomly selected logic unit form a second correspondence, determining whether the first correspondence is consistent with the second correspondence, and if not, using the second correspondence to add the logic unit currently corresponding to the randomly selected FPGA to obtain the currently accepted segmentation method of the hypergraph to be segmented until a preset termination condition is met;

[0009] Output the current best segmentation method, where the current best segmentation method is the segmentation method corresponding to the hypergraph to be segmented with the minimum communication delay among the hypergraphs to be segmented after each iteration at the current iteration number.

[0010] As a further improvement of the present invention, between the step of using the second correspondence to add the logic unit currently corresponding to the randomly selected FPGA and the step of obtaining the currently accepted segmentation method of the hypergraph to be segmented, the first iterative operation further includes:

[0011] Calculate the communication delay of the hypergraph to be segmented after adding the logic unit currently corresponding to the randomly selected FPGA;

[0012] Determine whether to accept the step of adding the logic unit currently corresponding to the randomly selected FPGA according to the communication delay;

[0013] If so, determine whether to update the current best segmentation method with the segmentation method obtained by this iterative operation.

[0014] As a further improvement of the present invention, the step of determining whether to accept the step of adding the logic unit currently corresponding to the randomly selected FPGA according to the communication delay includes:

[0015] If the communication delay is less than the communication delay corresponding to the segmentation method obtained by the previous iterative operation, accept the step of adding the logic unit currently corresponding to the randomly selected FPGA;

[0016] If the communication delay is greater than or equal to the communication delay corresponding to the segmentation method obtained by the previous iterative operation, determine whether to accept the step of adding the logic unit currently corresponding to the randomly selected FPGA according to a preset probability formula, where the probability formula is obtained based on the simulated annealing algorithm.

[0017] As a further improvement of the present invention, the step of determining whether to update the current best segmentation method with the segmentation method obtained by this iterative operation includes:

[0018] Find the communication delay corresponding to the current best partitioning method, and compare its magnitude with the communication delay corresponding to the partitioning method obtained in the current iteration operation;

[0019] If the communication delay corresponding to the current best partitioning method is greater than the communication delay corresponding to the partitioning method obtained in the current iteration operation, then update the current best partitioning method.

[0020] As a further improvement of the present invention, before performing the first iteration operation, the hypergraph partitioning method considering logic replication in a multi-FPGA system further includes setting initial parameters, where the initial parameters include an initial communication delay, an initial temperature, a cooling rate, and a termination temperature.

[0021] As a further improvement of the present invention, after updating the current best partitioning method according to the judgment result, the hypergraph partitioning method considering logic replication in a multi-FPGA system further includes updating the current temperature according to the cooling rate.

[0022] As a further improvement of the present invention, dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs includes: dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logic unit and the maximum resource constraint of each FPGA, where the weight of each logic unit is determined according to the usage amount of each logic unit for each resource.

[0023] As a further improvement of the present invention, dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logic unit and the maximum resource constraint of each FPGA includes:

[0024] Perform a first partitioning on all logic units according to the weight of each logic unit, so that each FPGA is initially configured with at least one logic unit;

[0025] For each FPGA, if the initial configuration does not meet its corresponding maximum resource constraint, obtain a small top heap priority queue corresponding to the FPGA according to each logic unit that occupies overloaded resources in the FPGA;

[0026] For each small top heap priority queue, perform a second iteration operation, where the second iteration operation includes: taking out the logic unit at the head of the queue from the small top heap priority queue, establishing a large top heap priority queue according to the connection degree of the logic unit with each FPGA, where each serial number in the large top heap priority queue corresponds to each FPGA one by one, and performing a moving operation on each logic unit that occupies overloaded resources according to the large top heap priority queue until the small top heap priority queue is empty.

[0027] As a further improvement of the present invention, obtaining the min-heap priority queue corresponding to the FPGA according to each logic unit occupying overloaded resources in the FPGA includes:

[0028] Obtaining the connection degree between each logic unit occupying overloaded resources and the FPGA where it is currently located;

[0029] Obtaining the min-heap priority queue corresponding to each FPGA according to the connection degree.

[0030] As a further improvement of the present invention, performing a moving operation on each logic unit occupying overloaded resources according to the max-heap priority queue includes:

[0031] Taking out the serial number at the head of the queue from the max-heap priority queue, and judging whether the logic unit at the head of the queue can move to the FPGA corresponding to the serial number at the head of the queue under the condition of satisfying the maximum resource constraint of the FPGA corresponding to the serial number at the head of the queue. If not, repeat the step of taking out the serial number at the head of the queue from the max-heap priority queue and making a judgment until the logic unit at the head of the queue can move to the FPGA corresponding to the current serial number at the head of the queue under the condition of satisfying the maximum resource constraint of the FPGA corresponding to the current serial number at the head of the queue;

[0032] Moving the logic unit at the head of the queue to the FPGA corresponding to the current serial number at the head of the queue.

[0033] The key steps of the present invention are divided into two parts: pre-placement and post-placement. Among them, the pre-placement includes a multi-level partitioning algorithm and a resource adjustment algorithm, and the post-placement includes a logic replication algorithm implemented by a genetic algorithm. Through the multi-level partitioning algorithm of the present invention, an FPGA deployment with significantly optimized latency can be obtained; through the resource adjustment algorithm, the deployment exceeding the FPGA computing resources is corrected to meet the FPGA resource constraints; through the logic replication algorithm implemented by the simulated annealing algorithm, the latency caused by cross-FPGA communication can be further reduced on this basis, the communication overhead can be reduced, and the system frequency can be increased. Brief Description of the Drawings

[0034] Figure 1 It is a flow chart of the method steps of the present invention;

[0035] Figure 2 It is a circuit topology diagram before logic replication;

[0036] Figure 3 It is a circuit topology diagram after logic replication. Detailed Embodiments

[0037] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention.

[0038] Among them, the same components are denoted by the same reference numerals. It should be noted that the terms "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to the directions in the drawings, and the terms "bottom surface" and "top surface", "inner" and "outer" refer to the directions towards or away from the geometric center of a specific component, respectively.

[0039] The term "and / or" in the following text is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " generally represents an "or" relationship between the associated objects before and after.

[0040] With the continuous progress of semiconductor technology, VLSI design has become increasingly complex. In order to ensure the functional correctness of a chip before tape-out and reduce the costs caused by design errors, due to its reconfigurable hardware environment, high verification speed, accuracy, and low cost, FPGAs are widely used in the prototype verification of VLSI design. And prototype verification is a crucial stage to ensure the success of VLSI design. As the scale of integrated circuit design becomes larger and larger, it is difficult for a hardware simulation platform to simulate a design with a scale of up to billions of gates using a single FPGA. Therefore, multi-FPGA systems are widely used to handle such projects. For example, in practical applications, a large-scale design may call a system containing dozens of FPGAs, and the way of dividing circuit logic units will directly affect the performance of the multi-FPGA system, including the effective utilization of logic array resources, high signal transmission speed, low communication latency, etc. In this scenario, a high-quality method is needed to partition the logic units of a large number of DUTs (devices under test) onto different FPGAs for deployment.

[0041] As Figure 1 shown, the embodiment of the present application provides a hypergraph partitioning method considering logic replication in a multi-FPGA system, which is characterized by including:

[0042] Dividing a plurality of logic units in the hypergraph to be partitioned into a plurality of FPGAs, and forming a first corresponding relationship between each FPGA and each logic unit currently corresponding to the configuration;

[0043] Perform the first iterative operation. The first iterative operation includes randomly selecting an FPGA and a logic unit, and finding the first corresponding relationship of the logic unit. Among them, the randomly selected FPGA and the randomly selected logic unit form a second corresponding relationship. Determine whether the first corresponding relationship is consistent with the second corresponding relationship. If not, use the second corresponding relationship to add the logic units currently corresponding to the randomly selected FPGA to obtain the currently accepted segmentation method of the hypergraph to be segmented until the preset termination condition is met;

[0044] Output the current best segmentation method. The current best segmentation method is the segmentation method corresponding to the hypergraph to be segmented with the minimum communication delay among the hypergraphs to be segmented after each iteration at the current iteration number.

[0045] Among them, the hypergraph to be segmented shows the positions of each logic unit in the multi-FPGA system in the unsegmented state and the connection relationships between each logic unit. Each logic unit is regarded as a node, and each connection relationship is regarded as a "hyperedge"; each FPGA only forms a first corresponding relationship with each logic unit currently corresponding to the configuration. That is, as the iterative operation progresses, when the logic units currently configured by each FPGA change, the first corresponding relationship also changes.

[0046] If the above judgment result is yes, delete the randomly selected logic unit from the FPGA in its first corresponding relationship to obtain the currently accepted segmentation method of the hypergraph to be segmented until the preset termination condition is met.

[0047] Specifically, the currently accepted segmentation method of the hypergraph to be segmented obtained in each iteration needs to be determined according to the currently accepted segmentation method of the hypergraph to be segmented obtained in the adjacent previous iterative operation, which is equivalent to being determined according to the segmentation method obtained in the adjacent previous iterative operation. The determination steps are as follows: First, determine whether to accept the step of adding the logic units currently corresponding to the randomly selected FPGA. If accepted, the currently accepted segmentation method of the hypergraph to be segmented obtained in the current iteration is the segmentation method corresponding to the hypergraph to be segmented obtained after performing the step of accepting to add the logic units currently corresponding to the randomly selected FPGA or the step of accepting to delete the randomly selected logic unit from the FPGA in its first corresponding relationship; if not accepted, the currently accepted segmentation method of the hypergraph to be segmented obtained in the current iteration is the segmentation method obtained in the adjacent previous iterative operation.

[0048] Among them, the step of determining whether the first correspondence is consistent with the second correspondence can be carried out with an FPGA or a logic unit as the main body. Exemplarily, if an FPGA is used as the main body, determining whether the first correspondence is consistent with the second correspondence is equivalent to determining whether the FPGA in the first correspondence of a randomly selected logic unit is the same as the randomly selected FPGA; if a logic unit is used as the main body, it is equivalent to determining whether the logic unit is within the first correspondence of a randomly selected FPGA.

[0049] After dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs in this embodiment, through a logic replication algorithm, that is, using simulated annealing to selectively replicate logic units, the number of "hyperedges" across FPGAs is reduced, thereby reducing the latency caused by cross-FPGA communication.

[0050] Further, if the first correspondence is inconsistent with the second correspondence, between the step of adding the logic unit of the currently corresponding configuration of the randomly selected FPGA with the second correspondence and the step of obtaining the currently accepted partitioning method of the hypergraph to be partitioned, the above first iterative operation further includes:

[0051] Calculating the communication latency of the hypergraph to be partitioned after adding the logic unit of the currently corresponding configuration of the randomly selected FPGA;

[0052] According to the communication latency, determining whether to accept the step of adding the logic unit of the currently corresponding configuration of the randomly selected FPGA;

[0053] If so, determining whether to update the current best partitioning method with the partitioning method obtained in this iterative operation.

[0054] Further, this embodiment provides a step of determining whether to accept adding the logic unit of the currently corresponding configuration of the randomly selected FPGA according to the communication latency, including:

[0055] If the communication latency is less than the communication latency corresponding to the partitioning method obtained in the previous iterative operation, accepting the step of adding the logic unit of the currently corresponding configuration of the randomly selected FPGA;

[0056] If the communication latency is greater than or equal to the communication latency corresponding to the partitioning method obtained in the previous iterative operation, determining whether to accept the step of adding the logic unit of the currently corresponding configuration of the randomly selected FPGA according to a preset probability formula, and the probability formula is obtained based on the simulated annealing algorithm.

[0057] Further, if the first correspondence is consistent with the second correspondence, between the step of deleting the randomly selected logic unit from the FPGA in its first correspondence and the step of obtaining the currently accepted partitioning method of the hypergraph to be partitioned, the first iterative operation further includes:

[0058] Calculate the communication delay of the hypergraph to be partitioned after randomly selected logic units are deleted from the FPGAs in their first corresponding relationships;

[0059] Judge whether to accept the step of deleting randomly selected logic units from the FPGAs in their first corresponding relationships according to the communication delay;

[0060] If so, determine whether to update the current best partitioning method with the partitioning method obtained in the current iteration operation.

[0061] Furthermore, this embodiment provides a step of judging whether to accept the step of deleting randomly selected logic units from the FPGAs in their first corresponding relationships according to the communication delay, including:

[0062] If the communication delay is less than the communication delay corresponding to the partitioning method obtained in the previous iteration operation, accept the step of deleting randomly selected logic units from the FPGAs in their first corresponding relationships;

[0063] If the communication delay is greater than or equal to the communication delay corresponding to the partitioning method obtained in the previous iteration operation, judge whether to accept the step of deleting randomly selected logic units from the FPGAs in their first corresponding relationships according to a preset probability formula.

[0064] Through the preset probability formula, this embodiment can, to a certain extent, accept the step of adding logic units to the current corresponding configurations of randomly selected FPGAs or the step of deleting randomly selected logic units from the FPGAs in their first corresponding relationships, so as to avoid falling into the local optimum situation and improve the possibility of finding the global optimum partitioning method.

[0065] Furthermore, this embodiment provides a step of determining whether to update the current best partitioning method with the partitioning method obtained in the current iteration operation, including:

[0066] Search for the communication delay corresponding to the current best partitioning method, and compare its size with the communication delay corresponding to the partitioning method obtained in the current iteration operation;

[0067] If the communication delay corresponding to the current best partitioning method is greater than the communication delay corresponding to the partitioning method obtained in the current iteration operation, update the current best partitioning method.

[0068] Among them, the partitioning method obtained in this iteration operation is the partitioning method currently accepted by the hypergraph to be partitioned obtained in this iteration operation; the communication delay corresponding to the partitioning method obtained in this iteration operation, when the first correspondence relationship is inconsistent with the second correspondence relationship, is the communication delay of the hypergraph to be partitioned obtained after accepting the step of adding the logic units of the currently corresponding configuration of the randomly selected FPGA, and when the first correspondence relationship is consistent with the second correspondence relationship, is the communication delay of the hypergraph to be partitioned obtained after accepting the step of deleting the randomly selected logic units from the FPGA in its first correspondence relationship.

[0069] Furthermore, before performing the first iteration operation, the above hypergraph partitioning method considering logic replication in a multi-FPGA system further includes setting initial parameters, where the initial parameters include the initial communication delay, the initial temperature, the cooling rate, and the termination temperature.

[0070] Furthermore, after updating the current best partitioning method according to the judgment result, the above hypergraph partitioning method considering logic replication in a multi-FPGA system further includes updating the current temperature according to the cooling rate.

[0071] Specifically, first define four parameters of the simulated annealing algorithm function SimulatedAnnealing: initSol (initial communication delay), initTemp (initial temperature), coolRate (cooling rate), stopCond (termination temperature), and initialize the current solution currSol to the input initSol, indicating that the algorithm starts from this initial solution:

[0072] Solution currSol = initSol

[0073] Among them, currSol will be continuously updated in subsequent iterations, and the determined initial temperature should be relatively high to increase the probability of accepting a worse solution in the early stage.

[0074] Then initialize the current temperature currTemp to the input initTemp:

[0075] double currTemp = initTemp

[0076] And calculate the communication delay of the current solution currSol through totaltime(currSol), and save it as bestVal. bestVal is used to compare the quality of different solutions to determine whether the current solution is better:

[0077] double bestVal = totaltime(currSol)

[0078] Then randomly select a pin and pair it with an FPGA to obtain a new pairing group:

[0079] Solution newSol = genNeighbor(currSol)

[0080] double currVal = totaltime(currSol)

[0081] double newVal = totaltime(newSol)

[0082] Among them, newSol represents a newly randomly selected pairing group, currVal represents the communication delay corresponding to the initial solution totaltime(currSol), and newVal represents the communication delay corresponding to the new solution totaltime(newSol), where the new solution is obtained by performing the first iteration operation on the new pairing group.

[0083] Specifically, first perform a logical replication operation on the new pairing group, that is, if the logical unit in the new pairing group is located in the FPGA in the new pairing group, then delete the logical unit in the FPGA; if the logical unit in the new pairing group is not located in the FPGA in the new pairing group, then copy the logical unit to the FPGA.

[0084] After performing this operation, if the communication delay of the hypergraph to be partitioned obtained is smaller, then directly accept this operation.

[0085] If after performing the above operation on the new pairing group, the communication delay of the hypergraph to be partitioned is worse instead, then determine whether to accept this operation according to a preset probability formula. The probability formula is determined based on the difference between the current temperature and the termination temperature. The higher the current temperature, the greater the probability of accepting this operation:

[0086] if(newVal < currVal || rand(0.0, 1.0) < exp(-(newVal - currVal) / currTemp))

[0087] According to the judgment result, obtain the currently accepted partitioning method and the current best partitioning method of the hypergraph to be partitioned, where the currently accepted partitioning method of the hypergraph to be partitioned is the new solution.

[0088] Finally, reduce the temperature according to the cooling rate coolRate, so that as the iteration progresses, the algorithm gradually converges and the chance of accepting a poor solution is reduced. When the temperature drops below the set termination condition stopCond, the main loop exits, the algorithm ends, the current best partitioning method is output, and the hypergraph to be partitioned is partitioned according to this output result.

[0089] After dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs in this embodiment, through the logic replication algorithm, the logic units are selectively replicated in an annealing manner to reduce the number of "hyperedges" across FPGAs, thereby further reducing communication latency. And through the annealing manner, it is ensured that the search scope can cover the entire solution space to avoid obtaining invalid solutions, where the gain in the annealing manner is set as the change amount of communication latency.

[0090] Furthermore, this embodiment provides a step of dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs, including: dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logic unit and the maximum resource constraint of each FPGA, and the weight of each logic unit is determined according to the usage amount of each resource by each logic unit.

[0091] Among them, the maximum resource constraint of each FPGA means that the usage amount of each type of resource on each FPGA does not exceed the upper limit, where the types of resources include FF (flip-flop), LUT (lookup table), BUFG (global buffer), TBUF (tri-state buffer), DCM (digital clock manager), BRAM (block random access memory), DSP (digital signal processor), PP (preprocessor), etc.

[0092] This embodiment takes into account that each logic unit needs to occupy various resources in the multi-FPGA system when implementing logical functions. For example, if a logic unit wants to implement a combinational logic function, such as logical operations like AND, OR, NOT, etc., it needs to use a LUT to store the truth table of the logical function, and find and output the corresponding logical result according to the input signal through the LUT to complete the combinational logic function. If a logic unit needs to process a large amount of data storage and reading operations, such as caching data, storing configuration information, etc., it needs to use BRAM. Therefore, this embodiment determines the weight according to the usage amount of each resource by each logic unit, which can better control the resource usage of each partition area during the partitioning process, reduce resource conflicts, and optimize the partitioning result.

[0093] Furthermore, this embodiment provides a method for dividing multiple logic units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logic unit and the maximum resource constraint of each FPGA, including:

[0094] Perform a first partitioning on all logic units according to the weight of each logic unit, so that each FPGA is initially configured with at least one logic unit;

[0095] For each FPGA, if the initial configuration does not meet its corresponding maximum resource constraint, obtain the corresponding min-heap priority queue for this FPGA according to each logic unit that occupies overloaded resources in this FPGA;

[0096] For each small top - heap priority queue, perform a second iterative operation. The second iterative operation includes: taking out the logical unit at the head of the queue from the small top - heap priority queue, establishing a large top - heap priority queue according to the connection degree of this logical unit with each FPGA, where each serial number in the large top - heap priority queue corresponds to each FPGA one by one, and performing a moving operation on each logical unit occupying overloaded resources according to the large top - heap priority queue until the small top - heap priority queue is empty.

[0097] A small top - heap is a data structure implemented based on a complete binary tree, where the value of each parent node is less than or equal to the value of its child nodes to implement a priority queue. The root node is the smallest element in the heap, supporting efficient insertion and deletion operations. The large top - heap is similar to the implementation of the small top - heap, except that the value of each parent node in the large top - heap is greater than or equal to the value of its child nodes, and the root node is the largest element in the heap.

[0098] In this embodiment, multiple logical units in the original hypergraph are divided according to the weight of each logical unit. In the multi - level division algorithm, at least one logical unit is initially configured for each FPGA, and then it is judged whether the initial configuration of each FPGA meets its corresponding maximum resource constraint. Finally, without exceeding the maximum resource constraint, an optimal division scheme for deploying the designed circuit in a multi - FPGA system is automatically explored, so that the explored circuit division scheme meets the maximum resource constraint of the FPGA.

[0099] Furthermore, this embodiment provides a method for obtaining the small top - heap priority queue corresponding to each FPGA according to each logical unit occupying overloaded resources in the FPGA, including:

[0100] Obtain the connection degree between each logical unit occupying overloaded resources and the FPGA where it is currently located;

[0101] Obtain the small top - heap priority queue corresponding to each FPGA according to the connection degree.

[0102] Furthermore, this embodiment provides a method for performing a moving operation on each logical unit occupying overloaded resources according to the large top - heap priority queue, including:

[0103] Take out the sequence number at the head of the queue from the max heap priority queue, and determine whether the logic unit at the head of the queue can be moved to the FPGA corresponding to the sequence number at the head of the queue under the condition of meeting the maximum resource constraint of the FPGA corresponding to the sequence number at the head of the queue. If not, repeat the step of taking out the sequence number at the head of the queue from the max heap priority queue and making the judgment until the logic unit at the head of the queue can be moved to the FPGA corresponding to the current sequence number at the head of the queue under the condition of meeting the maximum resource constraint of the FPGA corresponding to the current sequence number at the head of the queue;

[0104] Move the logic unit at the head of the queue to the FPGA corresponding to the current sequence number at the head of the queue.

[0105] Among them, in the max heap priority queue, the higher the connection degree of the FPGA to the logic unit at the head of the queue, the higher the priority, and the closer the position of its corresponding sequence number in the max heap priority queue is to the head of the queue.

[0106] Specifically, after initially configuring at least one logic unit for each FPGA according to the first division, judge whether each FPGA meets its corresponding maximum resource constraint according to the resource usage amount required by each logic unit initially configured in each FPGA when implementing the logic function. The situations where each FPGA does not meet the maximum resource constraint are different. For example, the usage amount of LUT in a certain FPGA exceeds the upper limit, the usage amount of FF in a certain FPGA exceeds the upper limit, and the usage amounts of LUT and FF in a certain FPGA both exceed the upper limit.

[0107] Then, for each FPGA whose initial configuration does not meet its corresponding maximum resource constraint, obtain the min heap priority queue corresponding to the FPGA according to each logic unit occupying overloaded resources in the FPGA. The overloaded resources are those whose usage amounts exceed the upper limit. Since there may be multiple resources in a single FPGA whose usage amounts exceed the upper limit, a single such FPGA may correspond to multiple min heap priority queues. In each min heap priority queue, the lower the connection degree of the logic unit to the current FPGA where it is located, the higher the priority, that is, the closer its position in the min heap priority queue is to the head of the queue.

[0108] After that, perform the second iterative operation on each min heap priority queue so that each FPGA after the movement operation can meet the maximum resource constraint.

[0109] In this embodiment, first, all logical units are subjected to a first partitioning according to the weights of each logical unit. Preferably, the method of the first partitioning is a multi-level partitioning algorithm. For some FPGAs, if the resources required by the logical units assigned to this part of the FPGA exceed the maximum resource constraint condition of this part of the FPGA, it is determined as a violation. Then, by performing a moving operation on the logical units, multiple logical units in the hypergraph to be partitioned can be partitioned into multiple FPGAs without increasing the total number of logical units; if after the first partitioning, each FPGA can meet its corresponding maximum resource constraint condition, there is no need to perform subsequent steps.

[0110] Exemplarily, as Figure 2 shown is a brief circuit topology diagram before logic replication, representing the interconnection of modules in the circuit. In the figure, two rectangles represent two FPGAs, and the letters A, B, C, D, E, and F represent different logical units. According to the partitioning method in the figure, the communication from logical unit B to C, D, and E are all cross-FPGA communications, with a total of 3 cross-FPGA communication links. If node B is moved to FPGA 2, it will bring two new cross-FPGA communication links, namely A—B and B—F. However, if a copy of node B is made and placed in FPGA 2, as Figure 3 shown, then there is only one cross-FPGA communication link left, which is A—B. Since the propagation delay of signals between FPGAs is much higher than that inside FPGAs, copying specific circuit logics in some FPGAs to other FPGAs to reduce the frequency of cross-FPGA communication can significantly reduce the communication delay.

[0111] Therefore, by copying some logical units to other FPGAs, at the cost of an increase in resource usage, the cross-FPGA communication frequency of logical units can be reduced, thereby significantly reducing the total communication delay, obtaining a better partitioning effect, and optimizing the system performance. Among them, it is still necessary to ensure that the FPGA resource usage does not exceed the limit before copying the logical units. The logical units generated by copying need to completely receive the input signals and can only send signals to nodes within the same FPGA.

[0112] A hypergraph partitioning method considering logic replication in a multi-FPGA system provided by an embodiment of this application can reduce the communication delay of the system by reducing the number of cross-FPGA communication edges. Compared with the traditional partitioning method that does not change the number of logical units, by using the logic replication method under the simulated annealing algorithm, the cross-FPGA communication delay can be reduced while increasing a certain number of logical units, optimizing the system performance, having good practical application value, and through the setting of termination conditions, a final partitioning result that is beneficial to timing optimization and easy for internal placement and routing of FPGAs can be given within a controllable time.

[0113] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0114] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0115] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0116] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A hypergraph partitioning method considering logic replication in a multi-FPGA system, characterized in that Including: Dividing multiple logical units in the hypergraph to be partitioned into multiple FPGAs, and forming a first corresponding relationship between each FPGA and each logical unit currently corresponding to the configuration; Performing a first iterative operation, the first iterative operation includes randomly selecting an FPGA and a logical unit, looking up the first corresponding relationship of the logical unit, where the randomly selected FPGA and the randomly selected logical unit form a second corresponding relationship, determining whether the first corresponding relationship is consistent with the second corresponding relationship, if not, using the second corresponding relationship to increase the logical units currently corresponding to the configuration of the randomly selected FPGA, obtaining the current accepted partitioning method of the hypergraph to be partitioned until a preset termination condition is met; Outputting the current best partitioning method, the current best partitioning method being the partitioning method corresponding to the hypergraph to be partitioned with the minimum communication delay among the hypergraphs to be partitioned after each iteration at the current iteration number.

2. The hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 1, characterized in that Between the step of using the second corresponding relationship to increase the logical units currently corresponding to the configuration of the randomly selected FPGA and the step of obtaining the current accepted partitioning method of the hypergraph to be partitioned, the first iterative operation further includes: Calculating the communication delay of the hypergraph to be partitioned after increasing the logical units currently corresponding to the configuration of the randomly selected FPGA; Judging whether to accept the step of increasing the logical units currently corresponding to the configuration of the randomly selected FPGA according to the communication delay; If so, determining whether to update the current best partitioning method with the partitioning method obtained in the current iterative operation.

3. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 2, characterized in that The step of judging whether to accept the step of increasing the logical units currently corresponding to the configuration of the randomly selected FPGA according to the communication delay includes: If the communication delay is less than the communication delay corresponding to the partitioning method obtained in the previous iterative operation, accepting the step of increasing the logical units currently corresponding to the configuration of the randomly selected FPGA; If the communication delay is greater than or equal to the communication delay corresponding to the partitioning method obtained in the previous iterative operation, judging whether to accept the step of increasing the logical units currently corresponding to the configuration of the randomly selected FPGA according to a preset probability formula, the probability formula being obtained based on the simulated annealing algorithm.

4. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 2, characterized in that The determining whether to update the current best partitioning method with the partitioning method obtained in the current iterative operation includes: Looking up the communication delay corresponding to the current best partitioning method and comparing its size with the communication delay corresponding to the partitioning method obtained in the current iterative operation; If the communication delay corresponding to the current best partitioning method is greater than the communication delay corresponding to the partitioning method obtained in the current iterative operation, then updating the current best partitioning method.

5. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 2, characterized in that, Before performing the first iterative operation, the hypergraph partitioning method considering logical replication in a multi-FPGA system further includes setting initial parameters, the initial parameters including an initial communication delay, an initial temperature, a cooling rate, and a termination temperature.

6. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 5, characterized in that, After updating the current best partitioning method according to the judgment result, the hypergraph partitioning method considering logical replication in a multi-FPGA system further includes updating the current temperature according to the cooling rate.

7. A hypergraph partitioning method considering logical replication in a multi-FPGA system according to claim 1, characterized in that Partitioning multiple logical units in the hypergraph to be partitioned into multiple FPGAs includes: partitioning the multiple logical units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logical unit and the maximum resource constraint of each FPGA, where the weight of each logical unit is determined according to the usage amount of each logical unit for each resource.

8. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 7, characterized in that, The step of partitioning the multiple logical units in the hypergraph to be partitioned into multiple FPGAs according to the weight of each logical unit and the maximum resource constraint of each FPGA includes: Performing a first partitioning on all logical units according to the weight of each logical unit, so that each FPGA is initially configured with at least one logical unit; For each FPGA, if the initial configuration does not meet its corresponding maximum resource constraint, a minimum heap priority queue corresponding to the FPGA is obtained according to each logical unit occupying overloaded resources in the FPGA; For each minimum heap priority queue, a second iterative operation is performed. The second iterative operation includes: taking out the logical unit at the head of the queue from the minimum heap priority queue, establishing a maximum heap priority queue according to the connection degree between the logical unit and each FPGA, where each serial number in the maximum heap priority queue corresponds to each FPGA one by one, and performing a moving operation on each logical unit occupying overloaded resources according to the maximum heap priority queue until the minimum heap priority queue is empty.

9. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 8, characterized in that The step of obtaining the minimum heap priority queue corresponding to the FPGA according to each logical unit occupying overloaded resources in the FPGA includes: Obtaining the connection degree between each logical unit occupying overloaded resources and the FPGA where it is currently located; Obtaining the minimum heap priority queue corresponding to each FPGA according to the connection degree.

10. A hypergraph partitioning method considering logic replication in a multi-FPGA system according to claim 8, characterized in that, The step of performing a moving operation on each logical unit occupying overloaded resources according to the maximum heap priority queue includes: Taking out the serial number at the head of the queue from the maximum heap priority queue, determining whether the logical unit at the head of the queue can be moved to the FPGA corresponding to the serial number at the head of the queue when meeting the maximum resource constraint of the FPGA corresponding to the serial number at the head of the queue. If not, repeat the step of taking out the serial number at the head of the queue from the maximum heap priority queue and making a judgment until the logical unit at the head of the queue can be moved to the FPGA corresponding to the current serial number at the head of the queue when meeting the maximum resource constraint of the FPGA corresponding to the current serial number at the head of the queue; Moving the logical unit at the head of the queue to the FPGA corresponding to the current serial number at the head of the queue.

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