Method for automatically generating MOS (Metal Oxide Semiconductor) transistor layout with standard cell structure
By adding power rails and ground rails to the MOS tube single finger Pcell, forming an independent unit structure, and horizontally mirroring and connection, the problem of inefficient automatic generation of MOS tube layout is solved, and automated layout is realized to adapt to the generation of standard unit structures of different technical nodes.
Patent Information
- Application Number
- CN202510296027.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-13
- Publication Date
- 2025-08-01
AI Technical Summary
The existing automatic generation method of MOS tube layout is inefficient, difficult to adapt to complex design rules, and lack of standardized structure, resulting in frequent manual adjustments and the inability to realize the automated layout of analog circuits.
By generating a single-finger Pcell of the MOS tube and adding a power rail and a ground rail to form an independent unit structure, horizontal mirroring and connection are performed, buffer structure is added, and MOS tube layout with standard unit structure is generated, and automated layout is achieved using digital automatic layout and wiring tools.
It realizes that the MOS tube layout is automatically generated without manual adjustment, which is efficient, complies with design specifications, supports digital-to-analog hybrid circuit layout automation, adapts to different technical nodes, and has the ability to splice with digital standard units.
Smart Images
Figure CN120409403A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for automatically generating a MOS transistor layout, and more particularly to a method for automatically generating a MOS transistor layout having a standard cell structure. Background Art
[0002] Traditional analog circuits, analog and mixed-signal circuit layouts usually rely on manual design, resulting in a long design cycle, low efficiency, and requiring high professional knowledge in the design of high-performance analog circuits. In addition, existing layout methods often have difficulty adapting to the complex design rules of advanced process nodes, restricting the design flexibility and reusability. In recent years, with the rapid development of digital circuit design, the technology of automatic placement and routing (PnR) of digital standard cells has gradually matured, but the design support for analog circuits is still insufficient. Therefore, there is an urgent need for a new type of cell structure to improve this situation.
[0003] Currently, the parameterized cell (Pcell) plays an important role in the field of integrated circuit design. It allows users to customize parameters when creating cells. Such cells are programmable, and by defining different parameter values, various variants can be generated to meet different specifications or performance requirements. A Pcell can be regarded as a programmable cell, and its shape and function are defined by changes in parameters, enabling designers to adjust the behavior of the cell by adjusting parameters without modifying the underlying graphics. When implementing a Pcell, it is necessary to define parameters, write code, and integrate the code into the library. A Pcell can quickly generate different layout versions through changes in parameters for iteration and optimization.
[0004] In modern integrated circuit design, MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors) are one of the core components that make up a circuit. To improve design efficiency and flexibility, designers have adopted the parametric cell (i.e., Pcell) technology to automatically generate MOS transistor layouts of different variants. When using the parametric cell technology to automatically generate MOS transistor layouts, a set of input parameters needs to be defined first. This set of input parameters is used to describe the key characteristics of the MOS transistor, such as gate length, gate width, source / drain region size, etc. Then, using the programming languages provided by EDA tools (such as Cadence Virtuoso or Synopsys CustomCompiler) (such as Verilog-A or Custom Script), a definition script for the parametric cell is written. The definition script needs to include the logic for generating the layout based on the input parameters, such as how to arrange the source / drain regions, the positions of the gates, and the layout of the metal connections. After running the definition script of the parametric cell, the EDA tool will automatically generate the corresponding MOS transistor layout according to the defined set of input parameters. The generated MOS transistor layout also needs to go through DRC (Design Rule Checking) and LVS (Layout Versus Schematic) checks to ensure that it complies with the process specifications and is correctly connected.
[0005] However, current Pcell tools often rely on fixed templates or limited parameter ranges, which restricts their ability to support diverse design requirements. This makes them less flexible and efficient when dealing with special design requirements. Especially in complex layout structures, the generated Pcells do not have a standard structure, and manual adjustment is still necessary. Therefore, when using the parametric cell technology to automatically generate MOS transistor layouts, it does not have a standardized structure similar to digital standard cells and cannot adapt to subsequent layout automation; in addition, manual adjustment is required, resulting in low efficiency. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide an automatic generation method for MOS transistor layouts with a standard cell structure that does not require manual adjustment after automatic generation of MOS transistor layouts, has high efficiency, and can support the layout automation of digital-analog hybrid circuits.
[0007] The technical solution adopted by the present invention to solve the above technical problem is: an automatic generation method for MOS transistor layouts with a standard cell structure, including the following steps:
[0008] Step 1: Generate a Pcell of a MOS transistor with a finger number of 1 and the same channel width and channel length as the MOS transistor whose layout is to be generated, and call it the MOS transistor single-finger Pcell;
[0009] Step 2: Add a power rail and a ground rail to the MOS transistor single-finger Pcell, and name the structure formed at this time the independent unit structure;
[0010] Step 3: Horizontally mirror the independent unit structure generated in Step 2 as the basic figure until the total number of independent unit structures is equal to the number of finger insertions of the MOS transistors in the layout to be generated. During the horizontal mirroring process, the subsequent horizontal mirroring is performed on the independent unit structure obtained in the previous step;
[0011] Step 4: Align all the independent unit structures obtained in Step 3 according to the width of their inner gate pins, arrange them horizontally, and horizontally connect the gate pins, source pins, and drain pins of all the independent unit structures using the second-layer metal (metal 2) to form an overall unit structure;
[0012] Step 5: Add gate pin markings at the gate pins of each independent unit structure of the overall unit structure generated in Step 4, add drain pin markings at the drain pins, and add source pin markings at the source pins. Also, add vias at the gate pins of each independent unit structure to connect the second-layer metal (metal 2) and the ga layer, add vias at the source pins to connect the second-layer metal (metal 2) and the od layer, and add vias at the drain pins to connect the second-layer metal (metal 2) and the od layer. At the same time, add a buffer structure on the left and right sides of the generated overall unit structure respectively. The buffer structure consists of virtual polysilicon, N-well, P-well, N-type doping region, and P-type doping region, and then generate the GDS file of the MOS transistor layout.
[0013] Compared with the prior art, the advantages of the present invention are as follows: After generating the MOS transistor single-finger Pcell, power rails and ground rails are added to the MOS transistor single-finger Pcell to form an independent unit structure. The independent unit structure can be regarded as a core similar to a Pcell of the same size, plus some peripheral structures. Each independent unit structure has power rails and ground rails. Such standardization ensures, on the one hand, that all independent unit structures have a unified height, and on the other hand, it also maintains horizontal spliceability, and helps to place all independent unit structures based on rows in the subsequent placement stage (horizontal mirroring) to form an overall unit structure. The addition of the buffer structure ensures that when multiple MOS transistor layouts with standard unit structures are adjacent to each other left and right, enough spacing is left between adjacent MOS transistor layouts with standard unit structures through the buffer structure to avoid any DRC errors of gaps or overlaps, so that the automatic layout and routing of the MOS transistor layout can be realized by using a digital automatic placement and routing tool (APR). When automatically laying out the layout, there is no need to solve complex DRC and LVS problems, and there is no need for further manual adjustment, which greatly reduces the time and cost required for layout drawing. The required MOS transistor layout can be generated within a few seconds, ensuring that the generated MOS transistor layout meets the design specifications and can precisely meet the performance requirements of the MOS transistor, fully meeting the needs of MOS transistor layout design. Thus, after the automatic generation of the MOS transistor layout, there is no need for manual adjustment, and the efficiency is relatively high; at the same time, source pin markings, drain pin markings, and gate pin markings are automatically added during the generation process, and vias are added to the source pins, drain pins, and gate pins respectively to connect different metal layers, which can optimize the problems that need to be manually added during subsequent use and greatly improve the efficiency. By adding peripheral structures (such as power rails, ground rails, buffer structures, etc.), it can be universal at different technology nodes. After verification, applying to 28nm and 65nm PDKs can both achieve MOS transistor layouts with standard structures; standardize the horizontal width and vertical height of the independent unit structure. The horizontal width and vertical height of the independent unit structure are integer multiples of the central poly pitch (CPP) and the power-ground (P / G) pitch (PGP) respectively. All independent unit structures have power rails and ground rails. Such standardization ensures that the heights of all independent unit structures are consistent and maintains horizontal spliceability, facilitating the subsequent row-based placement of independent unit structures, so that they can be seamlessly spliced with digital standard units, and the generated layout meets DRC and LVS rules, and realizes the symmetry and matching constraints of analog circuits through hierarchical PnR; thus, after the automatic generation of the MOS transistor layout, the present invention does not require manual adjustment, has relatively high efficiency, and can support the automation of mixed-signal circuit layouts.
[0014] Further, in step 2, the power supply track and the ground track are copied from the power supply track and the ground track in the standard inverter structure in the corresponding process digital standard cell library.
[0015] Further, in step 5, the buffer structure on the left side of the overall cell structure is formed by intercepting the left part of the layout and routing boundary PRBoundary in the standard inverter structure in the corresponding process digital standard cell library and the part that expands to the right by a distance of Contacted Poly Pitch (CPP) in a DRC rule, and then copying it to the left side of the overall cell structure. The buffer structure on the right side of the overall cell structure is formed by intercepting the right part of the layout and routing boundary PRBoundary in the standard inverter structure in the corresponding process digital standard cell library and the part that expands to the left by a distance of Contacted Poly Pitch (CPP) in a DRC rule, and then copying it to the right side of the overall cell structure. Description of the Drawings
[0016] Figure 1 Flowchart of the automatic MOS transistor layout generation method with a standard cell structure according to the present invention;
[0017] Figure 2 Schematic diagram of an existing single-finger Pcell;
[0018] Figure 3 Schematic diagram of a single-finger Pcell of a MOS transistor in the automatic MOS transistor layout generation method with a standard cell structure according to the present invention;
[0019] Figure 4 Schematic diagram of the standard inverter structure in the digital standard cell library;
[0020] Figure 5 Schematic diagram of adding a power supply track and a ground track in the automatic MOS transistor layout generation method with a standard cell structure according to the present invention;
[0021] Figure 6 Schematic diagram of the buffer structure in the automatic MOS transistor layout generation method with a standard cell structure according to the present invention;
[0022] Figure 7 Schematic diagram of generating a MOS transistor layout with a length of 60 nm and a width of 480 nm in a 28 nm PDK by using the automatic MOS transistor layout generation method with a standard cell structure according to the present invention;
[0023] Figure 8Schematic diagram of generating a MOS transistor layout with a length of 600 nm and a width of 420 nm in a 65 nm PDK using the MOS transistor layout automatic generation method with a standard cell structure of the present invention. Detailed implementation mode
[0024] The present invention will be further described in detail below in conjunction with the embodiments with reference to the drawings.
[0025] Embodiment 1: As Figures 1 to 6 shown, an automatic generation method for a MOS transistor layout with a standard cell structure includes the following steps:
[0026] Step 1: Generate a MOS transistor Pcell with a finger number of 1 that has the same channel width and channel length as the MOS transistor of the layout to be generated, and call it the MOS transistor single-finger Pcell;
[0027] Step 2: Add power rails and ground rails to the MOS transistor single-finger Pcell, and call the structure formed at this time the independent unit structure;
[0028] Step 3: Horizontally mirror the independent unit structure generated in Step 2 as the basic figure until the total number of independent unit structures is equal to the finger number of the MOS transistor of the layout to be generated. During the horizontal mirroring process, the subsequent horizontal mirroring is performed on the independent unit structure obtained in the previous time;
[0029] Step 4: Align all the independent unit structures obtained in Step 3 according to the width of their inner gate pins and arrange them horizontally. Since the gate pins, source pins, and drain pins in each independent unit structure are all in the second-layer metal metal2, horizontally connect the gate pins, source pins, and drain pins in all the independent unit structures using the second-layer metal metal 2 to form an overall unit structure;
[0030] Step 5: Add gate pin markings at the gate pins of each independent unit structure of the overall unit structure generated in Step 4, drain pin markings at the drain pins, and source pin markings at the source pins. Additionally, add vias on the gate pins of each independent unit structure to connect the second layer of metal (metal 2) and the ga layer, add vias on the source pins to connect the second layer of metal (metal 2) and the od layer, and add vias on the drain pins to connect the second layer of metal (metal 2) and the od layer. At the same time, add a buffer structure on the left and right sides of the generated overall unit structure. The buffer structure consists of dummy poly, N Well, P Well, NP, and PP, and then generate the GDS file of the MOS transistor layout.
[0031] In this embodiment, after generating a single-finger Pcell of the MOS transistor, power rails and ground rails are added to the single-finger Pcell of the MOS transistor to form an independent unit structure. The independent unit structure can be regarded as a core similar to a Pcell of the same size, plus some peripheral structures. Each independent unit structure has power rails and ground rails. Such standardization ensures, on the one hand, that all independent unit structures have a unified height, and on the other hand, it also maintains horizontal spliceability and helps to place all independent unit structures based on rows in the subsequent placement stage (horizontal mirroring) to form an overall unit structure. The addition of the buffer structure ensures that when multiple MOS transistor layouts with standard unit structures are adjacent to each other left and right, enough spacing is left between adjacent MOS transistor layouts with standard unit structures through the buffer structure to avoid any DRC errors of gaps or overlaps. Thus, the automatic layout and routing of the layout can be achieved by using the Automated Place and Route (APR) tool. When automatically laying out the layout, there is no need to solve complex DRC and LVS problems and no further manual adjustment is required, greatly reducing the time and effort required for manual drawing. The required MOS transistor layout can be generated within a few seconds, ensuring that the generated MOS transistor layout meets the design specifications and can precisely meet the performance requirements of the MOS transistor, fully meeting the needs of MOS transistor layout design. In addition, the independent unit structure is horizontally mirror-copied according to the channel width and channel length required by the MOS transistor, so that the design requirements of MOS transistor layouts with any width and length can be achieved. Whether it is an NMOS transistor or a PMOS transistor, the MOS transistor layout has complementary doping regions (NP and PP) and N-wells and P-wells. These redundant structures are required for horizontal spliceability with any other unit (including digital standard cells). Therefore, when used in mixed-signal circuit design, it can be seamlessly connected to digital standard cells and can be arranged adjacently in all directions, thus realizing the application of an automatic digital PnR engine. Combining with digital standard cells can achieve the automatic layout and routing of analog mixed-signal circuits and has broad application prospects in analog mixed-signal circuits and analog circuits.
[0032] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, in step 2, the power rails and ground rails are copied according to the power rails and ground rails in the standard inverter structure in the corresponding process digital standard cell library.
[0033] In this embodiment, in step 5, the buffer structure on the left side of the overall unit structure is formed by intercepting the left part of the layout and routing boundary PRBoundary in the standard inverter structure in the corresponding process digital standard cell library, and the part that expands to the right by a Contacted Poly Pitch (CPP) distance in a DRC rule, and then copying it to the left side of the overall unit structure. The buffer structure on the right side of the overall unit structure is formed by intercepting the right part of the layout and routing boundary PRBoundary in the standard inverter structure in the corresponding process digital standard cell library, and the part that expands to the left by a Contacted Poly Pitch (CPP) distance in a DRC rule, and then copying it to the right side of the overall unit structure.
[0034] To verify the performance of the automatic generation method of the MOS transistor layout with a standard cell structure of the present invention, the automatic generation method of the MOS transistor layout with a standard cell structure in Embodiment 2 of the present invention is used to generate a MOS transistor layout with a standard cell structure that is 60 nm long and 480 nm wide in a 28 nm PDK and a MOS transistor layout with a standard cell structure that is 600 nm long and 420 nm wide in a 65 nm PDK, respectively. Among them, the MOS transistor layout with a standard cell structure that is 60 nm long and 480 nm wide generated in the 28 nm PDK is as Figure 7 shown, and the MOS transistor layout with a standard cell structure that is 600 nm long and 420 nm wide generated in the 65 nm PDK is as Figure 8 shown.
[0035] Figure 7 In, for the MOS transistor layout with a standard cell structure that is 60 nm long and 480 nm wide generated in the 28 nm PDK, the left and right sides are buffer structures composed of dummy poly, N / P Well, and N / P doping regions, the top and bottom are power rails and ground rails, and the middle position is a core structure similar to a Pcell. Figure 8 In, for the MOS transistor layout with a standard cell structure that is 600 nm long and 420 nm wide generated in the 65 nm PDK, it is composed of a MOS transistor single-finger Pcell plus power rails, ground rails, and buffer structures. After horizontal mirroring, the corresponding finger number is obtained, and then the corresponding gate pin label, source pin label, drain pin label, and vias are added.
[0036] Analysis Figure 7It can be known that the buffer structures on the left and right sides are composed of dummy poly, N Well, P Well, NP (N-type doped region), and PP (P-type doped region), ensuring sufficient spacing between adjacent independent unit structures in the MOS transistor layout, thus avoiding any DRC errors of gaps or overlaps and eliminating the need for further manual adjustment. When the total channel width (W) is large, wider finger structures are allowed, reducing the required number of fingers, and the buffer structure can improve the area utilization rate.
[0037] Analysis Figure 8 It can be known that each independent unit structure of the generated MOS transistor layout with a standard structure has power rails and ground rails. Such standardization ensures, on the one hand, that all independent unit structures have a unified height, and on the other hand, maintains horizontal spliceability, facilitating subsequent row-based placement of independent unit structures. Moreover, the source pins, drain pins, and gate pins are horizontally connected using the second layer of metal (metal 2) and placed on specific routing rails for easy routing, which can greatly adapt to layout automation and is not achievable by Pcells. The entire process is universal across different technology nodes.
[0038] After the above verification, the automatic generation method of the MOS transistor layout with a standard cell structure of the present invention is applied to 28nm PDK and 65nm PDK. All steps are the same, and the MOS transistor layout with a standard cell structure can be achieved.
[0039] In summary, for the automatic generation method of the MOS transistor layout with a standard cell structure of the present invention, after generating the single-finger Pcell of the MOS transistor, power rails and ground rails are added to form independent unit structures, and then the independent unit structures are horizontally mirrored according to the number of fingers of the MOS transistor and aligned according to the width of the gate pins, and horizontally arranged to form an overall unit structure. The gate pins, source pins, and drain pins in the overall unit structure are horizontally connected respectively by the second layer of metal (metal 2) to form routing rails. Source pin labels, drain pin labels, and gate pin labels are added respectively to each independent unit structure in the overall unit structure, and vias are added to the gate pins to connect the second layer of metal (metal 2) and the ga layer, vias are added to the source pins to connect the second layer of metal (metal 2) and the od layer, and vias are added to the drain pins to connect the second layer of metal (metal 2) and the od layer. A buffer structure is also added respectively to the left and right sides of the generated overall unit structure, and then the GDS file of the MOS transistor layout is generated. Therefore, after the automatic generation of the MOS transistor layout, no manual adjustment is required, the efficiency is high, and it can support the layout automation of mixed-signal circuits.
Claims
1. An automatic generation method for the layout of a MOS transistor with a standard cell structure, characterized in that The steps include the following: Step 1: Generate a MOS transistor Pcell with a finger number of 1 and the same channel width and channel length as the MOS transistors in the layout to be generated, and call it the MOS transistor single-finger Pcell; Step 2: Add power rails and ground rails to the MOS transistor single-finger Pcell, and call the resulting structure the independent unit structure; Step 3: Horizontally mirror the independent unit structure generated in Step 2 as the basic figure until the total number of independent unit structures is equal to the finger number of the MOS transistors in the layout to be generated. During the horizontal mirroring process, the subsequent horizontal mirroring is performed on the independent unit structure obtained in the previous step; Step 4: Align all the independent unit structures obtained in Step 3 according to the width of their internal gate pins, arrange them horizontally, and horizontally connect the gate pins, source pins, and drain pins of all the independent unit structures using the second-layer metal (metal 2) to form an integrated unit structure; Step 5: Add gate pin markings at the gate pins of each independent unit structure, drain pin markings at the drain pins, and source pin markings at the source pins of the integrated unit structure generated in Step 4. Also, add vias at the gate pins of each independent unit structure to connect the second-layer metal (metal 2) and the ga layer, add vias at the source pins to connect the second-layer metal (metal 2) and the od layer, and add vias at the drain pins to connect the second-layer metal (metal 2) and the od layer. At the same time, add a buffer structure on the left and right sides of the generated integrated unit structure respectively. The buffer structure consists of dummy polysilicon, N-well, P-well, N-type doped region, and P-type doped region, and then generate the GDS file of the MOS transistor layout.
2. The automatic generation method of a MOS transistor layout with a standard cell structure according to claim 1, wherein In Step 2, the power rails and the ground rails are copied according to the power rails and the ground rails in the standard inverter structure in the corresponding process digital standard cell library.
3. The automatic generation method of a MOS transistor layout with a standard cell structure according to claim 1, characterized in that In Step 5, the buffer structure on the left side of the integrated unit structure is formed by intercepting the left part of the layout and routing boundary (PRBoundary) in the standard inverter structure in the corresponding process digital standard cell library and the part extended to the right by a Contacted Poly Pitch (CPP) distance in a DRC rule, and then copying it to the left side of the integrated unit structure. The buffer structure on the right side of the integrated unit structure is formed by intercepting the right part of the layout and routing boundary (PRBoundary) in the standard inverter structure in the corresponding process digital standard cell library and the part extended to the left by a Contacted Poly Pitch (CPP) distance in a DRC rule, and then copying it to the right side of the integrated unit structure.