Wiring tuning method and system and storage medium

Abstract

The invention relates to a wiring tuning method and system and a storage medium, and the method comprises the steps: drawing a vertical reference line and a horizontal reference line according to a central point of an element, recording a first intersection point of a wiring path and the vertical reference line and a second intersection point of the wiring path and the horizontal reference line, and forming a wiring region; acquiring all obstacles in the wiring area to generate a first constraint condition; unifying the format of the first constraint condition of each obstacle through the value combination of the binary variables to obtain a second constraint condition; constructing a linear programming model, and inputting a second constraint condition into the linear programming model; solving the linear programming model to obtain an optimal wiring path point coordinate; redrawing a wiring path, and recording the wiring path as an optimized wiring path; verifying whether the optimized wiring path meets a preset rule constraint or not; if yes, outputting an optimized wiring path as a final wiring tuning result; the scientization and systematization of the optimization of the wiring path are realized, and the global optimality of the optimization result is ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a method, a system, and a storage medium for wiring optimization. Background Art

[0002] In modern electronic design, wiring technology is a key link to ensure circuit performance, stability, and reliability. Reasonable wiring directly affects the signal transmission quality, can reduce electromagnetic interference, ensure signal integrity, and optimize heat dissipation performance. In addition, a good wiring design can also reduce power consumption and improve the anti-interference ability of the system; unreasonable wiring may lead to signal transmission delay, timing deviation, increased electromagnetic interference, and even affect the normal operation of the device. Therefore, wiring technology is crucial.

[0003] With the help of the software drawing function of the computer, the wiring design can give the most reasonable wiring path after online editing, drawing, and multiple modifications. However, during the drawing process, there may be obstacles on the wiring path. Due to the irregular distribution of the obstacles, after wiring, the automatic wiring will have problems close to the obstacles. At this time, the wiring is not optimal and cannot achieve the best wiring effect, resulting in the wiring result not meeting all design rule constraints and unable to achieve legal wiring. Summary of the Invention

[0004] In view of the above problems, the present application provides a method, a system, and a storage medium for wiring optimization, which solve the problems that need to consider automatic wiring and the proximity of obstacles during the wiring process.

[0005] To achieve the above object, in a first aspect, the present invention provides a method for wiring optimization, including the following steps:

[0006] Draw a vertical reference line and a horizontal reference line according to the center points of the components, and record the first intersection point of the vertical reference line and the wiring path and the second intersection point of the horizontal reference line and the wiring path to form a wiring area;

[0007] Obtain all the obstacles within the wiring area and generate a first constraint condition for the wiring area and multiple obstacles;

[0008] Generate a corresponding binary variable for each obstacle, and unify the format of the first constraint condition for each obstacle through the value combination of the binary variables to obtain a second constraint condition;

[0009] Construct a linear programming model, and input the second constraint condition into the linear programming model. The second constraint condition includes at least one of the coordinate dependency relationship of the wiring path, the value range of the boundary points, the minimum line length constraint, and the obstacle spacing constraint;

[0010] Solve the linear programming model to obtain the coordinates of the optimal wiring path points;

[0011] Redraw the wiring path according to the optimal wiring path point coordinates, denoted as the optimized wiring path;

[0012] Verify whether the optimized wiring path meets the preset rule constraints;

[0013] If so, output the optimized wiring path as the final wiring optimization result.

[0014] In some embodiments, two components are respectively provided at both ends of the wiring path. Denote one component as the first component and the other component as the second component. The first component has a first vertical reference line and a first horizontal reference line, the second component has a second vertical reference line and a second horizontal reference line, and the wiring area has a first boundary and a second boundary;

[0015] The first boundary is configured to connect the first vertical reference line and the second horizontal reference line; or, the first boundary is configured to connect the first vertical reference line and the horizontal canvas edge of the PCB board; or, the first boundary is configured to connect the first horizontal reference line and the vertical canvas edge of the PCB board;

[0016] The second boundary is configured to connect the second vertical reference line and the first horizontal reference line; or, the second boundary is configured to connect the second vertical reference line and the horizontal canvas edge of the PCB board; or, the second boundary is configured to connect the second horizontal reference line and the vertical canvas edge of the PCB board.

[0017] In some embodiments, assume that the A i component, B i component, C i component, and D i component affected by the i-th obstacle along the extension direction of the wiring path. The linear programming model is represented by formula (1), and formula (1) is as follows:

[0018]

[0019] In formula (1), Z is the expression function of the linear programming model, N is the total number of obstacles in the wiring area, b i is the ordinate of the i-th obstacle, is the ordinate of the A i component in the wiring path, is the ordinate of the D i component in the wiring path, is the abscissa of the B i component in the wiring path, is the abscissa of the A i component in the wiring path.

[0020] In some embodiments, the first constraint condition includes a vertical coordinate constraint condition and a horizontal coordinate constraint condition. The vertical coordinate constraint condition is represented by formula (2), and formula (2) is as follows:

[0021]

[0022] In formula (2), is the vertical coordinate of component C in the wiring path i and is the vertical coordinate of component B in the wiring path i and is the horizontal coordinate of component C in the wiring path i and is the horizontal coordinate of component B in the wiring path i and b i-1 is the vertical coordinate of the (i - 1)-th obstacle i+2 and b

[0023] is the vertical coordinate of the (i + 2)-th obstacle;

[0024]

[0025] The horizontal coordinate constraint condition is represented by formula (3), and formula (3) is as follows: is the horizontal coordinate of component A in the wiring path i and is the horizontal coordinate of the (i - 1)-th obstacle i and a i+1 is the horizontal coordinate of the i-th obstacle i+2 and a is the horizontal coordinate of the (i + 1)-th obstacle i and a

[0026] In some embodiments, the second constraint condition is represented by formula (4), and formula (4) is as follows:

[0027]

[0028] In formula (4), α i is the first binary variable of the i-th obstacle, β i is the second binary variable of the i-th obstacle, and S i is the minimum spacing value between the i-th obstacle and the wiring path, and M is an integer constant.

[0029] In some embodiments, the preset rule constraints include a minimum spacing constraint, a minimum line length constraint, and a clockwise wiring constraint.

[0030] In some embodiments, the minimum spacing constraint is represented by formula (5) as follows:

[0031]

[0032] In formula (5), S i is the minimum spacing value of the i-th obstacle from the wiring path, R i is the influence length of the i-th obstacle on the wiring path, L i is the actual spacing of the i-th obstacle from the wiring path, and W is the half line width of the wiring path.

[0033] In some embodiments, the wiring path includes multiple wiring path segments, and the minimum spacing constraint is represented by formula (6) as follows:

[0034]

[0035] In formula (6), (x j+1 , y j+1 ) are the end coordinates of the wiring path segment, (x j , y j ) are the start coordinates of the wiring path segment, and L is the minimum line length.

[0036] In a second aspect, the present invention provides a wiring optimization system, and when the wiring optimization system is executed, it implements the method described in the first aspect.

[0037] In a third aspect, the present invention further provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, they implement the method described in the first aspect.

[0038] Different from the prior art, the above technical solution can accurately identify obstacles in the wiring area and provide clear boundary solution constraints for wiring path planning by introducing vertical reference lines, horizontal reference lines, a first constraint condition, and a second constraint condition; using binary variables to format the first constraint condition greatly simplifies the computational complexity and improves the optimization efficiency; the introduction of a linear programming model can comprehensively consider various situations and solve them correspondingly to ensure the global optimality of the optimization result; through strict verification steps, the feasibility and reliability of the optimized wiring path are guaranteed; this method can not only effectively reduce the wiring length, reduce signal interference, but also improve the automation degree and design efficiency of wiring, and is especially suitable for complex wiring environments and high-density circuit designs.

[0039] The above description of the invention content is only an overview of the technical solution of this application. In order to enable those of ordinary skill in the art to more clearly understand the technical solution of this application, and thus can be implemented according to the content described in the text of the specification and the drawings, and in order to make the above objects, other objects, features and advantages of this application more easily understood, the following is described in conjunction with the specific embodiments of this application and the drawings. Description of the Drawings

[0040] The drawings are only used to illustrate the principles, implementation methods, applications, features and effects of the specific embodiments of the present invention and other related contents, and should not be regarded as a limitation to this application.

[0041] In the drawings of the specification:

[0042] Figure 1 It is a schematic diagram of method steps S101 to S108 for wiring optimization according to the present invention;

[0043] Figure 2 It is a schematic diagram of linear programming for wiring optimization according to the first exemplary embodiment;

[0044] Figure 3 It is a schematic diagram of linear programming for wiring optimization according to the second exemplary embodiment;

[0045] Figure 4 It is a schematic diagram of linear programming for wiring optimization according to the third exemplary embodiment; Detailed Description of the Embodiments

[0046] In order to elaborate in detail on the possible application scenarios, technical principles, specific implementable solutions, achievable purposes and effects, etc. of this application, the following is described in detail in conjunction with the specific embodiments listed and the drawings. The embodiments described herein are only used to more clearly illustrate the technical solution of this application, so they are only examples and cannot be used to limit the protection scope of this application.

[0047] Referring to "embodiment" in this text means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various positions in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in this application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form the corresponding implementable technical solution.

[0048] Unless otherwise defined, the meanings of the technical terms used in this text are the same as those generally understood by those skilled in the technical field to which this application belongs; the use of relevant terms in this text is only for describing specific embodiments and is not intended to limit this application.

[0049] In the description of the present application, the term "and / or" is an expression used to describe the logical relationship between objects, indicating that there can be three relationships. For example, A and / or B means: there is A, there is B, and there is both A and B at the same time. In addition, the character " / " in this article generally represents an "or" logical relationship between the associated objects before and after.

[0050] In the present application, terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantitative, primary-secondary or sequential relationships between these entities or operations.

[0051] Without more limitations, in the present application, the open-ended expressions such as "comprising", "including", "having" or other similar expressions used in the statements are intended to cover non-exclusive inclusion. These expressions do not exclude that there may be additional elements in the process, method or product including the said elements, so that the process, method or product including a series of elements may not only include those defined elements, but also include other elements not explicitly listed, or also include elements inherent to this process, method or product.

[0052] Similar to the understanding in the "Examination Guidelines", in the present application, expressions such as "greater than", "less than", "exceeding" are understood not to include the present number; expressions such as "above", "below", "within" are understood to include the present number. In addition, in the description of the embodiments of the present application, the meaning of "a plurality of" is two or more (including two), and similar expressions related to "many" are also understood in this way, such as "multiple groups", "multiple times", etc., unless otherwise specifically limited.

[0053] Please refer to Figure 1 , in the first aspect, the present embodiment provides a method for wiring optimization, including the following steps:

[0054] S101. Draw a vertical reference line and a horizontal reference line according to the center point of the component, and record the first intersection point of the vertical reference line and the wiring path and the second intersection point of the horizontal reference line and the wiring path to form a wiring area;

[0055] S102. Obtain all obstacles within the wiring area and generate a first constraint condition for the wiring area and multiple obstacles;

[0056] S103. Generate a corresponding binary variable for each obstacle, and unify the format of the first constraint condition for each obstacle through the value combination of the binary variables to obtain a second constraint condition;

[0057] S104. Construct a linear programming model and input the second constraint condition into the linear programming model. The second constraint condition includes at least one of the coordinate dependence relationship of the wiring path, the value range of the boundary points, the minimum wire length constraint, and the obstacle spacing constraint.

[0058] S105. Solve the linear programming model to obtain the optimal coordinates of the wiring path points.

[0059] S106. Redraw the wiring path according to the optimal coordinates of the wiring path points, which is denoted as the optimized wiring path.

[0060] S107. Verify whether the optimized wiring path meets the preset rule constraints.

[0061] S108. If so, output the optimized wiring path as the final wiring optimization result.

[0062] In step S101, taking the center point of the component as the reference, draw a vertical reference line and a horizontal reference line, and record the first intersection point of the wiring path and the vertical reference line, and the second intersection point of the horizontal reference line and the wiring path, so as to clarify the scope of the wiring area. This not only provides a clear boundary for subsequent wiring but also provides an initial reference point for path planning. It can be understood that the method shown in this embodiment divides the multi-point legalized wiring problem into two-point legalized wiring problems in multiple local areas, and thus determines the minimum unit for implementing the detailed wiring algorithm.

[0063] In step S102, detect the obstacles in the wiring area and generate corresponding first constraint conditions for each obstacle. The constraint conditions may involve the position, size of the obstacle, and the minimum spacing from other wiring paths, etc.

[0064] In step S103, in order to uniformly process the constraint conditions, introduce binary variables, generate corresponding binary variables according to each obstacle, and unify the format of the first constraint condition of each obstacle through the value combination of the binary variables to obtain the second constraint condition, thereby simplifying the subsequent calculation process.

[0065] In step S104, construct a linear programming model and input the formatted second constraint condition into the linear programming model. The second constraint condition includes at least one of the coordinate dependence relationship of the wiring path, the value range of the boundary points, the minimum wire length constraint, and the obstacle spacing constraint.

[0066] In step S105, the linear programming model comprehensively considers multiple factors such as the coordinate dependence relationship of the wiring path, the value range of boundary points, the minimum wire length constraint, and the obstacle spacing constraint. Through mathematical optimization methods, the optimal coordinates of the wiring path points are solved. It can be understood that there may be countless feasible solutions that satisfy the second constraint condition. If there are multiple wire networks to be wired in the wiring area simultaneously, when wiring the current wire network, the wiring space in the plane should be occupied as little as possible to leave enough space for the remaining wire networks to be wired, so as to improve the overall wiring success rate. Preferably, the clockwise wiring rule should be followed during wiring, that is, within the wiring area, the loop area formed by starting from the wiring starting point, going clockwise around the rectangular boundary to the wiring end point, and then winding back to the wiring starting point by the wiring trajectory is as small as possible, thereby obtaining the optimal coordinates of the wiring path points.

[0067] In step S106, based on the optimal coordinates of the wiring path points, the wiring path is redrawn to form an optimized wiring path, denoted as the optimized wiring path.

[0068] In steps S107 and S108, by verifying whether the optimized wiring path meets the preset rule constraints, the feasibility and reliability of the optimization result are ensured; if the verification passes, the optimized wiring path is output as the final wiring optimization result.

[0069] In this embodiment, by introducing the vertical reference line, the horizontal reference line, the first constraint condition, and the second constraint condition, the obstacles in the wiring area can be accurately identified, and clear boundary solution constraints can be provided for the wiring path planning; using binary variables to format the first constraint condition greatly simplifies the computational complexity and improves the optimization efficiency; the introduction of the linear programming model can comprehensively consider various situations and solve them correspondingly to ensure the global optimality of the optimization result; through strict verification steps, the feasibility and reliability of the optimized wiring path are guaranteed; this method can not only effectively reduce the wiring length, reduce signal interference, but also improve the automation degree and design efficiency of wiring, and is especially suitable for complex wiring environments and high-density circuit designs.

[0070] Corresponding to the first aspect, in the second aspect, this embodiment provides a wiring optimization system, and when the wiring optimization system is executed, the method described in the first aspect is realized. The steps implemented by the optimization system shown in this embodiment are consistent with those in the foregoing first aspect, and will not be elaborated here.

[0071] In some embodiments, two components are respectively provided at both ends of the wiring path. One of the components is denoted as the first component, and the other component is denoted as the second component. The first component has a first vertical reference line and a first horizontal reference line, the second component has a second vertical reference line and a second horizontal reference line, and the wiring area has a first boundary and a second boundary;

[0072] The first boundary is configured to connect the first vertical reference line to the second horizontal reference line; alternatively, the first boundary is configured to connect the first vertical reference line to the horizontal canvas edge of the PCB board; alternatively, the first boundary is configured to connect the first horizontal reference line to the vertical canvas edge of the PCB board;

[0073] The second boundary is configured to connect the second vertical reference line to the first horizontal reference line; alternatively, the second boundary is configured to connect the second vertical reference line to the horizontal canvas edge of the PCB board; alternatively, the second boundary is configured to connect the second horizontal reference line to the vertical canvas edge of the PCB board.

[0074] In this embodiment, the components arranged at both ends of the wiring path are defined as the first component and the second component. The first component has a first vertical reference line and a first horizontal reference line, while the second component has a second vertical reference line and a second horizontal reference line. The boundaries of the wiring area are jointly defined by the first vertical reference line, the first horizontal reference line, the second vertical reference line, the second horizontal reference line, and the edges of the PCB board. This joint definition can be understood as the first boundary and the second boundary of the wiring area being affected by these factors comprehensively; that is, in this embodiment, the boundaries of the wiring area are constructed through the geometric features of the components and the boundary conditions of the PCB board, enabling the precise definition of the wiring area; the first boundary can have three configuration methods: one is that the first vertical reference line is connected to the second horizontal reference line to form a closed boundary; the second is that the first vertical reference line extends to the horizontal canvas edge of the PCB board, using the boundary of the PCB board as part of the wiring area; the third is that the first horizontal reference line extends to the vertical canvas edge of the PCB board, also using the boundary of the PCB board to define the wiring area; similarly, the second boundary also has three configuration methods: one is that the second vertical reference line is connected to the first horizontal reference line; the second is that the second vertical reference line extends to the horizontal canvas edge of the PCB board; the third is that the second horizontal reference line extends to the vertical canvas edge of the PCB board; the boundary configuration method shown in this embodiment can dynamically adjust the wiring area according to the positions of the components and the layout of the PCB board, ensuring that the planning of the wiring path not only meets the requirements of component connection but also makes full use of the space of the PCB board, while avoiding conflicts with other components or obstacles.

[0075] In this embodiment, by using the first vertical reference line and the first horizontal reference line of the first component, the second vertical reference line and the second horizontal reference line of the second component, and the edge of the PCB board as boundary conditions, it is possible to dynamically adjust the routing area according to different component layouts and PCB designs, avoiding the limitations of traditional fixed-boundary methods; the flexible boundary configuration method can maximize the utilization of the PCB board space, reduce the detours and redundancies of the routing paths, thereby reducing the routing length and signal delay; by accurately dividing the routing area, it is possible to effectively avoid conflicts between the routing paths and other components or obstacles, improving the reliability and success rate of routing; not only improving the degree of automation of routing, but also significantly enhancing the optimization effect of the routing paths, especially suitable for complex layouts and high-density PCB designs, providing strong support for the miniaturization and high performance of electronic devices.

[0076] In some embodiments, let the A i component, B i component, C i component, and D i component affected by the i-th obstacle along the extension direction of the routing path. The linear programming model is represented by formula (1), and formula (1) is as follows:

[0077]

[0078] In formula (1), Z is the expression function of the linear programming model, N is the total number of obstacles in the routing area, b i is the ordinate of the i-th obstacle, is the ordinate of the A i component in the routing path, is the ordinate of the D i component in the routing path, is the abscissa of the B i component in the routing path, is the abscissa of the A i component in the routing path.

[0079] In some embodiments, the first constraint condition includes the ordinate constraint condition and the abscissa constraint condition. The ordinate constraint condition is represented by formula (2), and formula (2) is as follows:

[0080]

[0081] In formula (2), is the ordinate of the C i component in the routing path, is the ordinate of the B i component in the routing path, is the abscissa of the C i component in the routing path, For B in the wiring path i The abscissa of the component, b i-1 Is the ordinate of the (i - 1)-th obstacle, b i+2 Is the ordinate of the (i + 2)-th obstacle;

[0082] The abscissa constraint condition is represented by formula (3), and formula (3) is as follows:

[0083]

[0084] In formula (3), For A in the wiring path i The abscissa of the component, a i-1 Is the abscissa of the (i - 1)-th obstacle, a i Is the abscissa of the i-th obstacle, a i+1 Is the abscissa of the (i + 1)-th obstacle, a i+2 Is the abscissa of the (i + 2)-th obstacle, For D in the wiring path i The abscissa of the component, L is the minimum line length of the wiring path segment in the wiring path.

[0085] In some embodiments, the second constraint condition is represented by formula (4), and formula (4) is as follows:

[0086]

[0087] In formula (4), α i Is the first binary variable of the i-th obstacle, β i Is the second binary variable of the -th obstacle, S i Is the minimum spacing value of the i-th obstacle from the wiring path, M is an integer constant.

[0088] In some embodiments, the preset rule constraints include minimum spacing constraint, minimum line length constraint, and clockwise wiring constraint.

[0089] In some embodiments, the minimum spacing constraint is represented by formula (5), and formula (5) is as follows:

[0090]

[0091] In formula (5), S i Is the minimum spacing value of the i-th obstacle from the wiring path, R i Is the influence length of the i-th obstacle on the wiring path, L i Is the actual spacing of the i-th obstacle from the wiring path, W is the half line width of the wiring path.

[0092] In some embodiments, the wiring path includes a plurality of wiring path segments, and the minimum spacing constraint is represented by formula (6), and formula (6) is as follows:

[0093]

[0094] In formula (6), (x j+1 , y j+1 ) is the end coordinate of the wiring path segment, (x j , y j ) is the start coordinate of the wiring path segment, and L is the minimum line length.

[0095] In a third aspect, the present embodiment further provides a computer-readable storage medium, on which computer program instructions are stored, and the computer program instructions, when executed by a processor, implement the method described in the first aspect.

[0096] The computer program involved in this embodiment can be stored in a computer-readable storage medium of a computer device. The computer-readable storage medium of the computer device includes, but is not limited to, magnetic disks, magnetic tapes, magnetic cards, floppy disks, flash memories, optical discs, optical cards, read-only memories (ROMs), random access memories (RAMs), erasable programmable ROMs (EPROMs), and electrically erasable programmable ROMs (EEPROMs), etc., and also includes other biological, physical, or chemical structures that can achieve functions similar to or equivalent to the above-listed storage media, such as units with information storage capabilities such as DNA, RNA, and proteins. In a specific embodiment, the storage medium involved can be one of the above medium types or a combination of the above medium types. In different embodiments, the computer program involved in the embodiment can be centrally stored in a single medium or distributedly stored in multiple media. The memory containing the computer-readable storage medium of the computer device can be a non-volatile memory or a random access memory. These computer-readable storage media of the computer device can be built into the device or can be an external device or a part of an external device connected to the device involved in the embodiment. In some embodiments, the memory with the computer-readable storage medium of the computer device is deployed locally; in other embodiments, a scheme of deploying the memory away from the processor can also be adopted, such as a network-attached memory accessed via an RF circuit or an external port and a communication network, where the communication network can be the Internet, one or more internal networks, a local area network (LAN), a wide area wireless network (WLAN), a storage area network (SAN), etc., or a suitable combination thereof, as long as the computer device can access the memory. In addition, the computer program involved in the embodiment can be stored in plaintext / ciphertext form or can be designed as training data and integrated and recombinantly stored implicitly in the parameter state of a deep neural network or other machine learning models through model training.

[0097] By introducing the vertical reference line, horizontal reference line, first constraint condition, and second constraint condition, the above technical solution can accurately identify obstacles within the wiring area and provide clear boundary solution constraints for the wiring path planning; formatting the first constraint condition using binary variables greatly simplifies the computational complexity and improves the optimization efficiency; the introduction of the linear programming model can comprehensively consider various situations and solve them correspondingly to ensure the global optimality of the optimization result; through strict verification steps, the feasibility and reliability of the optimized wiring path are guaranteed; this method can not only effectively reduce the wiring length, reduce signal interference, but also improve the automation degree and design efficiency of wiring, especially suitable for complex wiring environments and high-density circuit designs.

[0098] For ease of understanding, this embodiment also provides the following three examples to specifically illustrate the foregoing technical solution:

[0099] The first example:

[0100] Please refer to Figure 2 , this embodiment provides a method for wiring optimization. As shown in Figure a, there are 7 obstacles with different sizes and shapes in the rectangular wiring area, and the obstacles are numbered 1 - 7 and denoted as O1, O2…, O7. The wiring result consists of wiring trajectory points A, B, C, D and the connected line segments AB, BC, CD before and after. The coordinates of points A, B, C, D are set as (x a , y a ), (x b , y b ), (x c , y c ), (x d , y d ). In Figure b, the center points of the obstacles are used as the obstacle coordinates and denoted as (a1, b1), (a2, b2),…, (a7, b7). The ray x = x b starting from point B and going down is taken as the α axis, and the ray x = x c starting from point C and going up is taken as the β axis. The wiring area is divided into four parts by the wiring trajectory and the area dividing line, and two-bit binary numbers are used to mark different areas, denoted as 00, 01, 10, 11 respectively. At the same time, the obstacles within the rectangular area are also divided into four types. The constraint conditions of the obstacles in different areas are different during linear programming; Figure c is a schematic diagram of the spacing constraint of the wiring result. Let the minimum spacing value be S. The upper and lower purple virtual broken lines in the figure are formed by moving the wiring result up and down at equal distances. The virtual broken lines are equidistant from the wiring result everywhere and the distance is the wiring spacing S. The wiring space surrounded by the upper and lower virtual broken lines constitutes the minimum spacing safety area of the wiring result. To meet the minimum spacing constraint, it is necessary to ensure that there are no obstacles within this area. The connecting lines of the corresponding broken line inflection points bisect the corners. For example, the 135° corner in the upper right is bisected into two 67.5° angles.

[0101] In this embodiment, considering the spacing constraint requirements, different spacing values are supported between the routing trace and different types of obstacles, and the minimum spacing between each obstacle and the routing is recorded as S i , i=1,2,…,7,S i Including obstacle coordinates to obstacle boundary length R i , the distance between the obstacle boundary and the trace is L i , half line width The topology naturally satisfies the routing direction and angle constraints. Considering the minimum line length constraint, L = W is the minimum line length. At the same time, considering the clockwise routing constraint, the routing space area above the broken line ABCD should be as small as possible. In summary, this routing scenario can be represented by a mathematical model as follows:

[0102] Minimize Z=b1-y a +x b -x a +b3-y d #Formula (1-1)

[0103] Subject to y a =y b ,y c =y d ,y c -y b =x c -x b #Formula (1-2)

[0104] b2≤y a ≤b1,b4≤y d ≤b3,x a =a1=a2,x d =a3=a4#Formula (1-3)

[0105]

[0106] y a +S i -b i ≤α i M+β i M# formula (1-5)

[0107]

[0108] y d +S i -b i ≤α i M+(1-β i )M#Formula (1-9)

[0109] b i +S i -y a ≤(1-α i )M+β i M # Formula (1-10)

[0110]

[0111] b i +S i -y d ≤(1-α i )M+(1-β i )M # Formula (1-13

[0112]

[0113] α i ,β i ∈(0,1) i=1,2,…,7 # Formula (1-15)

[0114] In this embodiment, the decision variables are the coordinates x a , x b , x c , x d , y a , y b , y c , y d , the coordinates a i , b i of the obstacle are constants, M is a sufficiently large integer constant, the objective function is given by Formula (1-1), which is the sum of the distance from obstacle O1 to point A, the distance of line segment AB, and the distance from obstacle O3 to point D. When Z takes the minimum value, the clockwise wiring constraint is satisfied; Formula (1-2) represents the coordinate dependency relationship between the wiring trajectory points under this topological structure, and the vertical distance between point B and point C is equal to the horizontal distance; Formula (1-3) determines the value range of the boundary points. Point A can be adjusted up and down between obstacles O1 and O2, and point D can be adjusted up and down between obstacles O3 and O4; Formula (1-4) represents the minimum line length constraint, and the length of each line segment is not less than L; at the same time, due to the division of the wiring area, the obstacles in different areas correspond to different constraint conditions, and the constraint conditions in different areas are mutually exclusive. Each obstacle can only select the constraint conditions corresponding to its own area and substitute them into the formula. In order to uniformly process the spacing constraints of all obstacles, two binary variables α i , β i are set for each obstacle respectively. Different value combinations of the binary variables correspond to different marked areas and are multiplied by M and substituted into the spacing constraint conditions, so as to achieve the unification of multiple mutually exclusive constraint conditions.

[0115] In this embodiment, the formulas (1-5) to (1-7) correspond to the constraint conditions of the 00 region, the formulas (1-8) and (1-9) correspond to the constraint conditions of the 01 region, the formulas (1-10) and (1-11) correspond to the 10 region, and the formulas (1-12) to (1-14) correspond to the 11 region. By introducing the 01 variables α i and β i on the right side of the equal signs in the formulas (1-5) to (1-14), it is ensured that only the constraint conditions of a certain region among the 4 pairs of constraint conditions are effective. Specifically, the formula (1-5) represents the distance and positional relationship between the obstacle located in the 00 region and the line segment AB. The ordinate y a of point A should be less than or equal to the ordinate b i of the obstacle minus the distance S i to this obstacle. The formula (1-6) means that the obstacle should be located on the left side of the region dividing line drawn upward from point C' in Figure c. The abscissa of point C' is derived from the coordinates of point C as The formula (1-7) means that the obstacle should be located in the upper left of the line B'C'. The formula (1-8) means that the obstacle O i in the 01 region is on the right side of the ray upward from point C'. The formula (1-9) means that the obstacle is above the line C'D'. The constraint conditions of other regions are similar and will not be elaborated here.

[0116] The second example:

[0117] Please refer to Figure 3 , this embodiment provides a method for wiring optimization. Denote the obstacle as O i , and the coordinates of the center point of the obstacle are (a i , b i ), i = 1, 2,..., 7. The coordinates of points A, B, C, and D are set as (x a , y a ), (x b , y b ), (x c , y c ), (x d , y d ) respectively. The minimum wire length is L. The wiring area is divided into four blocks of 00, 01, 10, and 11 by the ray α downward from point B and the ray β to the right of point C. Considering the minimum spacing constraint, the minimum wire length constraint, and the clockwise wiring constraint, this scenario can be linearly programmed as follows:

[0118] Minimize Z = b1 - y a + x b - x a + x d - a1 # Formula (1-16)

[0119] Subject to y a = y b ,x c = x d ,y c -y b = x c -x b # Formula (1-17)

[0120] b7 ≤ y a ≤ b1, a1 ≤ x d ≤ a2, xa = a1, y d = b1 = b2 # Formula (1-18)

[0121]

[0122] y a + S i -b i ≤ α i M + β i M # Formula (1-20)

[0123] a i + S i -x d ≤ α i M + β i M # Formula (1-21)

[0124]

[0125] x d + S i -a i ≤ α i M + (1 - β i )M # Formula (1-24)

[0126] b i + S i -y a ≤ (1 - α i )M + β i M # Formula (1-25)

[0127]

[0128] α i , β i ∈ (0,1) i = 1,2,…,7 # Formula (1-30)

[0129] In this embodiment, the decision variables are the coordinates x of points A, B, C, D a ,x b ,x c ,x d, y a , y b , y c , y d , the obstacle coordinate a i , b i are constants, M is a sufficiently large integer constant, the objective function is given by formula (1-16), which is the sum of the distance from obstacle O1 to point A, the distance of line segment AB, and the distance from obstacle O1 to point D, and solve for the coordinates of the wiring trajectory point that minimizes the value of Z; formula (1-17) represents the wiring line type constraint, formula (1-18) determines the value range of the boundary points, and formula (1-19) represents the minimum line length constraint; two 01 variables α i , β i are also set for each obstacle. Different value combinations of the variables correspond to the four wiring regions divided by axes α and β, realizing the unification of different region spacing constraints; among them, formulas (1-20) to (1-22) correspond to the constraint conditions of the 00 region, formulas (1-23) and (1-24) correspond to the constraint conditions of the 01 region, formulas (1-25) and (1-26) correspond to the 10 region, and formulas (1-27) to (1-29) correspond to the 11 region.

[0130] The third example:

[0131] Please refer to Figure 4 , this embodiment provides a method for wiring optimization. There are a total of 13 obstacles O1 to O in the figure 13 The center point coordinates are respectively denoted as (a i , b i ), i = 1, 2,..., 13, and the coordinates of points A, B, C, D, E, and F are respectively set as (x a , y a ), (x b , y b ), (x c , y c ), (x d , y d ), (x e , y e ), (x f , y f ). The minimum line length is set as L. To satisfy the clockwise wiring constraint, the lengths of line segments BC and DE are set as fixed values L, which are only used as connection line segments to change the wiring direction. The lengths of line segments AB, CD, and EF are adjustable. The four rays emitted from points B, C, D, and E divide the rectangular wiring frame into 6 sub-regions and are marked with three 01 variables α, β, and γ for different regions. Thus, this scenario can be linearly programmed as follows:

[0132] Minimize Z = b2 - y a + xb -x a +b4 - y f #Formula (1 - 31)

[0133] Subject to y a = y b , y e = y f , x c = x d

[0134]

[0135] b1 ≤ y a ≤ b2, b3 ≤ y f ≤ b4, x a = a1, x f = a3 #Formula (1 - 33)

[0136] x a + L ≤ x b , y c + L ≤ y d , x e + L ≤ x f #Formula (1 - 34)

[0137]

[0138] y e + S i - b i ≤ α i M + β i M + (1 - γ i )M #Formula (1 - 38)

[0139]

[0140] y a + S i - b i ≤ α i M + (1 - β i )M + γ i M #Formula (1 - 40)

[0141] a i + S i - x d ≤ α i M + (1 - β i )M + γ i M #Formula (1 - 41)

[0142]

[0143] xd +S i -a i ≤α i M+(1-β i )M+(1-γ i )M # Formula (1-46)

[0144]

[0145] b i +S i -y a ≤(1-α i )M+β i M+γ i M # Formula (1-48)

[0146]

[0147]

[0148] In this embodiment, the decision variables are the coordinates of each wiring trace point. In fact, only the coordinates of points A, B, and F need to be determined, and all coordinates can be calculated from the linear topological relationship. The obstacle coordinates (ai, bi) are constants, and M is a sufficiently large integer constant; the objective function is given by Formula (1-31), Formula (1-32) represents the wiring line type constraint, Formula (1-33) determines the value range of the boundary points, Formula (1-34) represents the minimum line length constraint, Formulas (1-35) to (1-37) correspond to the constraint conditions of the 000 region, Formulas (1-38), (1-39) correspond to the constraint conditions of the 001 region, Formulas (1-40) to (1-43) correspond to the 010 region, Formulas (1-44) to (1-47) correspond to the 011 region, Formulas (1-48), (1-49) correspond to the 100 region, Formulas (1-50) to (1-52) correspond to the 101 region, and Formula (1-53) represents α i ,β i ,γ i take values in the range of 0 and 1 and α i ,β i cannot be 1 at the same time.

[0149] By introducing a reference line and constraint conditions, obstacles within the wiring area can be accurately identified, and clear boundary conditions can be provided for the routing path planning; formatting the constraint conditions using binary variables greatly simplifies the computational complexity and improves the optimization efficiency; the introduction of a linear programming model makes the optimization of the routing path more scientific and systematic, capable of comprehensively considering various constraint conditions to ensure the global optimality of the optimization result; through strict verification steps, the feasibility and reliability of the optimized routing path are guaranteed; this method can not only effectively reduce the wiring length and signal interference but also improve the automation degree and design efficiency of wiring, especially suitable for complex wiring environments and high-density circuit designs.

[0150] Finally, it should be noted that although the above embodiments have been described in the text and drawings of the specification of this application, the patent protection scope of this application cannot be limited thereby. Any technical solutions obtained by equivalent structure or equivalent process substitution or modification based on the substantial concept of this application using the content recorded in the text and drawings of the specification of this application, as well as those directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, are all included in the patent protection scope of this application.

Claims

1. A method for wiring optimization, characterized in that, Including: Drawing a vertical reference line and a horizontal reference line based on the center point of the component, and recording the first intersection point of the vertical reference line and the wiring path, and the second intersection point of the horizontal reference line and the wiring path to form a wiring area; Obtaining all obstacles within the wiring area and generating a first constraint condition for the wiring area and multiple obstacles; Generating a corresponding binary variable for each obstacle, and unifying the format of the first constraint condition of each obstacle through the value combination of the binary variable to obtain a second constraint condition; Constructing a linear programming model, and inputting the second constraint condition into the linear programming model, where the second constraint condition includes at least one of the coordinate dependency relationship of the wiring path, the value range of the boundary points, the minimum line length constraint, and the obstacle spacing constraint; Solving the linear programming model to obtain the coordinates of the optimal wiring path points; Redrawing the wiring path according to the coordinates of the optimal wiring path points, denoted as the optimized wiring path; Verifying whether the optimized wiring path satisfies the preset rule constraints; If so, outputting the optimized wiring path as the final wiring optimization result.

2. The wiring optimization method according to claim 1, wherein Two components are respectively provided at both ends of the wiring path. Denote one component as the first component and the other component as the second component. The first component has a first vertical reference line and a first horizontal reference line, the second component has a second vertical reference line and a second horizontal reference line, and the wiring area has a first boundary and a second boundary; The first boundary is configured to connect the first vertical reference line and the second horizontal reference line; or, the first boundary is configured to be the first vertical reference line and the horizontal canvas edge of the PCB board; or, the first boundary is configured to be the first horizontal reference line and the vertical canvas edge of the PCB board; The second boundary is configured to connect the second vertical reference line and the first horizontal reference line; or, the second boundary is configured to be the second vertical reference line and the horizontal canvas edge of the PCB board; or, the second boundary is configured to be the second horizontal reference line and the vertical canvas edge of the PCB board.

3. The wiring optimization method according to claim 1, characterized in that, it is assumed that A affected by the i-th obstacle along the extension direction of the wiring path i components, B i components, C i components and D i components. The linear programming model is represented by formula (1), and the formula (1) is as follows: In formula (1), Z is the expression function of the linear programming model, N is the total number of obstacles in the wiring area, b i is the ordinate of the i-th obstacle, is the ordinate of component A i in the wiring path, is the ordinate of component D i in the wiring path, is the abscissa of component B i in the wiring path, is the abscissa of component A i in the wiring path.

4. The wiring optimization method according to claim 3, characterized in that The first constraint condition includes a vertical coordinate constraint condition and a horizontal coordinate constraint condition. The vertical coordinate constraint condition is represented by formula (2), and formula (2) is as follows: In formula (2), is the ordinate of component C i in the wiring path, is the ordinate of component B i in the wiring path, is the abscissa of component C i in the wiring path, is the abscissa of component B i in the wiring path, b i-1 is the ordinate of the (i - 1)-th obstacle, b i+h is the ordinate of the (i + h)-th obstacle; The horizontal coordinate constraint condition is represented by formula (3), and formula (3) is as follows: In formula (3), is the abscissa of component A in the wiring path, i a i-1 is the abscissa of the (i - 1)-th obstacle, i a i+1 is the abscissa of the i-th obstacle, i+h a is the abscissa of component D in the wiring path, i t is the minimum line length of the wiring path segment in the wiring path.

5. The wiring optimization method according to claim 4, characterized in that The second constraint condition is represented by formula (4), and formula (4) is as follows: In formula (4), α I is the first binary variable of the I-th obstacle, β i is the second binary variable of the -th obstacle, S i is the minimum spacing value of the i-th obstacle from the wiring path, and M is an integer constant.

6. The wiring optimization method according to claim 1, wherein, The preset rule constraints include a minimum spacing constraint, a minimum line length constraint, and a clockwise wiring constraint.

7. The wiring optimization method according to claim 6, characterized in that The minimum spacing constraint is represented by formula (5), and formula (5) is as follows: In formula (5), s i is the minimum spacing value of the i-th obstacle from the wiring path, and R i is the influence length of the i-th obstacle on the wiring path, and t i is the actual spacing of the i-th obstacle from the wiring path, and W is the half line width of the wiring path.

8. The wiring optimization method according to claim 6, characterized in that, The wiring path includes multiple wiring path segments. The minimum spacing constraint is represented by formula (6), and formula (6) is as follows: In formula (6), (x j+1 , y j+1 ) are the end coordinates of the wiring path segment, (x j , y j ) are the start coordinates of the wiring path segment, and t is the minimum line length.

9. A wiring optimization system, characterized in that, Applicable to the method described in any one of claims 1 to 8.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method described in any one of claims 1 to 8.

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