Quantum processing unit, manufacturing method thereof, and quantum computer

Abstract

The present invention discloses a quantum processing unit, a manufacturing method thereof, and a quantum computer, belonging to the technical field of quantum computers. The quantum processing unit comprises: a circuit board and an ion trap chip. The circuit board is provided with a chip mounting through-hole. The circuit board has a first circuit surface and a second circuit surface opposite to each other in a thickness direction thereof. The first circuit surface has a first bonding terminal, and the second circuit surface has a second bonding terminal. The ion trap chip has a first chip surface and a second chip surface opposite to each other in a thickness direction thereof. The first chip surface has a first electrode, and the second chip surface has a second electrode. The ion trap chip is fixedly arranged in the chip mounting through-hole of the circuit board. The circuit board and the ion trap chip can be connected by double-sided bonding, thereby facilitating an increase in the number of electrical connections established between the circuit board and the ion trap chip, reducing the bonding density on a single side, and reducing the bonding difficulty of the circuit board and the ion trap chip.

Description

Technical Field

[0001] The present invention relates to the field of quantum computer technology, and in particular to a quantum processing unit, a manufacturing method thereof, and a quantum computer. Background Art

[0002] Quantum bits (qubits) are the basic units of quantum computing. Increasing their number can significantly enhance the computing power of quantum processing units. As the number of qubits increases, more demands are placed on the ion trap chips in quantum processing units. Currently, there is a need for ion trap chips with smaller size and more extraction electrodes.

[0003] However, as the number of extraction electrodes on the ion trap chip increases, the extraction electrodes are arranged too densely, making it difficult to bond the extraction electrodes of the ion trap chip to the circuit board that carries them. Summary of the Invention

[0004] The present invention aims to solve at least one of the above-mentioned technical problems in the prior art to a certain extent. To this end, the present invention provides a quantum processing unit that can reduce the difficulty of bonding a circuit board and an ion trap chip.

[0005] The present invention also provides a method for manufacturing the quantum processing unit.

[0006] The present invention also proposes a quantum computer having the above-mentioned quantum processing unit.

[0007] According to an embodiment of the present invention, a quantum processing unit includes: a circuit board, the circuit board having a chip mounting through-hole, the circuit board having a first circuit surface and a second circuit surface opposite to each other in a thickness direction thereof, the first circuit surface having a first bonding terminal, and the second circuit surface having a second bonding terminal; an ion trap chip, the ion trap chip being fixed to the chip mounting through-hole, the ion trap chip having a first chip surface and a second chip surface opposite to each other in a thickness direction thereof, the first chip surface having a first electrode, and the second chip surface having a second electrode; wherein the first circuit surface and the first chip surface have the same orientation, and the first electrode is bonded to the first bonding terminal, and the second circuit surface and the second chip surface have the same orientation, and the second electrode is bonded to the second bonding terminal.

[0008] According to the quantum processing unit of an embodiment of the present invention, the ion trap chip is fixed to the chip mounting through-hole of the circuit board, and the circuit board and the ion trap chip can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip. The electrical connections between the circuit board and the ion trap chip can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty of the circuit board and the ion trap chip.

[0009] According to some embodiments of the present invention, in a thickness direction of the ion trap chip, the first electrode and the second electrode are staggered, and the first bonding terminal and the second bonding terminal are staggered.

[0010] According to some embodiments of the present invention, there are multiple first electrodes and multiple first bonding terminals, and they are bonded together in a one-to-one correspondence. There are multiple second electrodes and multiple second bonding terminals, and they are bonded together in a one-to-one correspondence.

[0011] According to some embodiments of the present invention, in the width direction of the ion trap chip, both ends of the first chip surface have at least one first electrode, and the first bonding terminal is arranged adjacent to the corresponding first electrode; in the length direction of the ion trap chip, both ends of the second chip surface have at least one second electrode, and the second bonding terminal is arranged adjacent to the corresponding second electrode.

[0012] According to some embodiments of the present invention, the circuit board has a filter circuit and a signal lead-out terminal, and the first bonding terminal and the second bonding terminal are both connected to the signal lead-out terminal through the filter circuit.

[0013] According to some embodiments of the present invention, a bearing protrusion is formed on a hole wall of the chip mounting through hole, and the ion trap chip is fixedly connected to the bearing protrusion via a fastener.

[0014] According to some embodiments of the present invention, the quantum processing unit further includes: a first packaging board, the first packaging board is opposite to the first circuit surface, the first packaging board is provided with a first operating through hole, and the first packaging board has a first supporting portion; a second packaging board, the second packaging board is opposite to the second circuit surface, the second packaging board is provided with a second operating through hole, and the second packaging board has a second supporting portion; wherein, in the thickness direction of the circuit board: the first packaging board and the second packaging board are clamped on both sides of the circuit board; the first operating through hole corresponds to the first bonding terminal, and the first operating through hole also corresponds to the first electrode; the second operating through hole corresponds to the second bonding terminal, and the second operating through hole also corresponds to the second electrode; the first supporting portion abuts against the area of ​​the first chip surface corresponding to the second electrode, and / or the first supporting portion abuts against the area of ​​the first circuit surface corresponding to the second electrode; the second supporting portion abuts against the area of ​​the second chip surface corresponding to the first electrode, and / or the second supporting portion abuts against the area of ​​the second circuit surface corresponding to the first electrode.

[0015] According to some embodiments of the present invention, outer surfaces of the first supporting portion and the second supporting portion are both coated with an insulating buffer adhesive layer.

[0016] According to another embodiment of the present invention, a method for manufacturing a quantum processing unit is provided, wherein the quantum processing unit is the aforementioned quantum processing unit and comprises the following steps: assembling the ion trap chip to the chip mounting through-hole; mounting the first packaging board and the second packaging board on both sides of the circuit board in the thickness direction; and bonding the first electrode to the first bonding terminal, and bonding the second electrode to the second bonding terminal.

[0017] According to the manufacturing method of the quantum processing unit of an embodiment of the present invention, the ion trap chip is fixed to the chip mounting through-hole of the circuit board, and the circuit board and the ion trap chip can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip. The electrical connections between the circuit board and the ion trap chip can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty of the circuit board and the ion trap chip. At the same time, the first support part and the second support part can directly or indirectly support the ion trap chip on the upper and lower sides of the ion trap chip to avoid damage and failure of the ion trap chip, which is beneficial to improving the yield of the quantum processing unit and reducing the manufacturing cost of the quantum processing unit.

[0018] A quantum computer according to another aspect of the present invention includes the aforementioned quantum processing unit.

[0019] According to a quantum computer according to an embodiment of the present invention, the ion trap chip of its quantum processing unit is fixed to the chip mounting through-hole of the circuit board. The circuit board and the ion trap chip can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board and the ion trap chip. The electrical connections between the circuit board and the ion trap chip can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty of the circuit board and the ion trap chip, which is beneficial to improving the performance of the quantum computer and reducing the manufacturing cost of the quantum computer.

[0020] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a circuit board and an ion trap chip according to an embodiment of the present invention;

[0022] Figure 2 is a top view of the connection between the circuit board and the ion trap chip according to an embodiment of the present invention;

[0023] Figure 3is a bottom view of the connection between the circuit board and the ion trap chip according to an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a quantum processing unit according to an embodiment of the present invention;

[0025] Figure 5 is an exploded diagram of a quantum processing unit according to an embodiment of the present invention;

[0026] Figure 6 is another exploded diagram of a quantum processing unit according to an embodiment of the present invention;

[0027] Figure 7 is a schematic structural diagram of a quantum processing unit at an ion trap chip according to an embodiment of the present invention;

[0028] Figure 8 is another structural schematic diagram of a quantum processing unit at an ion trap chip according to an embodiment of the present invention;

[0029] Figure 9 is a flow chart of a method for manufacturing a quantum processing unit according to an embodiment of the present invention.

[0030] Reference numerals:

[0031] Circuit board 1; first circuit surface 11; first bonding terminal 111; second circuit surface 12; second bonding terminal 121; chip mounting through hole 13; carrying protrusion 131; signal lead terminal 14;

[0032] Ion trap chip 2; first chip surface 21; first electrode 211; second chip surface 22; second electrode 221;

[0033] First packaging plate 3; first operation through hole 31; first support portion 32;

[0034] Second packaging plate 4; second operation through hole 41; second support portion 42;

[0035] Avoidance groove 5; footrest 6;

[0036] Quantum processing unit 10. DETAILED DESCRIPTION

[0037] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0038] In the description of the present invention, it should be understood that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0040] In the present invention, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections, or communication; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0041] The quantum processing unit 10 and its manufacturing method and quantum computer according to embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Reference Figure 1-Figure 3 As shown, a quantum processing unit 10 according to an embodiment of the present invention includes: a circuit board 1 and an ion trap chip 2, the circuit board 1 is provided with a chip mounting through-hole 13, the circuit board 1 has a first circuit surface 11 and a second circuit surface 12 opposite to each other in the thickness direction, the first circuit surface 11 has a first bonding terminal 111, and the second circuit surface 12 has a second bonding terminal 121, the ion trap chip 2 is fixed to the chip mounting through-hole 13, the ion trap chip 2 has a first chip surface 21 and a second chip surface 22 opposite to each other in the thickness direction, the first chip surface 21 has a first electrode 211, and the second chip surface 22 has a second electrode 221, wherein the first circuit surface 11 and the first chip surface 21 have the same orientation, and the first electrode 211 is bonded to the first bonding terminal 111, the second circuit surface 12 and the second chip surface 22 have the same orientation, and the second electrode 221 is bonded to the second bonding terminal 121.

[0043] Specifically, the circuit board 1 can be a carrier such as a ceramic substrate or a silicon substrate, which has good thermal stability and electrical insulation performance. The circuit board 1 is a double-sided circuit board. The circuit board 1 can be formed by laminating multiple boards. For example, the circuit board 1 is formed by laminating two or three boards. In the thickness direction of the circuit board 1, that is, in Figure 1 In the up and down directions, the circuit board 1 has a first circuit surface 11 and a second circuit surface 12 facing oppositely. The first circuit surface 11 can be the upper surface of the circuit board 1, and the second circuit surface 12 can be the lower surface of the circuit board 1. The first circuit surface 11 has a first bonding terminal 111, and the second circuit surface 12 has a second bonding terminal 121. The circuit board 1 can transmit DC voltage, radio frequency RF signal, and microwave signal through the first bonding terminal 111 and the second bonding terminal 121. At the same time, the circuit board 1 is provided with a chip mounting through hole 13, and the chip mounting through hole 13 can penetrate the circuit board 1 in the thickness direction of the circuit board 1. The chip mounting through hole 13 can be used to install the ion trap chip 2.

[0044] The ion trap chip 2 can be used to trap ions as quantum bits and perform quantum logic gate operations. The ion trap chip 2 is a double-sided chip. In the thickness direction of the ion trap chip 2, that is, in the Figure 1 In the up and down directions, the ion trap chip 2 has a first chip surface 21 and a second chip surface 22 facing oppositely. The first chip surface 21 can be the upper surface of the ion trap chip 2, and the second chip surface 22 can be the lower surface of the ion trap chip 2. The first chip surface 21 has a first electrode 211, and the second chip surface 22 has a second electrode 221.

[0045] The ion trap chip 2 can be fixedly connected to the chip mounting through-hole 13 on the circuit board 1 by means of fasteners, bonding, clamping, etc. The ion trap chip 2 can be at least partially embedded in the chip mounting through-hole 13. The ion trap chip 2 can also be fixedly connected to the chip mounting through-hole 13 on one side outside the chip mounting through-hole 13. After the ion trap chip 2 is fixed to the chip mounting through-hole 13, the first chip surface 21 and the first circuit surface 11 are oriented in the same direction, so that the first electrode 211 is bonded to the first bonding terminal 111. The second chip surface 22 and the second circuit surface 12 are oriented in the same direction, so that the second electrode 221 is bonded to the second bonding terminal 121.

[0046] It can be understood that the first electrode 211 and the first bonding terminal 111 can be connected through corresponding wire bonding, and the second electrode 221 and the second bonding terminal 121 can be connected through corresponding wire bonding. The wire can be a gold wire, aluminum wire or other conductive wire. The wire can pass through the chip mounting through hole 13 as needed to reduce the length of the lead.

[0047] According to the quantum processing unit 10 of an embodiment of the present invention, the ion trap chip 2 is fixed to the chip mounting through-hole 13 of the circuit board 1, and the circuit board 1 and the ion trap chip 2 can be connected by double-sided bonding, which is beneficial to increase the number of electrical connections established between the circuit board 1 and the ion trap chip 2. The electrical connections between the circuit board 1 and the ion trap chip 2 can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty of the circuit board 1 and the ion trap chip 2.

[0048] In some embodiments of the present invention, reference Figure 1-Figure 3 As shown, in the thickness direction of the ion trap chip 2 , the first electrode 211 and the second electrode 221 are staggered, and the first bonding terminal 111 and the second bonding terminal 121 are staggered.

[0049] Specifically, the thickness direction of the ion trap chip 2 is Figure 1 Up and down directions, Figure 2 and Figure 3 In the direction perpendicular to the paper, the first electrode 211 and the second electrode 221 are staggered, and the first bonding terminal 111 and the second bonding terminal 121 are staggered. That is, in the up and down directions, the projection of the first electrode 211 onto the second chip surface 22 does not overlap with the second electrode 221 on the second chip surface 22, and the projection of the first bonding terminal 111 onto the second circuit surface 12 does not overlap with the second bonding terminal 121 on the second circuit surface 12. Therefore, when the wire bonder bonds the first electrode 211 and the first bonding terminal 111, the wire bonder's splitting knife does not overlap the first electrode 211 and the first bonding terminal 111. 11 generates pressure in the up and down directions, and this pressure has little effect on the second electrode 221 and the second bonding terminal 121. When the wire bonding machine bonds the second electrode 221 and the second bonding terminal 121, the splitter of the wire bonding machine generates pressure in the up and down directions on the second electrode 221 and the second bonding terminal 121, and this pressure has little effect on the first electrode 211 and the first bonding terminal 111, thereby reducing the negative impact of the stress generated when the ion trap chip 2 and the circuit board 1 are bonded on one side on the other side, that is, reducing the risk of short circuit caused by wire connection failure after bonding, which is beneficial to improving the yield rate of the quantum processing unit 10.

[0050] For example, when the wire bonding machine first bonds the first electrode 211 and the first bonding terminal 111, and then bonds the second electrode 221 and the second bonding terminal 121, the pressure generated by the wire bonding machine's splitter when bonding the second electrode 221 and the second bonding terminal 121 has little effect on the first electrode 211 and the first bonding terminal 111, thereby reducing the risk of breakage or false connection of the wire connecting the first electrode 211 and the first bonding terminal 111.

[0051] In some embodiments of the present invention, reference Figure 2 and Figure 3 As shown, the number of the first electrodes 211 and the first bonding terminals 111 are both multiple and bonded one-to-one, and the number of the second electrodes 221 and the second bonding terminals 121 are both multiple and bonded one-to-one. Thus, the number of electrical connections between the circuit board 1 and the ion trap chip 2 is increased, so that the quantum processing unit 10 has a more precise electric field adjustment capability, and the quantum processing unit 10 has a higher-scale and higher-fidelity quantum operation capability.

[0052] In some embodiments of the present invention, the ion trap chip 2 can be a chip with an alumina ceramic carrier. The ion trap chip 2 can realize the arrangement of multiple first electrodes 211 and multiple second electrodes 221 on both sides on the first chip surface 21 and the second chip surface 22. The total number of the first electrodes 211 and the second electrodes 221 can be increased to improve the computing power of the quantum processing unit 10. At the same time, the volume of the ion trap chip 2 can be reduced, thereby reducing the risk of the ion trap chip 2 being broken.

[0053] In some embodiments of the present invention, reference Figure 1-Figure 3 As shown, in the width direction of the ion trap chip 2, both ends of the first chip surface 21 have at least one first electrode 211, and the first bonding terminal 111 is arranged adjacent to the corresponding first electrode 211. In the length direction of the ion trap chip 2, both ends of the second chip surface 22 have at least one second electrode 221, and the second bonding terminal 121 is arranged adjacent to the corresponding second electrode 221.

[0054] Specifically, the width direction of the ion trap chip 2 is Figure 1-Figure 3 In the left and right directions, one or more first electrodes 211 may be arranged at the left end of the first chip surface 21, and one or more first electrodes 211 may be arranged at the right end of the first chip surface 21. The first circuit surface 11 has first bonding terminals 111 adjacent to the first electrodes 211 arranged on the left and right sides of the chip mounting through-hole 13, respectively. The first electrode 211 at the left end of the first chip surface 21 may be bonded to the first bonding terminal 111 corresponding to the left side of the chip mounting through-hole 13 of the first circuit surface 11, and the first electrode 211 at the right end of the first chip surface 21 may be bonded to the first bonding terminal 111 corresponding to the left side of the chip mounting through-hole 13 of the first circuit surface 11. 211 can be bonded to the first bonding terminal 111 corresponding to the right side of the chip mounting through hole 13 on the first circuit surface 11 to reduce the length of the lead connecting the first electrode 211 and the first bonding terminal 111, thereby helping to reduce costs and improve bonding reliability. At the same time, compared to arranging multiple first electrodes 211 in a centralized manner, the embodiment of the present invention arranges multiple first electrodes 211 at the opposite left and right ends of the first chip surface 21, which can avoid the density of the first electrodes 211 on the first chip surface 21 being too high, so as to facilitate the bonding operation of the wire bonding machine.

[0055] The length direction of the ion trap chip 2 is Figure 1-Figure 3In the front-to-back direction, one or more second electrodes 221 may be arranged at the front end of the second chip surface 22, and one or more second electrodes 221 may be arranged at the rear end of the second chip surface 22. Second bonding terminals 121 adjacent to the second electrodes 221 are arranged on the front and rear sides of the chip mounting through-hole 13 of the second circuit surface 12, respectively. The second electrodes 221 at the front end of the second chip surface 22 may be bonded to the corresponding second bonding terminals 121 on the front side of the chip mounting through-hole 13 of the second circuit surface 12, and the second electrodes 221 at the rear end of the second chip surface 22 may be bonded to the corresponding second bonding terminals 121 on the rear side of the chip mounting through-hole 13 of the second circuit surface 12. This can reduce the length of the wires connecting the second electrodes 221 and the second bonding terminals 121, thereby reducing costs and improving bonding reliability. At the same time, compared to centrally arranging multiple second electrodes 221, the embodiment of the present invention arranges multiple second electrodes 221 at opposite front and rear ends of the second chip surface 22, thereby avoiding an excessively high density of the second electrodes 221 on the second chip surface 22, thereby facilitating bonding operations using a wire bonding machine.

[0056] In some embodiments of the present invention, reference Figure 1-Figure 3 As shown, the circuit board 1 has a filter circuit and a signal lead-out terminal 14 , and the first bonding terminal 111 and the second bonding terminal 121 are both connected to the signal lead-out terminal 14 through the filter circuit.

[0057] Specifically, the power supply or signal can be connected to the signal lead-out terminal 14. When the power supply or signal is transmitted to the ion trap chip 2 through the circuit board 1, it needs to be filtered by the filter circuit to reduce the interference of external noise on the ion trap chip 2 and improve the stability and control accuracy of the ion trap chip 2. At the same time, the electrodes and circuits inside the ion trap chip 2 will generate thermal noise and 1 / f noise, etc. These noises will interfere with the motion mode of the ions, affecting the transmission of quantum information and the fidelity of quantum manipulation. The filter circuit can suppress these internal noises and ensure the purity of the ion motion mode. In addition, the motion mode of the ions is the carrier of quantum information transmission. Some Raman quantum manipulation is coupled with the motion mode of the ions. Non-ideal changes in the ion motion state will greatly affect the fidelity of the quantum operation and cause decoherence effects. The filter circuit can provide pure electrical signals, reduce non-ideal changes in the ion motion state, and thus improve the fidelity of quantum manipulation.

[0058] In some embodiments, the total number of pins in all signal lead-out terminals 14 is N, the filtering circuit may include N filtering sub-circuits, each filtering sub-circuit is integrated with at least one filtering capacitor, and the total number of first bonding terminals 111 and second bonding terminals 121 is N, where N≥2 and is an integer, that is, each first bonding terminal 111 is electrically connected to a pin of a corresponding signal lead-out terminal 14 through a corresponding filtering sub-circuit, and each second bonding terminal 121 is electrically connected to a pin of a corresponding signal lead-out terminal 14 through a corresponding filtering sub-circuit, so that the signal crosstalk between different electrodes can be reduced through the filtering sub-circuit, thereby ensuring the purity of the electrical signal applied to each first electrode 211 and each second electrode 221 of the ion trap chip 2, and improving the control accuracy of the ion trap chip 2 on ions.

[0059] Reference Figure 1 As shown, there are two signal lead-out terminals 14. In the direction perpendicular to the thickness of the circuit board 1, the two signal lead-out terminals 14 are located at both ends of the circuit board 1, and the chip mounting through-hole 13 is located between the two signal lead-out terminals 14. For example, the chip mounting through-hole 13 is located at the center of the circuit board 1, one signal lead-out terminal 14 is located at the left end of the circuit board 1, and the other signal lead-out terminal 14 is located at the right end of the circuit board 1, so as to leave sufficient layout space for the filtering circuit, so that the filtering sub-circuits in the filtering circuit can be evenly separated and arranged, reducing the manufacturing difficulty of the circuit board 1, avoiding excessive concentration of the filtering sub-circuits, and reducing the risk of signal crosstalk.

[0060] In some embodiments of the present invention, reference Figure 1 and Figure 3 As shown, a bearing protrusion 131 is formed on the wall of the chip mounting through hole 13 , and the ion trap chip 2 is fixedly connected to the bearing protrusion 131 via a fastener.

[0061] In some embodiments, the fastener may be a screw that passes through the ion trap chip 2 and is threadedly engaged with the support protrusion 131. In other embodiments, the fastener may be a buckle that passes through the ion trap chip 2 and is snap-engaged with the support protrusion 131. The support protrusion 131 can increase the contact area between the ion trap chip 2 and the circuit board 1, thereby facilitating increased stability and reliability of the connection between the ion trap chip 2 and the circuit board 1.

[0062] Optionally, there may be multiple supporting protrusions 131 and multiple fasteners, and the ion trap chip 2 is connected to the supporting protrusions 131 via multiple fasteners, so as to further improve the stability and reliability of the connection between the ion trap chip 2 and the circuit board 1 .

[0063] In some embodiments of the present invention, reference Figure 4-Figure 8As shown, the quantum processing unit 10 further includes: a first packaging board 3 and a second packaging board 4, the first packaging board 3 is opposite to the first circuit surface 11, the first packaging board 3 is provided with a first operation through hole 31, the first packaging board 3 has a first support portion 32, the second packaging board 4 is opposite to the second circuit surface 12, the second packaging board 4 is provided with a second operation through hole 41, the second packaging board 4 has a second support portion 42, wherein, in the thickness direction of the circuit board 1: the first packaging board 3 and the second packaging board 4 are sandwiched between the two sides of the circuit board 1, the first operation through hole 31 corresponds to the first bonding terminal 111, the first The operating through hole 31 also corresponds to the first electrode 211, the second operating through hole 41 corresponds to the second bonding terminal 121, and the second operating through hole 41 also corresponds to the second electrode 221. The first supporting portion 32 abuts against the area corresponding to the first chip surface 21 and the second electrode 221, and / or the first supporting portion 32 abuts against the area corresponding to the first circuit surface 11 and the second electrode 221, the second supporting portion 42 abuts against the area corresponding to the second chip surface 22 and the first electrode 211, and / or the second supporting portion 42 abuts against the area corresponding to the second circuit surface 12 and the first electrode 211.

[0064] Among them, the first packaging plate 3 and the second packaging plate 4 can fix and protect the circuit board 1 on the upper and lower sides of the circuit board 1. The first packaging plate 3 and the second packaging plate 4 can also support at least one of the ion trap chip 2 and the circuit board 1 on the back of the bonding area to reduce the deformation of the ion trap chip 2 and the circuit board 1 during bonding.

[0065] In addition, the first packaging plate 3 and the second packaging plate 4 can be metal plates. The first packaging plate 3 and the second packaging plate 4 can shield external interference and the influence of stray electric fields on the ion trap chip 2 and the circuit board 1. At the same time, the first packaging plate 3 and the second packaging plate 4 can also export the heat of the ion trap chip 2 to enhance the heat dissipation capacity of the ion trap chip 2 and improve the performance of the ion trap chip 2.

[0066] Specifically, in the thickness direction of the circuit board 1, that is, Figure 4-Figure 8 In the up and down directions, the first packaging board 3 and the second packaging board 4 are clamped on both sides of the circuit board 1 to fix and support the circuit board 1. The first packaging board 3, the circuit board 1 and the second packaging board 4 can be connected by multiple fasteners such as screws and rivets.

[0067] The first packaging board 3 is provided with a first operating through hole 31. In the up and down directions, the first packaging board 3 is opposite to the first circuit surface 11, and the first operating through hole 31 corresponds to the first bonding terminal 111. The first operating through hole 31 also corresponds to the first electrode 211. When the first bonding terminal 111 is bonded to the first electrode 211, the pressure head of the wire bonding machine can be extended into the first operating through hole 31 to bond the first bonding terminal 111 to the first electrode 211 through wire bonding to avoid interference between the first packaging board 3 and the wire bonding machine.

[0068] The second packaging board 4 has a second supporting portion 42. In the up-down direction, the second supporting portion 42 abuts against the area corresponding to the second chip surface 22 and the first electrode 211, and / or the second supporting portion 42 abuts against the area corresponding to the second circuit surface 12 and the first electrode 211. That is, in the up-down direction, the second supporting portion 42 abuts against at least one area among the area corresponding to the second chip surface 22 and the first electrode 211 and the area corresponding to the second circuit surface 12 and the first electrode 211. Thus, when the first bonding terminal 111 is bonded to the first electrode 211, the second supporting portion 42 is located on the back side of the first electrode 211, and the second supporting portion 42 can support the ion trap chip 2 in the corresponding pressure area to reduce the deformation of the ion trap chip 2 when the first bonding terminal 111 is bonded to the first electrode 211, thereby avoiding cracks or damage to the ion trap chip 2 during bonding, thereby facilitating improving the yield rate of the quantum processing unit 10.

[0069] Reference Figure 4-Figure 8 In the illustrated embodiment, there are two second support portions 42 , which respectively abut against the areas of the second circuit surface 12 corresponding to the first electrodes 211 , that is, the two second support portions 42 respectively abut against two corresponding supporting protrusions 131 .

[0070] It should be noted that if there is no corresponding area between the second circuit surface 12 and the first electrode 211 in the up-down direction, that is, the projection of the first electrode 211 onto the second circuit surface 12 in the up-down direction is located outside the second circuit surface 12, then the second supporting portion 42 may only abut the area corresponding to the second chip surface 22 and the first electrode 211 (not shown in the figure).

[0071] If the second circuit surface 12 corresponds to only a portion of the first electrode 211 in the vertical direction, that is, a portion of the projection of the first electrode 211 onto the second circuit surface 12 in the vertical direction is located inside the second circuit surface 12, then the second supporting portion 42 can abut against the area of ​​the second circuit surface 12 corresponding to the portion of the first electrode 211, and the second supporting portion 42 also abuts against the area of ​​the second chip surface 22 corresponding to another portion of the first electrode 211 (not shown in the figure).

[0072] If the second circuit surface 12 corresponds to the entire area of ​​the first electrode 211 in the vertical direction, that is, the projection of the first electrode 211 on the second circuit surface 12 in the vertical direction is entirely located inside the second circuit surface 12, then the second support portion 42 may only abut against the area of ​​the second circuit surface 12 corresponding to the first electrode 211 (that is, Figures 1-8 embodiment shown).

[0073] The second packaging board 4 is provided with a second operating through hole 41. In the up and down directions, the second packaging board 4 is opposite to the second circuit surface 12, and the second operating through hole 41 corresponds to the second bonding terminal 121. The second operating through hole 41 also corresponds to the second electrode 221. When the second bonding terminal 121 is bonded to the second electrode 221, the pressure head of the wire bonding machine can be extended into the second operating through hole 41 to bond the second bonding terminal 121 to the second electrode 221 through wire bonding to avoid interference between the second packaging board 4 and the wire bonding machine.

[0074] The first packaging board 3 has a first supporting portion 32. In the up-down direction, the first supporting portion 32 abuts against the area corresponding to the first chip surface 21 and the second electrode 221, and / or the first supporting portion 32 abuts against the area corresponding to the first circuit surface 11 and the second electrode 221. That is, in the up-down direction, the first supporting portion 32 abuts against at least one area among the area corresponding to the first chip surface 21 and the second electrode 221, and the area corresponding to the first circuit surface 11 and the second electrode 221. Thus, when the second bonding terminal 121 is bonded to the second electrode 221, the first supporting portion 32 is located on the back side of the second electrode 221, and the first supporting portion 32 can support the ion trap chip 2 in the corresponding pressure area to reduce the deformation of the ion trap chip 2 when the second bonding terminal 121 is bonded to the second electrode 221, thereby avoiding cracks or damage to the ion trap chip 2 during bonding, thereby facilitating improving the yield rate of the quantum processing unit 10.

[0075] Reference Figure 4-Figure 8 In the illustrated embodiment, there are two first supporting portions 32 , and the two first supporting portions 32 abut against the front and rear ends of the first chip surface 21 , respectively.

[0076] It should be noted that if there is no corresponding area between the first circuit surface 11 and the second electrode 221 in the vertical direction, that is, the projection of the second electrode 221 on the first circuit surface 11 in the vertical direction is located outside the first circuit surface 11, then the first support portion 32 may only abut the area corresponding to the first chip surface 21 and the second electrode 221 (that is, Figures 1-8 embodiment shown).

[0077] If the first circuit surface 11 corresponds to only a portion of the second electrode 221 in the vertical direction, that is, a portion of the projection of the second electrode 221 onto the first circuit surface 11 in the vertical direction is located inside the first circuit surface 11, then the first supporting portion 32 can abut against the area of ​​the first circuit surface 11 corresponding to the portion of the second electrode 221, and the first supporting portion 32 also abuts against the area of ​​the first chip surface 21 corresponding to another portion of the second electrode 221 (not shown in the figure).

[0078] If the first circuit surface 11 corresponds to the entire area of ​​the second electrode 221 in the up-down direction, that is, the projection of the second electrode 221 onto the first circuit surface 11 in the up-down direction is entirely located inside the first circuit surface 11, then the first support portion 32 may only abut the area corresponding to the first circuit surface 11 and the second electrode 221 (not shown in the figure).

[0079] In addition, the provision of the first operating through hole 31 and the second operating through hole 41 can solve the problem of light path penetration, and enable light and signals to directly reach the ion trap chip 2 through the first operating through hole 31 or the second operating through hole 41 .

[0080] In some embodiments of the present invention, the outer surfaces of the first support portion 32 and the second support portion 42 are coated with an insulating buffer rubber layer. The insulating buffer rubber layer can make the first support portion 32 and the second support portion 42 have better electrical insulation performance, thereby avoiding the problem of the first support portion 32 and the second support portion 42 causing a short circuit in the ion trap chip 2, the circuit board 1 and the lead.

[0081] At the same time, the insulating buffer layer also has a buffering effect. When the quantum processing unit 10 operates at ultra-low temperature, the materials of various parts of the quantum processing unit 10 will produce corresponding micro-deformations due to the influence of low temperature, and the insulating buffer layer also acts as a buffer.

[0082] Reference Figure 4-Figure 6 As shown, the first packaging board 3 and the second packaging board 4 are also provided with avoidance grooves 5 corresponding to the signal lead-out terminals 14, so that the signal lead-out terminals 14 are exposed to the outside of the first packaging board 3 and the second packaging board 4, which is convenient for the subsequent lower connection of the signal lead-out terminals 14.

[0083] The first packaging board 3 and the second packaging board 4 can be provided with multiple foot pads 6, and the multiple foot pads 6 can be distributed around and in the middle of the first packaging board 3 and the second packaging board 4 on the side facing the circuit board 1. The first packaging board 3 and the second packaging board 4 are in contact with the circuit board 1 through the corresponding foot pads 6. Due to the height of the foot pads 6, an interlayer space that can accommodate the filter capacitor can be formed between the first packaging board 3 and the second packaging board 4 and the circuit board 1 to avoid damage to electronic components. In addition, the foot pads 6 can also be covered with an insulating buffer rubber layer to form an insulating and buffering effect.

[0084] According to the quantum processing unit 10 of an embodiment of the present invention, the ion trap chip 2 and the circuit board 1 both adopt a double-sided expansion structure, which reduces the overall size of the ion trap chip 2 and the circuit board 1 and realizes a greater number of electrical connections between the ion trap chip 2 and the circuit board 1. The first packaging board 3 and the second packaging board 4 have the functions of heat conduction, heat dissipation, support, shielding, fixation and protection, and the first operating through hole 31 and the second operating through hole 41 can directly control the ion trap chip 2, which also facilitates the control of the optical path.

[0085] Reference Figures 1-9 As shown, according to another embodiment of the present invention, a method for manufacturing a quantum processing unit, the quantum processing unit is the quantum processing unit of the above embodiment, and the method for manufacturing the quantum processing unit includes the following steps:

[0086] Step S1: assembling the ion trap chip to the chip mounting through hole.

[0087] The ion trap chip 2 can be mounted on the supporting protrusion 131 of the chip mounting through hole 13 by means of fasteners, and the circuit board 1 is integrated with a filter circuit.

[0088] Step S2: installing the first packaging board and the second packaging board on both sides of the circuit board in the thickness direction.

[0089] The first packaging board 3 and the second packaging board 4 can be mounted on the upper and lower sides of the circuit board 1 by fasteners, and the first supporting portion 32 and the second supporting portion 42 can directly or indirectly support the ion trap chip 2 on the upper and lower sides.

[0090] Step S3 , bonding the first electrode to the first bonding terminal, and bonding the second electrode to the second bonding terminal.

[0091] A wire bonding machine can be used to extend into the first operating through hole 31 and bond the first electrode 211 to the first bonding terminal 111 using a wire. Then, the quantum processing unit 10 is flipped over, and the wire bonding machine is extended into the second operating through hole 41 and bonded to the second electrode 221 to the second bonding terminal 121 using a wire.

[0092] According to the manufacturing method of the quantum processing unit 10 of an embodiment of the present invention, the ion trap chip 2 is fixed to the chip mounting through-hole 13 of the circuit board 1, and the circuit board 1 and the ion trap chip 2 can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board 1 and the ion trap chip 2. The electrical connections between the circuit board 1 and the ion trap chip 2 can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty between the circuit board 1 and the ion trap chip 2. At the same time, the first support portion 32 and the second support portion 42 can directly or indirectly support the ion trap chip 2 on the upper and lower sides of the ion trap chip 2 to prevent the ion trap chip 2 from being damaged and failing, which is beneficial to improving the yield of the quantum processing unit 10 and reducing the manufacturing cost of the quantum processing unit 10.

[0093] A quantum computer according to another embodiment of the present invention includes the quantum processing unit 10 of the above embodiment.

[0094] According to the quantum computer of an embodiment of the present invention, the ion trap chip 2 of its quantum processing unit 10 is fixed to the chip mounting through-hole 13 of the circuit board 1. The circuit board 1 and the ion trap chip 2 can be connected by double-sided bonding, which is beneficial to increasing the number of electrical connections established between the circuit board 1 and the ion trap chip 2. The electrical connections between the circuit board 1 and the ion trap chip 2 can also be dispersed on two different sides to reduce the bonding density on a single side and reduce the bonding difficulty of the circuit board 1 and the ion trap chip 2, which is beneficial to improving the performance of the quantum computer and reducing the manufacturing cost of the quantum computer.

[0095] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0096] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A quantum processing unit, characterized in that include: A circuit board (1), wherein the circuit board (1) is provided with a chip mounting through hole (13), the circuit board (1) having a first circuit surface (11) and a second circuit surface (12) facing each other in a thickness direction thereof, the first circuit surface (11) having a first bonding terminal (111), and the second circuit surface (12) having a second bonding terminal (121); An ion trap chip (2), the ion trap chip (2) being fixed to the chip mounting through hole (13), the ion trap chip (2) having a first chip surface (21) and a second chip surface (22) facing each other in a thickness direction thereof, the first chip surface (21) having a first electrode (211), and the second chip surface (22) having a second electrode (221); The first circuit surface (11) and the first chip surface (21) are oriented in the same direction, and the first electrode (211) is bonded to the first bonding terminal (111); the second circuit surface (12) and the second chip surface (22) are oriented in the same direction, and the second electrode (221) is bonded to the second bonding terminal (121).

2. The quantum processing unit according to claim 1, characterized in that In the thickness direction of the ion trap chip (2), the first electrode (211) and the second electrode (221) are staggered, and the first bonding terminal (111) and the second bonding terminal (121) are staggered.

3. The quantum processing unit according to claim 2, characterized in that The first electrodes (211) and the first bonding terminals (111) are both multiple in number and bonded to each other in a one-to-one correspondence; the second electrodes (221) and the second bonding terminals (121) are both multiple in number and bonded to each other in a one-to-one correspondence.

4. The quantum processing unit according to claim 3, characterized in that In the width direction of the ion trap chip (2), both ends of the first chip surface (21) are provided with at least one first electrode (211), and the first bonding terminal (111) is arranged adjacent to the corresponding first electrode (211); In the length direction of the ion trap chip (2), both ends of the second chip surface (22) are provided with at least one second electrode (221), and the second bonding terminal (121) is arranged adjacent to the corresponding second electrode (221).

5. The quantum processing unit according to claim 1, wherein: The circuit board (1) has a filter circuit and a signal lead-out terminal (14); the first bonding terminal (111) and the second bonding terminal (121) are both connected to the signal lead-out terminal (14) via the filter circuit.

6. The quantum processing unit according to claim 1, wherein: A bearing protrusion (131) is formed on the hole wall of the chip mounting through hole (13), and the ion trap chip (2) is fixedly connected to the bearing protrusion (131) via a fastener.

7. The quantum processing unit according to any one of claims 1 to 6, characterized in that The quantum processing unit further comprises: a first packaging board (3), the first packaging board (3) being opposite to the first circuit surface (11), the first packaging board (3) being provided with a first operation through hole (31), and the first packaging board (3) having a first supporting portion (32); a second packaging board (4), the second packaging board (4) being opposite to the second circuit surface (12), the second packaging board (4) being provided with a second operation through hole (41), and the second packaging board (4) having a second supporting portion (42); Wherein, in the thickness direction of the circuit board (1): The first packaging board (3) and the second packaging board (4) are clamped on both sides of the circuit board (1); The first operating through hole (31) corresponds to the first bonding terminal (111), and the first operating through hole (31) also corresponds to the first electrode (211); The second operating through hole (41) corresponds to the second bonding terminal (121), and the second operating through hole (41) also corresponds to the second electrode (221); The first supporting portion (32) abuts against an area corresponding to the first chip surface (21) and the second electrode (221), and / or the first supporting portion (32) abuts against an area corresponding to the first circuit surface (11) and the second electrode (221); The second supporting portion (42) abuts against an area of ​​the second chip surface (22) corresponding to the first electrode (211), and / or the second supporting portion (42) abuts against an area of ​​the second circuit surface (12) corresponding to the first electrode (211).

8. The quantum processing unit according to claim 7, characterized in that The outer surfaces of the first supporting portion (32) and the second supporting portion (42) are both coated with an insulating buffer rubber layer.

9. A method for manufacturing a quantum processing unit, characterized in that: The quantum processing unit is a quantum processing unit according to claim 7 or 8, and the manufacturing method of the quantum processing unit comprises the following steps: Assembling the ion trap chip to the chip mounting through hole; Installing the first packaging board and the second packaging board on both sides of the circuit board in the thickness direction; The first electrode is bonded to the first bonding terminal, and the second electrode is bonded to the second bonding terminal.

10. A quantum computer, characterized in that: Comprising a quantum processing unit according to any one of claims 1-8.

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