Analog-to-digital conversion circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides an analog-to-digital conversion circuit, a chip and electronic equipment, and the analog-to-digital conversion circuit comprises a comparison processing module, a switched capacitor module and a switch control module. A comparison processing module outputs a digital signal according to a comparison result of a first generation voltage and a second generation voltage and generates a feedback signal based on the digital signal, a switched capacitor module determines the first generation voltage and the second generation voltage according to a control signal, and a switch control module generates a control signal according to the feedback signal. The switching quantity of unit capacitors in the switched capacitor module is gradually reduced in each quantization stage, and the switching quantity of the unit capacitors is remarkably reduced along with the increase of the switching times in the quantization stage, so that the switching power consumption of the unit capacitors is reduced, and the precision loss caused by capacity mismatch of the unit capacitors is reduced; therefore, the precision of analog-to-digital conversion is improved, and nonlinear indexes such as differential nonlinearity and integral nonlinearity are improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and in particular, to an analog-to-digital conversion circuit, a chip, and an electronic device. Background Art

[0002] In an analog-to-digital conversion circuit with a capacitor array, the switching method of the capacitor array has an important impact on the overall performance, and the overall performance includes indicators such as area, power consumption, and non-linearity.

[0003] However, due to the influence of various factors, it is difficult to achieve the ideal value designed for the actual capacitance value of the capacitors in the capacitor array, which reduces the accuracy of analog-to-digital conversion. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide an analog-to-digital conversion circuit, a chip, and an electronic device to alleviate the above technical problems.

[0005] In a first aspect, an embodiment of this application provides an analog-to-digital conversion circuit, which includes a comparison processing module, a switched-capacitor module, and a switch control module. The comparison processing module is configured to output a digital signal according to the comparison result between a first generated voltage and a second generated voltage, and generate a feedback signal based on the digital signal; the switched-capacitor module is configured to determine the first generated voltage and the second generated voltage according to a control signal; the switch control module is configured to generate a control signal according to the feedback signal to sequentially reduce the switching number of unit capacitors in the switched-capacitor module in each quantization stage.

[0006] In a second aspect, an embodiment of this application further provides a chip, which includes the above-mentioned analog-to-digital conversion circuit.

[0007] In a third aspect, an embodiment of this application further provides an electronic device, which includes a device main body and the above-mentioned analog-to-digital conversion circuit or chip provided on the device main body.

[0008] The analog-to-digital conversion circuit, chip, and electronic device provided by the embodiments of this application output a digital signal according to the comparison result between a first generated voltage and a second generated voltage through the comparison processing module and generate a feedback signal based on the digital signal. The switched-capacitor module determines the first generated voltage and the second generated voltage according to the control signal, and the switch control module generates a control signal according to the feedback signal to sequentially reduce the switching number of unit capacitors in the switched-capacitor module in each quantization stage. As the number of switching times increases in the quantization stage, the switching number of unit capacitors will be significantly reduced, which not only reduces the switching power consumption of unit capacitors, but also reduces the accuracy loss caused by the capacitance mismatch of unit capacitors, thereby improving the accuracy of analog-to-digital conversion and improving non-linear indicators such as differential non-linearity and integral non-linearity.

[0009] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 The principle block diagram of the analog-to-digital conversion circuit provided by the embodiment of the present application is shown.

[0012] Figure 2 The principle block diagram of the comparison processing module is shown.

[0013] Figure 3 The principle block diagram of the switched-capacitor module is shown.

[0014] Figure 4 The circuit schematic diagram of the first switched-capacitor array is shown.

[0015] Figure 5 The circuit schematic diagram of the second switched-capacitor array is shown.

[0016] Figure 6 The principle block diagram of the switch control module is shown.

[0017] Figure 7 The circuit schematic diagram of the switching unit is shown.

[0018] Figure 8 The working flowchart of the analog-to-digital conversion circuit provided by the embodiment of the present application is shown.

[0019] Figure 9 The switch logic schematic diagram of the capacitor array provided by the embodiment of the present application is shown.

[0020] Figure 10 The differential non-linearity schematic diagram of the analog-to-digital conversion circuit in the related art is shown.

[0021] Figure 11 The integral non-linearity schematic diagram of the analog-to-digital conversion circuit in the related art is shown.

[0022] Figure 12 The differential non-linearity schematic diagram of the analog-to-digital conversion circuit provided by the embodiment of the present application is shown.

[0023] Figure 13 The integral non-linearity schematic diagram of the analog-to-digital conversion circuit provided by the embodiment of the present application is shown.

[0024] Figure 14 The schematic structural diagram of the chip provided by the embodiment of the present application is shown.

[0025] Figure 15 The schematic structural diagram of the electronic device provided by the embodiment of the present application is shown. Detailed implementation manners

[0026] The following describes in detail the implementation manners of the present application. The examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below by referring to the accompanying drawings are exemplary and are only used to explain the present application and cannot be construed as a limitation to the present application.

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0028] In the embodiments of the present application, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0029] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, solution, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, solution, article or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, solution, article or device including the said element.

[0030] In the description of the embodiments of the present application, words such as "example" or "for example" are used to represent examples, explanations or descriptions. Any embodiment or design solution described as "for example" or "for instance" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0031] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two, or more. For example, including at least one means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A and B and C.

[0032] It should be noted that "connection" in the embodiments of the present application can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0033] As a low-power medium-high-speed analog-to-digital converter (ADC), the design of the capacitor array of the digital-to-analog converter (DAC) and the switching method of the switches have an important impact on the overall performance of the ADC, especially on indicators such as area, power consumption, and non-linearity. Therefore, the research on the DAC capacitor array and its switching scheme is crucial.

[0034] Taking the simplest differential SAR ADC as an example, the switching scheme of its DAC capacitor array causes high power consumption, and its differential non-linearity (DNL) and integral non-linearity (INL) performances are very poor; while for the single-ended switching scheme (Monotonic scheme), although its DNL and INL performances are much better, this scheme will cause too large a change in the common-mode voltage (VCM) at both ends of the comparator, which in turn leads to the dynamic offset of the comparator, deteriorating the performance of the ADC, and this scheme is not applicable to the low-voltage domain; the switching scheme of the VCM_Based structure is not applicable to the low-voltage domain circuit because it requires an additional VCM generation circuit, and its DNL / INL performance is not very good either, and the additional VCM generation circuit will also consume more power.

[0035] In summary, there are situations where the switching scheme of the DAC capacitor array in the SAR ADC has high power consumption and poor performance indicators such as DNL and INL.

[0036] Based on the above analysis, the embodiments of the present application provide an analog-to-digital conversion circuit 100. Please refer to Figures 1 to 13, based on the original SAR ADC, the analog-to-digital conversion circuit 100 adds a switch control module 30, changes the switching logic of the feedback signal FB for the DAC capacitor array, and realizes the switching logic of the DAC capacitor array through the control signal CTL. It can gradually reduce the switching number of the unit capacitors in the switched-capacitor module 20 in each quantization stage. As the number of switching times increases in the quantization stage, the switching number of the unit capacitors will be significantly reduced. This not only reduces the switching power consumption of the unit capacitors, but also reduces the accuracy loss caused by the capacitance mismatch of the unit capacitors, thereby improving the accuracy of analog-to-digital conversion and improving non-linear indexes such as differential non-linearity and integral non-linearity.

[0037] An embodiment of the present application provides an analog-to-digital conversion circuit 100, as Figure 1 shown, the analog-to-digital conversion circuit 100 includes a comparison processing module 10, a switched-capacitor module 20, and a switch control module 30. The comparison processing module 10 is configured to output a digital signal DOUT according to the comparison result between the first generated voltage and the second generated voltage, and generate a feedback signal FB based on the digital signal DOUT; the switched-capacitor module 20 is configured to determine the first generated voltage and the second generated voltage according to the control signal CTL; the switch control module 30 is configured to generate the control signal CTL according to the feedback signal FB to gradually reduce the switching number of the unit capacitors in the switched-capacitor module 20 in each quantization stage.

[0038] It can be understood that for the analog-to-digital conversion circuit 100 provided by the embodiment of the present application, the comparison processing module 10 outputs the digital signal DOUT according to the comparison result between the first generated voltage and the second generated voltage and generates the feedback signal FB based on the digital signal DOUT, the switched-capacitor module 20 determines the first generated voltage and the second generated voltage according to the control signal CTL, and the switch control module 30 generates the control signal CTL according to the feedback signal FB to gradually reduce the switching number of the unit capacitors in the switched-capacitor module 20 in each quantization stage. As the number of switching times increases in the quantization stage, the switching number of the unit capacitors will be significantly reduced. This not only reduces the switching power consumption of the unit capacitors, but also reduces the accuracy loss caused by the capacitance mismatch of the unit capacitors, thereby improving the accuracy of analog-to-digital conversion and improving non-linear indexes such as differential non-linearity and integral non-linearity.

[0039] It should be noted that the analog-to-digital conversion circuit 100 can be a SAR ADC with various bit numbers, such as a SAR ADC with redundant bits and a non-binary SAR ADC. Successively reducing the switching number of unit capacitors in the switched-capacitor module 20 in each quantization stage means that there is one or more quantization stages between two sampling stages. For example, there are successively a first quantization stage, a second quantization stage, a third quantization stage, etc. Then, the switching number of unit capacitors in the first quantization stage is greater than that in the second quantization stage, the switching number of unit capacitors in the second quantization stage is greater than that in the third quantization stage, and so on.

[0040] Among them, the switching number of unit capacitors refers to the number of unit capacitors whose voltage at one end is switched from one voltage to another voltage in any quantization stage.

[0041] In some embodiments, as Figure 2 shown, the comparison processing module 10 includes a comparison unit 11, a switching unit 12, and a logic processing unit 13. The first input terminal of the comparison unit 11 is used to receive a first generated voltage, the second input terminal of the comparison unit 11 is used to receive a second generated voltage, and the output terminal of the comparison unit 11 is used to output a comparison result; the switching unit 12 is used to control the common-mode voltage VCM to be transmitted to the first input terminal and the second input terminal of the comparison unit 11 respectively in the sampling stage, and to prohibit the common-mode voltage VCM from being transmitted to the first input terminal and the second input terminal of the comparison unit 11 in the quantization stage; the logic processing unit 13 is used to output a digital signal DOUT according to the comparison result and generate a feedback signal FB based on the digital signal DOUT.

[0042] It should be noted that the comparison unit 11 can be a comparator. The first input terminal of the comparison unit 11 is the positive-phase input terminal (+) of the comparator, and the second input terminal of the comparison unit 11 is the anti-phase input terminal (-) of the comparator. The logic processing unit 13 can be a unit or circuit that executes the SAR logic, i.e., the successive approximation algorithm.

[0043] In some embodiments, as Figure 3 shown, the switched-capacitor module 20 includes a first switched-capacitor array 21 and a second switched-capacitor array 22. The first switched-capacitor array 21 is used to determine a first generated voltage according to a control signal CTL; the second switched-capacitor array 22 is used to determine a second generated voltage according to the control signal CTL.

[0044] It should be noted that in this embodiment, the voltage at one end of the unit capacitor can be switched to different power supply voltages VREF, ground voltages GND, or sampling voltages through the control signal CTL, so that the voltage at the other end of the unit capacitor changes, thereby forming corresponding first generated voltages and second generated voltages.

[0045] In some embodiments, such as Figure 4 As shown, the first switched-capacitor array 21 includes a plurality of first unit capacitors CU1 with the same capacitance and a plurality of first control switches K1. The first end of each first unit capacitor CU1 is connected to the first input terminal of the comparison unit 11; the common terminal of each first control switch K1 is connected to the second end of a first unit capacitor CU1, and each first control switch K1 controls the common terminal to be connected to one of the power supply voltage VREF, the ground voltage GND, and the first sampling voltage VIP according to the control signal CTL.

[0046] It should be noted that the first end of the first control switch K1 is connected to the power supply voltage VREF, the first end of the first control switch K1 is connected to the ground voltage GND, and the third end of the first control switch K1 is connected to the first sampling voltage VIP. When the common terminal of the first control switch K1 is connected to the first end of the first control switch K1, the common terminal of the first control switch K1 is connected to the power supply voltage VREF. When the common terminal of the first control switch K1 is connected to the second end of the first control switch K1, the common terminal of the first control switch K1 is connected to the ground voltage GND. When the common terminal of the first control switch K1 is connected to the third end of the first control switch K1, the common terminal of the first control switch K1 is connected to the first sampling voltage VIP.

[0047] Among them, the number of the first unit capacitors CU1 is related to the number of bits of the analog-to-digital conversion. Let the number of bits of the analog-to-digital conversion be N, and N is a positive integer, such as any one of 2 - 12. Then the number of the first unit capacitors CU1 is 2 to the power of N. Compared with the different capacitances of the first unit capacitors CU1 in the first switched-capacitor array 21, more mismatches may be introduced when switching different first unit capacitors CU1. In this embodiment, the first unit capacitors CU1 with the same capacitance are configured, which can avoid introducing more capacitance mismatches, thereby improving the analog-to-digital conversion accuracy.

[0048] In some embodiments, such as Figure 5As shown, the second switched-capacitor array 22 includes a plurality of second unit capacitors CU2 with the same capacitance and a plurality of second control switches K2. The first terminal of each second unit capacitor CU2 is connected to the second input terminal of the comparison unit 11; the common terminal of each second control switch K2 is connected to the second terminal of a second unit capacitor CU2, and each second control switch K2 controls the common terminal to be connected to one of the power supply voltage VREF, the ground voltage GND, and the second sampling voltage VIN according to the control signal CTL; wherein, the capacitance of a first unit capacitor CU1 is the same as that of a second unit capacitor CU2.

[0049] It should be noted that the first terminal of the second control switch K2 is connected to the power supply voltage VREF, the second terminal of the second control switch K2 is connected to the ground voltage GND, and the third terminal of the second control switch K2 is connected to the first sampling voltage VIP. When the common terminal of the second control switch K2 is connected to the first terminal of the second control switch K2, the common terminal of the second control switch K2 is connected to the power supply voltage VREF. When the common terminal of the second control switch K2 is connected to the second terminal of the second control switch K2, the common terminal of the second control switch K2 is connected to the ground voltage GND. When the common terminal of the second control switch K2 is connected to the third terminal of the second control switch K2, the common terminal of the second control switch K2 is connected to the second sampling voltage VIN.

[0050] Wherein, the number of the second unit capacitors CU2 is related to the number of bits of the analog-to-digital conversion, and the number of the second unit capacitors CU2 is 2 to the power of N. Compared with the different capacitances of the second unit capacitors CU2 in the second switched-capacitor array 22, more mismatches may be introduced when switching different second unit capacitors CU2. In this embodiment, the second unit capacitors CU2 with the same capacitance are configured, which can avoid introducing more capacitance mismatches, thereby improving the analog-to-digital conversion accuracy. Moreover, in this embodiment, the capacitance of the first unit capacitor CU1 is configured to be the same as that of the second unit capacitor CU2, which is beneficial to canceling the mismatch of the first unit capacitor CU1 and the mismatch of the second unit capacitor CU2 in the quantization stage, thereby avoiding introducing more capacitance mismatches and improving the analog-to-digital conversion accuracy.

[0051] In some embodiments, as Figure 6 shown, the switch control module 30 includes a first switch control unit 31 and a second switch control unit 32. The first switch control unit 31 is used to generate a first control signal, a second control signal, and a third control signal according to the feedback signal FB to successively reduce by at least half the switching number of the unit capacitors in the first switched-capacitor array 21 in each quantization stage; the second switch control unit 32 is used to generate a first control signal, a second control signal, and a third control signal according to the feedback signal FB to successively reduce by at least half the switching number of the unit capacitors in the second switched-capacitor array 22 in each quantization stage.

[0052] It should be noted that the control signal CTL in the above embodiments may include a first control signal, a second control signal, and a third control signal. For the first control signal, the second control signal, and the third control signal, in the same quantization stage, when the first switch control unit 31 controls the voltage applied to the first unit capacitor CU1 in the first switched capacitor array 21 to switch from the power supply voltage VREF to the ground voltage GND, the second switch control unit 32 controls the voltage applied to the second unit capacitor CU2 in the second switched capacitor array 22 to switch from the ground voltage GND to the power supply voltage VREF; or, when the first switch control unit 31 controls the voltage applied to the first unit capacitor CU1 in the first switched capacitor array 21 to switch from the ground voltage GND to the power supply voltage VREF, the second switch control unit 32 controls the voltage applied to the second unit capacitor CU2 in the second switched capacitor array 22 to switch from the power supply voltage VREF to the ground voltage GND.

[0053] Among them, at least halving means reducing to more than half. For example, if the number of switched unit capacitors in the first quantization stage is 8, then the number of switched unit capacitors in the subsequent second quantization stage is 4 or less.

[0054] In some of the embodiments, the first control signal is used to select a certain column of unit capacitors to be switched in the first switched capacitor array 21, the second control signal is used to select at least one row of unit capacitors to be switched from the column of unit capacitors selected by the first control signal; the third control signal is used to determine that a column of unit capacitors selected by the previous first control signal is the unit capacitor to be switched; in the first switched capacitor array 21, for the second terminal of the unit capacitor to be switched, the power supply voltage VREF is selected to be connected, and for the second terminal of the unit capacitor not to be switched, the ground voltage GND is selected to be connected.

[0055] In some of the embodiments, the first control signal is used to select a certain column of unit capacitors to be switched in the second switched capacitor array 22, the second control signal is used to select at least one row of unit capacitors to be switched from the column of unit capacitors selected by the first control signal; the third control signal is used to determine that a column of unit capacitors selected by the previous first control signal is the unit capacitor to be switched; in the second switched capacitor array 22, for the second terminal of the unit capacitor to be switched, the ground voltage GND is selected to be connected, and for the second terminal of the unit capacitor not to be switched, the power supply voltage VREF is selected to be connected.

[0056] It should be noted that the first control signal, the second control signal, and the third control signal are used to select the unit capacitors that need to be switched in each quantization stage. Among them, the unit capacitors to be switched refer to those that have both unit capacitors that need to be switched and those that do not need to be switched. The second control signal is required to further distinguish the unit capacitors that need to be switched from those that do not need to be switched.

[0057] In some embodiments, during the sampling stage, the second ends of the first unit capacitors CU1 are all connected to the first sampling voltage VIP, and the second ends of the second unit capacitors CU2 are all connected to the second sampling voltage VIN; during the quantization stage, the second ends of the first unit capacitors CU1 that need to be switched are selected to be connected to the power supply voltage VREF, and the second ends of the first unit capacitors CU1 that do not need to be switched are selected to be connected to the ground voltage GND; the second ends of the second unit capacitors CU2 that need to be switched are selected to be connected to the ground voltage GND, and the second ends of the second unit capacitors CU2 that do not need to be switched are selected to be connected to the power supply voltage VREF.

[0058] In some embodiments, as Figure 7 shown, the switching unit 12 includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the common-mode voltage VCM, the second end of the first switch S1 is connected to the first input terminal of the comparison unit 11, the first end of the second switch S2 is connected to the common-mode voltage VCM, and the second end of the second switch S2 is connected to the second input terminal of the comparison unit 11.

[0059] It should be noted that during the sampling stage, the first switch S1 and the second switch S2 are both closed, so that the upper plates of the first unit capacitors CU1 and the upper plates of the second unit capacitors CU2 are all connected to the common-mode voltage VCM; and it is controlled that the lower plates of the first unit capacitors CU1 are all connected to the first sampling voltage VIP, and the lower plates of the second unit capacitors CU2 are all connected to the second sampling voltage VIN. During the quantization stage, the first switch S1 and the second switch S2 are both opened, prohibiting the upper plates of the first unit capacitors CU1 and the upper plates of the second unit capacitors CU2 from being connected to the common-mode voltage VCM.

[0060] In summary, the switch control logic of the DAC array in the SAR ADC of each embodiment of the present application is described as follows by taking a 4-bit differential SAR ADC as an example:

[0061] Taking the first switched-capacitor array 21 as an example, the upper plate of each first unit capacitor CU1 is connected to the positive-phase input terminal of the comparison unit 11, and the lower plate of each first unit capacitor CU1 can be connected to the power supply voltage VREF, the ground voltage GND, or the first sampling voltage VIP through its respective switch control. The output result of the comparison unit 11 is connected to the logic processing unit 13 to provide the comparison result each time during the quantization process. The logic processing unit 13 can periodically output the codeword corresponding to the current input, and provide the input of the switch control logic, that is, the feedback signal FBFB<3:0>. This feedback signal FB is processed by the switch control logic and then outputs the control signals CTL for controlling the switches of the DAC array, namely the first control signal, the second control signal, and the third control signal. Among them, the number of bits of the feedback signal FB is the same as the number of bits of the analog-to-digital conversion.

[0062] Specifically, please refer to Figure 8 and Figure 9 Taking the first switched-capacitor array 21 of a 4-bit differential SAR ADC as an example, where the first switched-capacitor array 21 includes 16 first unit capacitors CU1 distributed in an array. For example, Figure 8 each square where the numbers 1-16 are located in represents the coding of a first unit capacitor CU1. The working process is described as follows:

[0063] Sampling stage: The upper plates of the first unit capacitors CU1 in the first switched-capacitor array 21 and the upper plates of the second unit capacitors CU2 in the second switched-capacitor array 22 are all connected to the common-mode voltage VCM. The lower plates of the first unit capacitors CU1 in the first switched-capacitor array 21 are all connected to the first sampling voltage VIP, and the lower plates of the second unit capacitors CU2 in the second switched-capacitor array 22 are all connected to the second sampling voltage VIN.

[0064] Quantization stage: After the sampling stage ends, the upper plates of the first unit capacitors CU1 in the first switched-capacitor array 21 and the upper plates of the second unit capacitors CU2 in the second switched-capacitor array 22 are all disconnected from the access of the common-mode voltage VCM. The lower plates of half of the first unit capacitors CU1 in the first switched-capacitor array 21 (for example, 8 first unit capacitors CU1 shown in the coding 1-8) are connected to the power supply voltage VREF, and the lower plates of the other half of the first unit capacitors CU1 (for example, 8 first unit capacitors CU1 shown in the coding 9-15) are connected to the ground voltage GND.

[0065] At this time, the comparison unit 11 will compare whether the difference between the first sampled voltage VIP and the second sampled voltage VIN is greater than 0 in the comparison stage, that is, "VIP > VIN?". If VIP > VIN, that is, "Yes", the comparison result of the comparison unit 11 is a high level, and the highest bit of the digital signal DOUT is 1. Then, through the first control signal, the second control signal, and the third control signal, the lower plates of a quarter of the first unit capacitors CU1 in the first switched-capacitor array 21 (for example, 4 first unit capacitors CU1 shown in codes 9-12) are connected to the power supply voltage VREF. If VIP < VIN, that is, "No", the comparison result of the comparison unit 11 is a low level, and the highest bit of the digital signal DOUT is 0. Then, through the first control signal, the second control signal, and the third control signal, the lower plates of a quarter of the first unit capacitors CU1 in the first switched-capacitor array 21 (for example, 4 first unit capacitors CU1 shown in codes 5-8) are connected to the ground voltage GND. And so on, the switching quantity of the first unit capacitor CU1 each time is half of the previous time until the switching quantity of the first unit capacitor CU1 is finally 1.

[0066] The switching quantity of the second unit capacitor CU2 in the second switched-capacitor array 22 is the same as or consistent with the switching quantity of the first unit capacitor CU1 in the first switched-capacitor array 21. The difference is that if the first unit capacitor CU1 to be switched in the first switched-capacitor array 21 is connected to the power supply voltage VREF, then the second unit capacitor CU2 to be switched in the second switched-capacitor array 22 is connected to the ground voltage GND; or, if the first unit capacitor CU1 to be switched in the first switched-capacitor array 21 is connected to the ground voltage GND, then the second unit capacitor CU2 to be switched in the second switched-capacitor array 22 is connected to the power supply voltage VREF.

[0067] Optionally, the sequential switching can be performed according to the Figure 8 encoding shown, or the switching can also be performed according to the inventive concept in the present application.

[0068] Among them, the logic of the switch control module 30 is used to complete the above switching method. Its specific principle is to regard the capacitor array as a matrix. The switch control module 30 generates the first control signal, the second control signal, and the third control signal according to one of the output signals of the logic processing unit 13, that is, the feedback signal FB (assuming it is FB<3:0>, at the beginning of quantization, FB<3:0> = 1000. When the first comparison unit 11 outputs a high level for the first time, then FB<3:0> = 1100; when the first comparator outputs a low level for the first time, then FB<3:0> = 0100, and so on).

[0069] Convert FB<3:0> to decimal. Among them, the second control signal CTL1 is the row selection signal. Every 1 unit, the first unit capacitor CU1 of the 2nd, 3rd, 1st, and 4th rows is sequentially selected; the first control signal CTL2 is the column selection signal. Every 4 units, the first unit capacitor CU1 of the 2nd, 3rd, 1st, and 4th columns is sequentially selected; the third control signal CTL3 is the column selection signal for the entire column. Every 4 units, the first unit capacitor CU1 of the 2nd, 3rd, 1st, and 4th columns is sequentially selected.

[0070] The specific selection rule for the first unit capacitor CU1 to be switched is as follows: CTL2 first determines which column's first unit capacitor CU1 to select, then CTL1 sequentially selects the first unit capacitor CU1 of the 2nd, 3rd, 1st, and 4th rows among them, and CTL3 selects all the first unit capacitors CU1 in the entire column selected by the previous CTL2. In the first switched-capacitor array 21, the lower plate of the selected first unit capacitor CU1 is connected to the power supply voltage VREF, and the lower plate of the unselected first unit capacitor CU1 is connected to the ground voltage GND; the second switched-capacitor array 22 is the opposite. The lower plate of the selected second unit capacitor CU2 is connected to the ground voltage GND, and the lower plate of the unselected second unit capacitor CU2 is connected to the power supply voltage VREF.

[0071] According to the above design, the capacitance switching logic of the switch control module 30 is as Figure 9 shown, where ⊙ represents the exclusive-NOR operation, the asterisk represents the AND operation, + represents the OR operation, ~ represents the negation operation, 1 represents the logic high level, 0 represents the logic low level, and D3, D2, D1, D0 respectively represent the four-bit data of FB<3:0> from high to low in sequence.

[0072] Among them, Figure 9 the above table in is to determine some intermediate data based on the feedback signal FB, Figure 9 and the following table in is to determine whether the first unit capacitor CU1 in the first switched-capacitor array 21 needs to be switched based on these intermediate data.

[0073] Specifically, in Figure 9 the above table, the calculation result of the formula D2⊙(D1×D0) in the square in the second row and second column is CTL1_1, the formula D3 in the square in the second row and third column is CTL2_1, and the calculation result of the formula D3×D2 in the square in the second row and fourth column is CTL3_1.

[0074] The calculation result of the formula D2⊙(D1+D0) in the square in the third row and second column is CTL1_2, the constant "1" in the square in the third row and third column is CTL2_2, and the calculation result of the formula D3+D2 in the square in the third row and fourth column is CTL3_2.

[0075] The calculation formula in the square at the second column of the fourth row, which is the calculation result of D2⊙D1, is CTL1_3. The calculation formula in the square at the third column of the fourth row, which is the calculation result of D3+D2, is CTL2_3. The calculation formula in the square at the fourth column of the fourth row, which is D3, is CTL3_3.

[0076] The calculation formula in the square at the second column of the fifth row is ～ The calculation result of D2 is CTL1_4. The calculation formula in the square at the third column of the fifth row, which is the calculation result of D3×D2, is CTL2_4. The constant "0" in the square at the fourth column of the fifth row is CTL3_4.

[0077] In Figure 9 the following table, the calculation formula shown in the second column of the second row, which is ( ～ (CTL1_1×CTL2_1)+CTL3_1), is used to represent whether the first unit capacitor CU1 encoded as 11 in Figure 8 needs to be switched. The calculation formula shown in the third column of the second row, which is ( ～ (CTL1_1×CTL2_2)+CTL3_2), is used to represent whether the first unit capacitor CU1 encoded as 3 in Figure 8 needs to be switched. The calculation formula shown in the fourth column of the second row, which is (CTL1_1×CTL2_3)+CTL3_3, is used to represent whether the first unit capacitor CU1 encoded as 7 in Figure 8 needs to be switched. The calculation formula shown in the fifth column of the second row, which is (CTL1_1×CTL2_4)+CTL3_4, is used to represent whether the first unit capacitor CU1 encoded as 15 in Figure 8 needs to be switched.

[0078] The calculation formula shown in the second column of the third row, which is ( ～ (CTL1_2×CTL2_1)+CTL3_1), is used to represent whether the first unit capacitor CU1 encoded as 9 in Figure 8 needs to be switched. The calculation formula shown in the third column of the third row, which is ( ～ (CTL1_2×CTL2_2)+CTL3_2), is used to represent whether the first unit capacitor CU1 encoded as 1 in Figure 8 needs to be switched. The calculation formula shown in the fourth column of the third row, which is (CTL1_2×CTL2_3)+CTL3_3, is used to represent whether the first unit capacitor CU1 encoded as 5 in Figure 8 needs to be switched. The calculation formula shown in the fifth column of the third row, which is (CTL1_2×CTL2_4)+CTL3_4, is used to represent whether the first unit capacitor CU1 encoded as 13 in Figure 8 needs to be switched.

[0079] The calculation formula shown in the second column of the fourth row, i.e., ( ～ (CTL1_3 × CTL2_1) + CTL3_1, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 10 in ～ (CTL1_3 × CTL2_2) + CTL3_2, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 2 in Figure 8 (CTL1_3 × CTL2_3) + CTL3_3, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 6 in

[0080] The calculation formula shown in the second column of the fifth row, i.e., ( ～ (CTL1_4 × CTL2_1) + CTL3_1, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 12 in ～ (CTL1_4 × CTL2_2) + CTL3_2, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 4 in Figure 8 (CTL1_4 × CTL2_3) + CTL3_3, the calculation result is used to represent Figure 8 whether the first unit capacitor CU1 encoded as 8 in

[0081] Among them, "×" represents the AND operation. In Figure 9 the following table, if the calculation result of the calculation formula is high level, the first unit capacitor CU1 corresponding to the calculation formula is connected to the power supply voltage VREF, and the second unit capacitor CU2 corresponding to the calculation formula is connected to the ground voltage GND; if the calculation result of the calculation formula is low level, the first unit capacitor CU1 corresponding to the calculation formula is connected to the ground voltage GND, and the second unit capacitor CU2 corresponding to the calculation formula is connected to the power supply voltage VREF.

[0082] In the quantization process of the SAR ADC, when the output of the comparison unit 11 is 0, the number of switched unit capacitors this time is only half of that of the previous time, or even lower. For example Figure 8 in Figure 8 , if the first comparison result is 0, according to the traditional principle of the SAR ADC, it is necessary to switch 8 unit capacitors at the highest bit to the ground voltage GND and 4 unit capacitors at the second highest bit to the power supply voltage VREF. In this way, the number of switched unit capacitors is 12. Correspondingly, the states of 12 switches need to be changed. However, by adopting the solution of this application, only 4 unit capacitors with codes 5-8 in the codes 1-8 need to be switched to the ground voltage GND. This can save the switching power consumption of the circuit. Moreover, more importantly, this solution can also improve the DNL and INL performance of the SAR ADC.

[0083] For example, usually, the worst DNL of the SAR ADC appears when the code value flips from 011..111 to 100..000, because at this time, the most switches are switched, introducing the mismatch of all unit capacitors. And in the solution used in this article, only one unit capacitor flips here, which can greatly reduce the DNL here. And in all cases, the number of switched unit capacitors is at most only half of that of the ordinary SAR ADC. That is, in the worst case, the introduced mismatch of the unit capacitor is reduced by at least half.

[0084] Among them, the influence of the mismatch of the unit capacitor on the SAR ADC with higher precision is greater. Therefore, taking a 12-bit SAR ADC as an example, in the case of a unit capacitor mismatch with sigma = 5‰, the DNL and INL of the ordinary SAR ADC and the SAR ADC of this solution are modeled, as Figures 10 to 13 shown:

[0085] Among them, Figures 10 to 13 the horizontal axis represents the number of sampling points, Figure 10 and Figure 12 the vertical axis in Figure 12 represents DNL, Figure 11 and Figure 13 the vertical axis in Figure 13 represents INL. Both DNL and INL are in units of LSB.

[0086] Since the smaller the absolute value of the maximum or minimum value of DNL and INL, the better. It can be seen from this that Figure 12 the absolute value of DNL in Figure 12 is less than Figure 10 the absolute value of DNL in Figure 10 , Figure 13 the absolute value of INL in Figure 13 is less than Figure 11 the absolute value of INL in Figure 11 . This shows that the solution provided by this application can not only optimize the two non-linear indexes of DNL and INL, but also reduce the switching power consumption and improve the precision.

[0087] Moreover, since the unit capacitors with the same capacitance are adopted in the switched-capacitor module 20, compared with the prior art where capacitors with larger capacitance are also used, the area of the unit capacitor can be further reduced.

[0088] An embodiment of the present application further provides a chip 200, as Figure 14 shown. The chip 200 includes the above-mentioned analog-to-digital conversion circuit 100. The chip 200 is also referred to as an integrated circuit (IC). The chip 200 may be, but is not limited to, a system-on-chip (SOC) chip or a system-in-package (SIP) chip.

[0089] It can be understood that since the chip 200 provided in the embodiment of the present application includes the above-mentioned analog-to-digital conversion circuit 100, it can also output a digital signal DOUT based on the comparison result of the first generated voltage and the second generated voltage through the comparison processing module 10 and generate a feedback signal FB based on the digital signal DOUT. The switched-capacitor module 20 determines the first generated voltage and the second generated voltage according to the control signal CTL, and the switch control module 30 generates the control signal CTL according to the feedback signal FB to gradually reduce the switching number of the unit capacitors in the switched-capacitor module 20 in each quantization stage. As the number of switching times increases in the quantization stage, the switching number of the unit capacitors will be significantly reduced. This not only reduces the switching power consumption of the unit capacitor, but also reduces the accuracy loss caused by the capacitance mismatch of the unit capacitor, thereby improving the accuracy of analog-to-digital conversion and enhancing non-linear indexes such as differential non-linearity and integral non-linearity.

[0090] An embodiment of the present application further provides an electronic device 300, as Figure 15 shown. The electronic device 30 includes a device body and the above-mentioned analog-to-digital conversion circuit 100 or chip 200 disposed in the device body. The electronic device 300 may be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, a car center screen, a car, a smart wearable device, a mobile terminal, or a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, and a point-of-sale (POS) terminal. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart light.

[0091] It can be understood that since the electronic device 300 provided by the embodiment of the present application includes the above-mentioned analog-to-digital conversion circuit 100 or chip 200, it can also output a digital signal DOUT based on the comparison result of the first generated voltage and the second generated voltage through the comparison processing module 10 and generate a feedback signal FB based on the digital signal DOUT. The switched-capacitor module 20 determines the first generated voltage and the second generated voltage according to the control signal CTL, and the switch control module 30 generates the control signal CTL according to the feedback signal FB to gradually reduce the switching number of the unit capacitors in the switched-capacitor module 20 in each quantization stage. As the number of switching times increases in the quantization stage, the switching number of the unit capacitors will be significantly reduced, which not only reduces the switching power consumption of the unit capacitors, but also reduces the accuracy loss caused by the capacitance mismatch of the unit capacitors, thereby improving the accuracy of analog-to-digital conversion and improving non-linear indexes such as differential non-linearity and integral non-linearity.

[0092] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the technical content disclosed above within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that, The analog-to-digital conversion circuit includes: a comparison processing module configured to output a digital signal according to a comparison result between a first generated voltage and a second generated voltage, and generate a feedback signal based on the digital signal; a switched-capacitor module configured to determine the first generated voltage and the second generated voltage according to a control signal; a switch control module configured to generate the control signal according to the feedback signal to successively reduce the switching number of unit capacitors in the switched-capacitor module in each quantization stage.

2. The analog-to-digital conversion circuit according to claim 1, wherein The comparison processing module includes: a comparison unit, a first input terminal of the comparison unit is configured to receive the first generated voltage, a second input terminal of the comparison unit is configured to receive the second generated voltage, and an output terminal of the comparison unit is configured to output the comparison result; a switching unit configured to control a common-mode voltage to be respectively transmitted to the first input terminal and the second input terminal of the comparison unit in a sampling stage, and prohibit the common-mode voltage from being transmitted to the first input terminal and the second input terminal of the comparison unit in the quantization stage; a logic processing unit configured to output a digital signal according to the comparison result and generate the feedback signal based on the digital signal.

3. The analog-to-digital conversion circuit according to claim 1, characterized in that The switched-capacitor module includes: a first switched-capacitor array configured to determine the first generated voltage according to the control signal; a second switched-capacitor array configured to determine the second generated voltage according to the control signal.

4. The analog-to-digital conversion circuit according to claim 3, wherein The first switched-capacitor array includes: a plurality of first unit capacitors with the same capacitance, a first end of each first unit capacitor is connected to a first input terminal of the comparison processing module; a plurality of first control switches, a common terminal of each first control switch is connected to a second end of a corresponding first unit capacitor, and each first control switch controls the common terminal to be connected to one of a power supply voltage, a ground voltage, and a first sampling voltage according to the control signal.

5. The analog-to-digital conversion circuit according to claim 4, wherein The second switched-capacitor array includes: a plurality of second unit capacitors with the same capacitance, a first end of each second unit capacitor is connected to a second input terminal of the comparison processing module; a plurality of second control switches, a common terminal of each second control switch is connected to a second end of a corresponding second unit capacitor, and each second control switch controls the common terminal to be connected to one of a power supply voltage, a ground voltage, and a second sampling voltage according to the control signal; wherein, the capacitance of one first unit capacitor is the same as that of one second unit capacitor.

6. The analog-to-digital conversion circuit according to claim 1, wherein The switch control module includes: a first switch control unit configured to generate a first control signal, a second control signal, and a third control signal according to the feedback signal to successively at least halve the switching number of the first unit capacitors in the switched-capacitor module in each quantization stage; A second switch control unit, which is configured to generate the first control signal, the second control signal, and the third control signal according to the feedback signal, so as to successively reduce by at least half the switching number of the second unit capacitors in the switched-capacitor module in each quantization stage.

7. The analog-to-digital conversion circuit according to claim 6, wherein The first control signal is used to select a certain column of first unit capacitors to be switched in the switched-capacitor module, and the second control signal is used to select at least one row of first unit capacitors to be switched from the first unit capacitors in the column selected by the first control signal; the third control signal is used to determine that a column of first unit capacitors selected by the previous first control signal is the first unit capacitors to be switched. In the switched-capacitor module, the second ends of the first unit capacitors to be switched are selected to be connected to the power supply voltage, and the second ends of the first unit capacitors that do not need to be switched are selected to be connected to the ground voltage.

8. The analog-to-digital conversion circuit according to claim 6, characterized in that The first control signal is used to select a certain column of second unit capacitors to be switched in the switched-capacitor module, and the second control signal is used to select at least one row of second unit capacitors to be switched from the second unit capacitors in the column selected by the first control signal; the third control signal is used to determine that a column of second unit capacitors selected by the previous first control signal is the second unit capacitors to be switched. In the switched-capacitor module, the second ends of the second unit capacitors to be switched are selected to be connected to the ground voltage, and the second ends of the second unit capacitors that do not need to be switched are selected to be connected to the power supply voltage.

9. The analog-to-digital conversion circuit according to any one of claims 4 to 8, characterized in that In the sampling stage, the second ends of all the first unit capacitors are connected to the first sampling voltage, and the second ends of all the second unit capacitors are connected to the second sampling voltage. In the quantization stage, the second ends of the first unit capacitors to be switched are selected to be connected to the power supply voltage, and the second ends of the first unit capacitors that do not need to be switched are selected to be connected to the ground voltage; the second ends of the second unit capacitors to be switched are selected to be connected to the ground voltage, and the second ends of the second unit capacitors that do not need to be switched are selected to be connected to the power supply voltage.

10. A chip, characterized in that, The chip includes the analog-to-digital conversion circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, The electronic device includes a device body and the chip according to claim 10 provided on the device body.

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