Functional substrate and manufacturing method thereof
By integrating the bypass capacitor with the target electric chip on the functional substrate, the problem of large layout space occupation and long supply paths caused by the separation of the bypass capacitor and the chip is solved, and the effect of improving the layout density and shortening the supply paths is achieved.
Patent Information
- Application Number
- CN202510359532.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, the bypass capacitor and the target electric chip are placed on both sides of the PCB motherboard, resulting in a large layout space occupied, affecting the integrated density of the motherboard and the power supply path is far away, so the voltage drop problem needs to be considered.
Integrate the bypass capacitor with the target electric chip on a functional substrate. Multiple groups of bypass capacitors are embedded inside the bypass capacitor plate, and are electrically connected to the chip pin through the pad. The pad and the chip pin position are set accordingly. The through holes are electrically connected to the ordinary pins to keep the pin arrangement consistent.
The layout space of the target battery chip and bypass capacitor on the PCB motherboard is reduced, the layout density of the motherboard is improved, and the supply path is shortened.
Smart Images
Figure CN120417232A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of circuit boards, and particularly to a functional substrate and a manufacturing method thereof. Background Art
[0002] Large-scale processing chips usually have many power supply pins, and the chips also require bypass capacitors to be placed nearby. A bypass capacitor, also known as a filtering capacitor, refers to a capacitor placed near the input pin of a power-consuming chip to filter out high-frequency harmonics in the power supply of the chip IC and reduce the interference of the noise in the power supply to the chip. Bypass capacitors are generally capacitors with small packages and small capacitance values.
[0003] In the prior art, most bypass capacitors and the target power-consuming chips are placed on two sides of the PCB main board respectively, and the power supply travels horizontally from the inner layer of the PCB main board to the via at the abdomen of the chip. This results in a relatively large layout space occupied by the target power-consuming chip on the PCB main board, affecting the integration density of the main board, and also causing a relatively long power supply path for the target power-consuming chip, where the voltage drop problem needs to be considered. Summary of the Invention
[0004] The main technical problem to be solved by this application is to provide a functional substrate and a manufacturing method thereof to release the layout space on the main board and improve the layout density of the main board.
[0005] This application provides a functional substrate, wherein the functional substrate includes: a target power-consuming chip, and a plurality of groups of pins are arranged on one side surface of the target power-consuming chip; a bypass capacitor board is arranged on the side of the target power-consuming chip where the plurality of groups of pins are arranged, and a plurality of groups of bypass capacitors are buried at positions corresponding to the plurality of groups of pins inside the bypass capacitor board, and each group of bypass capacitors is electrically connected to the plurality of groups of pins of the target power-consuming chip through a first pad on the surface of the bypass capacitor board.
[0006] Wherein, a second pad is further arranged on the side surface of the bypass capacitor board away from the target power-consuming chip, and the number of the second pads is the same as the number of pins on the target power-consuming chip; the setting positions of the second pads are the same as the setting positions of the pins of the target power-consuming chip.
[0007] Wherein, the pins include power pins and ordinary pins, the bypass capacitors are arranged corresponding to the power pins and are electrically connected to the power pins through the first pads.
[0008] Wherein, the bypass capacitor board further includes a plurality of through holes, the through holes are arranged corresponding to the ordinary pins and are electrically connected to the ordinary pins.
[0009] Wherein, the length of each group of bypass capacitors is the same as the distance between each group of pins, and the width of each group of bypass capacitors is less than the distance between adjacent two groups of pins.
[0010] The present application also provides a method for manufacturing a functional substrate, wherein the method for manufacturing the functional substrate includes: providing a target power chip; wherein a plurality of groups of pins are provided on one side surface of the target power chip; manufacturing a bypass capacitor plate according to the pins on the target power chip; wherein a plurality of groups of bypass capacitors are embedded inside the bypass capacitor plate, and a plurality of groups of first solder pads are provided on the side surface of the bypass capacitor plate close to the target power chip; soldering the pins on the surface of the target power chip one by one to the first solder pads on the surface of the bypass capacitor plate to form a functional substrate.
[0011] Among them, after the step of soldering the pins on the surface of the target power chip to the first pad on the surface of the bypass capacitor plate to form a functional substrate, it also includes: making solder balls on the side surface of the bypass capacitor plate away from the target power chip to form a second pad.
[0012] The number of the second pads is the same as the number of pins on the surface of the target power chip, and the arrangement positions of the second pads are the same as the arrangement positions of the pins on the surface of the target power chip.
[0013] Among them, the pins include power pins and ordinary pins; the step of making a bypass capacitor plate according to the pins on the target power-consuming chip includes: providing a board; embedding bypass capacitors at positions corresponding to each group of the power pins on the board, so that each group of the bypass capacitors is arranged corresponding to each group of the power pins; and making a first solder pad on the surface of one side of the board close to the target power-consuming chip.
[0014] Among them, the step of embedding bypass capacitors at positions corresponding to each group of power pins on the board so that each group of bypass capacitors is arranged corresponding to each group of power pins also includes: drilling through holes at positions corresponding to the ordinary pins on the board so that the through holes are arranged corresponding to the ordinary pins.
[0015] The beneficial effect of the present application is that by integrating the bypass capacitor and the target power-consuming chip on a functional substrate, and making the arrangement of the external pins on the functional substrate consistent with the pin arrangement of the original target power-consuming chip, the layout space of the target power-consuming chip and the bypass capacitor directly applied on the PCB mainboard can be reduced, and the layout density of the PCB mainboard can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.
[0017] Figure 1 Structural schematic diagram of an embodiment of the functional substrate provided by the present application;
[0018] Figure 2 Top view structural schematic diagram of a specific embodiment of the functional substrate provided by the present application;
[0019] Figure 3 Flow schematic diagram of a specific embodiment of the manufacturing method of the functional substrate provided by the present application;
[0020] Figure 4 Structural schematic diagram of a specific embodiment of the target power consumption chip provided by the present application;
[0021] Figure 5 Structural schematic diagram of a specific embodiment of the bypass capacitor board provided by the present application;
[0022] Figure 6 For Figure 3 Flow schematic diagram of a specific embodiment of step S12 in
[0023] Figure 7 Structural schematic diagram of an application scenario of the functional substrate provided by the present application. Specific embodiments
[0024] The following will elaborate on the solutions of the embodiments of the present application in conjunction with the accompanying drawings of the specification.
[0025] In the following description, for the purpose of illustration rather than limitation, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.
[0026] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless clearly indicated otherwise in the above. "Multiple" generally includes at least two, but does not exclude the case of including at least one.
[0027] It should be understood that the term "and / or" used herein is merely a description of the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.
[0028] It should be understood that the terms "comprising", "including", or any other variation are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a series of elements includes not only those elements but also other elements not explicitly listed, or elements that are inherent to such process, method, article, or apparatus. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the said elements.
[0029] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of this application, then such directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If the specific posture changes, then the directional indications will also change accordingly.
[0030] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, then such descriptions of "first", "second", etc. are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one such feature.
[0031] Referring to "embodiments" in this text means that the specific features, structures, or characteristics described in connection with the embodiments may be included in at least one embodiment of this application. The appearance of this phrase at each position in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.
[0032] This application provides a functional substrate. Specifically, please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the functional substrate provided by this application. As Figure 1 shown, the functional substrate includes: a target power consumption chip 10, and a bypass capacitor board 20.
[0033] Among them, multiple groups of pins 101 are provided on one side surface of the target power-consuming chip 10. Specifically, a plurality of pins 101 are provided on the surface of the target power-consuming chip 10, and every two pins 101 form a group. One of the pins is grounded and used as the negative power supply, and the other pin is used as the positive power supply.
[0034] The bypass capacitor board 20 is disposed on the side of the target power-consuming chip 10 where multiple groups of pins 101 are provided. Among them, multiple groups of bypass capacitors 201 are buried at positions corresponding to the multiple groups of pins 101 inside the bypass capacitor board 20, and each group of bypass capacitors 201 is electrically connected to the multiple groups of pins 101 of the target power-consuming chip 10 through the first pads 211 on the surface of the bypass capacitor board 20.
[0035] Among them, a plurality of first pads 211 are provided on the side surface of the bypass capacitor board 20 close to the target power-consuming chip 10, and a plurality of second pads 212 are provided on the side surface of the bypass capacitor board 20 far from the target power-consuming chip 10.
[0036] Preferably, the number of the second pads 212 is the same as the number of the pins 101 on the target power-consuming chip 10, and the setting positions of the second pads 212 are the same as the setting positions of the pins 101 on the target power-consuming chip 10, so that the formed functional substrate has the same pin definition as the original target power-consuming chip 10. It should be noted that the meaning that the setting positions of the second pads 212 are the same as the setting positions of the pins …
[0037] Among them, the pins 101 on the target power-consuming chip 10 include power supply pins and ordinary pins (not labeled). The bypass capacitors 201 are disposed corresponding to the power supply pins, and the bypass capacitors 201 inside the bypass capacitor board 20 are electrically connected to the power supply pins through the first pads 211. That is, the bypass capacitors 201 are disposed directly below the vertical projection plane of the power supply pins.
[0038] The bypass capacitor board 20 is further provided with a plurality of through holes 202, and the plurality of through holes 202 are disposed corresponding to the ordinary pins, and the through holes 202 of the bypass capacitor board 20 are electrically connected to the ordinary pins. That is, the through holes 202 are disposed directly below the vertical projection plane of the ordinary pins.
[0039] Preferably, the second pad 212 is a solder ball provided on the surface of the bypass capacitor plate 20 on the side facing away from the target power-consuming chip 10. The number of solder balls has the same pin definition (same number and position) as the pins 101 on the target power-consuming chip 10. The number of the second pads 212 includes the sum of the solder balls provided on the surface of the bypass capacitor 201 and the solder balls provided on the surface of the through hole 202.
[0040] Preferably, the length L of the bypass capacitor 201 is the same as the pitch between each group of pins 101. Please refer further to Figure 2 , Figure 2 which is a top view structural schematic diagram of a specific embodiment of the functional substrate provided by the present application. As Figure 2 shown, preferably, the width W of the bypass capacitor 201 is less than the pitch between adjacent two groups of pins. The length L is the setting direction of two pins 101 in the same group, and the width W is the direction perpendicular to the length L. From the top view, the pins 101 on the target power-consuming chip 10 are arranged in a matrix. The length L of each group of bypass capacitors 201 is the same as the pitch between each group of pins 101, so that the bypass capacitor 201 is exactly located directly below each group of pins 101. Preferably, the width W of each group of bypass capacitors 201 is less than the pitch between adjacent two groups of pins 101. Specifically, the width W of each group of bypass capacitors 201 is less than the pitch between adjacent two groups of pins 101 in the width direction. Preferably, the width W of each group of bypass capacitors 201 is less than half of the pitch between adjacent two groups of pins 101 in the width direction, so that adjacent two groups of bypass capacitors 201 are arranged at intervals, avoiding series interference formed by adjacent two groups of bypass capacitors 201.
[0041] In a specific embodiment, the bypass capacitor plate 20 is a kind of PCB board. Multiple groups of bypass capacitors 201 are buried at positions corresponding to multiple groups of pins 101 on the PCB board to form the bypass capacitor plate 20. In a specific implementation manner, manufacturing the bypass capacitor plate 20 includes: first opening a window in the PCB board to accommodate the bypass capacitor 201, then covering the board, and setting pads on the surface of the PCB board, thereby forming the bypass capacitor plate 20 buried with multiple groups of bypass capacitors 201. No specific limitation is made here.
[0042] The present application also provides a manufacturing method of a functional substrate. For details, please refer to Figure 3 , Figure 3 which is a flow schematic diagram of a specific embodiment of the manufacturing method of the functional substrate provided by the present application. As Figure 3 shown, the manufacturing method of the functional substrate includes:
[0043] Step S11: Provide a target power-consuming chip.
[0044] For details, please refer to Figure 4 , Figure 4Schematic diagram of a specific embodiment of the target power consumption chip provided by this application. One side surface of the target power consumption chip is provided with multiple groups of pins or multiple pins, and every two pins form a group, which is not limited herein. The target power consumption chip includes a power supply pin for providing a power signal.
[0045] Step S12: Fabricate a bypass capacitor board according to the pins on the target power consumption chip.
[0046] Specifically, refer to Figure 5 , Figure 5 Schematic diagram of a specific embodiment of the bypass capacitor board provided by this application. As Figure 5 shown, multiple groups of bypass capacitors 201 are buried inside the bypass capacitor board, and multiple groups of first pads 211 are provided on one side surface of the bypass capacitor board close to the target power consumption chip. Further, multiple groups of second pads 212 are also provided on the side surface of the bypass capacitor board far from the target power consumption chip, and the second pads 212 can be solder balls on the surface of the bypass capacitor board. The second pads 212 are arranged according to the pins on the surface of the target power consumption chip. Preferably, the number of the second pads 212 is the same as the number of the pins on the surface of the target power consumption chip, and preferably, the arrangement positions of the second pads 212 are also the same as the arrangement positions of the pins on the surface of the target power consumption chip.
[0047] Further preferably, the arrangement positions of the bypass capacitors in the bypass capacitor board are also designed according to the pins on the surface of the target power consumption chip. The pins on the surface of the target power consumption chip include power supply pins and ordinary pins. And bypass capacitors need to be provided for the power supply pins.
[0048] In a specific embodiment, specifically refer to Figure 6 , Figure 6 is Figure 3 Flow schematic diagram of a specific embodiment of step S12 in Figure 6 shown. As
[0049] Step S21: Provide a board.
[0050] The board can be a PCB board or other circuit boards.
[0051] Step S22: Bury bypass capacitors at positions corresponding to each group of power supply pins on the board so that each group of bypass capacitors is arranged corresponding to each group of power supply pins.
[0052] Specifically, make the bypass capacitors located directly below the power supply pins after combined soldering.
[0053] This step specifically includes: embedding bypass capacitors into the board using the ECP process. ECP (Embedded Chip Package) is an embedded chip package, which means embedding chip / resistor-capacitor components into the substrate / PCB board and using copper-plated vias for vertical interconnection to form an integrated package. Specifically, it includes: at the position where bypass capacitors need to be placed, embedding the bypass capacitors into the PCB board, and then leading out the pads of the bypass capacitors through laser holes on both the upper and lower sides of the bypass capacitors.
[0054] In a specific embodiment, it specifically includes: opening windows in the board to place multiple bypass capacitors, then covering the surface of the bypass capacitors with a cover plate, and then opening holes at the positions corresponding to the bypass capacitors on the surface of the cover plate, and the holes are filled with conductive metal.
[0055] In a further specific embodiment, step S22 further includes: drilling through holes at the positions corresponding to the ordinary pins on the board so that the through holes are correspondingly arranged with the ordinary pins.
[0056] Step S23: Fabricate first pads on one side surface of the board close to the target power-consuming chip.
[0057] Preferably, the first pads are correspondingly arranged with multiple pins (the quantity and setting positions are the same).
[0058] Among them, the first pads include a metal layer on the surface of the through holes and a metal layer on the surface of the bypass capacitors to achieve circuit connection.
[0059] Step S13: Weld the pins on the surface of the target power-consuming chip to the first pads on the surface of the bypass capacitor board one by one to form a functional substrate.
[0060] By welding the pins on the surface of the target power-consuming chip to the first pads together, an integrated whole is formed. Moreover, the formed functional substrate is also provided with pins in the same direction as the target power-consuming chip, and these pins are the second pads on the bypass capacitor board, and these pins (the second pads) have the same pin definition as the pins on the target power-consuming chip (the quantity and setting positions are the same).
[0061] In a specific embodiment, after step S13: fabricate second pads corresponding to the pins on the side surface of the bypass capacitor board facing away from the target power-consuming chip. Specifically, fabricate second pads corresponding to the pins on the surface of the target power-consuming chip. In other embodiments, the fabrication of the second pads can also be after step S23 in step S12, which is not limited herein. This step specifically includes: drilling holes on the back of the bypass capacitor to expose the bypass capacitor, and filling the holes with a metal layer to form conductive pads. Then fabricate solder balls on the surface of the conductive pads and the surface of the through holes to obtain the second pads.
[0062] Preferably, the second pad has the same number and position as the pins on the surface of the target power-consuming chip.
[0063] The second pad includes solder balls fabricated on the surface of the bypass capacitor board, so that the second pad protrudes from the surface of the bypass capacitor board (functional substrate), facilitating subsequent applications.
[0064] Among them, the second pad is electrically connected to the power supply pins (power pins) on the target power-consuming chip through the bypass capacitor in the bypass capacitor board, and is electrically connected to the common pins on the target power-consuming chip through the vias in the bypass capacitor board.
[0065] This application also provides an application device for the functional substrate. For details, please refer to Figure 7 , Figure 7 which is a schematic structural diagram of an application scenario of the functional substrate provided by this application. As Figure 7 shown, the functional substrate can be directly disposed on the PCB main board, thereby reducing the occupied space on the surface of the PCB main board and improving the layout density on the surface of the PCB main board. At the same time, power supply devices and other devices can be disposed on the back of the PCB main board, thereby greatly shortening the power supply path of the target power-consuming chip and improving the integration degree of the system.
[0066] The beneficial effects of this embodiment are as follows: By integrating the bypass capacitor and the target power-consuming chip on a functional substrate and making the arrangement of the external pins on the functional substrate consistent with the pin arrangement of the original target power-consuming chip, the layout space for directly applying the target power-consuming chip and the bypass capacitor on the PCB main board can be reduced, and the layout density of the PCB main board can be improved.
[0067] The above are only the implementation manners of this application, and do not limit the patent scope of this application accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or the simple recombination of method steps, or the direct or indirect application in other related technical fields shall be equally included in the patent protection scope of this application.
Claims
1. A functional substrate, characterized in that, The functional substrate includes: A target power-consuming chip, on one side surface of which there are multiple groups of pins; A bypass capacitor board, disposed on the side of the target power-consuming chip where there are multiple groups of pins. Multiple groups of bypass capacitors are embedded at positions corresponding to the multiple groups of pins inside the bypass capacitor board. Each group of bypass capacitors is electrically connected to the multiple groups of pins of the target power-consuming chip through the first pads on the surface of the bypass capacitor board.
2. The functional substrate according to claim 1, wherein On the surface of the bypass capacitor board away from the target power-consuming chip, there are also second pads. The number of the second pads is the same as the number of pins on the target power-consuming chip; the setting positions of the second pads are the same as the setting positions of the pins on the target power-consuming chip.
3. The functional substrate according to claim 1, wherein, The pins include power pins and ordinary pins. The bypass capacitors are arranged corresponding to the power pins and are electrically connected to the power pins through the first pads.
4. The functional substrate according to claim 3, wherein The bypass capacitor board further includes a plurality of through holes, which are arranged corresponding to the ordinary pins and are electrically connected to the ordinary pins.
5. The functional substrate according to claim 3, characterized in that, The length of each group of bypass capacitors is the same as the pitch between each group of pins, and the width of each group of bypass capacitors is less than the pitch between adjacent two groups of pins.
6. A manufacturing method of a functional substrate, characterized in that, The manufacturing method includes: Providing a target power-consuming chip; wherein, on one side surface of the target power-consuming chip, there are multiple groups of pins; Manufacturing a bypass capacitor board according to the pins on the target power-consuming chip; wherein, multiple groups of bypass capacitors are embedded inside the bypass capacitor board, and multiple groups of first pads are arranged on the surface of the bypass capacitor board close to the target power-consuming chip; Welding the pins on the surface of the target power-consuming chip to the first pads on the surface of the bypass capacitor board one by one to form a functional substrate.
7. The manufacturing method of the functional substrate according to claim 6, wherein, After the step of welding the pins on the surface of the target power-consuming chip to the first pads on the surface of the bypass capacitor board to form a functional substrate, it further includes: Manufacturing solder balls on the surface of the bypass capacitor board away from the target power-consuming chip to form second pads.
8. The manufacturing method of the functional substrate according to claim 7, characterized in that, The number of the second pads is the same as the number of pins on the surface of the target power-consuming chip, and the setting positions of the second pads are the same as the setting positions of the pins on the surface of the target power-consuming chip.
9. The manufacturing method of the functional substrate according to claim 8, wherein, The pins include power pins and ordinary pins; The step of manufacturing a bypass capacitor board according to the pins on the target power-consuming chip includes: Providing a board; Embedding bypass capacitors at positions corresponding to each group of the power pins on the board, so that each group of bypass capacitors is arranged corresponding to each group of the power pins; Manufacturing first pads on the surface of the board close to the target power-consuming chip.
10. The manufacturing method of the functional substrate according to claim 9, characterized in that, The step of embedding bypass capacitors at positions corresponding to each group of the power pins on the board, so that each group of bypass capacitors is arranged corresponding to each group of the power pins, further includes: Drilling through holes at positions corresponding to the ordinary pins on the board, so that the through holes are arranged corresponding to the ordinary pins.