Intelligent composite terminal structure for mosfet

Abstract

The invention relates to the field of semiconductors, and discloses an intelligent composite terminal structure for a mosfet, which comprises a plurality of near-source grooves and a plurality of terminal grooves at intervals of D. One side of at least one near-source groove is provided with a p-type well region, and at least one shoulder part of the p-type well region forms an N-type heavily doped source electrode; polycrystalline silicon layers are formed in the terminal grooves, each polycrystalline silicon layer is provided with an arc-shaped interface, and the distance D between the terminal grooves far away from the near-source grooves is larger than the distance D between the terminal grooves close to the near-source grooves. According to the intelligent composite terminal structure for the MOSFET, provided by the invention, the uniform distribution of an electric field, the improvement of the thermal management capability, the enhancement of the reliability and the optimization of the process compatibility are realized through the collaborative optimization of the terminal groove spacing and the polycrystalline silicon layer interface structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and specifically to an intelligent composite terminal structure for a MOSFET. Background Art

[0002] In the field of power semiconductor devices, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in high-voltage scenarios such as new energy vehicles and industrial control due to their high switching speed and low on-resistance. However, with the increase in the breakdown voltage rating of the device (such as above 200V), the uniformity and reliability of the electric field distribution in the terminal region have become key technical bottlenecks.

[0003] Traditional MOSFET terminal structures usually adopt equally spaced trench designs. Although they can regulate the electric field to a certain extent, there are the following problems:

[0004] Equally spaced trenches are prone to form electric field concentration in the chip edge region, leading to premature breakdown of the device and restricting the increase of the breakdown voltage (the breakdown voltage of traditional structures is generally lower than 200V). At the same time, too high density of edge trenches will compress the scribing lane width, resulting in insufficient mechanical strength during the scribing process.

[0005] The traditional polysilicon layer has a flat interface, resulting in uneven electric field distribution in the terminal region, a relatively high electric field difference between adjacent trenches, and local regions with too strong electric fields are prone to cause hot carrier effects, reducing the device life.

[0006] Under the equally spaced trench and flat interface structure, the heat conduction path of the polysilicon layer is single, local overheating is prone to occur in the edge trench region, and the temperature difference between the edge and the central trenches is relatively large, resulting in unstable device performance. Summary of the Invention

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] An intelligent composite terminal structure for a MOSFET includes a plurality of near-source trenches and a plurality of terminal trenches with a spacing of D. A p-type well region is configured on one side of at least one near-source trench, and an N-type heavily doped source is formed at at least one shoulder of the p-type well region; a polysilicon layer is formed in the terminal trenches, and the polysilicon layer has an arc-shaped interface. The spacing D of the terminal trenches far from the near-source trenches is greater than the spacing D of the terminal trenches close to the near-source trenches.

[0009] Further, the near-source trenches are connected through electrical contact holes, and a dielectric is formed on the upper parts of the near-source trenches, the terminal trenches, and the N-type heavily doped source.

[0010] Further, the upper and lower parts of the near-source trenches are isolated by an insulating isolation oxide layer. A control gate structure is arranged in the upper half of the near-source trenches, a shielding gate structure is arranged in the lower half of the near-source trenches, and a gate oxide layer is formed on the outer side surface of the control gate structure.

[0011] Further, the near-source trench and the terminal trench both form a trench oxide layer on the inner wall.

[0012] Further, a lightly doped epitaxial layer is formed above the N-type heavily doped substrate layer, and the near-source trench and the terminal trench are both formed based on the lightly doped epitaxial layer.

[0013] Further, the arc-shaped interface of the polysilicon layer is determined by simulation, including:

[0014] Construct a simulation model, set physical parameters, and determine the specific doping concentrations, carrier mobilities, and dielectric constants of the N-type heavily doped substrate layer and the lightly doped epitaxial layer; for the polysilicon layer, in addition to the initial doping concentration, its resistivity and thermal conductivity parameters also need to be set;

[0015] Set the boundary conditions of the model, determine the voltage values of the N-type heavily doped source, the control gate structure, and other electrodes, and set the environmental temperature and heat dissipation coefficient parameters;

[0016] Set the arc shape corresponding to the arc-shaped interface of the polysilicon layer;

[0017] Parameterize the key geometric parameters of the arc-shaped interface; during the simulation process, these parameters can be conveniently adjusted and optimized, and by changing the parameters, the changes in the electric field and thermal distribution can be observed;

[0018] Run the initial simulation to simulate the electric field and thermal distribution of the MOSFET under typical working conditions; record the distribution curve of the electric field strength and the temperature distribution nephogram in the arc-shaped interface of the polysilicon layer and its surrounding area, and analyze the regions with concentrated electric fields and excessive temperatures;

[0019] If it is found that the electric field is too concentrated at one end of the arc-shaped interface, the radius of curvature of this area can be increased to make the electric field distribution more dispersed; if there is local overheating, the shape of the arc can be adjusted to increase the heat conduction path;

[0020] According to the simulation, determine the optimal parameter combination of the arc-shaped interface of the polysilicon layer, including the arc type of the curve, the radius of curvature, the starting and ending angles of the arc, and the height of the arc.

[0021] Further, the spacing D of the terminal trenches is determined by simulation, including:

[0022] Construct a MOSFET structure model including the complete terminal region;

[0023] Design the spacing D of the terminal trenches:

[0024] Follow the principle that "the density of the terminal trenches close to the near-source trench is high and the density away from the edge is low" to determine the initial setting,

[0025] Define the spacing parameter array D = [D1, D2, D3], and implement batch simulation through parametric scripts;

[0026] The simulation optimization objectives are as follows:

[0027] The maximum electric field intensity in the terminal area is less than the threshold, and the electric field difference between adjacent trenches is less than the threshold;

[0028] The highest temperature of the polysilicon layer is less than the threshold, and the temperature difference between the edge trench and the center trench is less than the threshold;

[0029] Run the initial simulation to obtain the electric field contour map and temperature curve in the terminal area:

[0030] If the electric field intensity near the outermost terminal trench exceeds the threshold, reduce the spacing;

[0031] Reduce the spacing of the edge trenches with excessive electric fields, and increase the trench density to disperse charges;

[0032] Increase the spacing of the over-dense trenches in the near-source area to avoid excessive electric field coupling;

[0033] Add a silicon nitride charge compensation layer with a certain thickness at the bottom of the trench with too high temperature to enhance heat conduction.

[0034] Furthermore, when adjusting the spacing of the edge trenches, synchronously optimize the curvature of the arc-shaped interface of the polysilicon layer to improve the heat flow diffusion path.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] The intelligent composite terminal structure for MOSFET provided by the present invention realizes uniform electric field distribution, improved thermal management ability, enhanced reliability and optimized process compatibility through the coordinated optimization of the terminal trench spacing and the polysilicon layer interface structure. The specific beneficial effects are as follows:

[0037] Through simulation optimization, the terminal trench spacing increases gradually from the near-source area to the edge area, forming a "dense-sparse" transition structure. Compared with the traditional trenches with equal spacing, this design effectively reduces the electric field concentration phenomenon in the edge area (the edge electric field peak value decreases), avoids premature breakdown caused by too strong edge electric field, improves the breakdown voltage of the device, and at the same time, through the low-density trench design at the edge, ensures that the scribe lane width meets the mechanical strength requirements, balancing the electrical performance and manufacturing reliability.

[0038] The polysilicon layer adopts an arc-shaped interface. Through parametric adjustment of the simulation, the standard deviation of the electric field distribution in the terminal area is reduced, and the electric field difference between adjacent trenches is reduced, completely eliminating the local electric field concentration problem and improving the stability under high voltage. Description of the Drawings

[0039] Figure 1Overall diagram of the intelligent composite terminal structure for the MOSFET of this application;

[0040] Figure 2 Partial diagram of the intelligent composite terminal structure for the MOSFET of this application;

[0041] Figure 3 Partial diagram of the intelligent composite terminal structure for the MOSFET of this application. Detailed implementation manner

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0043] This application provides an intelligent composite terminal structure for a MOSFET, as Figure 1 , Figure 2 , Figure 3 , this application discloses an intelligent composite terminal structure for a MOSFET, including a plurality of near-source trenches 112 and a plurality of terminal trenches 113 with a spacing of D. A p-type well region 105 is configured on one side of at least one near-source trench 112, and an N-type heavily doped source electrode 100 is formed at at least one shoulder of the p-type well region 105; a polysilicon layer 111 is formed in the terminal trench 113, the polysilicon layer 111 has an arc-shaped interface, and the spacing D of the terminal trench 113 far from the near-source trench 112 is greater than the spacing D of the terminal trench 113 close to the near-source trench 112.

[0044] Specifically, the arc-shaped interface of the polysilicon layer 111 is determined through simulation:

[0045] Construct a simulation model, set physical parameters for various materials in the simulation model, and determine the specific doping concentrations, carrier mobilities, and dielectric constants of the N-type heavily doped substrate layer 108 and the lightly doped epitaxial layer 109. For the polysilicon layer 111, in addition to the initial doping concentration, its resistivity and thermal conductivity parameters also need to be set, and these parameters will affect the electric field and thermal distribution;

[0046] According to the actual working environment of the MOSFET, set the boundary conditions of the model, determine the voltage values of the N-type heavily doped source electrode 100, the control gate structure 102, and other electrodes, simulate the heat dissipation situation, and set the environmental temperature and heat dissipation coefficient parameters.

[0047] Set the arc shape corresponding to the arc-shaped interface of the polysilicon layer 111, including a sine arc, a cosine arc, and an arc based on a Bessel curve.

[0048] Parametrize the key geometric parameters of the arc-shaped interface. The key geometric parameters include the radius of curvature, the start and end angles of the arc, and the height of the arc. In this way, during the simulation process, these parameters can be conveniently adjusted and optimized, and by changing the parameters, the changes in the electric field and thermal distribution can be observed.

[0049] Run the initial simulation to simulate the electric field and thermal distribution of the MOSFET under typical operating conditions. Record the distribution curve of the electric field intensity and the temperature distribution contour map of the arc-shaped interface of the polysilicon layer 111 and its surrounding area, and analyze the regions with electric field concentration and the parts with excessive temperature.

[0050] If it is found that the electric field is too concentrated at one end of the arc-shaped interface, the radius of curvature of this region can be increased to make the electric field distribution more dispersed. If local overheating occurs, the shape of the arc can be adjusted to increase the heat conduction path and improve the heat dissipation situation.

[0051] According to the simulation, determine the optimal parameter combination of the arc-shaped interface of the polysilicon layer 111, including the arc type of the curve, the radius of curvature, the start and end angles of the arc, and the height of the arc.

[0052] Specifically, the spacing D of the terminal trench 113 is determined by simulation:

[0053] Construct a MOSFET structure model including the complete terminal region, including:

[0054] The N-type heavily doped substrate layer 108 and the lightly doped epitaxial layer 109, set the thickness such as 500 μm for the substrate layer and 10 μm for the epitaxial layer, and the doping parameters such as the substrate doping concentration of 1×10 20 cm -3 and the epitaxial layer of 5×10 16 cm -3 .

[0055] The near-source trench 112 and the terminal trench 113, the initial radius of curvature of the arc-shaped interface of the polysilicon layer 111 preset on the inner wall of the terminal trench is 5 μm, and the thickness of the trench oxide layer 110 is uniformly set to 200 nm.

[0056] The N-type heavily doped source 100, the control gate structure 102, the gate oxide layer 101 with a thickness of 30 nm, and the dielectric layer 104.

[0057] The grid division focuses on encrypting the grid accuracy of the terminal trench area ≤0.1 μm to ensure the accurate capture of the electric field gradient change.

[0058] Set the material parameters and boundary conditions: lightly doped epitaxial layer 109: electron mobility 1500 cm 2 / (V·s), dielectric constant 11.9ε0;

[0059] Polysilicon layer 111: initial doping concentration 5×1018 cm -3 n-type, resistivity 0.1 Ω·cm, thermal conductivity 150 W / (m·K);

[0060] Trench oxide layer 110: dielectric constant 3.9ε0, thermal conductivity 1.4 W / (m·K).

[0061] Boundary condition setting:

[0062] Bias voltage: the source 100 is grounded at 0 V, the gate 102 is applied with a forward driving voltage of 5 V, and the substrate 108 is connected to a negative bias voltage of -10 V to simulate the reverse bias state;

[0063] Heat dissipation condition: ambient temperature 25°C, set the heat dissipation coefficient at the terminal edge to 100 W / (m 2 ·K) to simulate the actual package heat dissipation environment.

[0064] Design of the spacing D of the terminal trench 113:

[0065] Follow the principle of "high density of terminal trenches close to the near-source trench 112 and low density far from the edge", and the initial setting is:

[0066] The spacing D1 between the 1st to 3rd terminal trenches close to the near-source area is 1.5 μm;

[0067] The spacing D2 between the 4th to 6th terminal trenches is 2.0 μm;

[0068] The spacing D3 between the last 2 terminal trenches at the edge is 2.5 μm to meet the reliability requirement that the scribing lane width ≥ 50 μm.

[0069] Define the spacing parameter array D = [D1, D2, D3], and implement batch simulation through a parameterized script. [[ID=3,7]]

[0070] Determine the simulation optimization objectives:

[0071] The maximum electric field strength in the terminal area ≤ 2×10 5 V / cm, and the electric field difference between adjacent trenches < 10%;

[0072] The highest temperature of the polysilicon layer 111 < 150°C, and the temperature difference between the edge trench and the center trench < 10°C. ,>

[0073] Run the initial simulation to obtain the electric field contour map and temperature curve in the terminal area:

[0074] If the electric field strength near the outermost terminal trench D3 = 2.5 μm reaches 2.5×10 5 V / cm and exceeds the threshold, and charge accumulation occurs due to the too large spacing, then reduce the spacing;

[0075] Reduce the spacing of the edge trench D3 with excessive electric field to 2.2 μm, and increase the trench density to disperse charges. For each additional trench, the spacing decreases by 0.1 μm;

[0076] Increase the spacing of the over-dense trench D1 in the near-source region to 1.8 μm to avoid excessive electric field coupling. For each 0.1 μm increase in the adjacent trench spacing, the peak electric field drops by about 5%.

[0077] Add a silicon nitride charge compensation layer with a thickness of 0.5 μm at the bottom of the trench with too high temperature. The thermal conductivity is 200 W / (m·K) to enhance heat conduction;

[0078] Preferably, when adjusting the edge trench spacing, synchronously optimize the curvature of the arc-shaped interface of the polysilicon layer 111. For example, increase the polysilicon curvature radius corresponding to the edge trench from 5 μm to 6 μm to improve the heat flow diffusion path.

[0079] Determine the optimal spacing combination, such as D1 = 1.7 μm in the near-source region, D2 = 2.1 μm in the middle region, and D3 = 2.3 μm in the edge region;

[0080] From the near-source region to the edge region, the spacing of the terminal trench 113 increases in a gradient to form a "dense-sparse" transition structure.

[0081] Specifically, the near-source trenches 112 are connected through the electrical contact holes 103, and a dielectric 104 is formed between the upper parts of the near-source trenches 112, the terminal trenches 113 and the N-type heavily doped source electrode 100.

[0082] Specifically, the inside of the near-source trench 112 is isolated from the upper and lower parts by the insulating isolation oxide layer 106. The upper half of the inside of the near-source trench 112 is provided with a control gate structure 102, the lower half of the inside of the near-source trench 112 is provided with a shielding gate structure 107, and a gate oxide layer 101 is formed on the outer side of the control gate structure 102.

[0083] Specifically, the near-source trench 112 and the terminal trench 113 both form a trench oxide layer 110 on the inner wall.

[0084] Specifically, a lightly doped epitaxial layer 109 is formed above the N-type heavily doped substrate layer 108, and the near-source trench 112 and the terminal trench 113 are both formed on the basis of the lightly doped epitaxial layer 109.

[0085] The electrical contact hole 103 penetrates the dielectric layer 104 to realize the top electrical connection of adjacent near-source trenches 112, ensure the potential consistency of the control gate structure 102, and avoid uneven channel conduction caused by uneven gate signals.

[0086] The contact holes are vertically distributed at the top edge of the near-source trench 112 with a uniform pitch of 5 μm. They are formed through photolithography and etching processes, with a pore size of 0.5 μm × 0.5 μm. The inside is filled with a tungsten W or aluminum Al metal layer, and the contact resistance ≤ 10 mΩ.

[0087] The dielectric layer 104 is made of silicon dioxide SiO2 or silicon nitride Si3N4, with a total thickness of 2 μm. It is deposited in two layers: the bottom layer of 1 μm is dense silicon oxide, used to isolate the trench from the external environment; the top layer of 1 μm is doped phosphosilicate glass PSG to enhance the surface flatness.

[0088] The dielectric layer 104 completely covers the upper surfaces of the near-source trench 112, the terminal trench 113, and the N-type heavily doped source electrode 100, leaving openings only at the electrical contact holes 103 and the source lead pad positions to form a complete insulation protection.

[0089] The insulating isolation oxide layer 106 divides the near-source trench 112 into upper and lower parts in the vertical direction: the upper half, accounting for 40% of the trench height, accommodates the control gate structure 102, and the lower half, accounting for 60%, integrates the shielding gate structure 107 to avoid the electric field coupling interference between the upper and lower gates.

[0090] After the etching of the near-source trench 112 and the terminal trench 113 is completed, a trench oxide layer 110 is grown on the sidewalls and bottom of the trench through wet oxidation or chemical vapor deposition CVD. The thickness is uniformly controlled at 200 nm, and the surface roughness ≤ 5 nm.

[0091] Material properties: silicon dioxide SiO2, density ≥ 2.2 g / cm 3 , dielectric constant 3.9ε0, effectively isolating the polysilicon layer 111 / gate structure in the trench from the lightly doped epitaxial layer 109, leakage current ≤ 1 nA / μm (@10V bias).

[0092] In the terminal trench 113, the trench oxide layer 110 serves as the substrate for the polysilicon layer 111. The polysilicon layer 111 with an arc-shaped interface grows along the inner wall of the trench and fits tightly with the oxide layer. The deviation of the curvature radius ≤ ±5% of the designed value of 5 μm, and is actually controlled within 4.75 - 5.25 μm.

[0093] The lightly doped epitaxial layer 109 is epitaxially grown on the surface of the substrate layer through chemical vapor deposition CVD, with a thickness of 10 μm, doped with arsenic As, and a concentration of 5×10 16 cm -3 , electron mobility 1500 cm 2 / (V·s), serving as the base layer for the near-source trench 112 and the terminal trench 113 to ensure uniform distribution of the electric field in the active area of the device.

[0094] The cooperation between the insulating isolation oxide layer 106 and the trench oxide layer 110 enables the electric field of the control gate 102 to be concentrated on the channel in the near-source region. The shielding gate 107 effectively weakens the coupling of the high drain voltage to the substrate and reduces the substrate current noise.

[0095] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An intelligent composite terminal structure for a MOSFET, characterized in that It includes a plurality of near-source trenches (112) and a plurality of terminal trenches (113) with a spacing of D. On one side of at least one near-source trench (112), a p-type well region (105) is configured, and an N-type heavily doped source (100) is formed at at least one shoulder of the p-type well region (105); a polysilicon layer (111) is formed in the terminal trench (113), and the polysilicon layer (111) has an arc-shaped interface. The spacing D of the terminal trench (113) far from the near-source trench (112) is greater than the spacing D of the terminal trench (113) close to the near-source trench (112).

2. The intelligent composite terminal structure for a MOSFET according to claim 1, characterized in that, The near-source trenches (112) are connected through electrical contact holes (103), and a dielectric (104) is formed above the near-source trenches (112), the terminal trenches (113), and the N-type heavily doped source (100).

3. The intelligent composite terminal structure for a MOSFET according to claim 2, wherein, The interior of the near-source trench (112) is isolated from the upper and lower parts by an insulating isolation oxide layer (106). A control gate structure (102) is arranged in the upper half of the interior of the near-source trench (112), and a shielding gate structure (107) is arranged in the lower half of the interior of the near-source trench (112). A gate oxide layer (101) is formed on the outer side surface of the control gate structure (102).

4. The intelligent composite terminal structure for a MOSFET according to claim 3, characterized in that, Both the near-source trench (112) and the terminal trench (113) form a trench oxide layer (110) on the inner wall.

5. The intelligent composite terminal structure for a MOSFET according to claim 4, wherein, A lightly doped epitaxial layer (109) is formed above the N-type heavily doped substrate layer (108), and the near-source trench (112) and the terminal trench (113) are both formed based on the lightly doped epitaxial layer (109).

6. The intelligent composite terminal structure for a MOSFET according to claim 5, characterized in that, The arc-shaped interface of the polysilicon layer (111) is determined by simulation, including:[[]] Constructing a simulation model, setting physical parameters, and determining the specific doping concentrations, carrier mobilities, and dielectric constants of the N-type heavily doped substrate layer (108) and the lightly doped epitaxial layer (109); for the polysilicon layer (111), in addition to the initial doping concentration, its resistivity and thermal conductivity parameters also need to be set; Setting the boundary conditions of the model, determining the voltage values of the N-type heavily doped source (100), the control gate structure (102), and other electrodes, and setting the environmental temperature and heat dissipation coefficient parameters; Setting the arc shape corresponding to the arc-shaped interface of the polysilicon layer (111); Parametrizing the key geometric parameters of the arc-shaped interface; during the simulation process, these parameters can be conveniently adjusted and optimized, and by changing the parameters, the changes in the electric field and thermal distribution can be observed; Running an initial simulation to simulate the electric field and thermal distribution of the MOSFET under typical working conditions; recording the distribution curve of the electric field intensity and the temperature distribution nephogram of the arc-shaped interface of the polysilicon layer (111) and its surrounding area, and analyzing the regions with concentrated electric fields and overheated parts; If it is found that the electric field is too concentrated at one end of the arc-shaped interface, the curvature radius of this region can be increased to make the electric field distribution more dispersed; if there is local overheating, the shape of the arc can be adjusted to increase the heat conduction path; According to the simulation, determining the optimal parameter combination of the arc-shaped interface of the polysilicon layer (111), including the arc type of the curve, the curvature radius, the starting and ending angles of the arc, and the height of the arc.

7. An intelligent composite terminal structure for a MOSFET according to claim 6, characterized in that, The spacing D of the terminal trench (113) is determined by simulation, including: Construct a MOSFET structure model including the complete terminal region; Design the pitch D of the terminal trench (113): Follow the principle of "high density of terminal trenches close to the near-source trench (112) and low density away from the edge" to determine the initial setting, Define the pitch parameter array D = [D1, D2, D3], and implement batch simulation through a parameterized script; The simulation optimization objectives are: The maximum electric field strength in the terminal region is less than the threshold, and the electric field difference between adjacent trenches is less than the threshold; The highest temperature of the polysilicon layer (111) is less than the threshold, and the temperature difference between the edge trench and the center trench is less than the threshold; Run the initial simulation to obtain the electric field contour map and temperature curve of the terminal region: If the electric field strength near the outermost terminal trench exceeds the threshold, reduce the pitch; Reduce the pitch of the edge trench with excessive electric field, and increase the trench density to disperse charges; Increase the pitch of the over-dense trenches in the near-source region to avoid excessive electric field coupling; Add a silicon nitride charge compensation layer with a certain thickness at the bottom of the trench with too high temperature to enhance heat conduction.

8. An intelligent composite terminal structure for a MOSFET according to claim 7, characterized in that, When adjusting the pitch of the edge trench, synchronously optimize the curvature of the arc interface of the polysilicon layer (111) to improve the heat flow diffusion path.

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