Control gate and floating gate and manufacturing method thereof
By adding virtual graphics to the mask version of Nand-flash memory and using self-aligned dual imaging technology, the damage problem of memory area etching to the peripheral logic area is solved, the yield and electrical uniformity of the device are improved, and the reliability of the device is ensured.
Patent Information
- Application Number
- CN202510559525.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-01
AI Technical Summary
In the manufacturing process of Nand-flash memory, in the etching process of memory area and peripheral logic area, the prior art cannot effectively avoid damage to the logic area, affecting device yield, electrical uniformity and reliability.
Self-aligned dual imaging technology is adopted to form the first and second photoresist patterns by adding virtual patterns to the mask plate to form control gates and floating gates in the memory area and the peripheral logic area respectively, increase the pattern density of the logic area, adjust the light transmittance of the mask plate, and avoid etching damage.
It improves the yield and electrical uniformity of the device, ensures the reliability of the device, avoids damage caused by differences in light transmittance, and adapts to the transmittance requirements of different products.
Smart Images
Figure CN120417458A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a control gate and a floating gate and a manufacturing method thereof. Background Art
[0002] With the continuous improvement of chip integration and the continuous reduction of size, the realization of the final function of a device requires the mutual cooperation of different sub-devices, such as N-type transistors, P-type transistors, memory areas, SRAM areas, etc. The process manufacturing of sub-devices is carried out on different areas of the wafer through mask exposure and etching. Currently, Nand-flesh memories are simply divided into two major parts: a memory area and a peripheral logic area. During the manufacturing process of Nand-flesh memories, when performing the gate process, in the memory area, the self-aligned double patterning technology (i.e., SADP) is adopted. First, the topography of the hard mask layer silicon nitride (SIN) is exposed using a mask (CG Mask). Then, the silicon nitride is used as a hard mask to etch the gate structure layer. While in the logic area, a normal mask (i.e., Poly Mask) is directly used, and photoresist is directly etched. Therefore, the memory area and the logic area do not use the same mask. The mask of the memory area only contains the device patterns of the memory area. And there are no patterns in the logic area part. Therefore, during the subsequent etching process, since etching is sensitive to transmittance, when etching the memory area, it is easy to cause damage to the logic area. At the same time, if different storage capacities are required, the sizes of the memory areas are different, and the transmittance of the masks of different products will be different, resulting in different degrees of damage. The existing solution is to adjust the process parameters of product etching to eliminate the above-mentioned damage. However, even so, the problem of device damage cannot be completely solved. Especially for the process with smaller size and higher integration, the requirements for the topography and critical dimensions after lithography are very strict, ultimately affecting the yield of the device and the electrical uniformity and reliability of the device.
[0003] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background technology of this invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of the present invention is to provide a control gate and a floating gate and a manufacturing method thereof to solve the problem of damage to the peripheral logic area when etching the memory area.
[0005] To solve the above technical problems, the present invention provides a manufacturing method of a control gate and a floating gate, including:
[0006] Provide a semiconductor substrate, the semiconductor substrate including a storage area and a peripheral logic area, the storage area and the peripheral logic area respectively including a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer sequentially deposited upward from a substrate;
[0007] Deposit a photoresist on the surface of the hard mask layer in the storage area and the peripheral logic area;
[0008] Provide a first mask, on which a storage area gate pattern and a dummy pattern are provided. Transfer the storage gate pattern to the photoresist layer in the storage area through exposure and development to form a first photoresist pattern. At the same time, transfer the dummy pattern to the photoresist layer in the peripheral logic area through exposure and development to form a second photoresist pattern, and the second photoresist pattern is used to increase the pattern density in the peripheral logic area;
[0009] Using the first photoresist pattern as a mask, etch the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer in sequence to form a first control gate and a first floating gate in the storage area.
[0010] Preferably, the first control gate and the first floating gate are formed by a self-aligned double patterning technique.
[0011] Preferably, after forming the first control gate and the first floating gate, the method further includes:
[0012] Form a second control gate and a second floating gate in the peripheral logic area.
[0013] Preferably, the width of the dummy pattern in the lateral direction is smaller than the width of the gate pattern in the peripheral logic area.
[0014] Preferably, the formation of the control gate and the floating gate by the self-aligned double patterning technique includes:
[0015] Using the first photoresist pattern and the second photoresist pattern as masks, perform patterning on the hard mask layer to form a mandrel;
[0016] Form sidewalls on both sides of the mandrel;
[0017] Remove the mandrel and retain the sidewalls on both sides of the mandrel;
[0018] Using the sidewall in the storage area as a hard mask, etch the control gate layer and the floating gate layer in sequence to form a first control gate and a first floating gate in the storage area.
[0019] Preferably, the formation of the second control gate and the second floating gate in the peripheral logic area includes:
[0020] Deposit a photoresist layer on the surface of the peripheral logic area, and the photoresist layer fills the sidewalls in the peripheral logic area;
[0021] A second mask is provided, on which gate patterns for the peripheral logic region are provided. The gate patterns are transferred to a photoresist layer through exposure and development to form a third photoresist pattern, and the position of the third photoresist pattern is the same as the position of the sidewall.
[0022] Using the third photoresist pattern as a mask, the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer are etched in sequence to form a second control gate and a second floating gate for the peripheral logic region respectively.
[0023] Preferably, after using the first photoresist pattern and the second photoresist pattern as masks to pattern the hard mask layer to form a mandrel, the method further includes performing chemical mechanical polishing on the mandrel.
[0024] Preferably, the material of the control gate layer is polysilicon, and the material of the floating gate layer is amorphous silicon.
[0025] Preferably, the density of the dummy patterns is different for different semiconductor devices.
[0026] Based on the same inventive concept, the present invention also provides a control gate and a floating gate, including:
[0027] Manufactured by using the etching method as described above.
[0028] Compared with the prior art, the manufacturing method of the control gate and the floating gate of the present invention has the following advantages:
[0029] By adding dummy patterns to the first mask, the present invention can add patterns to the areas where device patterns exist in the Logic region, improve the density of the patterns in the Logic region, change the light transmittance of the entire mask, and reduce the light transmittance of the Logic region, so that the light transmittance of the Logic region and the Cell region can be made as close as possible. Thus, when etching the second TEOS layer to form a mandrel in the Cell region, damage to the Logic region can be avoided, and the yield of the device, as well as the electrical uniformity and reliability of the device, can be improved.
[0030] The control gate and the floating gate provided by the present invention and the manufacturing method of the control gate and the floating gate provided by the present invention belong to the same inventive concept. Therefore, the control gate and the floating gate provided by the present invention have at least all the advantages of the manufacturing method of the control gate and the floating gate provided by the present invention, improving the yield of the device, as well as the electrical uniformity and reliability of the device. Description of the Drawings
[0031] Figure 1 is a schematic structural diagram of forming a photoresist pattern on a hard mask layer in an embodiment;
[0032] Figure 2 is a schematic structural diagram after etching the hard mask layer in an embodiment;
[0033] Figure 3 is a flowchart of a method for forming a control gate and a floating gate in an embodiment of the present invention;
[0034] Figure 4 is a schematic structural diagram of forming a photoresist pattern on the surface of a hard mask layer in an embodiment of the present invention;
[0035] Figure 5 is a schematic structural diagram of forming a mandrel in an embodiment of the present invention;
[0036] Figure 6 is a schematic structural diagram after modifying the mandrel in an embodiment of the present invention;
[0037] Figure 7 is a schematic structural diagram of forming sidewalls on both sides of the mandrel in an embodiment of the present invention;
[0038] Figure 8 is a schematic structural diagram after removing the mandrel in an embodiment of the present invention;
[0039] Figure 9 is a schematic structural diagram after depositing photoresist in the peripheral logic region in an embodiment of the present invention;
[0040] In the figure,
[0041] 10 - TEOS layer; 20 - photoresist pattern;
[0042] 100 - substrate; 200 - floating gate layer;
[0043] 300 - dielectric layer; 400 - control gate layer;
[0044] 500 - etch stop layer; 600 - first TEOS layer;
[0045] 700 - amorphous silicon layer; 800 - second TEOS layer;
[0046] 810 - first mandrel; 820 - second mandrel;
[0047] 830 - sidewall; 900 - photoresist;
[0048] 910 - first photoresist pattern; 920 - second photoresist pattern. Detailed implementation manners
[0049] To make the objectives, advantages, and features of the present invention more clear, the following further elaborates on the control gate and floating gate proposed by the present invention and their manufacturing methods in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in extremely simplified forms and use non-precise scales, solely for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0050] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0051] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0052] Refer Figure 1 And Figure 2 As shown, currently, in the Nand-flash memory, when performing the manufacturing process of the control gate and floating gate, the storage area (i.e., the Cell area) and the peripheral logic area (i.e., the Logic area) do not use the same mask. The mask of the Cell area only contains the device patterns of the Cell area. And there are no patterns in the mask of the Logic area. Therefore, through the mask of the Cell area, the following is formed in the Cell area Figure 1The photoresist pattern 20 shown. However, no photoresist pattern 20 is formed on the surface of the Logic region. During the subsequent etching of the TEOS layer 10, since the etching is sensitive to transmittance, damage is likely to be caused to the peripheral logic region during the etching of the storage region. If different storage capacity requirements lead to different sizes of the storage region, the transmittance of the mask of the Cell region of different products will be different, resulting in different degrees of damage, affecting the yield of the device, as well as the electrical uniformity and reliability of the device.
[0053] The core idea of the present invention is to provide a method for fabricating a control gate and a floating gate, which can avoid damaging the peripheral logic region during the etching of the storage region, so as to improve the yield of the device, as well as the electrical uniformity and reliability of the device.
[0054] To achieve the above idea, the present invention provides a method for fabricating a control gate and a floating gate, referring to Figures 3 to 9 a specific embodiment of a method for fabricating a control gate and a floating gate disclosed. The method for fabricating the control gate and the floating gate includes the following steps S1 to S5.
[0055] Step S1: Provide a semiconductor substrate, the semiconductor substrate includes a storage region and a peripheral logic region, and the storage region and the peripheral logic region respectively include a floating gate layer 200, a dielectric layer 300, a control gate layer 400, and a hard mask layer deposited sequentially from the substrate upwards.
[0056] Specifically, referring to Figure 3 and Figure 4 shown, provide a semiconductor substrate, the semiconductor substrate includes a storage region (i.e., the Cell region in Figure 4 ), and a peripheral logic region (i.e., the Logic region in Figure 4 ). The Cell region and the Logic region include a substrate 100, and a floating gate layer 200, a control gate layer 400, and a hard mask layer deposited sequentially from the substrate 100 upwards.
[0057] The material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, or silicon on insulator (SOI), etc., and doping regions can also be formed in the substrate 100.
[0058] The material of the floating gate layer 200 is amorphous silicon. The material of the control gate layer 400 is polycrystalline silicon. A dielectric layer 300 is provided between the floating gate layer 200 and the control gate layer 400. The dielectric layer 300 uses insulating materials, such as silicon, silicon dioxide, etc.
[0059] The hard mask layer includes an etch stop layer 500, a first TEOS layer 600, an amorphous silicon layer 700, and a second TEOS layer 800 deposited sequentially from the substrate 100 upwards. The material of the etch stop layer 500 is silicon nitride (SiN).
[0060] Step S2: Deposit a photoresist layer on the surface of the hard mask layer in the storage area and the peripheral logic area.
[0061] Step S3: Provide a first mask, on which a storage area gate pattern and dummy patterns are provided. Transfer the storage gate pattern to the photoresist layer in the storage area through exposure and development to form a first photoresist pattern 910. At the same time, transfer the dummy patterns to the photoresist layer in the peripheral logic area through exposure and development to form a second photoresist pattern 920, and the second photoresist pattern 920 is used to increase the pattern density in the peripheral logic area.
[0062] Specifically, as shown in Figure 3 and Figure 4 , provide a first mask, which is used to form device patterns in the Cell area. A Cell area gate pattern is provided on the first hard mask. The first hard mask layer is also provided with dummy patterns. The dummy patterns are located at the position where the Logic area is located. Transfer the Cell area gate pattern to the photoresist layer in the Cell area through exposure and development to form a first photoresist pattern 910. At the same time, transfer the dummy patterns to the photoresist layer in the Logic area through exposure and development to form a second photoresist pattern 920, that is, form a structure as shown in Figure 4 . The second photoresist pattern 920 is used to increase the pattern density in the Logic area.
[0063] The width of the dummy pattern in the transverse direction is smaller than the width of the gate pattern in the Logic area. When forming the gate pattern in the subsequent Logic area, it will not affect the topography of the gate pattern in the Logic area, thus avoiding affecting the control gate and floating gate in the Logic area.
[0064] In this embodiment, by adding dummy patterns to the first mask, dummy patterns can be added to the areas where there are device patterns in the Logic area, improving the pattern density in the Logic area, changing the light transmittance of the entire mask, reducing the light transmittance in the Logic area, and making the light transmittance in the Logic area and the Cell area as close as possible. Thus, when etching the second TEOS layer 800 to form a mandrel in the Cell area, damage to the Logic area can be avoided, improving the yield of the device, as well as the electrical uniformity and reliability of the device.
[0065] For different semiconductor device products, the density of the dummy patterns is different. According to the product capacity, add dummy patterns with different densities to make the transmittance of different products as close as possible. This not only solves the problem of damage to other non-storage areas during the etching process of the storage area, but also enables the etching process flows of different products on the same platform to be consistent, without the need to adjust the process parameters of each process step, greatly improving the yield and device reliability.
[0066] Step S4: Using the first photoresist pattern 910 as a mask, etch the hard mask layer, the control gate layer 400, the dielectric layer 300, and the floating gate layer 200 in sequence to form the first control gate and the first floating gate of the storage area respectively.
[0067] Specifically, referring Figures 3 to 8 as shown, the first control gate and the first floating gate are formed by self-aligned double patterning technology. The formation of the control gate and the floating gate by self-aligned double patterning technology includes:
[0068] First, using the first photoresist pattern 910 and the second photoresist pattern 920 as masks, pattern the hard mask layer to form mandrels. Using the first photoresist pattern 910 as a mask, etch the hard mask layer to form the first mandrel 810 in the hard mask layer of the Cell area and the second mandrel 820 in the hard mask layer of the Logic area.
[0069] After using the first photoresist pattern 910 and the second photoresist pattern 920 as masks to pattern the hard mask layer to form mandrels, the method further includes performing chemical mechanical polishing on the mandrels. By increasing the pattern density in the Logic area, the flatness of the polishing can also be improved when performing chemical mechanical polishing.
[0070] Next, in order to precisely control the critical dimension of the first mandrel 810, further wet-etch the first mandrel 810 to modify the first mandrel 810 to achieve a duty ratio of 1:3. After modification, the width of the first mandrel 810 in the lateral direction decreases, and the distance between two adjacent first mandrels 810 increases, forming a structure as Figure 6 shown.
[0071] Then, referring Figure 7 as shown, form sidewalls 830 on both sides of the first mandrel 810. At the same time, sidewalls 830 are also formed on both sides of the second mandrel 820. The sidewalls 830 can be either a single-layer structure or a multi-layer structure. The single-layer sidewalls 830 can be formed of silicon dioxide material. For the double-layer sidewalls 830, they can be composed of a silicon nitride sidewall and a silicon dioxide sidewall located outside the silicon nitride sidewall.
[0072] Secondly, referring Figure 8 as shown, use wet etching to remove the mandrels and retain the sidewalls 830 on both sides of the mandrels.
[0073] Finally, using the sidewall of the storage area as a hard mask, the control gate layer 400 and the floating gate layer 200 are etched in sequence to form the first control gate and the first floating gate of the storage area. Using the sidewall as a mask, the amorphous silicon layer 700, the second TEOS layer 800, and the etch stop layer 500 are etched in sequence, and a gate topography is formed on the etch stop layer 500. Using the gate topography as a mask, the control gate layer 400, the dielectric layer 300, and the floating gate layer 200 in the Cell area are etched to form the first control gate and the first floating gate.
[0074] Step S5: Form a second control gate and a second floating gate in the peripheral logic area.
[0075] Specifically, referring Figure 3 and Figure 9 as shown, first, a photoresist layer is deposited on the surface of the peripheral logic area, and the photoresist layer fills the sidewall 830 of the peripheral logic area. The photoresist 900 (i.e., PR) fills the sidewall 830 in the Logic area. The height of the photoresist 900 is greater than the height of the sidewall 830.
[0076] Next, a second mask is provided, and a gate pattern for the peripheral logic area is provided on the second mask. The gate pattern is transferred to the photoresist layer through exposure and development to form a third photoresist pattern, and the position of the third photoresist pattern is the same as the position of the sidewall 830. A second mask is provided, and a gate pattern for the peripheral logic area is provided on the second mask. The gate pattern for the peripheral logic area is transferred to the photoresist 900 through exposure and development to form a third photoresist pattern (not shown in the figure), and the position of the third photoresist pattern is the same as the position of the sidewall.
[0077] Then, using the third photoresist pattern as a mask, the hard mask layer, the control gate layer 400, the dielectric layer 300, and the floating gate layer 200 are etched in sequence to form the second control gate and the second floating gate of the peripheral logic area. Using the third photoresist pattern as a mask, the amorphous silicon layer 700, the second TEOS layer 800, and the etch stop layer 500 in the Logic area are etched in sequence, and a gate topography is formed on the etch stop layer 500 in the Logic area. Using the gate topography as a mask, the control gate layer 400, the dielectric layer 300, and the floating gate layer 200 in the Logic area are etched to form the second control gate and the second floating gate.
[0078] To implement the above idea, this embodiment also discloses a control gate and a floating gate, including:
[0079] Manufactured by using the etching method as described above.
[0080] The control gate and floating gate provided in this embodiment and the manufacturing method of the control gate and floating gate provided in this embodiment belong to the same inventive concept. Therefore, the control gate and floating gate provided in this embodiment have at least all the advantages of the manufacturing method of the control gate and floating gate provided in this embodiment, improving the yield of the device, as well as the electrical uniformity and reliability of the device.
[0081] In summary, the above embodiments have described in detail the different configurations of the control gate and floating gate and their manufacturing methods. Of course, the above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the content of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the protection scope of the claims.
Claims
1. A manufacturing method of a control gate and a floating gate, characterized in that, Comprising: Providing a semiconductor substrate, the semiconductor substrate including a storage area and a peripheral logic area, the storage area and the peripheral logic area respectively including a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer sequentially deposited upward from the substrate; Depositing a photoresist on the surface of the hard mask layer in the storage area and the peripheral logic area; Providing a first mask, the first mask being provided with a storage area gate pattern and a dummy pattern, transferring the storage gate pattern to the photoresist layer in the storage area through exposure and development to form a first photoresist pattern, and at the same time transferring the dummy pattern to the photoresist layer in the peripheral logic area through exposure and development to form a second photoresist pattern, the second photoresist pattern being used to increase the pattern density in the peripheral logic area; Using the first photoresist pattern as a mask, etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer in sequence to form a first control gate and a first floating gate in the storage area.
2. The manufacturing method of the control gate and the floating gate according to claim 1, wherein The first control gate and the first floating gate are formed by self-aligned double patterning technology.
3. The manufacturing method of the control gate and the floating gate according to claim 1, wherein, After forming the first control gate and the first floating gate, the method further includes: Forming a second control gate and a second floating gate in the peripheral logic area.
4. The manufacturing method of the control gate and the floating gate according to claim 3, wherein, The width of the dummy pattern in the lateral direction is less than the width of the gate pattern in the peripheral logic area.
5. The manufacturing method of the control gate and the floating gate according to claim 3, wherein The control gate and the floating gate are formed by self-aligned double patterning technology, including: Using the first photoresist pattern and the second photoresist pattern as masks to pattern the hard mask layer to form a mandrel; Forming sidewalls on both sides of the mandrel; Removing the mandrel and retaining the sidewalls on both sides of the mandrel; Using the sidewall in the storage area as a hard mask to etch the control gate layer and the floating gate layer in sequence to form a first control gate and a first floating gate in the storage area.
6. The manufacturing method of the control gate and the floating gate according to claim 5, characterized in that, Forming the second control gate and the second floating gate in the peripheral logic area includes: Depositing a photoresist layer on the surface of the peripheral logic area, the photoresist layer filling the sidewalls in the peripheral logic area; Providing a second mask, the second mask being provided with a gate pattern in the peripheral logic area, transferring the gate pattern to the photoresist layer through exposure and development to form a third photoresist pattern, the position of the third photoresist pattern being the same as the position of the sidewall; Using the third photoresist pattern as a mask to etch the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer in sequence to form a second control gate and a second floating gate in the peripheral logic area.
7. The manufacturing method of the control gate and the floating gate according to claim 5, characterized in that, After using the first photoresist pattern and the second photoresist pattern as masks to pattern the hard mask layer to form a mandrel, the method further includes performing chemical mechanical polishing on the mandrel.
8. The manufacturing method of the control gate and the floating gate according to claim 7, characterized in that The material of the control gate layer is polysilicon, and the material of the floating gate layer is amorphous silicon.
9. The manufacturing method of the control gate and the floating gate according to claim 1, characterized in that, For different semiconductor devices, the density of the dummy pattern is different.
10. A control gate and a floating gate, characterized in that, Comprising: Manufactured by using the etching method according to any one of claims 1-9.