A high-pressure annealing device and annealing method for indium phosphide wafers

Abstract

The present invention relates to a high-pressure annealing device and annealing method for indium phosphide wafers, comprising a high-pressure resistant box, a heater and a quartz tube arranged in the high-pressure resistant box; the heater is divided into a high-temperature end heater and a low-temperature end heater, one side of the quartz tube being the low-temperature end and the other side being the high-temperature end; a quartz boat for holding red phosphorus and a wafer sample holder for placing indium phosphide wafers are vacuum-sealed in the quartz tube; the quartz boat is arranged at the low-temperature end of the quartz tube, and the wafer sample holder is arranged at the high-temperature end of the quartz tube; the wafer sample holder is an arc-shaped concave structure, and a plurality of sample slots for upright placement of wafers are arranged in parallel on the upper side of the wafer sample holder; this solution can achieve the purpose of annealing wafers at a relatively high temperature, effectively avoid the decomposition of indium phosphide at high temperature, and simultaneously realize batch synchronous annealing of multiple indium phosphide wafers; annealing at high temperature can effectively reduce stress in the wafers, improve the electrical and mechanical properties of the wafers, and reduce the fragmentation rate.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor processing, and in particular relates to a high-voltage annealing device and an annealing method for indium phosphide wafers. Background Art

[0002] Indium phosphide (InP) is an important III-V compound semiconductor material. As a key optoelectronic and microelectronics foundational material, it can be used to manufacture lasers and detectors for fiber-optic communications, integrated circuits, and high-frequency microwave / millimeter wave devices.

[0003] Indium phosphide wafers, especially large ones, experience significant thermal stress due to the large radial temperature gradient during crystal growth. Furthermore, mechanical stress is generated during wafer processing. These stresses can easily cause wafer deformation and fragmentation during processing. Furthermore, high thermal stress leads to a high density of defects within the crystal, while mechanical stress can cause mechanical damage to the wafer. Annealing can reduce internal thermal and mechanical stresses in indium phosphide wafers, improving their mechanical strength; it can also reduce internal defects and improve their electrical performance.

[0004] Because the dissociation pressure of indium phosphide reaches 2.75 MPa near the melting point of InP (1060°C), existing processes for annealing in a vacuum or inert gas atmosphere can only be performed at relatively low temperatures, resulting in poor annealing results. This is because if annealing is performed at high temperatures (above 900°C) without the high-pressure protection of a phosphorus atmosphere, indium phosphide will easily decompose, resulting in losses.

[0005] During annealing, wafers are commonly placed in two ways: horizontally and vertically. A disadvantage of horizontal placement is that the upper and lower surfaces of the wafer have different degrees of contact with the atmosphere, which may affect the wafer's ultimate electrical uniformity and surface integrity. Vertical placement, in which the wafer is placed vertically (usually not completely vertically) on a rack, effectively avoids this problem of inconsistent contact with the atmosphere. However, due to the influence of gravity, the wafer may deform or shift its center of gravity during prolonged, high-temperature annealing, affecting its performance parameters.

[0006] Chinese patent application number CN201711105483.1, titled "Method for Annealing Iron-Doped Indium Phosphide Single Crystals," discloses a method for annealing iron-doped indium phosphide single crystals. The method involves placing the iron-doped indium phosphide single crystal and a red phosphorus spacer in a quartz tube, evacuating the tube, and sealing the tube. The sealed tube is then placed in an annealing furnace for annealing. This invention, which anneals the iron-doped indium phosphide single crystal and a red phosphorus spacer in a quartz tube, evacuating the tube, and sealing the tube, is a representative method. A common flaw is insufficient pressure control for the high-pressure protection of the phosphorus atmosphere during annealing.

[0007] In a Chinese patent application numbered CN201410135092.4 and titled "Indium Phosphide Wafer Annealing Box," the patent discloses a wafer carrier device comprising a base, a material holding chamber, a wafer platform, support columns, fixed columns, and a top cover. The material holding chamber is a chamber between the base and the wafer platform, and the wafer platform is fixed to the base. Each wafer platform has multiple support columns and multiple fixed columns, which are distributed in a divergent manner, and the wafer is placed above the support columns. This invention can, to a certain extent, solve the problem of inconsistent annealing surface morphology on the front and back sides of the wafer, but the structure is in multi-point fixed contact with the wafer, and problems such as local deformation may still occur during long-term annealing. Summary of the Invention

[0008] The purpose of the present invention is to provide a phosphorus atmosphere high pressure annealing device and method for indium phosphide wafers, which can anneal the wafers at a higher temperature, reduce the deformation of the wafers when placed upright, and realize batch synchronous annealing of multiple indium phosphide wafers.

[0009] In order to solve the above technical problems, the present invention discloses a high-pressure annealing device for indium phosphide wafers, comprising a high-pressure resistant box and a heater and a quartz tube arranged in the high-pressure resistant box; the heater is divided into a high-temperature end heater and a low-temperature end heater, one side of the quartz tube is the low-temperature end, and the other side is the high-temperature end; the low-temperature end heater is arranged outside the low-temperature end of the quartz tube, and the high-temperature end heater is arranged outside the high-temperature end of the quartz tube; a quartz boat for holding red phosphorus and a wafer sample holder for placing indium phosphide wafers are vacuum-sealed in the quartz tube; the quartz boat is arranged at the low-temperature end of the quartz tube, and the wafer sample holder is arranged at the high-temperature end of the quartz tube; a coolant pipe is provided on the inner wall of the high-pressure resistant box or an interlayer for circulating coolant is provided in the high-pressure resistant box; the wafer sample holder is an arc-shaped concave structure, and a plurality of sample slots for upright placement of wafers are arranged in parallel on the upper side of the wafer sample holder.

[0010] Preferably, the bottom of the sample tank is arc-shaped, and the curvature of the arc line of the bottom of the sample tank is not greater than the curvature of the circumference of the wafer.

[0011] Preferably, the upper ends of both side walls of the sample slot of the wafer sample holder are detachably provided with mounting bars, and a plurality of bosses for reducing the contact area between the side surface of the wafer and the sample slot are provided on a side wall of the mounting bar close to the sample slot.

[0012] Preferably, the maximum pressure-resistant box can withstand no less than 6 MPa.

[0013] Preferably, the quartz tube, wafer sample holder and quartz boat are all made of high-purity quartz.

[0014] Preferably, the high-temperature end heater and the low-temperature end heater are both electrically heated.

[0015] An annealing method using the above annealing device is characterized by comprising the following steps:

[0016] S1. Place the wafer in the sample slot of the wafer sample holder and then place it on the high-temperature end of the quartz tube; place a quartz boat filled with red phosphorus on the low-temperature end of the quartz tube, evacuate the quartz tube, and seal it by welding;

[0017] S2. Place the sealed quartz tube into the high-pressure box heater. After placement, the quartz boat is in the low-temperature heater cover area, and the wafer sample holder is in the high-temperature heater cover area.

[0018] S3. The low-temperature heater and the high-temperature end heater are heated simultaneously at a rate of 5-10°C / min to 500-550°C. At this time, the phosphorus vapor pressure in the quartz tube reaches the dissociation pressure of indium phosphide. While heating, an inert gas is slowly filled into the high-pressure box so that the pressure difference between the inside and outside of the quartz tube does not exceed 0.3 MPa during the heating process to maintain pressure balance inside and outside the quartz tube.

[0019] S4. The high temperature end heater is slowly raised to an annealing temperature of 900-950°C at a rate of 1-5°C / min, and the annealing temperature is maintained for 5-20 hours for annealing the wafer;

[0020] S5. First, lower the temperature of the high-temperature end heater to below 700°C at a rate of 1-5°C / min. Then, lower both the low-temperature end heater and the high-temperature end heater to room temperature at a rate of 1-5°C / min. This completes the annealing operation.

[0021] Preferably, in S2, one side of the high-pressure resistant box is raised so that the chip sample holder is tilted no more than 20°. At this time, the chip is on one side of the sample slot. After reaching the annealing temperature, the height of one side of the high-pressure resistant box is changed at regular intervals during the annealing process, and finally the tilt of the chip sample holder is made to not exceed -20°; during this process, the chip gradually rolls to the other side of the sample slot.

[0022] Preferably, in S1, the red phosphorus purity is >6N.

[0023] Preferably, in S1, the vacuum degree of the quartz tube after evacuation is less than 1×10 -4 Pa.

[0024] The high-pressure annealing device and annealing method for indium phosphide wafers of the present invention have at least the following advantages:

[0025] 1. It can achieve the purpose of annealing the wafer at a higher temperature, which can effectively avoid the decomposition of indium phosphide at high temperature. At the same time, it can realize batch synchronous annealing of multiple indium phosphide wafers. Annealing at high temperature can effectively reduce the stress in the wafer, improve the electrical and mechanical properties of the wafer, and reduce the fragmentation rate.

[0026] 2. The curvature of the arc at the bottom of the sample slot is greater than the curvature of the wafer circumference. During the annealing process, by changing the tilt angle of the wafer sample holder, the wafer can be slightly rotated along the sample slot, changing the contact position between the wafer and the sample slot, effectively avoiding problems such as wafer center of gravity shift and deformation during long-term high-temperature annealing.

[0027] 3. By setting up a mounting bar with a boss to reduce the contact area between the side of the chip and the sample slot, it is not only beneficial for the smooth rolling of the chip when the tilt angle of the chip sample holder is changed, but also the service life of the chip sample holder can be extended by replacing the mounting bar. At the same time, by replacing the mounting bar with different boss heights, the chip can be at different tilt angles when it is docked on the side wall of the sample slot.

[0028] 4. The quartz boat and the sample holder are temperature controlled separately at both ends, which is beneficial to maintain a lower gas pressure in the quartz tube while ensuring that indium phosphide does not decompose at high temperature, and can also reduce the loss of red phosphorus. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic structural diagram of a high-pressure annealing device for indium phosphide wafers.

[0030] Figure 2 The figure is a structural diagram of a mounting bar.

[0031] Figure 3 This is a schematic diagram of the bottom structure of a sample tank, wherein the arc arrow shows the rotation direction of the chip, and the straight arrow shows the movement direction of the bottom of the sample tank or one end of the high-pressure resistant box.

[0032] The numbers in the figure are: 1-high pressure resistant box, 2-quartz tube, 3-low temperature end heater, 4-high temperature end heater, 5-quartz boat, 6-red phosphorus, 7-wafer sample holder, 8-wafer, 9-mounting bar, 10-boss, 11-sample slot, 12-sample slot bottom. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below through examples so that those skilled in the art can implement the invention with reference to the description.

[0034] It should be understood that terms such as “having”, “including” and “comprising” used herein do not preclude the existence or addition of one or more other elements or combinations thereof. Example 1

[0035] like Figure 1-2As shown, a high-pressure annealing device for indium phosphide wafers comprises a high-pressure resistant box 1 and a heater and a quartz tube 2 arranged in the high-pressure resistant box; the heater is divided into a high-temperature end heater 4 and a low-temperature end heater 3, one side of the quartz tube is the low-temperature end, and the other side is the high-temperature end; the low-temperature end heater is arranged on the outside of the low-temperature end of the quartz tube, and the high-temperature end heater is arranged on the outside of the high-temperature end of the quartz tube; a quartz boat 5 for holding red phosphorus 6 and a wafer sample holder 7 for placing indium phosphide wafers are vacuum-sealed in the quartz tube; the quartz boat is arranged at the low-temperature end of the quartz tube, and the wafer sample holder is arranged at the high-temperature end of the quartz tube, a coolant pipe is provided on the inner wall of the high-pressure resistant box or an interlayer for circulating coolant is provided in the high-pressure resistant box; the wafer sample holder is an arc-shaped concave structure, and a plurality of sample slots 11 for upright placement of wafers 8 are arranged side by side on the upper side of the wafer sample holder.

[0036] The bottom of the sample slot is in an arc shape that matches the circumference of the wafer, that is, the wafer is fixed after being placed in the sample slot.

[0037] The wafer sample holder's sample slots are detachably provided with mounting bars 9 on the upper ends of both sides of the sample slot. A plurality of protrusions 10 are located on the side of the mounting bar near the sample slot to reduce the contact area between the wafer side and the sample slot. The width of the sample slot is greater than the thickness of the wafer, allowing for smooth insertion of the wafer. The wider sample slots also ensure a more consistent phosphorus atmosphere within each slot. However, to prevent excessive side tilt of the wafer when resting against the side of the sample slot, the protrusions are necessary to maintain a low side tilt angle when the wafer is upright.

[0038] The maximum pressure resistance of the high-pressure resistant box is not less than 6 MPa.

[0039] The quartz tube, the wafer sample holder and the quartz boat are all made of high-purity quartz, and the high-pressure resistant box is made of stainless steel.

[0040] The high temperature end heater and the low temperature end heater are both electrically heated. Example 2

[0041] An annealing method using the above annealing device is characterized by comprising the following steps:

[0042] S1. Place the wafer in the sample slot of the wafer sample holder and then place it on the high-temperature end of the quartz tube; place a quartz boat filled with red phosphorus on the low-temperature end of the quartz tube, evacuate the quartz tube, and seal it by welding;

[0043] S2. Place the sealed quartz tube into the high-pressure box heater. After placement, the quartz boat is in the low-temperature heater cover area, and the wafer sample holder is in the high-temperature heater cover area.

[0044] S3. Simultaneously raise the temperature of the low-temperature heater and the high-temperature end heater to 500-550°C at a rate of 5-10°C / min. At this point, the phosphorus vapor pressure in the quartz tube reaches the dissociation pressure of indium phosphide (2.75 MPa. During the annealing process, as long as the phosphorus vapor pressure in the quartz tube is not lower than the dissociation pressure of indium phosphide, it will not affect the annealing effect). While the temperature is rising, slowly fill the high-pressure box with inert gas so that the pressure difference between the inside and outside of the quartz tube does not exceed 0.3 MPa during the heating process (for example, the pressure outside the quartz tube is set to approximately 2.80 MPa) to maintain pressure balance inside and outside the quartz tube.

[0045] S4. Slowly raise the high-temperature end heater to an annealing temperature of 900-950°C at a rate of 1-5°C / min, and maintain the annealing temperature for 5-20 hours to anneal the wafer. It is worth noting that since the quartz boat and sample holder are temperature-controlled separately at both ends, it is necessary to ensure that there is sufficient spacing between the high-temperature end and the low-temperature end of the quartz tube so that the high-temperature area will not have a significant impact on the low-temperature area. If insulation material is installed between the quartz boat and the sample holder, the insulation material may introduce impurities at high temperatures, which will have an adverse effect on wafer annealing. If necessary, insulation material can be installed between the high-temperature end heater 4 and the low-temperature end heater 3 to prevent a significant temperature rise at the low-temperature end. If a significant temperature rise occurs at the low-temperature end during annealing, inert gas should be added to the high-pressure chamber.

[0046] S5. First, lower the temperature of the high-temperature end heater to below 700°C at a rate of 1-5°C / min. Then, lower both the low-temperature end heater and the high-temperature end heater to room temperature at a rate of 1-5°C / min. This completes the annealing operation.

[0047] In S1, the red phosphorus purity is greater than 6N.

[0048] In S1, the vacuum degree of the quartz tube after evacuation is less than 1×10 -4 Pa. Example 3

[0049] like Figure 3 As shown, it is similar to Example 1, except that the bottom of the sample tank is arc-shaped, and the curvature of the arc of the bottom 9 of the sample tank is smaller than the curvature of the circumference of the wafer.

[0050] During annealing, the process is similar to Example 2, with the difference being that, in S2, one side of the high-pressure resistant box is raised so that the chip sample holder is tilted no more than 20°. At this time, the chip is on one side of the sample slot. After reaching the annealing temperature, the height of one side of the high-pressure resistant box is changed at regular intervals during the annealing process, and ultimately the tilt of the chip sample holder is made to not exceed -20°. For example, the height of one side of the high-pressure resistant box can be fine-tuned every 0.5 hours to cause the chip to roll slightly. During the entire annealing process, the rolling distance of the chip exceeds 1 / 5 of the circumference of the chip. During this process, the chip gradually rolls to the other side of the sample slot. After the wafer rolls, the contact position with the bottom of the sample tank and the boss changes, which can effectively prevent the wafer from deformation, center of gravity shift and other problems. In actual operation, due to the friction between the wafer and the side wall of the sample tank, the wafer may not roll during a certain adjustment due to the wafer sample holder angle adjustment being too small. This has little effect on the product annealing effect. At the same time, due to the presence of the boss on the mounting bar, the wafer tilt angle can be effectively reduced, and the friction between the wafer and the side wall of the sample tank can be reduced, which can effectively avoid the wafer from not rolling during a certain adjustment.

[0051] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and embodiments shown and described herein.

Claims

1. A high-pressure annealing device for indium phosphide wafers, characterized in that: The invention comprises a high-pressure-resistant box and a heater and a quartz tube arranged in the high-pressure-resistant box; the heater is divided into a high-temperature end heater and a low-temperature end heater, one side of the quartz tube is the low-temperature end, and the other side is the high-temperature end; the low-temperature end heater is arranged outside the low-temperature end of the quartz tube, and the high-temperature end heater is arranged outside the high-temperature end of the quartz tube; a quartz boat for holding red phosphorus and a wafer sample holder for placing indium phosphide wafers are vacuum-sealed in the quartz tube; the quartz boat is arranged at the low-temperature end of the quartz tube, and the wafer sample holder is arranged at the high-temperature end of the quartz tube; a coolant pipe is provided on the inner wall of the high-pressure-resistant box or an interlayer for circulating coolant is provided in the high-pressure-resistant box; the wafer sample holder is an arc-shaped concave structure, and a plurality of sample slots for upright placement of wafers are arranged side by side on the upper side of the wafer sample holder; The bottom of the sample tank is arc-shaped, and the curvature of the arc of the bottom of the sample tank is smaller than the curvature of the wafer circumference; when one side of the high-pressure resistant box is raised, the upright wafer rolls along the sample tank and docks at a new position, thereby preventing the wafer from deforming and shifting its center of gravity during the annealing process; The upper ends of both side walls of the sample slot of the wafer sample rack are detachably provided with mounting strips, and a plurality of bosses for reducing the contact area between the wafer side and the sample slot are provided on one side wall of the mounting strip near the sample slot.

2. The high pressure annealing device according to claim 1, characterized in that: The maximum pressure resistance of the high-pressure resistant box is not less than 6 MPa.

3. The high pressure annealing device according to claim 1, characterized in that: The quartz tube, the wafer sample holder and the quartz boat are all made of high-purity quartz material.

4. The high pressure annealing device according to claim 1, characterized in that: The high temperature end heater and the low temperature end heater are both electrically heated.

5. An annealing method using the annealing device according to claim 1, characterized in that: The steps include: S1. Place the wafer in the sample slot of the wafer sample holder and then place it on the high-temperature end of the quartz tube; place a quartz boat filled with red phosphorus on the low-temperature end of the quartz tube, evacuate the quartz tube, and seal it by welding; S2. Place the sealed quartz tube into the high-pressure box heater. After placement, the quartz boat is in the low-temperature heater cover area, and the wafer sample holder is in the high-temperature heater cover area. S3. The low-temperature heater and the high-temperature end heater are heated simultaneously at a rate of 5-10°C / min to 500-550°C. At this time, the phosphorus vapor pressure in the quartz tube reaches the dissociation pressure of indium phosphide. While heating, an inert gas is slowly filled into the high-pressure box so that the pressure difference between the inside and outside of the quartz tube does not exceed 0.3 MPa during the heating process to maintain pressure balance inside and outside the quartz tube. S4. The high temperature end heater is slowly raised to an annealing temperature of 900-950°C at a rate of 1-5°C / min, and the annealing temperature is maintained for 5-20 hours for annealing the wafer; S5. First, lower the temperature of the high-temperature end heater to below 700°C at a rate of 1-5°C / min. Then, lower both the low-temperature end heater and the high-temperature end heater to room temperature at a rate of 1-5°C / min. This completes the annealing operation.

6. The annealing method according to claim 5, characterized in that In S2, one side of the high-pressure box is raised so that the chip sample holder is tilted no more than 20°. At this time, the chip is on one side of the sample slot. After reaching the annealing temperature, the height of one side of the high-pressure box is changed at regular intervals during the annealing process, and finally the tilt of the chip sample holder is made to not exceed -20°; during this process, the chip gradually rolls to the other side of the sample slot, and the rolling distance of the chip exceeds 1 / 5 of the circumference of the chip; after rolling, the contact position of the chip with the bottom of the sample slot and the boss changes.

7. The annealing method according to claim 5, characterized in that In S1, the red phosphorus purity is greater than 6N.

8. The annealing method according to claim 5, characterized in that In S1, the vacuum degree of the quartz tube after evacuation is less than 1×10 -4 Pa.

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