Test response compression method, electronic equipment, readable storage medium and program product

Abstract

The invention provides a test response compression method, electronic equipment, a readable storage medium and a program product. The method comprises the following steps: receiving a circuit response signal output by a scanning forest; the scanning forest comprises a plurality of scanning tree sets, each scanning tree set is driven by different clock signals, each scanning tree set comprises a plurality of scanning trees, and each scanning tree comprises a plurality of scanning chains; any scanning chain to be accessed is selected from a target scanning tree set, the compatibility of the scanning chain to be accessed and an accessed scanning chain is determined according to precursor information of a corresponding scanning trigger, and the accessed scanning chain is connected with a target XOR sub-network corresponding to the target scanning tree set. The target XOR sub-network comprises at least one XOR tree; and under the condition that the any one scan chain to be accessed is compatible with each accessed scan chain in any one XOR tree in the target XOR sub-network, accessing the scan chain to be accessed into the any one XOR tree.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a test response compression method, electronic equipment, a readable storage medium, and a program product. Background Art

[0002] Integrated circuit testing technology is a core approach for efficiently detecting and diagnosing chip manufacturing defects by embedding testability structures such as scan chains. Traditional approaches directly output the complete responses of all scan chains, resulting in exponential growth in test time and hardware overhead with circuit scale, making it increasingly difficult to meet the testing requirements of highly integrated chips. Therefore, improving test efficiency and reducing hardware overhead while ensuring test accuracy has become a major challenge facing the industry.

[0003] In related technologies, an exclusive-OR (XOR) compression structure is often used to reduce test data volume by combining the outputs of multiple scan chains into a single compressed signal. However, this method still has the following drawbacks: First, clock domain isolation and timing constraints are not considered during scan chain allocation, which can easily lead to signal contention or timing violations, resulting in compression distortion and even fault masking. Second, the fixed allocation strategy between different XOR trees results in resource waste and low hardware utilization. Summary of the Invention

[0004] In view of this, the present invention provides a test response compression method, electronic device, readable storage medium and program product to address the deficiencies in the related art.

[0005] Specifically, the present invention is achieved through the following technical solutions:

[0006] According to a first aspect of the present invention, a test response compression method is provided, the method comprising:

[0007] Receive a circuit response signal output by a scan forest; the scan forest includes multiple scan tree sets, each scan tree set is driven by a different clock signal, each scan tree set includes multiple scan trees, and each scan tree includes chains that are compatible, and connect the scan chain to be connected to any of the XOR trees.

[0008] According to a second aspect of the present invention, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method of the first aspect when executing the program.

[0009] According to a third aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the steps of the method according to the first aspect.

[0010] According to a fourth aspect of the present invention, there is provided a computer program product comprising a computer program or instructions, which implement the steps of the method according to the first aspect when executed by a processor.

[0011] In this specification, a circuit response signal output by a scan forest is received, and the scan forest includes a plurality of scan tree sets driven by different clock signals, each scan tree set includes a plurality of scan trees, and each scan tree further includes a plurality of scan chains, each scan chain consisting of cascaded scan triggers. By dividing the scan tree set according to the clock signal, it is ensured that the scan chains in the same XOR sub-network belong to the same clock domain, fundamentally eliminating the risk of cross-clock domain signal competition and timing violation, and avoiding compression distortion; at the same time, for any scan chain to be connected selected from the target scan tree set, the compatibility of the scan chain to be connected with the scan chain already connected in the target XOR sub-network can be determined based on the predecessor information of the corresponding scan trigger, and when any of the scan chains to be connected is compatible with each scan chain already connected in any XOR tree in the target XOR sub-network, the scan chain to be connected is connected to any of the XOR trees, thereby preventing fault masking caused by timing conflicts, optimizing resource allocation between XOR trees due to load imbalance, and improving hardware utilization. Ultimately, high-precision and low-overhead collaborative optimization of test response compression is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0013] Figure 1 1 is a schematic diagram of an integrated circuit test system according to an embodiment of the present invention;

[0014] Figure 2 This is a flow chart of a test response compression method according to an embodiment of the present invention;

[0015] Figure 3 is a schematic diagram of a linear feedback shift register shown in an embodiment disclosed in the present invention;

[0016] Figure 4 1 is a schematic diagram of the architecture of a test response compressor shown in an embodiment disclosed in the present invention;

[0017] Figure 5 is a schematic diagram of an integrated circuit testing system according to an embodiment of the present invention;

[0018] Figure 61 is a schematic diagram of an XOR tree in an XOR sub-network shown in an embodiment disclosed in the present invention;

[0019] Figure 7 It is a schematic diagram of a single stuck-at fault test and a transition delay fault test shown in an embodiment disclosed in the present invention;

[0020] Figure 8 is a schematic structural diagram of an electronic device shown in an embodiment of the present invention;

[0021] Figure 9 This is a block diagram of a test response compression device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, like numbers in different figures represent like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention.

[0023] The terms used in this invention are for the purpose of describing specific embodiments only and are not intended to limit the invention. The singular forms "a," "the," and "the" used in this invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0024] It should be understood that although the terms "first," "second," "third," etc. may be used in the present invention to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0025] The following describes in detail an embodiment of the test response compression method of this specification with reference to the accompanying drawings.

[0026] Figure 1 FIG. 1 is a schematic diagram of an integrated circuit test system according to an embodiment of the present invention. Figure 1As shown, the integrated circuit test system in this specification may include a software feedback shift register 10 (Linear Feedback Shift Register, SLFSR), a phase shifter 20 (Phase Shifter, PS), multiple multiplexers 30 (Multiplexer, MUX), a scan forest 40, a response compressor 50 and a feature analyzer 60.

[0027] The multi-stage linear feedback shift register 10 is a reconfigurable test pattern generation module that dynamically adjusts the feedback logic structure by configuring primitive polynomials of different levels. It includes multiple cascaded flip-flops and a programmable multiplexer, allowing control signals to switch the number of shift register levels and feedback paths, thereby adapting to changes in the scan forest 40's topology and target fault types.

[0028] Phase shifter 20 receives the test vector output by SLFSR and generates driving signals with different timing through multi-level phase shift. Each level of output corresponds to a specific phase shift, which is used to control the timing isolation of the scan tree set by multiplexer 30.

[0029] Multiplexer 30, the dynamic distribution hub of the scan chain, receives multi-phase test signals from phase shifter 20 and selects access paths for the target scan tree set in scan forest 40 according to a preset strategy. The gating logic of each MUX is strictly bound to the clock domain division of scan forest 40.

[0030] The scan forest 40 uses a hierarchical clock domain architecture and includes multiple scan tree sets driven by independent clocks. Each scan tree set includes multiple scan trees 410, each scan tree 410 includes multiple scan chains 420, and each scan chain 420 includes multiple cascaded scan triggers. The scan triggers are derived from the combinational logic of the circuit under test 70. For example, the scan tree set corresponding to clock domain A includes scan trees A1 and A2, where A1 includes scan chains A1-1 to A1-n, and the triggers of each chain are synchronously driven by clock CLK_A. Among them, this structure physically isolates scan chains in different clock domains to ensure that only scan chains with the same timing constraints exist within the same XOR sub-network corresponding to the target scan tree set, thereby eliminating cross-clock domain interference.

[0031] The response compressor 50 can include multiple XOR sub-networks, each corresponding to a set of scan trees in a specific clock domain. It employs a compatibility access mechanism, selecting any scan chain to be accessed from a target scan tree set containing at least one XOR tree. The compatibility of the scan chain to be accessed with the already accessed chains in the target XOR tree is determined based on the predecessor information of the corresponding scan trigger. If the scan chain to be accessed is compatible with every scan chain in any XOR tree, it can be accessed, thus avoiding masking of faulty responses. Furthermore, a load balancing algorithm dynamically adjusts the number of scan chains in the XOR tree to maximize hardware resource utilization.

[0032] The signature analyzer 60 receives the compressed signal output by the response compressor 50 and compares it bit by bit with the stored expected response. It then uses a difference location algorithm to identify the fault type and location. Furthermore, it includes a built-in timing calibration module that, combined with the clock domain partitioning information from the scan forest, independently analyzes the compression results for different clock domains, avoiding misjudgments caused by cross-domain signal jitter. The analysis results are output as a fault mapping table, precisely noting the physical coordinates and logical hierarchy of stuck-at faults in the circuit under test.

[0033] Those skilled in the art will understand that the execution objects of the operations mentioned above involving selecting the scan chain to be connected, determining compatibility based on predecessor information, and connecting the scan chain to be connected to any XOR tree can be adjusted according to actual conditions. For example, any of the above operations can be executed by the processing unit built into the response compressor 50, or can be executed by other computing modules connected to the response compressor 50. This is not limited in this specification.

[0034] The embodiments of the present disclosure do not limit the specific implementation of the multi-stage linear feedback shift register 10, phase shifter 20, multiple multiplexers 30, scan forest 40, response compressor 50, and feature analyzer 60. Those skilled in the art can configure them according to actual conditions and needs. For example, they can all be implemented using software-defined technology. Taking the multi-stage linear feedback shift register 10 as an example, it can be implemented based on a software-defined linear feedback shift register 10 (SLFSR). In specific implementation, it can be implemented using logic processing components such as FPGA and CPLD.

[0035] Those skilled in the art will appreciate that the number of registers in the above-mentioned linear feedback shift register LFSR can be referred to as the level of the linear feedback shift register LFSR. The maximum period of an n-stage LFSR is 2n-1. The sequence generated by the LFSR with a period of 2n-1 can be referred to as an m-sequence. The characteristic polynomial corresponding to the m-sequence LFSR feedback function is called a primitive polynomial. The embodiment of the present disclosure does not limit the specific level size (the size of n) of the multi-stage linear feedback shift register 10, and those skilled in the art can set it according to actual conditions and needs.

[0036] Specifically, a decompressor in a multi-stage linear feedback shift register (LFSR) can generate a test stimulus signal for a scan forest. The scan forest can further generate an output signal as a circuit response signal based on the received test stimulus signal. The decompressor can include an additional shift register for controlling the linear feedback shift register and a binary tree consisting of multiple AND gates, thereby providing a standardized implementation path for generating the test stimulus signal and ensuring that all components work together. Each AND gate is a two-input AND gate with two inputs and one output. The two inputs of each AND gate are respectively connected to the linear feedback shift register and the additional shift register. At the same time, the output of each AND gate can also be connected to the linear feedback shift register and, together with the scan input of a preset test seed, is connected to a two-input multiplexer to generate the test stimulus signal.

[0037] by Figure 2 For example, the n-level registers S0~Sn-1 of LFSR are used to store data and shift and transfer them in sequence. It is the basic storage structure for realizing linear feedback logic. Feedback signals a0-a are derived from each level of registers. n-1This input can be fed into the decompressor's XOR gates for logical operations. Together with the input into the corresponding XOR gates is an additional shift register R in the decompressor. Based on the logical characteristics of the XOR gates, this additional shift register R can be used to store the tap coefficients Cn that control the LFSR, enabling dynamic adjustment of the LFSR bits involved in the feedback operation. For example, when a bit in the additional shift register is 1, the corresponding LFSR bit participates in the feedback calculation; when it is 0, the bit is masked. This configurable tap mechanism enables the decompressor to adapt to different scan forest structures and target fault types, such as single stuck-at faults or transition delay fault testing. In short, by switching the tap coefficients, different test vectors can be generated, thereby improving the flexibility and universality of the test solution. As for the output end of the XOR gate, it can be connected to the scan input end of the preset test seed, that is, the "scan-in seeds", through a two-input multiplexer (MUX) to connect to the lowest-order trigger of the LFSR. At this time, through the selection control of the multiplexer, the above-mentioned decompressor can flexibly switch between the "seed initialization mode" of directly inputting the preset seed and the "feedback drive mode" of generating the vector based on the XOR tree calculation feedback function, taking into account the convenience of the initial configuration of the test and the autonomy of the subsequent vector generation, avoiding the separation problem of seed injection and feedback mechanism, and ultimately improving the generation efficiency of the test stimulus signal suitable for the above-mentioned scan forest.

[0038] In summary, the multi-stage linear feedback shift register 10 of the embodiment of this specification can implement primitive polynomials of different orders as needed to flexibly output test vectors based on the structure of the scan forest 40 and the target fault type. The phase shifter 20 performs phase shifting on the test vectors and outputs test vectors of different phases to drive the connected multiplexer 30, so that the response compressor 50 compresses the circuit response signal output by the scan forest 40 to obtain a compressed circuit response signal. The signature analyzer 60 then compares and analyzes the compressed circuit response signal with the expected circuit response signal to obtain a fault test result for the circuit under test 70, thereby achieving efficient testing of the circuit under test 70. The compression method of the response compressor 50 will be further discussed in detail in this specification.

[0039] Figure 3 The following is a flow chart of a test response compression method provided by an exemplary embodiment; the method is applied to an electric vehicle and may include the following steps:

[0040] Step S302, receiving a circuit response signal output by a scan forest; the scan forest includes multiple scan tree sets, each scan tree set is driven by a different clock signal, each scan tree set includes multiple scan trees, each scan tree includes multiple scan chains, each scan chain includes multiple cascaded scan triggers, and the scan triggers come from the combinational logic of the circuit under test.

[0041] First, the circuit response signal output by the above-mentioned scan forest can be received. This is a type of integrated circuit testing that can be regarded as a corresponding response signal (Response) generated by the internal logic of the circuit under test after the test vector (Test Pattern) is input into the circuit under test. These response signals can be captured and output by the scan chain to determine whether there is a fault in the circuit under test. As mentioned above, the above-mentioned scan forest can adopt a clock domain architecture, which includes multiple scan tree sets driven by independent clock signals. Each set is further divided into multiple scan trees, and each scan tree is composed of several scan chains. Each scan chain contains cascaded scan triggers, which are derived from the combinational logic of the circuit under test. By dividing the scan tree set by clock domain, it is ensured that the scan chains in the same clock domain share synchronous timing to avoid cross-domain signal competition.

[0042] In addition, the so-called combinational logic of the circuit under test refers to the combinational logic circuit in the digital circuit, and can be simply referred to as the combinational circuit. Its characteristic is that the output at any time depends only on the combination of the current input signals and is independent of the historical state of the circuit. This type of circuit is usually composed of logic gates such as AND gates, OR gates, and NOT gates, and does not contain timing elements such as triggers or latches, so it cannot store states. In actual scan testing, the functions of the combinational logic circuit can be connected in series into a scan chain through scan triggers to inject test vectors and capture response signals, thereby detecting manufacturing defects or logical errors. For example, the input and output of combinational logic such as AND gates can be connected through scan chains to achieve the propagation and observation of fault effects.

[0043] Step S304: select any scan chain to be connected from the target scan tree set, and determine the compatibility of the scan chain to be connected with the scan chain that has been connected based on the predecessor information of the corresponding scan trigger. The scan chain that has been connected is connected to the target XOR sub-network corresponding to the target scan tree set, and the target XOR sub-network includes at least one XOR tree.

[0044] When selecting a scan chain to be connected from the target scan tree set, its compatibility with the scan chain already connected in the target XOR sub-network can be determined based on the predecessor information of the scan trigger. The so-called predecessor information can be used to characterize the timing dependency or logical connection relationship of the scan triggers in the above scan chain; each XOR sub-network (XOR Sub-network), including the above target XOR sub-network, can establish a one-to-one corresponding association relationship with different scan tree sets. In other words, an XOR sub-network refers to a local compression unit in a response compressor for a specific scan tree set driven by the same gated clock, and each sub-network independently processes the output signal of its corresponding scan tree set; accordingly, the so-called XOR network (XOR Network) can be regarded as the XOR logical structure of the entire response compressor in a broad sense, which can contain multiple XOR sub-networks.

[0045] If the trigger of the chain to be connected shares common predecessor logic with any of the triggers of an already connected chain in the target XOR tree, a timing conflict risk is identified and access is denied. Conversely, if all connected chains have no predecessor dependency conflicts, they are considered compatible. For example, if the trigger predecessor node of scan chain A1-2 has no overlapping combinational logic paths with scan chain A1-1 already connected in the XOR tree, scan chains A1-1 and A1-2 can be determined to be compatible.

[0046] Based on this, in this specification, the compatibility between the scan chain to be connected and the scan chain already connected can be determined by following the intersection determination logic.

[0047] In one embodiment, first precursor information of the first scan flip-flop to be connected to the scan chain and second precursor information of the second scan flip-flop already connected to the scan chain can be obtained, wherein the first precursor information is used to represent the logic unit connected to the first scan flip-flop through the combinational logic and can be simply referred to as the combinational predecessor, and the second precursor information is used to represent the logic unit connected to the second scan flip-flop through the combinational logic. Then, the intersection of the logic units corresponding to the first and second precursor information in the target test cycle can be determined. If the intersection is empty, it can be determined that the scan chain to be connected and the already connected scan chain are compatible with each other; if the intersection is not empty, it can be determined that the scan chain to be connected and the already connected scan chain are incompatible with each other. Taking the first precursor information of the first scan flip-flop as an example, this information can be used to represent all upstream logic units, such as logic gates and registers, that are directly or indirectly connected to the flip-flop through the combinational logic of the circuit under test. At the same time, the second precursor information of the second scan flip-flop already connected to the scan chain in the target XOR sub-network is obtained, and its definition is consistent with the first precursor information. For example, if the first scan flip-flop is driven by an AND gate G1 and an OR gate G2 on a combinational logic path, the first predecessor information includes G1, G2 and their connection relationship.

[0048] Assume that scan chain C1(v 1，1 , v 1，2 ,…,v 1，d ) in each scanning unit, the subset of PPI and PI is R(v 1，1 ), R(v 1，2 ),…,R(v 1，d )、scan chain C2(v 2，1 , v 2，2 ,…,v 2，d ) in each scanning unit, the subset of PPI and PI is R(v 2，1 ), R(v 2，2 ),…,R(v 2，d ), then if R(v 1，1 )∩R(v 2，1 )=Ф,R(v 1，2 )∩R(v 2，2 )=Ф,…,R(v 1，d )∩R(v 2，d )=Ф, then C1 is compatible with C, otherwise they are incompatible.

[0049] For the above embodiment, in the above target test cycle, the logic unit set corresponding to the above first precursor information and the above second precursor information is compared. If the two are incompatible with each other and there is a common logic unit, for example, both contain AND gate G3, it can be determined that there is an intersection, that is, the subsequent steps are refused to be executed, that is, access is prohibited to avoid signal superposition conflicts caused by shared logic; on the contrary, if the logic units are completely independent, the intersection is empty, which means that the two scan chains are compatible with each other and there is no shared combinational logic dependency in the target test cycle, and the subsequent steps can be allowed to be executed, that is, linking the chain to be accessed to the current XOR tree. Among them, the above target test cycle can be composed of the shift cycle required for the test data to be moved into the scan chain and the capture cycle of the response of the capture circuit in the single fixed-type fault test scenario. In the jump delay fault test scenario, it can be composed of the shift cycle required for the test data to be moved into the scan chain, the launch cycle required to trigger the signal jump, and the capture cycle. Clearly, the above logic cell intersection determination mechanism can effectively prevent signal contention from masking real faults after merging scan chains with shared combinational logic, thereby improving test coverage. Furthermore, by incorporating the timing constraints of the target test cycle, it ensures that intersection analysis focuses solely on logic paths relevant to the current test, avoiding the redundant limitations of static analysis. For example, in test cycle T1, the predecessor logic of scan chains C and D has no intersection, allowing the merge. However, in cycle T2, if their predecessor logic adds a new shared cell, the merge is dynamically rejected, ensuring independent and reliable compression results for each cycle.

[0050] As mentioned above, the above target test can be further set to different periods to adapt to the timing constraint requirements of different test scenarios.

[0051] In one embodiment, the target test is a single test cycle consisting of a shift cycle and a capture cycle. Taking a scan chain with a depth of d as an example, its target test cycle is equivalent to d Shift cycles + 1 Capture cycle. If the target scan tree set corresponding to the k target XOR sub-networks contains a scan tree consisting of multiple scan chains, its target test cycle is equivalent to k*d Shift cycles + 1 Capture cycle. At this time, the trigger precursor information of the scan chain to be connected and the scan chain that has been connected can be analyzed by intersection. If the combinational logic drive units of the two have no shared path in the same test cycle, they are determined to be compatible, otherwise they are determined to be incompatible. Figure 4 The single stuck-at fault test related circuit structure is shown on the left side of part (a), where two scan chains (v1, v2, ..., vd) and (u1, u2, ..., ud) are connected to an XOR gate, and Figure 4In the actual single stuck-at fault test circuit shown on the right side of part (a), in addition to the basic primary inputs (PIs), primary outputs (POs), and primary parallel inputs (PPIs), there are multiple such scan chain pairs, that is, the PPO (Primary Parallel Output) corresponding to the scan unit of each pair of scan chains can be connected to d different XOR gates at the same time.

[0052] On this basis, for single stuck-at fault testing, if there are multiple scan chains, for example ((v 1，1 , v 1，2 ,…,v 1，d ), (v 2，1 , v 2，2 ,…,v 2，d ),…,(v n，1 , v n，2 ,…,v n，d )) are connected to the same XOR tree and require the trigger inputs of the corresponding positions of each scan chain, such as v 1，1 , v 2，1 ,…,v n，1 The subsequent groups with the same position do not have the same combinational predecessors in the circuit combinational logic. This ensures that the signal paths of each scan chain are relatively independent during the test process, avoiding confusion in test results caused by the same combinational predecessors, thereby more accurately detecting single stuck-at faults.

[0053] In another embodiment, the target test cycle is a continuous test cycle consisting of a shift cycle, a launch cycle, and a capture cycle. Taking a scan chain with a depth of d as an example, its target test cycle is equivalent to d Shift cycles + 1 Launch cycle + 1 Capture cycle. If the target scan tree set corresponding to the k target XOR sub-networks contains a scan tree composed of multiple scan chains, its target test cycle is equivalent to k*d Shift cycles + 1 Launch cycle + 1 Capture cycle, further expanding the intersection determination range of the predecessor information. If there is a shared unit in the combinational logic path of the two within the continuous cycle, it is determined to be incompatible. Figure 4 The DFT (Design for Testability) structure of the transition delay fault test (Launch-Off-Capture, LOC) under the two-frame circuit model is shown on the left side of (b). The two scan chain outputs are connected to an XOR gate, specifically (v1, u1), (v2, u2), ..., (vd, ud) are connected to an XOR gate input respectively. Among them, for the above two-frame circuit model, Figure 4In the actual transition delay fault test circuit shown on the right side of part (b), each frame circuit is the combinational logic of the circuit under test. In the first frame circuit, each scan flip-flop input PPO is directly connected to the corresponding output PPI of that flip-flop. At the input end of the first frame, each PPI directly fans out to the inputs of multiple flip-flops, and these scan flip-flops are divided into the same group when constructing the scan tree. In summary, in the LOC transition delay fault test circuit, the PPIs corresponding to the flip-flops in the same scan flip-flop group in the scan tree are driven by the same input signal in the first frame circuit, further clarifying the signal drive and circuit connection relationship of the test circuit to adapt to the transition delay fault test requirements.

[0054] On this basis, for LOC transition delay fault, an XOR tree is constructed based on the two-frame circuit model. 1，1 , v 1，2 ,…,v 1，d ), (v 2，1 , v 2，2 ,…,v 2，d ),…,(v n，1 , v n，2 ,…,v n，d ))When connected to the same XOR tree, the trigger input of the corresponding position of each scan chain is required, such as v 1，1 , v 2，1 ,…,v n，1 On this basis, and for subsequent groups with the same position, there are no identical combined predecessors in the two-frame circuit model. This is because transition delay fault testing needs to consider the transmission and changes of signals in the two-frame circuit. Ensuring the independence of the signal paths of each scan chain helps accurately detect transition delay faults.

[0055] Step S306 : If any scan chain to be connected is compatible with each connected scan chain in any XOR tree in the target XOR sub-network, the scan chain to be connected is connected to any XOR tree.

[0056] After passing compatibility verification, the scan chain to be connected can be dynamically assigned to any XOR tree in the target XOR subnet. This XOR tree can follow corresponding scan chain assignment rules, such as randomly selecting an XOR tree or selecting the XOR tree with the least load. For example, assigning the scan chain to the XOR tree with the least load can dynamically adjust the load threshold by monitoring the number of connected chains and signal latency in real time. For example, if XOR tree X currently has five connected scan chains and the latency is below a preset threshold, the scan chain to be connected will be assigned to XOR tree X first.

[0057] The above only lists the scan chain access method under ideal circumstances. In fact, dynamic XOR tree expansion and optimized access can be achieved based on the compatibility results, the number of XOR trees for the XOR sub-network, and the scan output threshold.

[0058] For example, if the scan chain to be connected is incompatible with every connected scan chain in the target XOR subnetwork, and the number of XOR trees in the target XOR subnetwork is less than the scan output threshold, a new XOR tree can be constructed for the scan chain to be connected. Of course, if the number of XOR trees in the target XOR subnetwork is greater than or equal to the scan output threshold, the scan chain to be connected can be connected to an XOR tree with a relatively smaller number of intersections to minimize the impact of logical conflicts on the compression results. In other words, the former isolates incompatible chains by adding new XOR trees to prevent fault responses from being masked; the latter reduces the probability of conflicts by minimizing the number of intersections when hardware resources are limited.

[0059] The following combination Figures 5-7 , the XOR subnetwork in a test response compressor and the architecture of the XOR tree and scan chain therein are discussed.

[0060] First, if Figure 5 As shown in FIG, as an integrated circuit test system for a single stuck-at fault test device, the test response compressor can have k XOR sub-networks, and the multiple XOR sub-networks output compressed response signals through the multiplexer MUX respectively. All scan trees driven by each clock signal construct an XOR sub-network. Each XOR sub-network contains multiple scan outputs, namely O1, O2, ..., O k , then the above test response compressor can be considered to contain: Omax=max(O1,O2,…,O k ) outputs, and Omax outputs are connected to the Automatic Test Equipment (ATE). The first output of each XOR sub-network is connected to the input of the first multiplexer, the second outputs of the k XOR sub-networks are connected to the input of the second multiplexer, and the last output is connected to the kth multiplexer. Of course, the multiplexers at the end may not have k inputs. Among them, at most k multiplexers in the above-mentioned test response compressor can have the same control signal as the DMUX used at the test stimulus compression structure end, that is, when the test stimulus signal is placed in the scan tree subset activated by the clock signal, the response compressor output is open to the corresponding response compressor sub-network. In addition, the scan chain (f 1，1 , f 1，2 ,…,f 1，d ), (f 2，1 , f 2，2 ,…,f 2，d ),…,(fw，1 , f w，2 ,…,f w，d ) can meet the following conditions: Scan unit group (f 1，1 , f 2，1 ,…,f w，1 ) In a single frame, the combination circuit does not contain the same combination predecessor, (f 1，2 , f 2，2 ,…,f w，2 ) does not contain the same combinational predecessor in the combinational circuit of a single frame, ..., the scan trigger group in the combinational circuit of a single frame (f 1，d , f 2，d ,…,f w，d ) do not contain the same combination of predecessors. If any node c in the two scan chains 1，1 and c 2，1 , c 1，2 and c 2，2 ,…,c 1，l and c 2，l The two scan chains are considered compatible if they do not have the same predecessor in a single-frame combinational logic circuit. The two scan chains can be connected to the same XOR gate.

[0061] Based on this, Figure 6 An embodiment of a 4-output test response compressor is shown. The figure specifically contains 8 XOR sub-networks 1 to 8 driven by different gated clocks. Except for sub-networks 2 and 7, the other 6 XOR sub-networks all contain 4 scan outputs. At the same time, for the four scan outputs shown in the figure, the first three multiplexers (MUX) are connected to 8 outputs, and the last one is connected to 6 inputs.

[0062] against Figure 6 Each XOR sub-network in Figure 7 As shown, multiple scan chains C1 to C2 in the same scan tree set can be received. 18 , where it is assumed that no XOR tree exists when the scan chain C1 is connected to the target XOR sub-network, so a new XOR tree can be created and connected to it. If C1 is incompatible with another scan chain C2 to be connected, then C 2可以Placed in the second XOR tree. C3 is incompatible with C1 and C2, so it is placed in the third XOR tree. Scan chain C4 is compatible with C1 and is therefore placed in the first XOR tree. C5 is incompatible with C1 or C4, but is compatible with C4, so it is placed in the second XOR tree. C6 is incompatible with C1 or C4, and is also incompatible with C2 or C5, but is compatible with C3, so it is placed in the third XOR tree. C7 is compatible with C1 and C4, and C8 is also compatible with C1, C4, and C7, so C7 and C8 are both placed in the first XOR tree. C9 is incompatible with the first XOR tree, but is compatible with C2 and C5, so it is placed in the second XOR tree. C 10 It is incompatible with the first XOR tree and the second XOR tree, but it is compatible with C3 and C6, so it is placed in the third XOR tree. 11 It is compatible with C1, C4, C7, and C8, and is therefore placed in the first XOR tree. 12 and C1, C4, C7, C8, and C 11 Compatible, so it is placed in the first XOR tree. Scan chain C 13 It is incompatible with the first XOR tree, but compatible with the second XOR tree, so it is placed in the second XOR tree. 14 Incompatible with the first XOR tree, but compatible with C3, C6, and C 10 compatible, and thus placed into the third XOR tree. C 15 It is compatible with the first XOR tree and is therefore placed in the first XOR tree. 16 The same can be incorporated into the first XOR tree. Scan chain C 17 It is incompatible with a scan chain in the second XOR tree and is also incompatible with the third XOR tree. 17 Put it into the fourth XOR tree. C 18 Incompatible with two, three, and four XOR trees, but compatible with C 17 is compatible, and is therefore placed into the fourth XOR tree. Figure 7 All scan chains in, or Figure 6 The single XOR sub-network in is formally constructed and can be used to compress the test response signal and then output the output results SO1~SO4 of each XOR tree.

[0063] In addition, after the scan chain to be connected is successfully linked to the target XOR tree, the number of scan chains connected to the XOR tree can be monitored in real time, and the memory recycling mechanism can be triggered to avoid the waste of hardware resources due to the long-term occupation of redundant memory. Specifically, it means that when the above-mentioned scan chain to be connected is connected to any of the above-mentioned XOR trees, and the number of scan chains of any of the above-mentioned XOR trees is equal to the scan chain threshold (Maximum Chains per Network, MCN, that is, the maximum number of scan chains allowed for each XOR subnetwork), the memory occupied by the scan trigger in any of the above-mentioned XOR trees when constructing the XOR tree can be released, wherein the scan chain threshold can be obtained based on preset rules or manual input, and the value of the scan output port number (Number of Scan Outputs, NSO) of the above-mentioned response compressor is similar, and this is not restricted in this specification.

[0064] It can be understood that in the aforementioned embodiments, the scan chain in which each scan flip-flop machine resides only calculates structural information once to arrive at the PPI and PI set for each scan flip-flop, thereby reducing the CPU time required to construct the test response compressor. Furthermore, after each XOR tree is constructed, all information stored in the associated scan flip-flops is fully released, reducing memory overhead. Because the scan chain is divided into multiple subsets based on the scan tree, the memory consumption required to store the scan unit structural information at any given time can be efficiently controlled.

[0065] Figure 8 This is a schematic structural diagram of an electronic device in an exemplary embodiment. Figure 8 At the hardware level, the electronic device includes a processor 802, an internal bus 810, a network interface 804, memory 806, and non-volatile storage 808, and may also include other necessary hardware. The processor reads the corresponding computer program from the non-volatile storage into the internal memory and then runs it, forming a risk code detection device at the logical level. Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware. In other words, the execution of the following processing flow is not limited to individual logic units and can also be hardware or logic devices.

[0066] Figure 9 A block diagram of a test response compression device is shown in an embodiment of the present invention. Figure 9 , the device can be used for Figure 8 In the device shown, to implement the technical solution of the present invention, the device includes:

[0067] a signal receiving unit 902 configured to receive a circuit response signal output by a scan forest; the scan forest comprising multiple scan tree sets, each scan tree set driven by a different clock signal, each scan tree set comprising multiple scan trees, each scan tree comprising multiple scan chains, each scan chain comprising multiple cascaded scan flip-flops, each scan flip-flop being derived from the combinational logic of the circuit under test;

[0068] a compatibility determination unit 904 configured to select any scan chain to be connected from the target scan tree set, and determine the compatibility of the scan chain to be connected with an already connected scan chain based on the predecessor information of the corresponding scan trigger, wherein the already connected scan chain is connected to a target XOR sub-network corresponding to the target scan tree set, wherein the target XOR sub-network includes at least one XOR tree;

[0069] The scan chain adding unit 906 is configured to add the scan chain to be added to any XOR tree in the target XOR sub-network if the scan chain to be added is compatible with each scan chain already added to the XOR tree.

[0070] Optionally, the compatibility determination unit 904 is specifically configured to:

[0071] Obtaining first precursor information of a first scan trigger to be connected to the scan chain, and second precursor information of a second scan trigger already connected to the scan chain, wherein the first precursor information is used to characterize a logic unit connected to the first scan trigger through the combinational logic, and the second precursor information is used to characterize a logic unit connected to the second scan trigger through the combinational logic;

[0072] Determine an intersection of logic units corresponding to the first precursor information and the second precursor information, respectively, in a target test cycle;

[0073] When the intersection is empty, determining that the scan chain to be connected is compatible with the scan chain already connected;

[0074] When the intersection is not empty, it is determined that the scan chain to be connected is incompatible with the scan chain already connected.

[0075] Optionally, the target test cycle is a single test cycle or two consecutive test cycles.

[0076] Optionally, when the scan chain to be accessed is incompatible with each of the scan chains already connected in the target XOR sub-network, and the number of XOR trees in the target XOR sub-network is less than a scan output threshold, constructing a new XOR tree for access by the scan chain to be accessed;

[0077] When the scan chain to be accessed is incompatible with each of the already accessed scan chains in the target XOR sub-network, and the number of XOR trees in the target XOR sub-network is greater than or equal to a scan output threshold, the scan chain to be accessed is accessed into an XOR tree with a relatively smaller number of corresponding intersections.

[0078] Optionally, the device further includes:

[0079] A memory release unit is used to release the memory occupied by the scan trigger in any XOR tree when constructing the XOR tree when the scan chain to be connected is connected to any XOR tree and the number of scan chains of any XOR tree is equal to the scan chain threshold.

[0080] Optionally, the circuit response signal is an output signal generated by the scanning forest based on a received test excitation signal, and the test excitation signal is generated by a decompressor based on a linear feedback shift register, and the decompressor includes an additional shift register for controlling the linear feedback shift register, and a binary tree composed of multiple AND gates.

[0081] Optionally, the input end of each AND gate is connected to the linear feedback shift register and the additional shift register respectively, the output end of each AND gate is connected to the linear feedback shift register, and is connected to a two-input multiplexer together with the scan input end of the preset test seed to generate the test excitation signal.

[0082] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0083] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0084] Based on the same concept as the above method, this specification also provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor implements the steps of the method described in any of the above embodiments by running the executable instructions.

[0085] Based on the same concept as the above method, this specification also provides a computer-readable storage medium on which computer instructions are stored. When the instructions are executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0086] Based on the same concept as the above method, this specification also provides a computer program product, including a computer program / instruction, which implements the steps of the method described in any of the above embodiments when executed by a processor.

[0087] Embodiments of the subject matter and functional operations described in this specification may be implemented in the following: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier to be executed by a data processing device or to control the operation of the data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information and transmit it to a suitable receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0088] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform the corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0089] Computers suitable for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or the computer will be operably coupled to such mass storage devices to receive data from them or to transmit data to them, or both. However, a computer does not necessarily have such devices. In addition, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0090] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0091] Although this specification includes many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of specific embodiments of specific inventions. Certain features described in multiple embodiments within this specification may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may work in certain combinations as described above and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may point to a sub-combination or a variation of the sub-combination.

[0092] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these operations be performed in the particular order shown or performed sequentially, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0093] Thus, specific embodiments of the subject matter have been described. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0094] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A test response compression method, characterized in that: The method comprises: receiving a circuit response signal output by a scan forest; the scan forest comprising a plurality of scan tree sets, each scan tree set being driven by a different clock signal, each scan tree set comprising a plurality of scan trees, each scan tree comprising a plurality of scan chains, each scan chain comprising a plurality of cascaded scan flip-flops, the scan flip-flops being derived from the combinational logic of the circuit under test; Selecting any scan chain to be connected from the target scan tree set, and determining the compatibility of the scan chain to be connected with an already connected scan chain based on the predecessor information of the corresponding scan trigger, wherein the already connected scan chain is connected to a target XOR sub-network corresponding to the target scan tree set, wherein the target XOR sub-network includes at least one XOR tree; In a case where any scan chain to be connected is compatible with each scan chain already connected in any XOR tree in the target XOR sub-network, the scan chain to be connected is connected to any XOR tree.

2. The method according to claim 1, characterized in that The determining, based on the predecessor information of the corresponding scan trigger, the compatibility of the scan chain to be connected and the scan chain already connected, includes: Obtaining first precursor information of a first scan trigger to be connected to the scan chain, and second precursor information of a second scan trigger already connected to the scan chain, wherein the first precursor information is used to characterize a logic unit connected to the first scan trigger through the combinational logic, and the second precursor information is used to characterize a logic unit connected to the second scan trigger through the combinational logic; Determine an intersection of logic units corresponding to the first precursor information and the second precursor information, respectively, in a target test cycle; When the intersection is empty, determining that the scan chain to be connected is compatible with the scan chain already connected; When the intersection is not empty, it is determined that the scan chain to be connected is incompatible with the scan chain already connected.

3. The method according to claim 2, characterized in that The target test cycle is a single test cycle consisting of a displacement cycle and a capture cycle, or a continuous test cycle consisting of a displacement cycle, a start cycle and a capture cycle.

4. The method according to claim 2, characterized in that The method further comprises: When the scan chain to be connected is incompatible with each connected scan chain in the target XOR sub-network, and the number of XOR trees in the target XOR sub-network is less than a scan output threshold, constructing a new XOR tree for the scan chain to be connected to be connected; When the scan chain to be accessed is incompatible with each of the already accessed scan chains in the target XOR sub-network, and the number of XOR trees in the target XOR sub-network is greater than or equal to a scan output threshold, the scan chain to be accessed is accessed into an XOR tree with a relatively smaller number of corresponding intersections.

5. The method according to claim 1, wherein The method further comprises: When the scan chain to be connected is connected to any XOR tree and the number of scan chains of any XOR tree is equal to the scan chain threshold, the memory occupied by the scan trigger in any XOR tree when constructing the XOR tree is released.

6. The method according to claim 1, characterized in that The circuit response signal is an output signal generated by the scanning forest based on a received test excitation signal. The test excitation signal is generated by a decompressor based on a linear feedback shift register. The decompressor includes an additional shift register for controlling the linear feedback shift register and a binary tree composed of multiple AND gates.

7. The method according to claim 6, characterized in that The input end of each AND gate is connected to the linear feedback shift register and the additional shift register respectively, the output end of each AND gate is connected to the linear feedback shift register, and is connected to a two-input multiplexer together with the scan input end of the preset test seed to generate the test excitation signal.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer program product, characterized in that The method comprises a computer program or an instruction, which implements the steps of the method according to any one of claims 1 to 7 when the computer program or the instruction is executed by a processor.

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