A pipeline divider calculation method and system with variable precision and throughput

Abstract

The present invention provides a pipeline divider calculation method and system with variable precision and throughput. The method includes: configuring divider parameters, including dividend data bit width, divisor data bit width, pipeline clock cycle number, cardinality, and quotient set; constructing a multi-stage divider unit based on the divider parameters, each stage of the divider unit including a divider calculation unit and a register unit; selecting an operating mode of the divider, including a serial mode, a pipeline parallel mode, and an iterative parallel mode; controlling the input path of each stage of the divider unit according to the selected operating mode, each stage of the divider unit generating a corresponding stage quotient value and a stage remainder, each stage of the divider unit being stored by the register unit of the stage and used as output data, until all divider units complete the calculation of the corresponding division operation task, and then outputting the final quotient value and final remainder of the corresponding division operation task. The present invention optimizes the quotient selection method and improves divider performance.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip computing, and in particular to a pipeline divider computing method and system with variable precision and throughput. Background Art

[0002] Common hardware dividers in existing general-purpose processor chips such as CPUs and GPUs, as well as digital signal processors, often use serial computation and lack a pipelined architecture. These dividers typically require multiple clock cycles to complete a full division operation, making it difficult to achieve high-throughput concurrent computations and limiting their performance in high-speed data processing scenarios. Furthermore, the output precision of existing dividers is typically fixed, making it difficult to flexibly adjust to different computing scenarios. This makes it difficult to strike a balance between computational accuracy and resource overhead, resulting in poor adaptability and flexibility. Summary of the Invention

[0003] The present invention provides a pipeline divider calculation method and system with variable precision and throughput. By optimizing a traditional hardware divider, the performance of the divider is improved. The iterative operation of the divider is expanded into multiple divider calculation units, and registers are inserted between the divider calculation units to achieve variable throughput and precision. Furthermore, by flexibly configuring the divider's operating mode, the present invention can meet the needs of division calculations in different application scenarios.

[0004] An embodiment of the present invention provides a pipeline divider calculation method with variable precision and throughput, comprising:

[0005] Configuring divider parameters, wherein the divider parameters include the dividend data bit width, the divisor data bit width, the number of pipeline clock cycles, the base number, and the quotient set of the divider;

[0006] Constructing a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, a plurality of simplified division calculation units, a quotient post-processing unit, and a ripple carry adder unit, wherein the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles, and the cardinality, and according to a derivation formula for allocating the quotient bit to the stage;

[0007] Selecting an operating mode of the divider, wherein the operating mode includes a serial mode, a pipeline parallel mode, and an iterative parallel mode;

[0008] According to the selected operating mode, the input path of the divider unit of each level is controlled, and the first-round division calculation unit and multiple simplified division calculation units of the divider unit of each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level, until all the divider units complete the calculation of the corresponding division operation task, and then output the final quotient value and final remainder of the corresponding division operation task.

[0009] Preferably, the divider parameters are set during the initialization phase of the pipeline divider calculation method, and remain unchanged during the execution of the pipeline divider calculation method after being set.

[0010] Preferably, the serial mode is such that the input data of the subsequent divider unit are all the output data of the previous divider unit, and a division operation task is completed sequentially through multiple pipeline clock cycles. The calculation accuracy of the serial mode is the data bit width of the dividend.

[0011] The pipeline parallel mode is that each level of divider unit receives the parallel input data corresponding to the level respectively, and multiple division operation tasks are completed in parallel within one pipeline clock cycle. The calculation accuracy of the pipeline parallel mode is determined according to the pipeline parallel accuracy calculation formula;

[0012] The iterative parallel mode is that the input data of the divider unit at each level are the output data of the divider unit at this level in the previous pipeline clock cycle, and multiple division operation tasks are completed in parallel within multiple pipeline clock cycles. The calculation accuracy of the iterative parallel mode is the bit width of the dividend data.

[0013] Preferably, when the operation mode is a serial mode, the first-stage divider unit is controlled to receive serial input data in the first pipeline clock cycle, the first-round division calculation unit of the first-stage divider unit calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the division operation task, and multiple simplified division calculation units respectively calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the division operation task, the first bit quotient value and all corresponding bit quotient values ​​are processed by the post-quotient processing unit of the stage to generate the stage quotient value, and the corresponding bit remainder carry term of the last simplified division calculation unit in the first-stage divider unit is processed. The bit term and the remainder sum term are processed by the ripple carry adder of this stage to generate the stage remainder of this stage. The stage quotient value and the stage remainder of this stage are both stored by the register unit of this stage and serve as the output data of the divider unit of this stage. In each subsequent pipeline clock cycle, the divider unit of the next stage sequentially receives the output data of the divider unit of the previous stage, completes the calculation of the stage quotient value and the stage remainder of this stage, until all the divider units complete the calculation of the corresponding division operation tasks, and in the last pipeline clock cycle, the divider unit of the last stage outputs the final quotient value and final remainder of a division operation task;

[0014] When the operation mode is the pipeline parallel mode, the divider unit of each level is controlled to receive the corresponding parallel input data in the same pipeline clock cycle respectively. The first round division calculation unit of the divider unit of each level parallelly calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the corresponding division operation task. The plurality of simplified division calculation units parallelly calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the corresponding division operation task. The first bit quotient value of the divider unit of each level and all the corresponding bit quotient values ​​of the level are parallelized by the first round division calculation unit. The stage quotient post-processing unit generates the stage quotient value of this stage. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in each stage of the divider unit are processed by the ripple carry adder of this stage to generate the stage remainder of this stage. The stage quotient value and the stage remainder of this stage are both stored by the register unit of this stage and serve as the output data of the divider unit of this stage. After all the divider units complete the calculation of the corresponding division operation tasks, the divider units of each stage output a final quotient value and final remainder of the corresponding division operation task.

[0015] Preferably, the formula for deriving the quotient allocation series is:

[0016]

[0017] Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

[0018] Preferably, the pipeline parallel accuracy calculation formula is:

[0019]

[0020] Where m is the number of simplified division calculation units, and Radix is ​​the radix.

[0021] Preferably, the first-round division calculation unit includes:

[0022] Divisor normalization processing, normalizing the divisor and adjusting the value of the divisor to the interval;

[0023] Alignment shift processing, shifting the dividend to the left, or shifting the received remainder carry term and remainder sum term to the left, the number of bits of the left shift being determined according to the base;

[0024] Divisor pre-shift: pre-shift the normalized divisor according to the set quotient set and cardinality;

[0025] The quotient selection process determines the first quotient value based on the normalized divisor and the partial bits of the left-shifted dividend;

[0026] Subtrahend selection processing, selecting the corresponding subtrahend according to the first quotient value;

[0027] Carry-save addition processing, inputting the selected subtrahend and the left-shifted dividend into the carry-save adder to obtain the remainder carry term and the remainder sum term used to represent the first remainder;

[0028] Quotient conversion processing, converting the first quotient value into the corresponding positive quotient value according to the real-time conversion algorithm;

[0029] Each of the simplified division calculation units includes:

[0030] Shift the remainder left, shifting the remainder carry term and the remainder sum term left, where the number of bits of the left shift is determined according to the base;

[0031] Simplify the quotient selection process and determine the corresponding bit quotient value based on the normalized divisor, the carry term and the remainder sum term after the left shift, and the quotient threshold set generated by the first round of division calculation unit;

[0032] Subtrahend selection processing, selecting the corresponding subtrahend according to the corresponding bit quotient value;

[0033] Carry-save addition processing, inputting the selected subtrahend and the shifted dividend into the carry-save adder to obtain the remainder carry term and remainder sum term used to represent the corresponding bit remainder;

[0034] The quotient conversion process performs a sign conversion on the corresponding bit quotient value according to the real-time conversion algorithm to convert the corresponding bit quotient value into a corresponding positive quotient value.

[0035] Preferably, the working mode of the first-round division calculation unit includes a first-round calculation mode and a degenerate compatibility mode;

[0036] When the divider unit is a first-stage divider unit in a serial mode, or each stage of the divider unit in a first pipeline clock cycle in an iterative parallel mode, or each stage of the divider unit in a pipeline parallel mode, and the operating mode is a first-round calculation mode, the divisor normalization processing and the divisor pre-shift function are enabled, and the alignment shift processing is to left-shift the dividend, and the number of bits of the left shift is determined according to the base number;

[0037] When the divider unit is a second-stage divider unit and a subsequent-stage divider unit in a serial mode, or a divider unit in a second pipeline clock cycle and each subsequent pipeline clock cycle in an iterative parallel mode, and the operating mode is a degenerate compatible mode, the divisor normalization processing and the divisor pre-shift function are disabled, and the alignment shift processing is to left-shift the received remainder carry term and remainder sum term, and the number of bits of the left shift is determined according to the radix;

[0038] The post-quotient processing unit includes an enabled state and a bypass state, wherein the enabled state is that the post-quotient processing unit is in an activated running state, and the bypass state is that the post-quotient processing unit is in a non-running state that does not participate in the calculation;

[0039] When the operation mode of the divider is the serial mode, the quotient post-processing unit of the last stage of the divider unit is in an enabled state, and the quotient post-processing units of the other stages of the divider unit are in a bypass state.

[0040] When the operation mode of the divider is pipeline parallel mode, the quotient post-processing unit of each level of the divider unit is in an enabled state;

[0041] When the operation mode of the divider is the iterative parallel mode, the quotient post-processing units of each stage of the divider unit in the last pipeline clock cycle are all in the enabled state, and the quotient post-processing units of each stage of the divider unit in other pipeline clock cycles are all in the bypass state.

[0042] Preferably, the number of stages of the divider unit is the number of pipeline clock cycles.

[0043] An embodiment of the present invention further provides a pipeline divider computing system with variable precision and throughput, comprising:

[0044] Configuring a divider parameter module to configure divider parameters, wherein the divider parameters include the dividend data bit width, the divisor data bit width, the number of pipeline clock cycles, the base number, and the quotient set of the divider;

[0045] Constructing a divider unit module, constructing a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit, and a ripple carry adder unit, wherein the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles, and the cardinality, and according to a derivation formula for the quotient bit allocation stage;

[0046] Configure the operation mode module to select the operation mode of the divider, wherein the operation mode includes serial mode, pipeline parallel mode and iterative parallel mode;

[0047] The execution division operation module controls the input path of the divider unit of each level according to the selected operation mode. The first-round division calculation unit and multiple simplified division calculation units of the divider unit of each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level. After all the divider units complete the calculation of the corresponding division operation task, the final quotient value and final remainder of the corresponding division operation task are output.

[0048] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0049] The embodiment of the present invention provides a pipeline divider calculation method and system with variable precision and throughput, the method comprising: configuring divider parameters, wherein the divider parameters include the dividend data bit width, divisor data bit width, pipeline clock cycle number, cardinality and quotient set of the divider; constructing a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit and a ripple carry adder unit, wherein the number of the simplified division calculation units is determined based on the dividend data bit width, pipeline clock cycle number and cardinality, and according to a quotient bit allocation stage derivation formula; selecting an operating mode of the divider, wherein the operating mode includes a serial mode, a pipeline parallel mode and a register unit. Iterative parallel mode; according to the selected operating mode, the input path of the divider unit of each level is controlled, and the first-round division calculation unit and multiple simplified division calculation units of the divider unit of each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level, until all the divider units complete the calculation of the corresponding division operation task, and then output the final quotient value and final remainder of the corresponding division operation task. The present invention configures divider parameters and determines the number of simplified division calculation units according to the quotient bit allocation series derivation formula. It can flexibly adjust the configuration of the divider calculation units according to different precision and throughput requirements, avoid resource waste, and ensure the coordinated matching of the divider output precision and structural efficiency.

[0050] Furthermore, by setting different operating modes, the divider can flexibly adapt to different usage scenarios and differentiated requirements for precision and throughput. Serial mode ensures high precision, pipeline parallel mode improves throughput, and iterative parallel mode enables high-precision parallel processing of multiple tasks, meeting the computing power requirements of different application scenarios and improving the adaptability and scalability of the overall computing architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0052] Figure 1A flow chart of a calculation method for a pipeline divider with variable precision and throughput provided by one embodiment of the present invention;

[0053] Figure 2 A schematic diagram of the structure of multiple simplified division calculation units in serial mode provided by one embodiment of the present invention;

[0054] Figure 3 A schematic flow chart of a calculation method for a pipeline divider with variable precision and throughput provided by another embodiment of the present invention;

[0055] Figure 4 A schematic diagram of the structure of multiple simplified division calculation units in a pipeline parallel mode provided by one embodiment of the present invention;

[0056] Figure 5 A schematic flow chart of a calculation method for a pipeline divider with variable precision and throughput provided by yet another embodiment of the present invention;

[0057] Figure 6 A schematic diagram of the structure of multiple simplified division calculation units in an iterative parallel mode provided by one embodiment of the present invention;

[0058] Figure 7 A schematic structural diagram of a divider calculation unit provided in one embodiment of the present invention;

[0059] Figure 8 A schematic diagram of a module of a pipeline divider computing system with variable precision and throughput provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0061] The technical solution of the present invention is described in detail below with reference to specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0062] To address the challenges of existing technologies, embodiments of the present invention provide a pipeline divider calculation method and system with variable precision and throughput. By optimizing traditional hardware dividers, the performance of the divider is improved. The iterative operations of the divider are expanded into multiple divider calculation units, and registers are inserted between the divider calculation units to achieve variable throughput and precision. Furthermore, the present invention flexibly configures operating modes to meet the needs of division calculations in various application scenarios.

[0063] Example 1: Figure 1 A flow chart of a pipeline divider calculation method with variable precision and throughput provided by an embodiment of the present invention. Figure 1 , an embodiment of the present invention provides a pipeline divider calculation method with variable precision and throughput, comprising:

[0064] Step S101: configuring divider parameters, wherein the divider parameters include the dividend data bit width, divisor data bit width, pipeline clock cycle number, base number and quotient set of the divider.

[0065] In this embodiment, the divider parameters include the divider's dividend data bit width (AW), divisor data bit width (BW), pipeline clock cycle number (Cycle), radix (Radix) and quotient set (such as {-r, -(r-1),…, -1, 0, 1,…, (r-1), r}).

[0066] The divider parameters are set during the initialization phase of the pipeline divider calculation method, and remain unchanged during the execution of the pipeline divider calculation method after being set.

[0067] Step S102: construct a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit and a ripple carry adder unit, and the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles and the cardinality, and according to the quotient bit allocation stage derivation formula.

[0068] In this embodiment, the number of stages of the divider unit is the number of pipeline clock cycles (CYCLE).

[0069] The formula for deriving the quotient allocation series is:

[0070]

[0071] Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

[0072] It should be noted that in the derivation formula of the quotient distribution series, It is expressed as the number of quotient bits that each divider calculation unit needs to output, Indicates the number of quotient bits output in one iteration in each divider calculation unit. For example, AW=16, CYCLE=4, Radix=4, in serial mode, the calculation accuracy is 16 bits, and the final output result needs to go through 4 pipeline clock cycles, with a radix of 4. The number of divider unit stages is equal to the pipeline clock cycle, which is 4. The number of quotient bits that each level of divider unit needs to output is 4 (16 / 4=4). In each level of divider unit, the number of quotient bits generated in each iteration is , each level of division operation unit iterates 2 times (4 / 2=2), then according to the formula for deriving the number of stages allocated by the quotient, each level of the divider unit is equipped with 1 first-round division calculation unit (srt_first_round) and 1 simplified division calculation unit (srt_lite).

[0073] Step S103: Selecting the operating mode of the divider to be the serial mode.

[0074] In this embodiment, the serial mode is that the input data of the subsequent stage divider unit are all the output data of the previous stage divider unit, and a division operation task is completed sequentially through multiple pipeline clock cycles. The calculation accuracy of the serial mode is the dividend data bit width (AW).

[0075] Step S104: When the operation mode is the serial mode, the first-stage divider unit is controlled to receive serial input data in the first pipeline clock cycle, the first-round division calculation unit of the first-stage divider unit calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the division operation task, and multiple simplified division calculation units respectively calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the division operation task, the first bit quotient value and all corresponding bit quotient values ​​are processed by the post-quotient processing unit of the stage to generate the stage quotient value, and the corresponding bit remainder of the last simplified division calculation unit in the first-stage divider unit is calculated. The carry term and the remainder sum term are processed by the ripple carry adder of this stage to generate the stage remainder of this stage. The stage quotient value and the stage remainder of this stage are both stored by the register unit of this stage and serve as the output data of the divider unit of this stage. In each subsequent pipeline clock cycle, the divider unit of the next stage receives the output data of the divider unit of the previous stage in turn to complete the calculation of the stage quotient value and the stage remainder of this stage, until all the divider units complete the calculation of the corresponding division operation tasks, and the divider unit of the last stage outputs the final quotient value and final remainder of a division operation task in the last pipeline clock cycle.

[0076] In this embodiment, the first-round division calculation unit includes:

[0077] Normalize the divisor and adjust the divisor value to the range .

[0078] The alignment shift process is to left-shift the dividend, or to left-shift the carry term of the remainder and the remainder sum term. The number of bits of the left shift is determined according to the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0079] Divisor pre-shifting performs pre-shifting on the normalized divisor according to the quotient set and radix. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, the output of the pre-shifted divisor d is {-2d, -d, 0, d, 2d}.

[0080] The quotient selection process determines the first quotient value based on the normalized divisor and the partial bits of the left-shifted dividend. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, when r = 2, r is the maximum value of the current quotient set. Based on the normalized divisor d, the corresponding quotient thresholds {th_d, …, th_rd} are decoded. The absolute value of the partial bits of the left-shifted dividend z is compared with {th_d, …, th_rd} to determine the first quotient value. If |z| >= th_2d, the first quotient value q0 = 2. If |z| >= th_1d, the first quotient value q0 = 1. Otherwise, the first quotient value q0 = 0. If z < 0, the first quotient value q0 is negated.

[0081] The subtrahend selection process selects the corresponding subtrahend based on the first quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q = -1, the subtrahend value is d.

[0082] In the carry-save addition process, the selected subtrahend and the left-shifted dividend z are input into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the first-order remainder.

[0083] The quotient conversion process converts the first quotient value into the corresponding positive quotient value according to the real-time conversion algorithm.

[0084] After the first round of division calculation unit (srt_first_round) calculates the first quotient value and the remainder carry term and remainder sum term of the first remainder, it passes them to the first reduced division calculation unit (srt0_lite) for the next step of processing.

[0085] Each of the simplified division calculation units includes:

[0086] The remainder is shifted left, and the carry term and the remainder sum term are shifted left. The number of bits of the left shift is determined by the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0087] The simplified quotient selection process determines the corresponding bitwise quotient value based on the normalized divisor d, the carry term v of the left-shifted remainder, the remainder sum term s, and the quotient threshold set generated by the first-round division calculation unit. In terms of hardware design, the simplified quotient selection process of the streamlined division calculation unit reduces the quotient selection circuitry of the first-round division calculation unit by one level.

[0088] The subtrahend selection process selects the corresponding subtrahend according to the corresponding bit quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q=-1, the value of the subtrahend is d.

[0089] In the carry-save addition process, the selected subtrahend and the shifted dividend z are input into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the corresponding bit remainder.

[0090] The quotient conversion process performs a sign conversion on the corresponding bit quotient value according to the real-time conversion algorithm to convert the corresponding bit quotient value into a corresponding positive quotient value.

[0091] After each simplified division calculation unit (srt_lite) completes the calculation, the corresponding quotient value, the remainder carry term, and the remainder sum term are passed to the next simplified division calculation unit (srt_lite) for further processing. After all m simplified division calculation units have completed calculations, the quotient value for the first digit and the m quotient values ​​for the corresponding digits of that stage are processed by the quotient post-processing unit to obtain the stage-by-stage quotient value. The remainder carry term and remainder sum term of the mth simplified division calculation unit are processed by the ripple carry adder unit to obtain the stage-by-stage remainder calculation.

[0092] The quotient post-processing unit shifts the first quotient value calculated by the first-round division calculation unit (srt_first_round) and the m corresponding quotient values ​​calculated by the m simplified division calculation units (srt_lite) to obtain the stage quotient value of this level.

[0093] The ripple carry adder unit adds the corresponding remainder bit item v and the remainder sum item s calculated by the m-th simplified division calculation unit to obtain the stage remainder of this level.

[0094] At this point, the calculation of the divider unit of this stage is completed, and the stage-by-stage quotient value and the stage-by-stage remainder of this stage are stored by the register unit of this stage and serve as output data of the divider unit of this stage.

[0095] In serial mode, in the next pipeline clock cycle, the selector of the next-level divider unit selects the output data of the previous-level divider unit and passes it to the first-round division calculation unit of the divider calculation unit of this level for further processing.

[0096] The working modes of the first-round division calculation unit include a first-round calculation mode and a degenerate compatibility mode.

[0097] When the divider unit is a first-stage divider unit in serial mode and the working mode is a first-round calculation mode, the divisor normalization processing and the divisor pre-shift function are enabled, and the alignment shift processing is to left-shift the dividend, and the number of bits of the left shift is determined according to the base.

[0098] When the divider unit is the second-stage divider unit in serial mode and the working mode of the subsequent-stage divider unit is the degenerate compatible mode, the divisor normalization processing and the divisor pre-shift function are turned off, and the alignment shift processing is to left-shift the received remainder carry term and remainder sum term, and the number of bits of the left shift is determined according to the base.

[0099] The post-quotient processing unit includes an enabled state and a bypass state. The enabled state indicates that the post-quotient processing unit is in an active operating state, and the bypass state indicates that the post-quotient processing unit is in a non-operating state and does not participate in the calculation. When the operating mode of the divider is a serial mode, the post-quotient processing unit of the last stage of the divider unit is in the enabled state, and the post-quotient processing units of the divider units of the other stages are all in the bypass state.

[0100] After all the divider units complete the calculation of the corresponding division operation tasks, the CYCLE-th level divider unit outputs the final quotient and final remainder of a division operation task in the CYCLE-th pipeline clock cycle.

[0101] In serial mode, a division operation task is completed in CYCLE pipeline clock cycles, and the calculation accuracy of the serial mode is the data bit width of the dividend (AW).

[0102] Figure 2 A schematic diagram of the structure of multiple simplified division calculation units in serial mode provided by one embodiment of the present invention. Figure 2 , the structure of multiple reduced division calculation units in serial mode includes:

[0103] In this embodiment, the multi-stage divider unit is configured according to hardware parameters and includes a CYCLE-stage divider unit. Each stage of the divider unit includes a selector, a divider calculation unit, and a register unit, wherein:

[0104] The selector is used to determine the input path of the divider unit in that stage based on the selected operating mode. When the operating mode is serial mode, the selector of the first-stage divider unit selects the serial input data as the input data of that stage. The selector of each subsequent stage of divider unit selects the output data of the previous stage of divider unit as the input data of that stage.

[0105] The divider calculation unit is used to calculate the stage-by-stage quotient value and the stage-by-stage remainder of the stage.

[0106] The register unit is used to receive and store the stage-specific quotient value and the stage-specific remainder of the stage, and use them as output data of the divider unit of the stage.

[0107] In serial mode, a division operation task passes through the CYCLE-level divider unit. Each level of the divider unit includes a first-round division calculation unit, m simplified division calculation units, quotient post-processing units and ripple carry adder units. Each level of the divider unit calculates within one pipeline clock cycle. The quotient value of the bit.

[0108] During the first pipeline clock cycle, the first-stage divider unit receives serial input data and calculates the stage-by-stage quotient and remainder for that stage. Both the stage-by-stage quotient and the stage-by-stage remainder are stored by the register unit for that stage and serve as the output data of the divider unit for that stage. In each subsequent pipeline clock cycle, each stage divider unit receives the output data of the previous stage divider unit and continues to calculate the division task until the division task is completed. Therefore, the serial mode completes all quotient and remainder calculations for a division task within CYCLE consecutive pipeline clock cycles, with a calculation accuracy equal to the dividend data bit width (AW).

[0109] Serial mode is suitable for applications where serial input data is required and high computational accuracy is crucial. While ensuring computational accuracy, this mode enables all dividers in the pipeline to operate continuously, avoiding idle computing resources and improving overall computational efficiency. Compared to pipeline parallel mode, serial mode offers higher computational accuracy. Compared to iterative parallel mode, its output can be pipelined, making it more suitable for real-time digital signal processing in fields such as image processing and communications.

[0110] Example 2: Figure 3 A flow chart of a pipeline divider calculation method with variable precision and throughput provided by another embodiment of the present invention. Figure 3 , an embodiment of the present invention provides a pipeline divider calculation method with variable precision and throughput, comprising:

[0111] Step S201: configuring divider parameters, wherein the divider parameters include the dividend data bit width, divisor data bit width, pipeline clock cycle number, base number and quotient set of the divider.

[0112] In this embodiment, the divider parameters include the divider's dividend data bit width (AW), divisor data bit width (BW), pipeline clock cycle number (Cycle), radix (Radix) and quotient set (such as {-r, -(r-1),…, -1, 0, 1,…, (r-1), r}).

[0113] The divider parameters are set during the initialization phase of the pipeline divider calculation method, and remain unchanged during the execution of the pipeline divider calculation method after being set.

[0114] Step S202: construct a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit and a ripple carry adder unit, and the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles and the cardinality, and according to the quotient bit allocation stage derivation formula.

[0115] In this embodiment, the number of stages of the divider unit is the number of pipeline clock cycles (CYCLE).

[0116] The formula for deriving the quotient allocation series is:

[0117]

[0118] Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

[0119] Step S203: Selecting the operation mode of the divider to be the pipeline parallel mode.

[0120] In this embodiment, the pipeline parallel mode is that each level of divider unit receives the parallel input data corresponding to the level respectively, and multiple division operation tasks are completed in parallel within one pipeline clock cycle. The calculation accuracy of the pipeline parallel mode is determined according to the pipeline parallel accuracy calculation formula.

[0121] The pipeline parallel accuracy calculation formula is:

[0122]

[0123] Where m is the number of simplified division calculation units, and Radix is ​​the radix.

[0124] Step S204: When the operation mode is the pipeline parallel mode, the divider units at each level are controlled to receive corresponding parallel input data in the same pipeline clock cycle. The first round division calculation unit of the divider unit at each level parallelly calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the corresponding division operation task. The plurality of simplified division calculation units parallelly calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the corresponding division operation task. The first bit quotient value of the divider unit at each level and all corresponding bit quotients of the level are parallelized. The value is processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in each level of the divider unit are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level. After all the divider units complete the calculation of the corresponding division operation tasks, the divider units of each level output a final quotient value and a final remainder of the corresponding division operation task.

[0125] In this embodiment, the first-round division calculation unit includes:

[0126] Normalize the divisor and adjust the divisor value to the range .

[0127] The alignment shift process is to left-shift the dividend, or to left-shift the carry term of the remainder and the remainder sum term. The number of bits of the left shift is determined according to the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0128] Divisor pre-shifting performs pre-shifting on the normalized divisor according to the quotient set and radix. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, the output of the pre-shifted divisor d is {-2d, -d, 0, d, 2d}.

[0129] The quotient selection process determines the first quotient value based on the normalized divisor and the partial bits of the left-shifted dividend. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, when r = 2, r is the maximum value of the current quotient set. Based on the normalized divisor d, the corresponding quotient thresholds {th_d, …, th_rd} are decoded. The absolute value of the partial bits of the left-shifted dividend z is compared with {th_d, …, th_rd} to determine the first quotient value. If |z| >= th_2d, the first quotient value q0 = 2. If |z| >= th_1d, the first quotient value q0 = 1. Otherwise, the first quotient value q0 = 0. If z < 0, the first quotient value q0 is negated.

[0130] The subtrahend selection process selects the corresponding subtrahend based on the first quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q = -1, the subtrahend value is d.

[0131] In the carry-save addition process, the selected subtrahend and the left-shifted dividend z are input into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the first-order remainder.

[0132] The quotient conversion process converts the first quotient value into the corresponding positive quotient value according to the real-time conversion algorithm.

[0133] After the first round of division calculation unit (srt_first_round) calculates the first quotient value and the remainder carry term and remainder sum term of the first remainder, it passes them to the first reduced division calculation unit (srt0_lite) for the next step of processing.

[0134] Each of the simplified division calculation units includes:

[0135] The remainder is shifted left, and the carry term and the remainder sum term are shifted left. The number of bits of the left shift is determined by the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0136] The simplified quotient selection process determines the corresponding bitwise quotient value based on the normalized divisor d, the carry term v of the left-shifted remainder, the remainder sum term s, and the quotient threshold set generated by the first-round division calculation unit. In terms of hardware design, the simplified quotient selection process of the streamlined division calculation unit reduces the quotient selection circuitry of the first-round division calculation unit by one level.

[0137] The subtrahend selection process selects the corresponding subtrahend according to the corresponding bit quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q=-1, the value of the subtrahend is d.

[0138] Carry-save addition processing, inputting the selected subtrahend and the shifted dividend z into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the corresponding bit remainder;

[0139] The quotient conversion process performs a sign conversion on the corresponding bit quotient value according to the real-time conversion algorithm to convert the corresponding bit quotient value into a corresponding positive quotient value.

[0140] After each simplified division calculation unit (srt_lite) in each stage of the divider completes the corresponding quotient value, the remainder carry term, and the remainder sum term, the values ​​are passed to the next simplified division calculation unit (srt_lite) for further processing. After all m simplified division calculation units have completed their calculations, the first quotient value and the mth quotient values ​​are processed by the quotient post-processing unit to obtain the stage-by-stage quotient value for that stage. The corresponding remainder carry term and remainder sum term of the mth simplified division calculation unit are processed by the ripple carry adder unit to obtain the stage-by-stage remainder calculation for that stage.

[0141] The quotient post-processing unit shifts the first quotient value calculated by the first-round division calculation unit (srt_first_round) and the m corresponding quotient values ​​calculated by the m simplified division calculation units (srt_lite) to obtain the stage quotient value of this level.

[0142] The ripple carry adder unit adds the corresponding remainder bit item v and the remainder sum item s calculated by the m-th simplified division calculation unit to obtain the stage remainder of this level.

[0143] At this point, the calculation of the divider unit of this stage is completed, and the stage-by-stage quotient value and the stage-by-stage remainder of this stage are stored by the register unit of this stage and serve as output data of the divider unit of this stage.

[0144] The first-round division calculation unit has an operating mode including a first-round calculation mode and a degenerate compatibility mode. When the divider unit is a divider unit at each stage in a pipeline parallel mode, the operating mode is the first-round calculation mode, the divisor normalization processing and the divisor pre-shift function are enabled, and the alignment shift processing is to left-shift the dividend, and the number of bits of the left shift is determined according to the base.

[0145] The post-quotient processing unit includes an enabled state and a bypass state. The enabled state indicates that the post-quotient processing unit is in an active operating state, and the bypass state indicates that the post-quotient processing unit is in a non-operating state and does not participate in the calculation. When the operating mode of the divider is pipeline parallel mode, the post-quotient processing unit of each stage of the divider unit is in the enabled state.

[0146] After the CYCLE-level divider units complete the calculation of the corresponding division operation tasks in parallel within the same pipeline clock cycle, each level of the divider units outputs a final quotient value and a final remainder of the corresponding division operation task.

[0147] In the pipeline parallel mode, CYCLE division operation tasks are calculated and completed within the same pipeline clock cycle. The calculation accuracy of the pipeline parallel mode is calculated by the pipeline parallel accuracy calculation formula.

[0148] Figure 4 A schematic diagram of the structure of multiple simplified division calculation units in a pipeline parallel mode provided by an embodiment of the present invention. Figure 4 , the structure of multiple simplified division calculation units in pipeline parallel mode includes:

[0149] In this embodiment, the multi-stage divider unit is configured according to hardware parameters and includes a CYCLE-stage divider unit. Each stage of the divider unit includes a selector, a divider calculation unit, and a register unit, wherein:

[0150] The selector is used to determine the input path of the divider unit of this stage according to the selected operating mode. When the operating mode is pipeline parallel mode, the selector of each divider stage selects the corresponding parallel input data as the input data of this stage.

[0151] The divider calculation unit is used to calculate the stage-by-stage quotient value and the stage-by-stage remainder value of the stage.

[0152] The register unit is used to receive and store the stage-specific quotient value and the stage-specific remainder of the stage, and use them as output data of the divider unit of the stage.

[0153] In the pipeline parallel mode, CYCLE division operation tasks are simultaneously assigned to CYCLE-level divider units in one pipeline clock cycle. Each level of divider unit includes a first-round division calculation unit, m simplified division calculation units, quotient post-processing units and ripple carry adder units. Each level of divider unit calculates in one pipeline clock cycle. Therefore, CYCLE division operations are completed within one pipeline clock cycle. The computational accuracy of the pipeline parallel mode is determined by the pipeline parallel accuracy calculation formula.

[0154] Pipeline parallel mode is suitable for applications where parallel input data is required and the accuracy of the calculation results is relatively low. Pipeline parallel mode can complete multiple division tasks within a single pipeline clock cycle, significantly improving throughput. Compared with serial mode, pipeline parallel mode has higher data throughput and is more suitable for low-precision, high-data-volume calculations. Compared with iterative parallel mode, pipeline parallel mode uses fewer resources and can achieve pipeline output, making it more suitable for parallel or multi-threaded real-time processing systems.

[0155] Example 3: Figure 5 A flow chart of a pipeline divider calculation method with variable precision and throughput provided by another embodiment of the present invention. Figure 5 , an embodiment of the present invention provides a pipeline divider calculation method with variable precision and throughput, comprising:

[0156] Step S301: configuring divider parameters, wherein the divider parameters include the dividend data bit width, divisor data bit width, pipeline clock cycle number, base number and quotient set of the divider.

[0157] In this embodiment, the divider parameters include the divider's dividend data bit width (AW), divisor data bit width (BW), pipeline clock cycle number (Cycle), radix (Radix) and quotient set (such as {-r, -(r-1),…, -1, 0, 1,…, (r-1), r}).

[0158] The divider parameters are set during the initialization phase of the pipeline divider calculation method, and remain unchanged during the execution of the pipeline divider calculation method after being set.

[0159] Step S302: construct a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit and a ripple carry adder unit, and the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles and the base, and according to the quotient bit allocation stage derivation formula.

[0160] In this embodiment, the number of stages of the divider unit is the number of pipeline clock cycles (CYCLE).

[0161] The formula for deriving the quotient allocation series is:

[0162]

[0163] Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

[0164] Step S303: Selecting the operation mode of the divider to be the iterative parallel mode.

[0165] In this embodiment, the iterative parallel mode is that the input data of the divider unit at each level are the output data of the divider unit at this level in the previous pipeline clock cycle, and multiple division operation tasks are completed in parallel within multiple pipeline clock cycles. The calculation accuracy of the iterative parallel mode is the bit width of the dividend data.

[0166] Step S304: When the operation mode is the iterative parallel mode, the divider unit of each level is controlled to receive the corresponding parallel input data in the first pipeline clock cycle respectively, the first round division calculation unit of the divider unit of each level parallelly calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the corresponding division operation task, and multiple simplified division calculation units parallelly calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the corresponding division operation task, the first bit quotient value of the divider unit of each level and all the corresponding bit quotient values ​​of the level are processed by the post-quotient processing unit of the level to generate the stage quotient value of the level, and the corresponding bit remainder carry term and the remainder sum term of the last simplified division calculation unit in the divider unit of each level are processed by the traveling wave The carry adder generates the stage remainder of this level. The stage quotient and stage remainder of the divider unit of each level in this pipeline clock cycle are stored by the register unit of this level and serve as the output data of the divider unit of this level in this pipeline clock cycle. In each subsequent pipeline clock cycle, the divider unit of each level receives the output data of the divider unit of this level in the previous pipeline clock cycle, completes the iterative calculation of the stage quotient and stage remainder of this level corresponding to the division operation task, until all the divider units complete the calculation of the corresponding division operation task, and in the last pipeline clock cycle, the divider unit of each level outputs a final quotient and final remainder of the corresponding division operation task.

[0167] In this embodiment, the first-round division calculation unit includes:

[0168] Normalize the divisor and adjust the divisor value to the range .

[0169] The alignment shift process is to left-shift the dividend, or to left-shift the carry term of the remainder and the remainder sum term. The number of bits of the left shift is determined according to the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0170] Divisor pre-shifting performs pre-shifting on the normalized divisor according to the quotient set and radix. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, the output of the pre-shifted divisor d is {-2d, -d, 0, d, 2d}.

[0171] The quotient selection process determines the first quotient value based on the normalized divisor and the partial bits of the left-shifted dividend. For example, if the radix is ​​4 and the quotient set is {-2, -1, 0, 1, 2}, when r = 2, r is the maximum value of the current quotient set. Based on the normalized divisor d, the corresponding quotient thresholds {th_d, …, th_rd} are decoded. The absolute value of the partial bits of the left-shifted dividend z is compared with {th_d, …, th_rd} to determine the first quotient value. If |z| >= th_2d, the first quotient value q0 = 2. If |z| >= th_1d, the first quotient value q0 = 1. Otherwise, the first quotient value q0 = 0. If z < 0, the first quotient value q0 is negated.

[0172] The subtrahend selection process selects the corresponding subtrahend based on the first quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q = -1, the subtrahend value is d.

[0173] In the carry-save addition process, the selected subtrahend and the left-shifted dividend z are input into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the first-order remainder.

[0174] The quotient conversion process converts the first quotient value into the corresponding positive quotient value according to the real-time conversion algorithm.

[0175] After the first round of division calculation unit (srt_first_round) calculates the first quotient value and the remainder carry term and remainder sum term of the first remainder, it passes them to the first reduced division calculation unit (srt0_lite) for the next step of processing.

[0176] Each of the simplified division calculation units includes:

[0177] The remainder is shifted left, and the carry term and the remainder sum term are shifted left. The number of bits of the left shift is determined by the radix. For example, when the radix is ​​4, the left shift is 2 bits.

[0178] The simplified quotient selection process determines the corresponding bitwise quotient value based on the normalized divisor d, the carry term v of the left-shifted remainder, the remainder sum term s, and the quotient threshold set generated by the first-round division calculation unit. In terms of hardware design, the simplified quotient selection process of the streamlined division calculation unit reduces the quotient selection circuitry of the first-round division calculation unit by one level.

[0179] The subtrahend selection process selects the corresponding subtrahend according to the corresponding bit quotient value. For example, when the radix is ​​4, the quotient set is {-2, -1, 0, 1, 2}, and q=-1, the value of the subtrahend is d.

[0180] Carry-save addition processing, inputting the selected subtrahend and the shifted dividend z into the carry-save adder to obtain the remainder carry term v and the remainder sum term s used to represent the corresponding bit remainder;

[0181] The quotient conversion process performs a sign conversion on the corresponding bit quotient value according to the real-time conversion algorithm to convert the corresponding bit quotient value into a corresponding positive quotient value.

[0182] After each simplified division calculation unit (srt_lite) in each stage of the divider completes the corresponding quotient value, the remainder carry term, and the remainder sum term, the values ​​are passed to the next simplified division calculation unit (srt_lite) for further processing. After all m simplified division calculation units have completed their calculations, the first quotient value and the mth quotient values ​​are processed by the quotient post-processing unit to obtain the stage-by-stage quotient value for that stage. The corresponding remainder carry term and remainder sum term of the mth simplified division calculation unit are processed by the ripple carry adder unit to obtain the stage-by-stage remainder calculation for that stage.

[0183] The quotient post-processing unit shifts the first quotient value calculated by the first-round division calculation unit (srt_first_round) and the m corresponding quotient values ​​calculated by the m simplified division calculation units (srt_lite) to obtain the stage quotient value of this level.

[0184] The ripple carry adder unit adds the corresponding remainder bit item v and the remainder sum item s calculated by the m-th simplified division calculation unit to obtain the stage remainder of this level.

[0185] At this point, the calculation of the divider unit of this stage is completed, and the stage-by-stage quotient value and the stage-by-stage remainder of this stage are stored by the register unit of this stage and serve as output data of the divider unit of this stage.

[0186] In the iterative parallel mode, in the next pipeline clock cycle, the selector of each level of divider unit selects the output data of the divider unit at this level in the previous pipeline clock cycle and passes it to the first round of division calculation unit of the divider calculation unit at this level for further processing.

[0187] The working modes of the first-round division calculation unit include a first-round calculation mode and a degenerate compatibility mode.

[0188] When the divider unit is each level of the divider unit within the first pipeline clock cycle in the iterative parallel mode, and the working mode is the first round calculation mode, the divisor normalization processing and the divisor pre-shift function are enabled, and the alignment shift processing is to left shift the dividend, and the number of bits of the left shift is determined according to the base.

[0189] When the divider unit is a divider unit in the second pipeline clock cycle and each subsequent pipeline clock cycle in the iterative parallel mode, the divisor normalization processing and the divisor pre-shift function are turned off, and the alignment shift processing is to left-shift the received remainder carry term and remainder sum term, and the number of bits of the left shift is determined according to the base.

[0190] The post-quotient processing unit includes an enabled state and a bypass state. The enabled state indicates that the post-quotient processing unit is in an active operating state, and the bypass state indicates that the post-quotient processing unit is in a non-operating state and does not participate in calculations. When the operating mode of the divider is an iterative parallel mode, the post-quotient processing unit of each stage of the divider unit in the last pipeline clock cycle is in the enabled state, and the post-quotient processing unit of each stage of the divider unit in other pipeline clock cycles is in the bypass state.

[0191] After all the divider units complete the calculation of the corresponding division operation tasks, in the CYCLE-th pipeline clock cycle, the CYCLE-level divider unit outputs the final quotient value and final remainder of the CYCLE division operation tasks.

[0192] In the iterative parallel mode, CYCLE division operations are completed within CYCLE pipeline clock cycles. The calculation accuracy of the pipeline parallel mode is the data bit width of the dividend (AW).

[0193] Figure 6 A schematic diagram of the structure of multiple simplified division calculation units in an iterative parallel mode provided by one embodiment of the present invention. Figure 6 , the structure of multiple simplified division calculation units in iterative parallel mode includes:

[0194] In this embodiment, the multi-stage divider unit is configured according to hardware parameters and includes a CYCLE-stage divider unit. Each stage of the divider unit includes a selector, a divider calculation unit, and a register unit, wherein:

[0195] The selector determines the input path for the divider unit at that stage based on the selected operating mode. When the operating mode is iterative parallel mode, in the first pipeline clock cycle, the selector for each divider unit selects the corresponding parallel input data as the input data for that stage. In each subsequent pipeline clock cycle, the selector for each divider unit selects the output data of that divider unit in the previous pipeline clock cycle.

[0196] The divider calculation unit is used to calculate the stage-by-stage quotient value and the stage-by-stage remainder of the stage.

[0197] The register unit is used to receive and store the stage-specific quotient value and the stage-specific remainder of the stage, and use them as output data of the divider unit of the stage.

[0198] In the iterative parallel mode, CYCLE division operation tasks are assigned to CYCLE-level divider units at the same time. Each level of divider unit includes a first-round division calculation unit, m simplified division calculation units, quotient post-processing units and ripple carry adder units. Each level of divider unit calculates within one pipeline clock cycle. The quotient value of the bit.

[0199] In the first pipeline clock cycle, the first-level divider unit receives the corresponding parallel input data. In each subsequent pipeline clock cycle, each level of divider unit continues to iteratively calculate the corresponding division task based on the output data of the divider unit of this level in the previous pipeline clock cycle until the calculation of all division operation tasks is completed.

[0200] In iterative parallel mode, CYCLE division tasks are calculated over CYCLE pipeline clock cycles. Therefore, iterative parallel mode offers both high throughput and high precision, making it suitable for applications with parallel input data and demanding precision. Iterative parallel mode balances multi-task parallel processing with high-precision output for each task. Compared to pipeline parallel mode, iterative parallel mode offers higher output precision. Compared to serial mode, it offers greater parallel processing capabilities, improving overall throughput while maintaining high precision, making it more suitable for multi-task-intensive systems.

[0201] Figure 7 A schematic diagram of the structure of a divider calculation unit provided by an embodiment of the present invention. Figure 7 , the structure of the divider calculation unit includes:

[0202] Each level of the divider unit includes a first-round division calculation unit, m simplified division calculation units, a quotient post-processing unit, and a ripple carry adder unit. The number of simplified division calculation units is determined based on the divider parameters according to the quotient bit allocation series derivation formula, which is:

[0203]

[0204] Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

[0205] By configuring the divider parameters to determine the number of simplified divide units (srt_lite), the method accurately allocates the number of bits required to perform calculations at each divider level based on the dividend data width and the number of pipeline clock cycles, thereby ensuring overall computational accuracy. This method also avoids the resource waste associated with fixed structural configurations, enabling the divider to adapt to varying computational loads and performance requirements. The configurable nature of the simplified divide unit effectively improves hardware utilization and system integration.

[0206] Figure 8 A block diagram of a pipeline divider computing system with variable precision and throughput provided by an embodiment of the present invention. Figure 8 , a pipeline divider computing system 800 with variable precision and throughput, comprising:

[0207] A divider parameter configuration module 801 configures divider parameters, wherein the divider parameters include the dividend data bit width, the divisor data bit width, the number of pipeline clock cycles, the base number, and the quotient set of the divider;

[0208] A divider unit construction module 802 constructs a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit, and a ripple carry adder unit, wherein the number of simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles, and the cardinality, and according to a formula for deriving the quotient bit allocation stage number;

[0209] Configuring an operating mode module 803 to select an operating mode of the divider, wherein the operating modes include a serial mode, a pipeline parallel mode, and an iterative parallel mode;

[0210] The execution division operation module 804 controls the input path of the divider unit of each stage according to the selected operation mode. The first-round division calculation unit and multiple simplified division calculation units of the divider unit of each stage respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this stage are processed by the quotient post-processing unit of this stage to generate the stage quotient value of this stage. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this stage are processed by the ripple carry adder of this stage to generate the stage remainder of this stage. The stage quotient value and the stage remainder of this stage are both stored by the register unit of this stage and serve as the output data of the divider unit of this stage. After all the divider units complete the calculation of the corresponding division operation task, the final quotient value and final remainder of the corresponding division operation task are output.

[0211] In summary, the variable precision and throughput pipeline divider calculation method and system of the embodiment of the present invention include: configuring divider parameters, the divider parameters include the dividend data bit width, divisor data bit width, pipeline clock cycle number, cardinality and quotient set of the divider; constructing a multi-stage divider unit based on the divider parameters, each stage of the divider unit includes a divider calculation unit and a register unit, the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit and a ripple carry adder unit, the number of the simplified division calculation units is based on the dividend data bit width, pipeline clock cycle number and cardinality, and is determined according to the quotient bit allocation stage derivation formula; according to the selected operating mode , controlling the input path of the divider unit at each level, the first-round division calculation unit and multiple simplified division calculation units of the divider unit at each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term, all the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level, the corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level, the stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level, until all the divider units complete the calculation of the corresponding division operation task, and output the final quotient value and final remainder of the corresponding division operation task. The present invention configures divider parameters and determines the number of simplified division calculation units according to the quotient bit allocation series derivation formula. It can flexibly adjust the configuration of the divider calculation units according to different precision and throughput requirements, avoid resource waste, and ensure the coordinated matching of the divider output precision and structural efficiency.

[0212] Furthermore, by setting different operating modes, the divider can flexibly adapt to different usage scenarios and differentiated requirements for precision and throughput. Serial mode ensures high precision, pipeline parallel mode improves throughput, and iterative parallel mode enables high-precision parallel processing of multiple tasks, meeting the computing power requirements of different application scenarios and improving the adaptability and scalability of the overall computing architecture.

[0213] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pipeline divider calculation method with variable precision and throughput, characterized in that: include: Configuring divider parameters, wherein the divider parameters include the dividend data bit width, the divisor data bit width, the number of pipeline clock cycles, the base number, and the quotient set of the divider; Constructing a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, a plurality of simplified division calculation units, a quotient post-processing unit, and a ripple carry adder, and the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles, and the radix; Selecting an operating mode of the divider, wherein the operating mode includes a serial mode, a pipeline parallel mode, and an iterative parallel mode; According to the selected operating mode, the input path of the divider unit of each level is controlled, and the first-round division calculation unit and multiple simplified division calculation units of the divider unit of each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level, until all the divider units complete the calculation of the corresponding division operation task, and then output the final quotient value and final remainder of the corresponding division operation task.

2. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: The divider parameters are set during the initialization phase of the pipeline divider calculation method, and remain unchanged during the execution of the pipeline divider calculation method after being set.

3. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: The serial mode is that the input data of the subsequent stage divider unit are all the output data of the previous stage divider unit, and a division operation task is completed in sequence through multiple pipeline clock cycles. The calculation accuracy of the serial mode is the data bit width of the dividend; The pipeline parallel mode is that each level of the divider unit receives the parallel input data corresponding to the level respectively, and multiple division operation tasks are completed in parallel within one pipeline clock cycle. The calculation accuracy of the pipeline parallel mode is determined according to the number and cardinality of the simplified division calculation units; The iterative parallel mode is that the input data of the divider unit at each level are the output data of the divider unit at this level in the previous pipeline clock cycle, and multiple division operation tasks are completed in parallel within multiple pipeline clock cycles. The calculation accuracy of the iterative parallel mode is the bit width of the dividend data.

4. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: When the operation mode is the serial mode, the first-stage divider unit is controlled to receive serial input data in the first pipeline clock cycle, the first-round division calculation unit of the first-stage divider unit calculates the first-bit quotient value and the first-bit remainder carry term and the remainder sum term of the division operation task, and multiple simplified division calculation units respectively calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the division operation task, the first bit quotient value and all corresponding bit quotient values ​​are processed by the post-quotient processing unit of the stage to generate the stage quotient value, and the corresponding bit remainder carry term of the last simplified division calculation unit in the first-stage divider unit is processed. The sum of the remainder and the remainder is generated by the ripple carry adder of the stage to generate the stage remainder of the stage. The stage quotient value and the stage remainder of the stage are both stored by the register unit of the stage and serve as the output data of the divider unit of the stage. In each subsequent pipeline clock cycle, the divider unit of the next stage sequentially receives the output data of the divider unit of the previous stage and completes the calculation of the stage quotient value and the stage remainder of the stage. After all the divider units have completed the calculation of the corresponding division operation tasks, the divider unit of the last stage outputs the final quotient value and final remainder of a division operation task in the last pipeline clock cycle. When the operation mode is the pipeline parallel mode, the divider unit of each level is controlled to receive the corresponding parallel input data in the same pipeline clock cycle respectively. The first round division calculation unit of the divider unit of each level parallelly calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the corresponding division operation task. The plurality of simplified division calculation units parallelly calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the corresponding division operation task. The first bit quotient value of the divider unit of each level and all the corresponding bit quotient values ​​of the level are parallelized by the first round division calculation unit. The stage quotient post-processing unit generates a stage quotient value for that stage. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in each stage of the divider unit are processed by the ripple carry adder of that stage to generate a stage remainder for that stage. The stage quotient value and stage remainder for that stage are both stored by the register unit of that stage and serve as output data of the divider unit of that stage. After all the divider units complete the calculation of the corresponding division operation tasks, each stage of the divider unit outputs a final quotient value and final remainder for the corresponding division operation task. When the operation mode is the iterative parallel mode, the divider units at each level are controlled to receive corresponding parallel input data in the first pipeline clock cycle respectively, the first-round division calculation unit of the divider units at each level calculates the first bit quotient value and the first bit remainder carry term and the remainder sum term of the corresponding division operation task in parallel, a plurality of simplified division calculation units calculate the corresponding bit quotient value and the corresponding bit remainder carry term and the remainder sum term of the corresponding division operation task in parallel, the first bit quotient value of the divider units at each level and all the corresponding bit quotient values ​​of the level are processed by the post-quotient processing unit of the level to generate the stage quotient value of the level, the corresponding bit remainder carry term and the remainder sum term of the last simplified division calculation unit in the divider units at each level are processed by the ripple carry addition unit of the level The divider generates a stage remainder for this stage. The stage quotient and stage remainder of the divider unit at each stage in this pipeline clock cycle are stored by the register unit at this stage and serve as the output data of the divider unit at this stage in this pipeline clock cycle. In each subsequent pipeline clock cycle, the divider unit at each stage receives the output data of the divider unit at this stage in the previous pipeline clock cycle, and completes the iterative calculation of the stage quotient and stage remainder of the corresponding division operation task. After all the divider units complete the calculation of the corresponding division operation task, the divider unit at each stage outputs a final quotient and final remainder of the corresponding division operation task in the last pipeline clock cycle.

5. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: The number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles and the cardinality, and is specifically derived by the following formula: Among them, ceil() is rounded up, AW is the data bit width of the dividend, CYCLE is the number of pipeline clock cycles, and Radix is ​​the base.

6. The pipeline divider calculation method with variable precision and throughput according to claim 3, wherein: The calculation accuracy of the pipeline parallel mode is determined according to the number and cardinality of the simplified division calculation units and is specifically calculated by the following formula: Where m is the number of simplified division calculation units, and Radix is ​​the radix.

7. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: The first-round division calculation unit includes: Normalize the divisor and adjust the divisor value to the range ; Alignment shift processing, shifting the dividend to the left, or shifting the received remainder carry term and remainder sum term to the left, where the number of bits of the left shift is determined according to the base; Divisor pre-shift: pre-shift the normalized divisor according to the set quotient set and cardinality; The quotient selection process determines the first quotient value based on the normalized divisor and the partial bits of the left-shifted dividend; Subtrahend selection processing, selecting the corresponding subtrahend according to the first quotient value; Carry-save addition processing, inputting the selected subtrahend and the left-shifted dividend into the carry-save adder to obtain the remainder carry term and the remainder sum term used to represent the first-order remainder; Quotient conversion processing, converting the first quotient value into the corresponding positive quotient value according to the real-time conversion algorithm; Each of the simplified division calculation units includes: Shift the remainder left, shifting the remainder carry term and the remainder sum term left, where the number of bits of the left shift is determined according to the base; Simplify the quotient selection process and determine the corresponding bit quotient value based on the normalized divisor, the carry term and the remainder sum term after the left shift, and the quotient threshold set generated by the first round of division calculation unit; Subtrahend selection processing, selecting the corresponding subtrahend according to the corresponding bit quotient value; Carry-save addition processing, inputting the selected subtrahend and the shifted dividend into the carry-save adder to obtain the remainder carry term and the remainder sum term used to represent the corresponding bit remainder; The quotient conversion process performs a sign conversion on the corresponding bit quotient value according to the real-time conversion algorithm to convert the corresponding bit quotient value into a corresponding positive quotient value.

8. The pipeline divider calculation method with variable precision and throughput according to claim 7, characterized in that: The working modes of the first-round division calculation unit include a first-round calculation mode and a degenerate compatibility mode; When the divider unit is a first-stage divider unit in a serial mode, or each stage of the divider unit in a first pipeline clock cycle in an iterative parallel mode, or each stage of the divider unit in a pipeline parallel mode, and the operating mode is a first-round calculation mode, the divisor normalization processing and the divisor pre-shift function are enabled, and the alignment shift processing is to left-shift the dividend, and the number of bits of the left shift is determined according to the base number; When the divider unit is a second-stage divider unit and a subsequent-stage divider unit in a serial mode, or a divider unit in a second pipeline clock cycle and each subsequent pipeline clock cycle in an iterative parallel mode, and the operating mode is a degenerate compatible mode, the divisor normalization processing and the divisor pre-shift function are disabled, and the alignment shift processing is to left-shift the received remainder carry term and remainder sum term, and the number of bits of the left shift is determined according to the radix; The post-quotient processing unit includes an enabled state and a bypass state, wherein the enabled state is that the post-quotient processing unit is in an activated running state, and the bypass state is that the post-quotient processing unit is in a non-running state that does not participate in the calculation; When the operation mode of the divider is a serial mode, the quotient post-processing unit of the last stage divider unit is in an enabled state, and the quotient post-processing units of the other stages divider units are in a bypass state; When the operation mode of the divider is the pipeline parallel mode, the quotient post-processing unit of each level of the divider unit is in an enabled state; When the operation mode of the divider is the iterative parallel mode, the quotient post-processing units of each stage of the divider unit in the last pipeline clock cycle are all in the enabled state, and the quotient post-processing units of each stage of the divider unit in other pipeline clock cycles are all in the bypass state.

9. The pipeline divider calculation method with variable precision and throughput according to claim 1, wherein: The number of stages of the divider unit is the number of pipeline clock cycles.

10. A pipeline divider computing system with variable precision and throughput, characterized in that: include: Configuring a divider parameter module to configure divider parameters, wherein the divider parameters include the dividend data bit width, the divisor data bit width, the number of pipeline clock cycles, the base number, and the quotient set of the divider; Constructing a divider unit module, constructing a multi-stage divider unit based on the divider parameters, wherein each stage of the divider unit includes a divider calculation unit and a register unit, wherein the divider calculation unit includes a first-round division calculation unit, multiple simplified division calculation units, a quotient post-processing unit, and a ripple carry adder, and the number of the simplified division calculation units is determined based on the dividend data bit width, the number of pipeline clock cycles, and the radix; Configure the operation mode module to select the operation mode of the divider, wherein the operation mode includes serial mode, pipeline parallel mode and iterative parallel mode; The execution division operation module controls the input path of the divider unit of each level according to the selected operation mode. The first-round division calculation unit and multiple simplified division calculation units of the divider unit of each level respectively complete the calculation of the corresponding bit quotient value and the corresponding bit remainder carry term and remainder sum term. All the corresponding bit quotient values ​​of this level are processed by the quotient post-processing unit of this level to generate the stage quotient value of this level. The corresponding bit remainder carry term and remainder sum term of the last simplified division calculation unit in this level are processed by the ripple carry adder of this level to generate the stage remainder of this level. The stage quotient value and the stage remainder of this level are both stored by the register unit of this level and serve as the output data of the divider unit of this level. After all the divider units complete the calculation of the corresponding division operation task, the final quotient value and final remainder of the corresponding division operation task are output.

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