Synchronization signal sampling violation solving method and system and electronic equipment

Abstract

The invention discloses a synchronous signal sampling violation solving method, a synchronous signal sampling violation solving system and electronic equipment. A clock signal clk subjected to step delay is sampled by a synchronous signal sysref through a hold time detection circuit, and the clock signal clk is sampled by the synchronous signal sysref subjected to step delay through an establishment time detection circuit; secondly, binary coding and mapping are carried out on a sampling result, then a time sequence violation judgment and phase correction circuit is used for judging the time sequence violation condition of the current synchronous circuit in a segmented mode based on the coding and mapping result, and phase modulation control code words are released; and then according to the phase modulation control code word, the signal delay circuit is controlled to adjust the to-be-corrected signal. The synchronous sampling process only relates to a sysref signal and a clk signal, so that the problem of time sequence violation existing in a clock sampling synchronous signal can be solved, and the consistency among multiple modules or multiple systems is ensured; moreover, the method, system or device provided by the embodiment of the invention can be completely integrated in each subsystem, so that the resource consumption of the system level is reduced.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and in particular to a solution, system and electronic equipment for synchronous signal sampling violation. Background Art

[0002] In a distributed high-speed synchronous sampling system, high-precision synchronization circuits are usually required to achieve synchronization between multiple systems or modules. Whether each system or module can accurately sample the synchronization signal determines the performance and reliability of the synchronization system.

[0003] The synchronization signal sysref is generated by the even-number division of the clock clk. When each subsystem circuit has synchronization requirements, clk samples sysref to generate a set signal. However, in high-speed system applications, due to hardware signal delays, after sysref / clk reaches each subsystem, its sampling relationship is inconsistent with the initial one, such as Figure 1 This is a synchronization case of three subsystems. Due to circuit delay, the signal of subsystem 3 enters the clk setup / hold violation interval, and the synchronization of this subsystem is uncertain.

[0004] To address synchronization signal sampling violations, a related technique involves sampling the ODELAY delay unit of the FPGA chip, which independently adjusts the sysref signal connected to each subsystem. This method selects the same input data for each subsystem, uses the output data of one subsystem as a reference, and compares the phase differences of the data from the remaining subsystems to guide the adjustment of the sysref delay control. This method uses a delay circuit that exists only in the FPGA chip, which is limited in applications with a large number of subsystems. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a solution, system and electronic device for synchronous signal sampling violation. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] According to a first aspect of an embodiment of the present invention, a method for solving a synchronization signal sampling violation is provided, the method comprising:

[0007] The hold time detection circuit samples the clock signal clk with the synchronization signal sysref after the step delay, and the setup time detection circuit samples the clock signal clk with the synchronization signal sysref after the step delay;

[0008] Inputting the sampling result obtained by the hold time detection circuit into the hold time coding circuit for binary coding and mapping, and inputting the sampling result obtained by the setup time detection circuit into the setup time coding circuit for binary coding and mapping;

[0009] Using the timing violation judgment and phase correction circuit, based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, the timing violation status of the current synchronization circuit is judged in segments, and the phase modulation control codeword is released;

[0010] According to the phase modulation control codeword, the control signal delay circuit adjusts the signal to be corrected.

[0011] In one embodiment of the present invention, the holding time detection circuit sampling the clock signal clk after the step delay using the synchronization signal sysref includes:

[0012] Through the hold time detection circuit, the synchronization signal sysref is used to sample the clock signal clk after N step delays to obtain an N-bit sampling result, where the sum of the N step delays is ≥ the hold time requirement;

[0013] The step of sampling the clock signal clk using the step-delayed synchronization signal sysref by establishing a time detection circuit comprises:

[0014] By setting up a time detection circuit, the clock signal clk is sampled with M step-delayed synchronization signals sysref to obtain M-bit sampling results, where the sum of the M step delays is ≥ the settling time requirement.

[0015] In one embodiment of the present invention, inputting the sampling result obtained by the hold time detection circuit into the hold time encoding circuit for binary encoding and mapping includes:

[0016] Inputting the sampling result obtained by the holding time detection circuit into the holding time encoding circuit, encoding and compressing the data bit width according to the preset first encoding table, and then mapping it to the holding time encoding map;

[0017] The step of inputting the sampling result obtained by the setup time detection circuit into the setup time encoding circuit for binary encoding and mapping includes:

[0018] The sampling result obtained by the setup time detection circuit is input into the setup time coding circuit, and the data bit width is compressed by coding according to the preset second coding table, and then mapped to the setup time coding map.

[0019] In one embodiment of the present invention, the timing violation judgment and phase correction circuit is used to segmentally judge the timing violation status of the current synchronization circuit based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, and release the phase modulation control codeword, including:

[0020] The coding results of the hold time coding circuit and the setup time coding circuit are combined into a timing detection codeword by using a timing violation judgment and phase correction circuit; based on the corresponding results of the timing detection codeword in a preset timing judgment table, the timing violation status of the current synchronization circuit is judged in segments; and based on the hold time coding diagram and the setup time coding diagram, a corresponding phase modulation control codeword is generated and released to the control signal delay circuit; the phase modulation control codeword includes a coarse modulation code and a fine modulation code.

[0021] In one embodiment of the present invention, controlling the signal delay circuit to adjust the signal to be corrected according to the phase modulation control codeword includes:

[0022] Turning on the signal delay circuit, configuring a first phase modulation control codeword, and adjusting the signal to be corrected according to the first phase modulation control codeword;

[0023] determining a timing violation condition of the synchronization circuit after adjustment by the first phase modulation control codeword;

[0024] If there is a violation, the signal delay circuit is turned on again, a second phase modulation control codeword is configured, and the signal to be corrected is adjusted according to the second phase modulation control codeword;

[0025] determining a timing violation condition of the synchronization circuit after adjustment by the second phase modulation control codeword;

[0026] If there is a violation, an error is reported; if there is no violation, the adjustment is completed.

[0027] In one embodiment of the present invention, controlling the signal delay circuit to adjust the signal to be corrected according to the phase modulation control codeword includes:

[0028] According to a preset decoding table, the phase modulation control codeword is subjected to temperature code decoding processing to obtain a temperature codeword;

[0029] According to the temperature codeword, the signal delay circuit is controlled to increase in delay according to a unit step length, so as to adjust the signal to be corrected.

[0030] According to a second aspect of an embodiment of the present invention, a system for resolving synchronous signal sampling violation is provided, the system comprising: a hold time detection circuit and a hold time encoding circuit, a setup time detection circuit and a setup time encoding circuit, a timing violation judgment and phase correction circuit, and a signal delay circuit;

[0031] The input end of the hold time detection circuit is connected to the output end of the signal delay circuit and the input end of the setup time detection circuit, and the output end is connected to the input end of the hold time coding circuit; the output end of the setup time detection circuit is connected to the input end of the setup time coding circuit, the input end of the timing violation judgment and phase correction circuit is connected to the output ends of the hold time coding circuit and the setup time coding circuit, and the output end is connected to the signal delay circuit;

[0032] The hold time detection circuit uses the synchronization signal sysref to sample the clock signal clk after the step delay, and the hold time encoding circuit is used to binary encode and map the sampling result obtained by the hold time detection circuit; the setup time detection circuit uses the step delayed synchronization signal sysref to sample the clock signal clk, and the setup time encoding circuit is used to binary encode and map the sampling result obtained by the setup time detection circuit; the timing violation judgment and phase correction circuit is used to segmentally judge the timing violation status of the current synchronization circuit based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, and release the phase modulation control codeword; the signal delay circuit adjusts the signal to be corrected according to the phase modulation control codeword.

[0033] In one embodiment of the present invention, the hold time detection circuit includes a specified number of custom inverters and a high-speed flip-flop.

[0034] In one embodiment of the present invention, the signal delay circuit includes a coarse adjustment circuit and a fine adjustment circuit. The coarse adjustment circuit includes a specified number of inverters connected in series, and the fine adjustment circuit includes a specified number of groups of identical switch capacitors.

[0035] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, the device comprising:

[0036] one or more processors;

[0037] a computer-readable medium configured to store one or more programs;

[0038] When the one or more programs are executed by the one or more processors, the one or more processors implement the synchronization signal sampling violation solution as described in any one of the first aspects.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The embodiments of the present invention provide a solution, system, and electronic device for solving the problem of synchronous signal sampling violation. First, a hold time detection circuit uses a synchronous signal sysref to sample a clock signal clk that has undergone a step delay, and a setup time detection circuit uses the step delayed synchronous signal sysref to sample the clock signal clk. Then, the sampling result obtained by the hold time detection circuit is input into a hold time coding circuit for binary coding and mapping, and the sampling result obtained by the setup time detection circuit is input into a setup time coding circuit for binary coding and mapping. Then, a timing violation judgment and phase correction circuit is used to judge the timing violation status of the current synchronous circuit in segments based on the coding and mapping results of the hold time coding circuit and the setup time coding circuit, and a phase modulation control codeword is released. Then, according to the phase modulation control codeword, a signal delay circuit is controlled to adjust the signal to be corrected. The synchronous sampling process of the present invention only involves the sysref signal and the clk signal. There is no need to generate a higher-frequency clock to calculate the phase and adjust the delay to resolve the timing violation of the clock sampling synchronization signal, thereby ensuring consistency among multiple modules or multiple systems. The method, system, or device provided by the embodiment of the present invention can be fully integrated within each subsystem, reducing resource consumption at the system level, and no excessive constraints on routing and pins are required during hardware implementation.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A signal violation diagram provided in the background technology of the present invention;

[0043] Figure 2 A flowchart of a method for solving a synchronization signal sampling violation problem provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of holding time determination provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of establishing time determination provided by an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of retention time coding provided by an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of establishing time coding provided by an embodiment of the present invention;

[0048] Figure 7 A diagram illustrating a method for handling sysref / clk synchronous sampling violations according to an embodiment of the present invention;

[0049] Figure 8Schematic diagram of an ADC synchronous sampling system provided by an embodiment of the present invention;

[0050] Figure 9 A schematic diagram of a hold time detection circuit provided by an embodiment of the present invention;

[0051] Figure 10 A schematic diagram of a setup time detection circuit provided by an embodiment of the present invention;

[0052] Figure 11 A schematic diagram of a delay circuit provided by an embodiment of the present invention;

[0053] Figure 12 An equivalent circuit diagram of a coarse adjustment circuit provided by an embodiment of the present invention;

[0054] Figure 13 An equivalent circuit diagram of a fine adjustment circuit provided by an embodiment of the present invention;

[0055] Figure 14 An automatic correction flow chart provided by an embodiment of the present invention;

[0056] Figure 15 A diagram of a system for resolving synchronization signal sampling violations provided by an embodiment of the present invention;

[0057] Figure 16 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] This invention is suitable for applications requiring strict synchronization, such as high-speed clock dividers, 204B multi-channel data transmission and reception with deterministic delay, and DDS modulation / demodulation. It is used to address synchronous signal sampling in GHz-class high-speed sampling systems, identify setup and hold time violations during synchronous signal sampling, and provide solutions.

[0059] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0060] Example 1

[0061] Reference Figure 2 , shows a flowchart of the steps of a solution to synchronization signal sampling violation provided according to embodiment 1 of the present invention.

[0062] The solution to the synchronization signal sampling violation in this embodiment includes the following steps:

[0063] Step 101: A hold time detection circuit uses a synchronization signal sysref to sample a clock signal clk that has undergone a step delay, and a setup time detection circuit uses a synchronization signal sysref to sample the clock signal clk that has undergone a step delay.

[0064] Specifically, when the clock signal clk after the step delay is sampled by the synchronization signal sysref through the hold time detection circuit, and the clock signal clk after the step delay is sampled by the synchronization signal sysref through the setup time detection circuit, the clock signal clk after the N step delays can be sampled by the synchronization signal sysref through the hold time detection circuit to obtain an N-bit sampling result. <H0H1H2H3H4……H N >, used to determine the hold time relationship between the sysref signal and the clk signal, where the sum of N step delays ≥ the hold time requirement; by establishing a time detection circuit, the clock signal clk is sampled with the synchronous signal sysref with M step delays to obtain an M-bit sampling result <S0S1S2S3S4……S M >, used to determine the setup time relationship between the sysref signal and the clk signal, where the sum of M step delays ≥ the setup time requirement.

[0065] For example, in the hold time detection circuit, taking 8 steps as an example, Figure 3 As shown, if the sysref signal is in the D6 area of the low level of the clk signal, the sampling result of the sysref signal is 1 after d6 step delays, and the sampling result before d6 is 0, then the sampling result can be expressed as 8'b00000011; if the sysref signal is in the D6 area of the high level interval of the clk signal, then after 6 step delays, the sampling result of the sysref signal on the clk signal is 0, and the sampling result before d6 is 1, then the sampling result can be expressed as 8'b11111100.

[0066] In the setup time detection circuit, such as Figure 4 As shown, if the rising edge of the clk signal is in the d7 interval of the sysref signal, the sampled result can be expressed as 8'b00000001, and if the falling edge of the clk signal is in the d7 interval of the sysref signal, the sampled result can be expressed as 8'b11111110.

[0067] Step 102: Input the sampling result obtained by the hold time detection circuit into the hold time coding circuit for binary coding and mapping, and input the sampling result obtained by the setup time detection circuit into the setup time coding circuit for binary coding and mapping.

[0068] Specifically, when the sampling result obtained by the hold time detection circuit is input into the hold time coding circuit for binary encoding and mapping, the sampling result obtained by the hold time detection circuit can be input into the hold time coding circuit, encoded according to the preset first coding table to compress the data bit width, and then mapped to the hold time coding diagram.

[0069] Exemplarily, the time-keeping coding circuit performs binary coding on the N-bit result obtained by the sampling to compress the data bit width. Taking 8 steps as an example, an 8-bit sampling result is obtained. The 8-bit sampling result is encoded according to Table 1 and mapped to Figure 5 The hold time encoding diagram in Figure 1 shows the phase relationship between the sysref signal and the clk signal determined by the encoded 4-bit value, providing guidance for hold time adjustment.

[0070] Table 1 The first coding table

[0071]

[0072]

[0073] Specifically, when the sampling result obtained by the establishment time detection circuit is input into the establishment time coding circuit for binary encoding and mapping, the sampling result obtained by the establishment time detection circuit can be input into the establishment time coding circuit, encoded according to the preset second coding table to compress the data bit width, and then mapped to the establishment time coding diagram.

[0074] For example, a time coding circuit is established to perform binary coding on the M bit result obtained by sampling to compress the data bit width. Taking 8 steps as an example, an 8-bit sampling result is obtained. The 8-bit sampling result is encoded according to the coding method in Table 2 and then mapped to Figure 6 The setup time coding diagram shown in the figure uses the encoded 4-bit value to determine the setup time phase relationship between the sysref signal and the clk signal, providing guidance for setup time adjustment.

[0075] Table 2 The second coding table

[0076] Sampling results Encoding results 8’b0000_0000 4’h8 8’b0000_0001 4’h7 8’b0000_0011 4’h6 8’b0000_0111 4’h5 8’b0000_1111 4’h4 8’b0001_1111 4’h3 8’b0011_1111 4’h2 8’b0111_1111 4’h1 8’b1111_1111 4’h0 8’b1111_1110 4'hF 8’b1111_1100 4'hE 8’b1111_1000 4'hD 8’b1111_0000 4'hC 8’b1110_0000 4'HB 8’b1100_0000 4'hA 8’b1000_0000 4’h9

[0077] Step 103: Using the timing violation judgment and phase correction circuit, based on the coding and mapping results of the hold time coding circuit and the build time coding circuit, the timing violation status of the current synchronization circuit is judged in segments, and the phase modulation control codeword is released.

[0078] Specifically, the timing violation judgment and phase correction circuit can be used to combine the coding results of the hold time coding circuit and the build time coding circuit into a timing detection codeword; then, based on the corresponding results of the timing detection codeword in the preset timing judgment table, the timing violation status of the current synchronization circuit is judged in segments; and based on the hold time coding diagram and the build time coding diagram, the corresponding phase modulation control codeword is generated and released to the control signal delay circuit; the phase modulation control codeword includes a coarse modulation code and a fine modulation code.

[0079] In this embodiment, the timing violation determination circuit can combine the encoding results of the hold time encoding circuit and the setup time encoding circuit for timing violation determination. Using an 8-bit detection circuit as an example, the hold time code h_code<3:0> and the setup time code s_code<3:0> are combined into the timing detection word {h_code<3:0>, s_code<3:0>}. The timing violation status of the current synchronization circuit is then determined in segments, referring to the preset timing determination tables Tables 3 and 4. Table 3 guides the sampling of the synchronization signal sysref on the rising edge of the clock, while Table 4 guides the sampling of the synchronization signal sysref on the falling edge of the clock. The phase correction circuit is used to release the phase modulation control codeword based on the determination and the hold time encoding diagram and setup time encoding diagram. The phase modulation control codeword supports custom configuration or system-internal self-correction configuration. The self-correction configuration automatically generates the corresponding control word based on the timing determination, ensuring that the timing violation disappears after the control is issued.

[0080] Table 3 First preset timing decision table

[0081] Timing detection codeword Timing decision 8:00 AM / 8:01 AM / … / 8:07 AM Rising edge synchronous sampling is prone to setup time violations, and the violation probability is inversely proportional to the codeword size 8'h08 / 8'h18 / … / 8'h88 Rising edge synchronous sampling without setup / hold time violation (hold margin optimum phase) 8'h89 / 8'h8A / … / 8'h8F Rising edge synchronous sampling without setup / hold time violation (optimal setup / hold margin phase) 8’h80 Rising edge synchronous sampling without setup / hold time violation (optimal setup margin phase) 8'h90 / 8'hA0 / … / 8'hF0 Rising edge synchronous sampling is prone to hold time violations, and the violation probability is proportional to the codeword size 8’h00 Rising edge synchronous sampling is prone to setup / hold time violations

[0082] Table 4 Second preset timing decision table

[0083] Timing detection codeword Timing decision 8'h89 / 8'h8A / … / 8'h8F Falling edge synchronous sampling is prone to setup time violations, and the violation probability is inversely proportional to the codeword size 8'h80 / 8'h90 / … / 8'hF0 Falling edge synchronous sampling without setup / hold time violation (hold margin optimum phase) 8'h89 / 8'h8A / … / 8'h8F Falling edge synchronous sampling without setup / hold time violation (optimal setup / hold margin phase) 8’h80 Falling edge synchronous sampling without setup / hold time violation (optimal setup margin phase) 8'h90 / 8'hA0 / … / 8'hF0 Falling edge synchronous sampling is prone to hold time violations, and the violation probability is proportional to the codeword size 8’h00 Falling edge synchronous sampling is prone to setup / hold time violations

[0084] Step 104: Control the signal delay circuit according to the phase modulation control codeword to adjust the signal to be corrected.

[0085] For example, Figure 7 This is the method for handling sysref / clk synchronous sampling violations. Taking the adjustment of the sysref signal as an example, a delay circuit (i.e., the signal delay circuit described above) is inserted into its propagation path. The specific delay value can be configured according to the control ladder (the control ladder can refer to the graphics or code values of the hold time coding diagram and the setup time coding diagram). The delay range is greater than the sampling setup + hold time requirements.

[0086] An embodiment of the present invention provides a solution to a synchronization signal sampling violation. First, a hold time detection circuit uses a synchronization signal sysref to sample a clock signal clk that has undergone a step delay, and a setup time detection circuit uses the step delayed synchronization signal sysref to sample the clock signal clk. Then, a sampling result obtained by the hold time detection circuit is input into a hold time coding circuit for binary coding and mapping, and a sampling result obtained by the setup time detection circuit is input into a setup time coding circuit for binary coding and mapping. Then, a timing violation judgment and phase correction circuit is used to judge the timing violation status of the current synchronization circuit in segments based on the coding and mapping results of the hold time coding circuit and the setup time coding circuit, and a phase modulation control codeword is released. Then, according to the phase modulation control codeword, a control signal delay circuit is used to adjust the synchronization signal sysref or the clock signal clk. The synchronous sampling process of the present invention only involves the sysref signal and the clk signal. There is no need to generate a higher-frequency clock to calculate the phase and adjust the delay to resolve the timing violation of the clock sampling synchronization signal, thereby ensuring consistency among multiple modules or multiple systems. The method, system, or device provided by the embodiment of the present invention can be fully integrated within each subsystem, reducing resource consumption at the system level, and no excessive constraints on routing and pins are required during hardware implementation.

[0087] Example 2

[0088] This embodiment will take a case of verification and implementation in a 1G high-speed ADC synchronous sampling system as an example to illustrate the present invention in more detail.

[0089] Figure 8 This is a schematic diagram of the ADC synchronous sampling system. The ADC array uses the same set of sysref / clk signals. The internal chip requires setup / hold times of 56ps / 64ps for synchronous sampling of the sysref signal. Custom components are used in the ADC analog portion to build the setup / hold detection circuit and the sysref signal delay circuit. Standard components are used in the ADC digital portion to encode the detection value and decode the system's delay control code. The system FPGA accesses ADC information through register reads and writes, performing timing violation detection and phase correction.

[0090] In this embodiment, the hold time detection circuit may include a specified number of custom inverters and high-speed flip-flops. Figure 9 , Figure 9As a schematic diagram of the hold time detection circuit, in this embodiment, 8 customized inverters are used to implement 8 step delay phases of the clk signal, accompanied by 8 high-speed triggers to implement the sysref signal sampling of the multi-phase clk signal, where the delay of the inverter is customized to 8ps, and the total delay of the 8 phases is 64ps. The total setup + hold time requirement of the customized high-speed trigger is less than 8ps. At this time, the circuit can cover the complete hold time interval.

[0091] The setup time detection circuit can refer to Figure 10 , Figure 10 To establish a time detection circuit, this embodiment uses seven customized inverters to implement seven step-delay phases for the sysref signal, accompanied by eight high-speed triggers to implement multi-phase sysref signal sampling of the clk signal. The inverter delay is customized to 8 ps, and the total delay of the seven phases is 56 ps. The total setup and hold time requirements of the customized high-speed triggers are less than 8 ps. At this time, the circuit can cover the entire setup time interval.

[0092] The results of the above two detection circuits are transmitted to the digital domain ( Figure 8 In the digital circuit module), the digital circuit obtains the 8-bit sysref / clk phase code by referring to Table 1 and Table 2 in Example 1. The code word is uploaded to the FPGA via the SPI bus as a read-only register. At this time, the system makes a current violation judgment by referring to Table 3 and Table 4 in Example 1. Figure 5 Figure 6 The system sends phase adjustment codewords (phase adjustment codewords) to the ADC based on the coded values in the ADC. In this example, the system sends two sets of 8-bit phase adjustment codewords, namely coarse adjustment codewords (8'd000-8'd192) and fine adjustment codewords (8'd000-8'd128).

[0093] After the ADC receives the phase modulation control codeword, the digital circuit performs temperature code decoding processing according to Table 5 and Table 6.

[0094] In this embodiment, the phase modulation control codeword can be temperature-coded according to a preset decoding table (Table 5 below presets a coarse adjustment code decoding table, and Table 6 presets a fine adjustment code decoding table) to obtain a temperature codeword; then, based on the temperature codeword, the control signal delay circuit delay is increased according to a unit step size to achieve adjustment of the signal to be corrected.

[0095] Table 5 Preset coarse code decoding table

[0096] Coarse code <![CDATA[Temperature code (C 191 C 190 ……C2C1C0)]]> Delay control 8’d000 192’b0000_0000_......_0000_0000 0*coarse adjustment delay step 8’d001 192’b0000_0000_......_0000_0001 1*coarse delay step 8’d002 192’b0000_0000_......_0000_0011 2*coarse delay step …… …… …… 8’d191 192’b0111_1111_......_1111_1111 191*coarse delay step 8’d192 192’b1111_1111_......_1111_1111 192*coarse delay step

[0097] Table 6 Preset fine-tuning code decoding table

[0098]

[0099]

[0100] Temperature codeword is used to directly control the Figure 11 The delay circuit is internally divided into a coarse adjustment circuit and a fine adjustment circuit. According to the input temperature codeword, the circuit delay increases according to the unit step size.

[0101] In this embodiment, the equivalent circuit diagram of the coarse adjustment circuit is shown in FIG. Figure 12 , can be composed of 192 inverters in series. According to the inverter transmission delay t = K * RC (C is the load capacitance, R is the on-resistance), the circuit design of each inverter RC is controllable, and under normal working conditions, it is R n *C n After the system configures the coarse adjustment delay value, the inverter RC corresponding to the temperature code bit becomes (R n *C n +R d *C d ), the RC change is customized in the design to bring about a delay of 1.75ps, and the coarse adjustment uses this delay value as the adjustment unit. Figure 13 , can access 128 groups of identical switched capacitors (C unit ), fine-tune the delay control word (temperature codeword) to determine the number of connected capacitors, and the final total capacitance C total =Σ(sw i *C unit The charge and discharge time of the capacitor at the signal node is proportional to the capacitance value, enabling adjustable signal delay. The design customizes the delay change for each capacitor to 0.25 ps, with this delay value used as the unit for fine-tuning. The entire delay circuit supports delay adjustment from 0 to 368 ps (a range greater than 56 + 64 ps), meeting the setup / hold time requirements of ADC synchronous sampling.

[0102] Phase correction in the example system described above supports both manual and automatic calibration. For manual calibration, the user can customize the delay (including coarse and fine adjustment control) by referring to the readback 8-bit encoding result and sending it to the ADC to complete the phase adjustment process. For automatic calibration, the calibration process can be completed spontaneously at the system level (in the FPGA) or integrated into the ADC.

[0103] Reference Figure 14Schematic diagram of the automatic correction process. Specifically, first, the signal delay circuit is turned on, the first phase-modulation control codeword is configured, and the signal to be corrected is adjusted according to the first phase-modulation control codeword; then the timing violation of the synchronization circuit after adjustment by the first phase-modulation control codeword is judged; if a violation exists, the signal delay circuit is turned on again, the second phase-modulation control codeword is configured (the corresponding control word can be automatically generated based on the timing judgment and the coding diagram), and the signal to be corrected is adjusted according to the second phase-modulation control codeword; then the timing violation of the synchronization circuit after adjustment by the second phase-modulation control codeword is judged; if a violation exists, an error is reported; if no violation exists, the adjustment is completed.

[0104] Before the auto-calibration process begins, the user can preset a calibration value for the system call. This calibration value can be set based on actual requirements and consumes two sysref cycles to perform a timing check. The first check determines timing violations, while the second check confirms the effectiveness of the preset configuration (i.e., the preset calibration value). The preset configuration directly impacts the calibration results. For example, for a 1G clock in this example, given the total setup and hold time requirement of 110ps, a preset delay value of 300ps fully meets the timing requirement with a margin, making it suitable for resolving all synchronous sampling violations at the current clock frequency.

[0105] The method provided by the embodiments of the present invention resolves timing violations associated with clock sampling synchronization signals, ensuring consistency across multiple systems. The synchronous sampling process involves only sysref and clk, eliminating the need to generate higher-frequency clocks for phase calculation and delay adjustment. Furthermore, the exemplary system fully integrates subsystems, reducing resource consumption at the higher system level. Hardware implementation eliminates the need for excessive routing and pinout constraints.

[0106] Example 3

[0107] The embodiment of the present invention also provides a system, such as Figure 15 As shown, the system 90 includes:

[0108] Hold time detection circuit 900 and hold time coding circuit 902, setup time detection circuit 904 and setup time coding circuit 906, timing violation judgment and phase correction circuit 908, and signal delay circuit 910.

[0109] The input end of the hold time detection circuit 900 is connected to the output end of the signal delay circuit 910 and the input end of the setup time detection circuit 904, and the output end is connected to the input end of the hold time coding circuit 902. The output end of the setup time detection circuit 904 is connected to the input end of the setup time coding circuit 906. The input end of the timing violation determination and phase correction circuit 908 is connected to the output ends of the hold time coding circuit 902 and the setup time coding circuit 906, and the output end is connected to the signal delay circuit 910.

[0110] The hold time detection circuit 900 uses the synchronization signal sysref to sample the clock signal clk after the step delay, and the hold time coding circuit 902 is used to binary encode and map the sampling result obtained by the hold time detection circuit 900; the setup time detection circuit 904 uses the step delay synchronization signal sysref to sample the clock signal clk, and the setup time coding circuit 906 is used to binary encode and map the sampling result obtained by the setup time detection circuit 904; the timing violation judgment and phase correction circuit 908 is used to segmentally judge the timing violation status of the current synchronization circuit based on the coding and mapping results of the hold time coding circuit 902 and the setup time coding circuit 906, and release the phase modulation control codeword; the signal delay circuit 910 adjusts the signal to be corrected according to the phase modulation control codeword.

[0111] In one embodiment, the holding time detection circuit includes a specified number of customized inverters and a high-speed flip-flop.

[0112] In one embodiment, the signal delay circuit includes a coarse adjustment circuit and a fine adjustment circuit. The coarse adjustment circuit includes a specified number of inverters connected in series, and the fine adjustment circuit includes a specified number of groups of identical switch capacitors.

[0113] As for the system embodiment, since it is basically similar to the aforementioned method embodiment, the relevant parts can be referred to the partial description of the method embodiment and will not be repeated here.

[0114] The synchronous signal sampling violation resolution system provided by the embodiment of the present invention only involves the sysref signal and the clk signal in the synchronous sampling process. There is no need to generate a higher-frequency clock to calculate the phase and adjust the delay to resolve the timing violation of the clock sampling synchronous signal, thereby ensuring consistency between multiple modules or multiple systems. The system or device provided by the embodiment of the present invention can be fully integrated within each subsystem, reducing resource consumption at the system level, and there is no need to impose too many constraints on routing and pins during hardware implementation.

[0115] Example 4

[0116] The embodiment of the present invention further provides an electronic device, such as Figure 16 As shown, it includes a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302, and the memory 303 communicate with each other through the communication bus 304.

[0117] Memory 303, used for storing computer programs;

[0118] The processor 301 is configured to execute the program 305 stored in the memory 303, and implement the following steps:

[0119] The clock signal clk that has undergone a step delay is sampled using the synchronization signal sysref through the hold time detection circuit, and the clock signal clk is sampled using the step delay synchronization signal sysref through the setup time detection circuit; the sampling result obtained by the hold time detection circuit is input into the hold time coding circuit for binary coding and mapping, and the sampling result obtained by the setup time detection circuit is input into the setup time coding circuit for binary coding and mapping; the timing violation judgment and phase correction circuit is used to judge the timing violation status of the current synchronization circuit in segments based on the coding and mapping results of the hold time coding circuit and the setup time coding circuit, and release the phase modulation control codeword; according to the phase modulation control codeword, the signal delay circuit is controlled to adjust the signal to be corrected.

[0120] The communication bus mentioned in the electronic device mentioned above may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or only one type of bus.

[0121] The communication interface is used for communication between the above electronic device and other devices.

[0122] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0123] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0124] The method provided in the embodiments of the present invention can be applied to electronic devices. Specifically, the electronic devices can be desktop computers, portable computers, smart mobile terminals, servers, etc. This is not limited here; any electronic device that can implement the present invention falls within the scope of protection of the present invention.

[0125] As for the electronic device / storage medium embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0126] It should be noted that the electronic device and storage medium of the embodiments of the present invention are respectively the electronic device and storage medium to which the above-mentioned solution to the synchronization signal sampling violation is applied. All embodiments of the above-mentioned solution to the synchronization signal sampling violation are applicable to the electronic device and storage medium, and can achieve the same or similar beneficial effects.

[0127] By using the terminal device provided by the embodiment of the present invention, proper nouns and / or fixed phrases can be displayed for user selection, thereby reducing user input time and improving user experience.

[0128] The terminal device exists in various forms, including but not limited to:

[0129] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and are primarily designed to provide voice and data communications. These terminals include smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones.

[0130] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0131] (3) Portable entertainment devices: These devices can display and play multimedia content. These devices include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0132] (4) Other electronic devices with data interaction functions.

[0133] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0134] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0135] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0136] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices (equipment), or computer program products. Therefore, the application can adopt the form of complete hardware embodiment, complete software embodiment, or the embodiment in combination with software and hardware, which are all collectively referred to as "module" or "system" herein. Moreover, the application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The computer program is stored / distributed in a suitable medium, provided together with other hardware or as a part of hardware, or other distribution forms can be adopted, such as by the Internet or other wired or wireless telecommunication systems.

[0137] The present application is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (devices) and computer program products of the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0140] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A solution to synchronization signal sampling violation, characterized in that: The method comprises: The hold time detection circuit samples the clock signal clk with the synchronization signal sysref after the step delay, and the setup time detection circuit samples the clock signal clk with the synchronization signal sysref after the step delay; Inputting the sampling result obtained by the hold time detection circuit into the hold time coding circuit for binary coding and mapping, and inputting the sampling result obtained by the setup time detection circuit into the setup time coding circuit for binary coding and mapping; Using the timing violation judgment and phase correction circuit, based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, the timing violation status of the current synchronization circuit is judged in segments, and the phase modulation control codeword is released; According to the phase modulation control codeword, the control signal delay circuit adjusts the signal to be corrected.

2. The method according to claim 1, characterized in that The method of sampling the clock signal clk after the step delay by using the synchronization signal sysref through the hold time detection circuit includes: Through the hold time detection circuit, the synchronization signal sysref is used to sample the clock signal clk after N step delays to obtain an N-bit sampling result, where the sum of the N step delays is ≥ the hold time requirement; The step of sampling the clock signal clk using the step-delayed synchronization signal sysref by establishing a time detection circuit comprises: By setting up a time detection circuit, the clock signal clk is sampled with M step-delayed synchronization signals sysref to obtain an M-bit sampling result, where the sum of the M step delays is ≥ the settling time requirement.

3. The method according to claim 1, characterized in that The step of inputting the sampling result obtained by the holding time detection circuit into the holding time encoding circuit for binary encoding and mapping includes: Inputting the sampling result obtained by the holding time detection circuit into the holding time encoding circuit, encoding and compressing the data bit width according to the preset first encoding table, and then mapping it to the holding time encoding map; The step of inputting the sampling result obtained by the setup time detection circuit into the setup time encoding circuit for binary encoding and mapping includes: The sampling result obtained by the setup time detection circuit is input into the setup time coding circuit, and the data bit width is compressed by coding according to the preset second coding table, and then mapped to the setup time coding map.

4. The method according to claim 3, characterized in that The timing violation judgment and phase correction circuit is used to judge the timing violation status of the current synchronization circuit in segments based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, and release the phase modulation control codeword, including: The coding results of the hold time coding circuit and the setup time coding circuit are combined into a timing detection codeword by using a timing violation judgment and phase correction circuit; based on the corresponding results of the timing detection codeword in a preset timing judgment table, the timing violation status of the current synchronization circuit is judged in segments; and based on the hold time coding diagram and the setup time coding diagram, a corresponding phase modulation control codeword is generated and released to the control signal delay circuit; the phase modulation control codeword includes a coarse modulation code and a fine modulation code.

5. The method according to claim 1, wherein The controlling signal delay circuit to adjust the signal to be corrected according to the phase modulation control codeword includes: Turning on the signal delay circuit, configuring a first phase modulation control codeword, and adjusting the signal to be corrected according to the first phase modulation control codeword; determining a timing violation condition of the synchronization circuit after adjustment by the first phase modulation control codeword; If there is a violation, the signal delay circuit is turned on again, a second phase modulation control codeword is configured, and the signal to be corrected is adjusted according to the second phase modulation control codeword; determining a timing violation condition of the synchronization circuit after adjustment by the second phase modulation control codeword; If there is a violation, an error is reported; if there is no violation, the adjustment is completed.

6. The method according to claim 1, characterized in that The controlling signal delay circuit to adjust the signal to be corrected according to the phase modulation control codeword includes: According to a preset decoding table, the phase modulation control codeword is subjected to temperature code decoding processing to obtain a temperature codeword; According to the temperature codeword, the signal delay circuit is controlled to increase in delay according to a unit step length, so as to adjust the signal to be corrected.

7. A synchronous signal sampling violation resolution system, characterized in that: The system includes: a hold time detection circuit and a hold time coding circuit, a setup time detection circuit and a setup time coding circuit, a timing violation judgment and phase correction circuit, and a signal delay circuit; The input end of the hold time detection circuit is connected to the output end of the signal delay circuit and the input end of the setup time detection circuit, and the output end is connected to the input end of the hold time coding circuit; the output end of the setup time detection circuit is connected to the input end of the setup time coding circuit, the input end of the timing violation judgment and phase correction circuit is connected to the output ends of the hold time coding circuit and the setup time coding circuit, and the output end is connected to the signal delay circuit; The hold time detection circuit uses the synchronization signal sysref to sample the clock signal clk after the step delay, and the hold time encoding circuit is used to binary encode and map the sampling result obtained by the hold time detection circuit; the setup time detection circuit uses the step delayed synchronization signal sysref to sample the clock signal clk, and the setup time encoding circuit is used to binary encode and map the sampling result obtained by the setup time detection circuit; the timing violation judgment and phase correction circuit is used to segmentally judge the timing violation status of the current synchronization circuit based on the encoding and mapping results of the hold time encoding circuit and the setup time encoding circuit, and release the phase modulation control codeword; the signal delay circuit adjusts the signal to be corrected according to the phase modulation control codeword.

8. The system according to claim 7, characterized in that The hold time detection circuit includes a specified number of custom inverters and a high-speed flip-flop.

9. The system according to claim 7, wherein: The signal delay circuit includes a coarse adjustment circuit and a fine adjustment circuit. The coarse adjustment circuit includes a specified number of inverters connected in series, and the fine adjustment circuit includes a specified number of groups of identical switch capacitors.

10. An electronic device, characterized in that: The device comprises: one or more processors; a computer-readable medium configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the synchronization signal sampling violation solution according to any one of claims 1 to 6.

Images