Multilayer ceramic capacitor
By optimizing the structure and size ratio of the dielectric layer and the internal electrode layer, the problem of balancing capacitors and insulation breakdown voltages during miniaturization and large capacitance is solved, and the reliability and durability in the confined space is improved.
Patent Information
- Application Number
- CN202380090044.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-01-13
- Filing Date
- 2023-10-16
- Publication Date
- 2025-08-05
AI Technical Summary
In the process of miniaturization and large capacitance, the existing stacked ceramic capacitors are complicated to manufacture and difficult to balance the capacitor and insulation breakdown voltage in the height and width directions, affecting reliability.
A dielectric layer and internal electrode layer structure of a specific ratio is adopted, including a BaTiO3-based dielectric layer and Ni internal electrode layer, combined with the particle design of the core-shell structure, and the size ratio of the side gap part and the outer layer part is optimized by controlling the offset in the lamination direction and width direction and interface Sn segregation.
The balance of capacitance and insulation breakdown voltages is achieved in size-limited devices, which improves reliability and durability and enhances high-temperature load life.
Smart Images
Figure CN120435751A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a laminated ceramic capacitor. Background Art
[0002] In multilayer ceramic capacitors, a technology is known that can reduce withstand voltage failure while also accommodating increased capacitance (Patent Document 1). This technology achieves both reduced withstand voltage failure and increased capacitance by adjusting the curvature radius of the corners of the internal electrode layers and the curvature radius of the ridges of the laminate.
[0003] Prior art literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2005-259772 Summary of the Invention
[0006] Problems to be solved by the invention
[0007] However, in the conventional multilayer ceramic capacitor described above, the shapes of the internal electrode layers and the shapes of the ridges of the multilayer body need to be adjusted, which complicates the manufacturing process.
[0008] In recent years, due to the further performance and miniaturization of portable devices, the demand for smaller and larger-capacitance multilayer ceramic capacitors has increased. The purpose of the present invention is to provide a multilayer ceramic capacitor that can achieve a balance between capacitance and insulation breakdown voltage in devices with size constraints in the height and width directions and ensure sufficient reliability.
[0009] Technical solutions to solve problems
[0010] In order to solve the above-mentioned problems, the present invention provides a multilayer ceramic capacitor, comprising: a multilayer body, comprising a multilayer body small piece and a side gap portion, wherein the multilayer body small piece has an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, and an outer layer portion respectively arranged on both sides of the stacking direction of the inner layer portion, wherein the side gap portions are respectively arranged on both sides of the width direction of the multilayer body small piece orthogonal to the stacking direction; and external electrodes respectively arranged on both sides of the length direction of the multilayer body intersecting the stacking direction and the width direction, wherein the dielectric layer contains Ba and Ti, the internal electrode layer contains Ni, and when the dimension of the multilayer ceramic capacitor in the length direction is set to L0 and the dimension in the stacking direction is set to T0, the When the dimension in the width direction is set to W0, 1.7≤L0 / T0≤2.3, and 1.0≤W0 / T0≤1.4, in a cross section passing through the stacking direction and the width direction at the center of the longitudinal direction, when the offset in the width direction of the ends of the internal electrode layers adjacent to each other in the stacking direction is set to d, d≤5μm, Sn with an atomic composition percentage of 2at% or more is segregated at the interface between the internal electrode layer and the dielectric layer, when the dimension in the width direction of the side gap portion is set to WS and the dimension in the stacking direction of the outer layer portion is set to TG, 0.3≤WS / TG≤0.6, and the dimension WI of the internal electrode layer in the width direction is T0 <WI。
[0011] Effects of the Invention
[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can achieve a balance between capacitance and breakdown voltage within size constraints and ensure sufficient reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment.
[0014] Figure 2 yes Figure 1 sectional view of the multilayer ceramic capacitor 1 taken along line II-II.
[0015] Figure 3 yes Figure 1 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.
[0016] Figure 4 yes Figure 3 Magnified view of the S part.
[0017] Figure 5 This is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 . DETAILED DESCRIPTION
[0018] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 1 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.
[0019] (Multilayer ceramic capacitor 1)
[0020] Multilayer ceramic capacitor 1 is substantially rectangular parallelepiped and includes a laminate 2 and a pair of external electrodes 3 provided at both ends of laminate 2. Laminate 2 includes inner layer portion 11 in which a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 are stacked.
[0021] In the following description, terms indicating directions of the multilayer ceramic capacitor 1 are used. In the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the longitudinal direction L. The direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked is referred to as the stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.
[0022] In addition, in the following description, Figure 2 Of the six outer peripheral surfaces of the stacked body 2 shown, a pair of outer peripheral surfaces opposing each other in the stacking direction T is referred to as the main surface A, a pair of outer peripheral surfaces opposing each other in the width direction W is referred to as the side surface B, and a pair of outer peripheral surfaces opposing each other in the length direction L is referred to as the first end surface C1 and the second end surface C2. In the case where it is not necessary to distinguish between the first end surface C1 and the second end surface C2 for description, they are collectively referred to as the end surface C.
[0023] Regarding the multilayer ceramic capacitor 1, when the dimension in the length direction L is L0, the dimension in the stacking direction T is T0, and the dimension in the width direction W is W0, the range is preferably 1.15 ≤ L0 ≤ 1.25 μm, more preferably approximately 1.220 μm, preferably 0.65 ≤ W0 ≤ 0.75 μm, more preferably approximately 0.725 μm, and preferably 0.55 ≤ T0 ≤ 0.65 μm, more preferably approximately 0.620 μm. This ensures the required height and width dimensions and capacitance that can be installed in equipment subject to height and width dimension constraints.
[0024] Furthermore, it is preferable that 1.7≤L0 / T0≤2.3 and 1.0≤W0 / T0≤1.4. This ensures the dimensions in the height and width directions and the capacitance that can be installed in a device subject to the constraints of the dimensions in the height and width directions.
[0025] Furthermore, the ratio of L0, T0, and W0 is preferably L0:T0:W0 = 2:1:1.2. This ensures the dimensions in height and width that can be installed in a device subject to height and width dimension constraints and ensures the capacity.
[0026] (Laminate 2)
[0027] The laminate 2 includes laminate small pieces 10 and side gaps 20 .
[0028] (Laminate Small Piece 10)
[0029] The laminated small piece 10 includes an inner layer portion 11 and outer layer portions 12 arranged on both principal surface A sides of the inner layer portion 11 .
[0030] (Inner layer 11)
[0031] The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrode layers 15. Details of the dielectric layers 14 and the internal electrode layers 15 will be described later.
[0032] (Outer layer 12)
[0033] The outer layer 12 is made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer 11. The dimension TG of the outer layer 12 in the stacking direction T is preferably 36 μm ≤ TG ≤ 43 μm, and more preferably approximately 40 μm. This dimension ensures that the required capacitance can be maintained while being compatible with devices subject to size constraints.
[0034] (Side gap 20)
[0035] The side gaps 20 are provided on both side surfaces B of the laminated piece 10. The side gaps 20 cover the ends of the internal electrode layers 15 exposed on both side surfaces in the width direction W. The side gaps 20 are made of the same dielectric ceramic material as the dielectric layers 14.
[0036] (Dimensions of the side gap 20)
[0037] When the dimension WS of the width direction W of the side gap portion 20 is set to 15μm≤WS≤20μm, more preferably about 17μm. Furthermore, the ratio of the dimension WS of the width direction W of the side gap portion 20 to the dimension TG of the stacking direction T of the outer layer portion 12 is preferably 0.3≤WS / TG≤0.6, more preferably 0.4≤WS / TG≤0.5. By setting this dimension ratio, a size that can be installed in equipment with size restrictions can be achieved while ensuring the required capacitance.
[0038] (External electrode 3)
[0039] The external electrodes 3 include a first external electrode 3A provided on the first end surface C1 of the stacked body 2, and a second external electrode 3B provided on the second end surface C2 of the stacked body 2. When there is no need to distinguish between the first external electrode 3A and the second external electrode 3B for description, they are collectively referred to as the external electrodes 3. The external electrodes 3 cover not only the end surface C but also a portion of the principal surface A and the side surface B on the side of the end surface C.
[0040] (Dielectric layer 14)
[0041] Figure 4 yes Figure 3 An enlarged view of the S portion of the dielectric layer 14. Dielectric layer 14 comprises BaTiO3 containing Ba and Ti as a base material. Furthermore, BaTiO3 contains rare earth elements such as Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb as a solid solution as the first element M1, and Ni diffused from internal electrode layer 15 and other optionally added additive elements as a solid solution as the second element M2. BaTiO3 containing Ba and Ti is a ferroelectric base material with a very large dielectric constant, thereby significantly increasing the capacitance of the multilayer ceramic capacitor 1.
[0042] M1 is due to the Ba in the lattice of the BaTiO3 perovskite compound. 2+ Part of M1 3+ Ni is substituted and solid-dissolved in the particle 140. Ni is substituted and solid-dissolved in the particle 140. 4+ A portion of is replaced by Ni2+ and dissolved in the particles 140.
[0043] Dielectric layer 14 includes a plurality of particles 140. Each particle 140 has a core-shell structure comprising a core 141 located in the center and a shell 142 surrounding core 141. Core 141 contains less of the aforementioned elements in solid solution than shell 142, resulting in a structure closer to pure BaTiO3. The molar ratio of Ba to Ti in particles 140 of core 141 is higher than that in particles 140 of shell 142.
[0044] Since the molar ratio of Ba to Ti contained in the particles 140 of the core portion 141 is higher than the molar ratio of Ba to Ti contained in the particles 140 of the shell portion 142 , the insulation resistance is improved.
[0045] The shell 142 has a larger amount of the first element M1 than the core 141. Therefore, near the grain boundary, the M1 3+ and Ba 2+ Ba vacancies are generated by substitution of BaTiO3. As a result, oxygen vacancies are bound to Ba vacancies within dielectric layer 14, thereby suppressing the movement of oxygen vacancies in dielectric layer 14 when a DC voltage is applied. As a result, the reliability of multilayer ceramic capacitor 1 including dielectric layer 14 containing BaTiO3 is improved.
[0046] However, the particle 140 is not limited to the core-shell structure, and the first element and the second element may be uniformly distributed throughout the particle 140 .
[0047] (Number of particles in dielectric layer 14)
[0048] The multilayer ceramic capacitor 1 according to the embodiment is described below as an example.
[0049] Rated voltage: 6.3V
[0050] Initial capacitance: 15μF
[0051] Effective capacitance: 5μF at DC3V
[0052] Insulation breakdown voltage: 60V
[0053] In this case, the thickness (dimension in the stacking direction T) TD of dielectric layer 14 is preferably 0.67 μm ≤ TD ≤ 0.73 μm, more preferably approximately 0.70 μm. The number of dielectric layers 14 is preferably 405 or more and 430 or less. The particle size of particles 140 is preferably 150 nm or more and 200 nm, and the average number GN of particles 140 in the thickness direction (stacking direction T) of dielectric layer 14 is preferably 3 ≤ GN ≤ 4.
[0054] By setting the thickness (dimension in the stacking direction T) TD of the dielectric layer 14 to 0.67 μm ≤ TD ≤ 0.73 μm or less, it is possible to achieve a size of the multilayer ceramic capacitor 1 that can be mounted in a device whose overall height dimension of the multilayer ceramic capacitor 1 is restricted. By setting the average value GN of the number of particles 140 in the thickness direction (stacking direction T) of the dielectric layer 14 to 3 ≤ GN ≤ 4, it is possible to achieve a size that can be mounted in a device with size restrictions, and it is possible to suppress a decrease in the insulation resistance of the dielectric layer 14.
[0055] Furthermore, the multilayer ceramic capacitor 1 according to the embodiment is described below as another example.
[0056] Required characteristics: 10V
[0057] Initial capacitance: 10μF
[0058] Effective capacitance: 4μF at DC3V
[0059] Insulation breakdown voltage: 80V
[0060] In this case, the thickness (dimension in the stacking direction T) TD of dielectric layer 14 is preferably 0.85 μm ≤ TD ≤ 0.91 μm, more preferably approximately 0.88 μm. The number of dielectric layers 14 is preferably 350 or more and 375 or less. The particle size of particles 140 is preferably 150 nm or more and 200 nm, and the average number GN of particles 140 in the thickness direction (stacking direction T) of dielectric layer 14 is preferably 4 ≤ GN ≤ 5.
[0061] By setting the thickness (dimension in the stacking direction T) TD of the dielectric layer 14 to be 0.85 μm ≤ TD ≤ 0.91 μm or less, it is possible to achieve a size of the multilayer ceramic capacitor 1 that can be mounted in a device where the overall height dimension of the multilayer ceramic capacitor 1 is restricted. By setting the average value GN of the number of particles 140 in the thickness direction (stacking direction T) of the dielectric layer 14 to 4 ≤ GN ≤ 5, it is possible to comply with the dimensional restriction in the height direction and suppress a decrease in the insulation resistance of the dielectric layer 14.
[0062] As will be described later, facing portions 152 of adjacent internal electrode layers 15 serve as effective portions that function as capacitors. The particle diameter of dielectric layer 14 between these effective portions is preferably larger than that of the dielectric particles in side gaps 20 .
[0063] Regarding the dielectric, a larger particle diameter results in a higher dielectric constant, while a smaller particle diameter leads to higher moisture resistance and good durability. The particle diameter of the dielectric layer 14 between the active portions is larger than that of the dielectric in the side clearance portion 20. Therefore, a high dielectric constant can be ensured between the active portions, and sufficient capacitance can be ensured. In addition, high moisture resistance can be obtained in the side clearance portion 20, so high moisture resistance and durability can be obtained as a whole.
[0064] (Internal electrode layer 15)
[0065] When the dimension of the internal electrode layer 15 in the width direction W is set as WI, T0 < WI. In addition, when the dimension (thickness) of the internal electrode layer 15 in the stacking direction T is set as T1, it is preferable that 0.49 μm ≤ T1 ≤ 0.55 μm, and more preferably around 0.53 μm.
[0066] By setting T0 < WI when the dimension of the internal electrode layer 15 in the width direction W is set as WI, the height of the multilayer ceramic capacitor 1 that can be mounted in a device with dimensional constraints can be ensured, and the internal electrode area can be ensured to be wide. Therefore, the capacitance of the multilayer ceramic capacitor 1 can be ensured to be large.
[0067] In addition, the internal electrode layer 15 is formed of a metal material, but it is not filled with the metal material without gaps. There are portions in the internal electrode layer 15 that contain voids where there is no metal material. When the ratio of the metal material in the internal electrode layer 15 is set as the coverage rate (coating rate), this coverage rate is preferably 85% or more.
[0068] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately arranged. In addition, when there is no need to particularly distinguish between the first internal electrode layer 15A and the second internal electrode layer 15B for explanation, they are uniformly described as the internal electrode layer 15.
[0069] The first internal electrode layer 15A includes a first opposing portion 152a that opposes the second internal electrode layer 15B, and a first lead-out portion 151a that extends from the first opposing portion 152a toward the first end face C1 side. The end of the first lead-out portion 151a is exposed on the first end face C1 and is electrically connected to the first external electrode 3A described later.
[0070] The second internal electrode layer 15B includes a second opposing portion 152b that opposes the first internal electrode layer 15A, and a second lead-out portion 151b that extends from the second opposing portion 152b toward the second end face C2. The end of the second lead-out portion 151b is electrically connected to the second external electrode 3B described later.
[0071] With the internal electrode layers 15 described above, charge is stored in the first opposing portion 152a of the first internal electrode layer 15A and the second opposing portion 152b of the second internal electrode layer 15B, thereby functioning as capacitors. The opposing portions 152 of the adjacent internal electrode layers 15 are effective portions that function as capacitors.
[0072] (Offset d)
[0073] Although described later, the laminated small piece 10 is formed by cutting a mother block, so the side surfaces are formed flat by cutting, exposing the ends of the internal electrode layer 15. The side gaps 20 are formed on both side surfaces of the laminated small piece 10 by a so-called side gap 20 post-attachment method.
[0074] Therefore, if Figure 3 As shown, in the cross section WT, which passes through the center of the stack 2 in the width direction W and the stacking direction T, the positional offset d between the width direction W end portions of the first and second internal electrode layers 15A, 15B, which are vertically adjacent in the stacking direction T, is small, d ≤ 5 μm. In other words, the width direction W end portions of the first and second internal electrode layers 15A, 15B, which are vertically adjacent in the stacking direction T, are located at substantially the same position in the width direction W, and their positions are consistent in the stacking direction T.
[0075] When d≦5 μm, the area of the internal electrode layer 15 can be ensured to be as wide as possible within the size restriction, thereby ensuring a higher capacitance of the multilayer ceramic capacitor 1 .
[0076] The internal electrode layer 15 has Ni as its main component and also contains Sn. Furthermore, in the interface vicinity region 153 of the internal electrode layer 15, which is approximately 20 nm from the surface facing the dielectric layer 14, Sn is segregated at an atomic composition percentage of 2 at% or more. In other words, Figure 4 The illustrated interface vicinity region 153 contains more Sn than other portions of the internal electrode layer 15 .
[0077] Internal electrode layer 15 is formed by firing a conductive paste for forming the internal electrode, which contains Ni powder, Ni-Sn alloy powder, and a common material containing a Sn component. During the firing process, the common material containing the Sn component is attracted to the dielectric layer 14, which has a high affinity for the material. Furthermore, the Sn component mixed in the common material is also attracted to the dielectric layer 14.
[0078] As a result, Sn is more likely to be present in the interface region 153 near the dielectric layer 14 than within the internal electrode layer 15. This causes Ni-Sn alloying in the internal electrode layer 15, changing the state of the interface region 153 near the interface. Specifically, the alloying of Ni and Sn (Ni-Sn alloying) changes the state (potential barrier height) of the interface between the ceramic dielectric layer 14 and the internal electrode layer 15, which is believed to contribute to an improvement in high-temperature load life. In particular, the presence of a high amount of Ni-Sn alloy in the interface region 153 near the interface is believed to play a significant role in improving the high-temperature load life. Consequently, a highly reliable multilayer ceramic capacitor 1 with excellent high-temperature load life can be obtained.
[0079] (Method for Manufacturing Multilayer Ceramic Capacitor 1)
[0080] Figure 5 This is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 .
[0081] The method for manufacturing the multilayer ceramic capacitor 1 includes a raw material sheet preparing step S1 , a raw material sheet laminating step S2 , a mother block cutting step S3 , a side gap forming step S4 , a first firing step S5 , an external electrode forming step S6 , and a second firing step S7 .
[0082] (Raw material sheet production process S1)
[0083] A raw material powder is obtained by adding powders containing the first element M1 and other additive elements to a barium titanate-based perovskite compound powder containing Ti and Ba. A ceramic slurry containing the raw material powder, a binder, and a solvent is prepared.
[0084] The ceramic slurry is formed into a sheet on a carrier film using a die coater, a gravure coater, a micro gravure coater, or the like, thereby producing a ceramic green sheet for the inner layer portion 11 and a ceramic green sheet for the outer layer portion 12 .
[0085] A conductive paste for forming the internal electrodes, which contains Ni powder, Ni-Sn alloy powder, and a common material mixed with Sn components, is printed onto the ceramic green sheet for the inner layer portion 11 by screen printing, inkjet printing, gravure printing, or the like, forming a stripe-shaped pattern. This prepares a raw material sheet in which the conductive paste for forming the internal electrode layer 15 is printed on the surface of the ceramic green sheet for the inner layer portion 11, which will become the dielectric layer 14.
[0086] (Raw material sheet stacking step S2)
[0087] Specifically, the plurality of raw material sheets are stacked so that the strips of conductive paste face the same direction and are offset by half a pitch in the width direction W between adjacent raw material sheets.
[0088] Furthermore, ceramic green sheets for the outer layer portion 12 are stacked on both sides of the stacked raw material sheets. The stacked raw material sheets and the ceramic green sheets for the outer layer portion 12 are then thermocompressed to form a mother block.
[0089] (Master block cutting process S3)
[0090] Next, the mother block is cut into a size corresponding to the size of the laminated body small piece 10 .
[0091] (Side Gap Forming Step S4)
[0092] Next, ceramic green sheets for side gaps are attached to both sides of the laminated small piece 10 to form layers that will become the side gaps 20. Since the laminated small piece 10 is formed by cutting a mother block, the side faces are flattened by the cutting, exposing the ends of the internal electrode layers 15. The side gaps 20 are formed on both sides of the laminated small piece 10 using a so-called side gap post-attachment process.
[0093] (First Firing Step S5)
[0094] The small pieces of the stacked small pieces 10 in which the layers forming the side gap portions 20 are formed are degreased in a nitrogen atmosphere under predetermined conditions, and then fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to form the stacked body 2.
[0095] Internal electrode layer 15 is formed by firing a conductive paste for forming the internal electrode, which contains Ni powder, Ni-Sn alloy powder, and a common material containing a Sn component. During this firing process, the common material containing the Sn component is attracted to the dielectric layer 14, which has a high affinity for the material. Furthermore, the Sn component mixed in the common material is also attracted to the dielectric layer 14.
[0096] (External Electrode Forming Step S6)
[0097] Next, a conductive paste for forming the external electrodes 3 is applied to the end surface C of the laminate 2 .
[0098] (Second Firing Step S7)
[0099] Then, the laminate 2 is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time. This allows the external electrodes 3 to be baked onto the laminate 2, thereby manufacturing the laminated ceramic capacitor 1.
[0100] Alternatively, the first firing step may not be included, and the laminated body 2 may be fired together with the external electrodes 3 in the second firing step.
[0101] As described above, the multilayer ceramic capacitor 1 according to the embodiment includes:
[0102] A laminate 2 includes a laminated body piece 10 having an inner layer portion 11 in which dielectric layers 14 and internal electrode layers 15 are alternately stacked, and outer layer portions 12 arranged on both sides of the inner layer portion 11 in a stacking direction T, and side gap portions 20 arranged on both sides of the laminated body piece 10 in a width direction W orthogonal to the stacking direction T; and
[0103] The external electrodes 3 are arranged on both sides of the length direction L that intersects the stacking direction T and the width direction W of the stacked body 2.
[0104] The dielectric layer 14 contains Ba and Ti, and the internal electrode layer 15 contains Ni.
[0105] When the dimension of the multilayer ceramic capacitor 1 in the longitudinal direction L is L0, the dimension in the stacking direction T is T0, and the dimension in the width direction W is W0,
[0106] 1.7≤L0 / T0≤2.3, and 1.0≤W0 / T0≤1.4,
[0107] In a cross section passing through the stacking direction T and the width direction W at the center of the longitudinal direction L, when the positional offset in the width direction W of the ends of the internal electrode layers 15 adjacent to each other in the stacking direction T is d, d≤5μm,
[0108] At the interface between the internal electrode layer 15 and the dielectric layer 14, Sn having an atomic composition percentage of 2 at % or more is segregated.
[0109] When the dimension of the side gap portion 20 in the width direction W is denoted as WS and the dimension of the outer layer portion 12 in the stacking direction T is denoted as TG, 0.3≤WS / TG≤0.6,
[0110] When the dimension of the width direction W of the internal electrode layer 15 is denoted as WI, T0 <WI。
[0111] (Effect)
[0112] As described above, Sn with an atomic composition percentage of 2 at% or more segregates at the interface between the internal electrode layer 15 and the dielectric layer 14. This causes Ni-Sn alloying in the internal electrode layer 15, changing the state of the interface between the dielectric layer 14 and the internal electrode layer 15. Specifically, Ni and Sn form an alloy (Ni-Sn alloying), which changes the state (potential barrier height) of the interface between the ceramic dielectric layer 14 and the internal electrode layer 15. This results in a highly reliable multilayer ceramic capacitor 1 with an improved high-temperature load life.
[0113] In addition, when the offset amount of the positions in the width direction W at the ends in the width direction W of the internal electrode layers 15 adjacent to each other in the stacking direction T in the cross-section passing through the stacking direction T and the width direction W at the center in the length direction L is set as d, d ≤ 5 μm. Therefore, when the dimension in the stacking direction T of the outer layer portion 12 is set as TG, the dimension WS in the width direction W of the side gap portion 20 can be thinned to 0.3 ≤ WS / TG ≤ 0.6. Thus, when the dimension in the length direction L of the multilayer ceramic capacitor 1 is set as L0, the dimension in the stacking direction T is set as T0, and the dimension in the width direction W is set as W0, at dimensions where 1.7 ≤ L0 / T0 ≤ 2.3 and 1.0 ≤ W0 / T0 ≤ 1.4, the dimension WI in the width direction W of the internal electrode layer 15 can be increased to T0 < WI, thereby increasing the area of the internal electrode layer 15.
[0114] In addition, when the dimension in the stacking direction T of the dielectric layer 14 is set as TD, in the case of 0.67 μm ≤ TD ≤ 0.73 μm, the average value of the number of particles in the stacking direction T in the dielectric layer 14 is 3 ≤ GN ≤ 5. That is, the average value GN of the number of particles is relatively large. Therefore, compared with the case where the number of particles is 1, the grain boundaries in the dielectric layer 14 become more, and thus the insulation resistance value becomes higher and the durability is improved.
[0115] In addition, when the dimension in the stacking direction T of the dielectric layer 14 is set as TD, in the case of 0.85 μm ≤ TD ≤ 0.91 μm, the average value of the number of particles in the stacking direction T in the dielectric layer 14 is 4 ≤ GN ≤ 5. That is, the average value GN of the number of particles is relatively large. Therefore, compared with the case where the number of particles is 1, the grain boundaries in the dielectric layer 14 become more, and thus the insulation resistance value becomes higher and the durability is improved.
[0116] Regarding the multilayer ceramic capacitor 1, the dimension L0 in the length direction L is 1.15 ≤ L0 ≤ 1.25 μm, the dimension W0 in the width direction W is 0.65 ≤ W0 ≤ 0.75 μm, the dimension T0 in the stacking direction T is 0.55 ≤ T0 ≤ 0.65 μm, the dimension WS in the width direction W of the side gap portion 20 is 15 μm ≤ WS ≤ 20 μm, and the dimension TG in the stacking direction T of each of the outer layer portions 12 is 36 μm ≤ TG ≤ 43 μm. Therefore, in equipment restricted by dimensions, it is a dimension with high versatility that ensures the balance between capacitance and insulation breakdown voltage.
[0117] Dielectric layer 14 includes a plurality of particles 140. Particles 140 have a core-shell structure including a core 141 and a shell 142 surrounding core 141. The molar ratio of Ba to Ti in particles 140 in core 141 is higher than the molar ratio of Ba to Ti in particles 140 in shell 142. Therefore, the temperature characteristics of the dielectric constant can be flattened, thereby improving reliability.
[0118] As described above, according to the multilayer ceramic capacitor 1 of the embodiment, it is possible to provide a multilayer ceramic capacitor 1 that can achieve a balance among initial capacitance, effective capacitance, and breakdown voltage within size constraints and ensure sufficient reliability.
[0119] While the embodiments of the present invention have been described above, the present invention includes the following combinations.
[0120] <1> A laminated ceramic capacitor comprising: a laminated body including a laminated body piece and side gap portions, wherein the laminated body piece includes an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions arranged on both sides of the inner layer portion in a lamination direction, the side gap portions being arranged on both sides of the laminated body piece in a width direction perpendicular to the lamination direction; and
[0121] The external electrodes are respectively arranged on both sides of the length direction of the stacked body intersecting the stacking direction and the width direction, wherein
[0122] The dielectric layer contains Ba and Ti, and the internal electrode layer contains Ni.
[0123] When the dimension of the multilayer ceramic capacitor in the longitudinal direction is L0, the dimension in the stacking direction is T0, and the dimension in the width direction is W0,
[0124] 1.7≤L0 / T0≤2.3, and 1.0≤W0 / T0≤1.4,
[0125] In a cross section passing through the stacking direction and the width direction at the center of the longitudinal direction, when the positional offset in the width direction of the ends of the internal electrode layers adjacent to each other in the stacking direction is d, d≤5μm,
[0126] At the interface between the internal electrode layer and the dielectric layer, Sn having an atomic composition percentage of 2 at % or more is segregated.
[0127] When the dimension of the side gap portion in the width direction is WS and the dimension of the outer layer portion in the stacking direction is TG, 0.3≤WS / TG≤0.6,
[0128] The width dimension WI of the internal electrode layer is T0 <WI。
[0129] <2> according to <1> The multilayer ceramic capacitor, wherein
[0130] When the dimension of the dielectric layer in the stacking direction is defined as TD, 0.67 μm ≤ TD ≤ 0.73 μm, and
[0131] The dielectric layer includes a plurality of particles, and an average number of particles in the dielectric layer in the stacking direction is 3≤GN≤4.
[0132] <3> according to <1> The multilayer ceramic capacitor, wherein
[0133] When the dimension of the dielectric layer in the stacking direction is defined as TD, 0.85 μm ≤ TD ≤ 0.91 μm, and
[0134] The dielectric layer includes a plurality of particles, and an average number of particles in the stacking direction of the dielectric layer is 4≤GN≤5.
[0135] <4> according to <1> to <3> The multilayer ceramic capacitor according to any one of the preceding claims, wherein:
[0136] The length dimension L0 is 1.15≤L0≤1.25μm,
[0137] The width dimension W0 is 0.65≤W0≤0.75μm,
[0138] The dimension T0 in the stacking direction is 0.55≤T0≤0.65μm,
[0139] The width dimension WS of the side gap portion is 15 μm ≤ WS ≤ 20 μm.
[0140] A dimension TG of each of the outer layer portions in the stacking direction is 36 μm ≤ TG ≤ 43 μm.
[0141] <5> according to <1> to <4> The multilayer ceramic capacitor according to any one of the preceding claims, wherein:
[0142] The dielectric layer comprises a plurality of particles,
[0143] The particles have a core-shell structure, which includes a core portion and a shell portion surrounding the core portion.
[0144] The molar ratio of Ba to Ti contained in the particles of the core portion is higher than the molar ratio of Ba to Ti contained in the particles of the shell portion.
[0145] Description of Reference Numerals
[0146] 1: Multilayer ceramic capacitor;
[0147] 2: laminate;
[0148] 3: external electrode;
[0149] 10: small piece of laminate;
[0150] 11: inner layer;
[0151] 12: outer layer;
[0152] 14: dielectric layer;
[0153] 15: internal electrode layer;
[0154] 20: lateral clearance;
[0155] 140: granules;
[0156] 141: nuclear department;
[0157] 142: shell;
[0158] 151a: Departure;
[0159] 151b: Departure;
[0160] 152: Opposing part;
[0161] 152a: First opposing portion;
[0162] 152b: second opposing portion;
[0163] 153: Area near the interface.
Claims
1. A multilayer ceramic capacitor comprising: a laminate having a laminated body piece and side gap portions, the laminated body piece having an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions arranged on both sides of the inner layer portion in a lamination direction, the side gap portions being arranged on both sides of the laminated body piece in a width direction perpendicular to the lamination direction; and external electrodes arranged on both sides of the laminate in a length direction intersecting the lamination direction and the width direction, wherein: The dielectric layer contains Ba and Ti, and the internal electrode layer contains Ni. When the dimension of the multilayer ceramic capacitor in the longitudinal direction is L0, the dimension in the stacking direction is T0, and the dimension in the width direction is W0, 1.7≤L0 / T0≤2.3, and 1.0≤W0 / T0≤1.4, In a cross section passing through the stacking direction and the width direction at the center of the longitudinal direction, when the positional offset in the width direction of the ends of the internal electrode layers adjacent to each other in the stacking direction is d, d≤5μm, At the interface between the internal electrode layer and the dielectric layer, Sn having an atomic composition percentage of 2 at % or more is segregated. When the dimension of the side gap portion in the width direction is WS and the dimension of the outer layer portion in the stacking direction is TG, 0.3≤WS / TG≤0.6, The width dimension WI of the internal electrode layer is T0 <WI。 2. The multilayer ceramic capacitor according to claim 1, wherein When the dimension of the dielectric layer in the stacking direction is defined as TD, 0.67 μm ≤ TD ≤ 0.73 μm, and The dielectric layer includes a plurality of particles, and an average number of particles in the dielectric layer in the stacking direction is 3≤GN≤4.
3. The multilayer ceramic capacitor according to claim 1, wherein When the dimension of the dielectric layer in the stacking direction is defined as TD, 0.85 μm ≤ TD ≤ 0.91 μm, and The dielectric layer includes a plurality of particles, and an average number of particles in the stacking direction of the dielectric layer is 4≤GN≤5.
4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The length dimension L0 is 1.15≤L0≤1.25μm, The width dimension W0 is 0.65≤W0≤0.75μm, The dimension T0 in the stacking direction is 0.55≤T0≤0.65μm, The width dimension WS of the side gap portion is 15 μm ≤ WS ≤ 20 μm. A dimension TG of each of the outer layer portions in the stacking direction is 36 μm ≤ TG ≤ 43 μm.
5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The dielectric layer comprises a plurality of particles, The particles have a core-shell structure, which includes a core portion and a shell portion surrounding the core portion. The molar ratio of Ba to Ti contained in the particles of the core portion is higher than the molar ratio of Ba to Ti contained in the particles of the shell portion.
Citation Information
Patent Citations
Laminated ceramic capacitor
JP2005259772A