Preparation method for protecting advanced process semiconductor sample structure in material analysis

Abstract

The invention provides a preparation method for protecting an advanced process semiconductor sample structure in material analysis, and relates to the field of preparation methods of semiconductor samples, and the preparation method comprises the following steps: S1, preparing an advanced process semiconductor sample; s2, preparing an aluminum oxide layer on the surface of the semiconductor sample; s3, preparing a graphene material; s4, covering the surface of the aluminum oxide layer with a graphene layer; and S5, repeating the step S4, and covering the surface of the advanced process semiconductor sample with a plurality of graphene layers. The graphene which is stable in chemical component, good in ductility and high in mechanical strength is used for replacing an original protective layer, the preparation method is simple, the preparation temperature (room temperature) is low, and the test piece cannot be deformed or damaged due to irradiation of electron beams or ion beams. The preparation quality and efficiency of the protection layer of the advanced process semiconductor sample in material analysis are effectively improved, the semiconductor sample is prevented from being deformed or damaged, the semiconductor sample structure below can be effectively protected, and the analysis yield of an advanced semiconductor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor sample preparation methods, and in particular to a preparation method for protecting advanced process semiconductor sample structures in material analysis. Background Art

[0002] Currently, to prevent deformation or damage to semiconductor sample structures during sample preparation for materials analysis, a protective layer is typically applied to the sample surface. Three main methods exist for applying protective layers to semiconductor sample structures: physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Based on the characteristics of the semiconductor sample structure, an appropriate target material or precursor is selected to deposit the protective layer on the sample surface to protect the sample.

[0003] However, all three of these techniques require the semiconductor sample to be placed in a specific chamber during the fabrication process. To ensure the cleanliness of the protective layer, the fabrication environment must be kept in a vacuum. Due to the growth mechanism of the protective layer, the sample temperature must also be kept within a certain range (100-200 degrees Celsius) during the fabrication process. PVD may even expose the sample to ion beam radiation.

[0004] Advanced semiconductor samples have small critical dimensions (CDs), ranging from 10-50 nanometers. Using PVD or CVD methods to prepare these samples can result in incomplete coverage of the protective layer. This complicates subsequent focused ion beam (FIB) preparation, causing tool marks and distorting the interpretation of the results. Furthermore, the materials used in advanced semiconductor samples are relatively fragile and susceptible to deformation or damage due to temperature, electron beams, or ion beams. For example, photoresist materials react and deteriorate if the sample temperature exceeds 50-60°C. PVD or CVD methods for preparing protective layers require sample temperatures exceeding 100°C, making them unsuitable for preparing protective layers for advanced semiconductor samples. While ALD can lower the process temperature to room temperature, it still requires the sample to be placed in a vacuum chamber. Furthermore, due to its slow growth rate, preparation takes longer than other methods, making it suitable only for thinner protective layers. Summary of the Invention

[0005] The present invention aims to address the shortcomings of the prior art by proposing a method for preparing a protective layer for protecting advanced semiconductor sample structures during material analysis. This method replaces the existing protective layer with graphene, a chemically stable, ductile, and mechanically strong material. The preparation method is simple and operates at a low temperature (room temperature), preventing the sample from deformation or damage from electron or ion beam irradiation.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A preparation method for protecting advanced process semiconductor sample structures in material analysis, comprising the following steps: S1: Prepare advanced process semiconductor samples; Prepare advanced process semiconductor samples, the surface of which includes semiconductor structures; S2: Preparation of aluminum oxide layer on the surface of semiconductor sample; A layer of aluminum oxide is deposited on the surface of a semiconductor sample using atomic layer deposition. This ensures uniform thickness and easy control of the thickness, ensuring that the aluminum oxide can be evenly and flatly spread across the entire test piece. Atomic layer deposition can be performed at room temperature to avoid high temperatures that damage the advanced semiconductor structure.

[0007] S3: prepare graphene material; Purchase graphene sheets; graphene sheets use copper foil as a substrate, and the graphene is laid flat on the copper foil substrate by van der Waals forces; each piece of graphene purchased is used as a graphene / copper foil substrate test piece for future use; the simple structure makes it easy to separate the graphene from the copper foil substrate and transfer the graphene layer to the semiconductor sample.

[0008] S4: covering the surface of the aluminum oxide layer with a graphene layer; Using a focused ion beam machine, graphene on a copper foil substrate is transferred to the surface of a semiconductor sample prepared with an aluminum oxide layer at room temperature, forming a graphene layer. Graphene has a stable chemical composition, good ductility, and high mechanical strength. As a protective layer, it can withstand irradiation or cutting by electron or ion beams during sample preparation, effectively protecting the underlying structure.

[0009] S5: Repeat step S4 to coat the surface of the advanced semiconductor sample with multiple graphene layers. The multi-layer graphene layer protects the surface of the semiconductor, preventing damage to the semiconductor structure and improving the semiconductor analysis yield.

[0010] The present invention uses graphene materials with stable chemical composition, good ductility, and high mechanical strength to make the protective layer. The preparation method is simple and can be transferred to the semiconductor at room temperature. Since graphene has only one atomic layer, when it is pasted on an advanced process semiconductor sample, it is easy to fit closely along the sample surface contour at room temperature in order to reduce the surface energy of the test piece, and it will not cause deformation or damage to the sample surface structure. At the same time, it also ensures that subsequent graphene can also be easily stacked tightly layer by layer. In addition, the high mechanical strength of graphene can withstand the irradiation or cutting of electron beams or ion beams during the sample preparation process, effectively protecting the underlying structure and having strong protective properties.

[0011] Furthermore, step S4 includes: 1) Place the graphene / copper foil substrate specimen on the specimen carrier in the focused ion beam instrument, with the graphene facing upwards; 2) Move the specimen stage of the focused ion beam machine toward the tungsten nanoprobe, stopping at a distance of 1-2 mm. Move the tungsten nanoprobes individually until they touch the four corners of the graphene. 3) Using a focused ion beam machine, platinum was evaporated onto the surface where the tungsten nanoprobe tip contacts the graphene. 4) Move the specimen stage of the focused ion beam instrument away from the tungsten nanoprobe to separate the graphene from the copper foil substrate, leaving the graphene suspended in the air. 5) Place the semiconductor sample with the aluminum oxide layer on the specimen stage of the focused ion beam instrument and move the specimen stage toward the tungsten nanoprobes, stopping at a distance of 0.1-0.2 mm. Then, move the specimen stage to position the semiconductor sample in the middle of the four tungsten nanoprobes. 6) Using a focused ion beam (FIB) system, the tip of four tungsten nanoprobes is sequentially cut off, leaving only the first 100-150 nanometers of material. The graphene is then deposited onto a semiconductor sample coated with an aluminum oxide layer, conforming to the surface contours of the sample to form a graphene layer. This simple and easy-to-use protective layer is prepared by transferring the graphene layer at room temperature, preventing damage to the semiconductor during advanced manufacturing processes. The high bonding strength of graphene and aluminum oxide ensures a tight bond between the graphene and the surface of the semiconductor sample, preventing voids and shedding of the protective layer, thereby extending the protective layer's effectiveness.

[0012] Furthermore, the thickness of the aluminum oxide layer is 1-2 nanometers. By preparing a thinner aluminum oxide layer, the graphene can be bonded to the aluminum oxide layer while reducing the mismatch between the graphene and the semiconductor structure, ensuring a strong bonding force between the graphene and the semiconductor structure, preventing the semiconductor from falling off, and extending the life of the semiconductor.

[0013] Furthermore, the size of the graphene sheet is 1×1~5×5 mm 2 The thickness of the copper foil is about 15-20 microns. It is easy to select and use. By adjusting the size of the copper foil substrate, it can be used to meet the needs of advanced semiconductors of different sizes. By transferring the tangible graphene product to prepare the protective layer, the preparation method is simple, fast and easy to operate.

[0014] Furthermore, the platinum vapor deposition area ranges from 100×100 to 200×200 square nanometers. This ensures a strong bond between the tungsten nanoprobe and the graphene, preventing it from falling off. By vaporizing a larger area for connection, the larger force application surface is created when separating the graphene from the copper foil substrate, ensuring uniform force application and avoiding stress concentration. This allows for complete separation of the graphene, ensuring the integrity of the prepared graphene protective layer and its high protective performance.

[0015] Furthermore, in step S5, the steps of step S4 are repeated 10-15 times, sequentially covering the upper surface of the previously prepared graphene layer with graphene. This method allows for the preparation of thicker protective layers by increasing the number of graphene layers prepared. This shortens the preparation time and improves the safety and service life of the semiconductor by using multiple protective layers.

[0016] Furthermore, the tungsten nanoprobes configured for the focused ion beam instrument have tips measuring 30-50 nanometers. This meets the demands of advanced semiconductor manufacturing, enabling more precise nanomanipulation. The smaller tip reduces the risk of damage to samples and graphene, preserving the inherent properties and structural integrity of these advanced semiconductor samples and graphene.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention uses a graphene material with stable chemical composition, good ductility, and high mechanical strength to make a protective layer, the preparation method is simple, and it can be transferred to the semiconductor at room temperature. Since graphene has only one atomic layer, when it is pasted on an advanced process semiconductor sample, it is easy to fit tightly along the surface contour of the sample at room temperature for the purpose of reducing the surface energy of the test piece, and it will not cause deformation or damage to the surface structure of the sample. At the same time, subsequent graphene is also easy to stack tightly layer by layer, which is suitable for preparing protective layers of different thicknesses. In addition, graphene has high mechanical strength and can withstand the irradiation or cutting of electron beams or ion beams during the sample preparation process, effectively protecting the underlying structure and having strong protective properties. This method effectively improves the quality and efficiency of the preparation of protective layers for advanced process semiconductor samples used in material analysis, prevents deformation or damage to semiconductor samples, can effectively protect the underlying semiconductor sample structure, and prolongs the service life of the semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1This is a flow chart of the steps of the preparation method for protecting advanced process semiconductor sample structures in material analysis according to the present invention; Figure 2 A top view of an advanced process semiconductor sample of the present invention; Figure 3 is a cross-sectional view of an advanced process semiconductor sample of the present invention; Figure 4 This is a cross-sectional view of the advanced process semiconductor sample of the present invention after the aluminum oxide layer is prepared; Figure 5 A plan view of the graphene purchased for the present invention; Figure 6 A cross-sectional view of the graphene purchased for the present invention; Figure 7 Schematic diagram of the structure of the tungsten nanoprobe and graphene positions in the focused ion beam (FIB) machine of the present invention; Figure 8 This is a schematic diagram of the structure of platinum-connected tungsten nanoprobes and graphene prepared by evaporation on a focused ion beam (FIB) machine in the present invention; Figure 9 This is a schematic diagram of the structure of an advanced process semiconductor sample covered with a graphene layer according to the present invention; Figure 10 Schematic diagram of the structure of the advanced process semiconductor sample of the present invention covered with 12-17 layers of graphene layers. DETAILED DESCRIPTION

[0019] In order to provide a further understanding of the purpose, structure, features, and functions of the present invention, the present invention is described in detail below with reference to the embodiments.

[0020] like Figure 1 A preparation method for protecting an advanced process semiconductor sample structure in material analysis comprises the following steps: S1: Prepare advanced process semiconductor samples; Prepare an advanced process semiconductor sample, as shown in Figure 2 and Figure 3 As shown, the sample surface includes a semiconductor structure; Advanced process semiconductors refer to semiconductor chips produced using manufacturing processes with smaller feature sizes and higher integration.

[0021] Semiconductor structure refers to the microscopic material composition or device structure with specific electrical properties, including crystal structure, doped conductive areas, etc.

[0022] S2: Preparation of aluminum oxide layer on the surface of semiconductor sample; A layer of aluminum oxide (AlO) was deposited on the sample surface using atomic layer deposition (ALD). x) layer, as shown in Figure 4, with an aluminum oxide thickness of 1-2 nanometers. Using atomic layer deposition (ALD), aluminum oxide can evenly and smoothly cover the entire surface of the semiconductor sample to form a semiconductor sample wafer.

[0023] S3: prepare graphene material; 10-15 graphene sheets purchased from the market (such as ACS MATERIAL brand), as shown in Figure 5, with sizes ranging from 1×1 to 5×5 mm 2 .

[0024] Commercially available graphene substrates are copper foil, as shown in Figure 6. The copper foil is approximately 15-20 microns thick. Graphene is bonded to the copper foil substrate in a single atomic layer, bonded by weak van der Waals forces. This weak bonding makes it easy to separate the graphene. Each piece of graphene purchased is used as a graphene / copper foil substrate test piece.

[0025] S4: covering the surface of the aluminum oxide layer with a graphene layer; Using a focused ion beam (FIB) machine, the graphene on the purchased copper foil substrate was transferred to the surface of a semiconductor sample prepared with an aluminum oxide layer at room temperature to form a graphene layer.

[0026] 1) Place the purchased graphene / copper foil substrate specimen on the specimen carrier in the focused ion beam (FIB) machine, with the graphene facing upwards.

[0027] This focused ion beam (FIB) instrument is equipped with four piezoelectrically movable tungsten nanoprobes, each with a tip size of 30-50 nanometers. It also includes a specimen carrier capable of vertical (Y-direction) and X- and Y-direction movement, as well as a vapor deposition system and a focused ion beam (FIB) cutting module. This method utilizes the existing FIB instrument and does not introduce any structural improvements or innovations. The functions utilized are already present in the FIB instrument, so the detailed description of the FIB instrument structure and functions is omitted.

[0028] 2) Move the specimen stage of the focused ion beam (FIB) machine toward the tungsten nanoprobe (upward) and stop at a distance of 1-2 mm from the tungsten nanoprobe. Then, use piezoelectric movement to make the tungsten nanoprobe contact the four corners of the graphene, as shown in Figure 7.

[0029] 3) Using the evaporation system in a focused ion beam (FIB) machine, platinum was evaporated onto the surface where the tungsten nanoprobe tip contacts the graphene. The evaporation area was 100×100 to 200×200 square nanometers, as shown in Figure 8.

[0030] 4) Move the specimen stage of the focused ion beam (FIB) machine away from the tungsten nanoprobes (downward). Since the graphene is firmly connected to the four tungsten nanoprobes via platinum, the copper foil substrate moves with the specimen stage, separating the graphene from the copper foil substrate, leaving the graphene suspended in mid-air.

[0031] 5) Place the semiconductor sample coupon prepared with atomic layer deposition (ALD) aluminum oxide (step S2, as shown in Figure 4) on the coupon stage of the focused ion beam (FIB) instrument. Move the coupon stage upward toward the tungsten nanoprobes until it is 0.1-0.2 mm away from the tungsten nanoprobes. Then, move the coupon stage in the X and Y directions to adjust the position of the semiconductor sample coupon to the center of the four tungsten nanoprobes.

[0032] 6) The focused ion beam (FIB) cutting module is used to sequentially cut off the front 100-150 nanometers of material from four tungsten nanoprobes. Due to gravity, the graphene lands on a semiconductor sample wafer prepared with atomic layer deposition (ALD) aluminum oxide, as shown in Figure 9.

[0033] Because graphene has a high degree of bonding with aluminum oxide, when graphene with only one atomic layer is pasted on an advanced process semiconductor sample with a thin aluminum oxide layer, the graphene can easily fit closely along the surface contour of the sample without creating gaps.

[0034] The preparation temperature of the present invention is at room temperature, and the chemical composition of graphene is quite stable and not easily reacted with other substances. Therefore, it can be safely ensured that the semiconductor structure on the surface of the advanced process semiconductor sample will not be deformed or damaged.

[0035] S5: Repeat step S4 to cover the surface of the advanced process semiconductor sample with multiple graphene layers.

[0036] Repeat step S4 10-15 times, gradually covering the graphene on the graphene / copper foil substrate test piece with the upper surface of the previously prepared graphene layer. Finally, there will be 12-17 layers of graphene attached to the surface of the advanced process semiconductor sample, as shown in Figure 10, completing the preparation of the protective layer.

[0037] The present invention has been described with reference to the above embodiments. However, the above embodiments are merely exemplary embodiments of the present invention. It should be noted that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and improvements that do not depart from the spirit and scope of the present invention are intended to be protected by the present invention.

Claims

1. A preparation method for protecting advanced process semiconductor sample structures in material analysis, characterized by: The following steps are involved: S1: Prepare advanced process semiconductor samples; Prepare advanced process semiconductor samples, the surface of which includes semiconductor structures; S2: Preparation of aluminum oxide layer on the surface of semiconductor sample; A layer of aluminum oxide is deposited on the surface of a semiconductor sample using atomic layer deposition; S3: prepare graphene material; Purchase graphene flakes; graphene flakes are formed by using copper foil as a substrate, with the graphene being flattened on the copper foil substrate by van der Waals forces; use each purchased graphene flake as a graphene / copper foil substrate test piece for future use; S4: covering the surface of the aluminum oxide layer with a graphene layer; Using a focused ion beam machine, at room temperature, graphene on a copper foil substrate was transferred to the surface of a semiconductor sample prepared with an aluminum oxide layer to form a graphene layer; S5: Repeat step S4 to cover the surface of the advanced process semiconductor sample with multiple graphene layers.

2. The method for protecting advanced semiconductor sample structures in material analysis according to claim 1, wherein: Step S4 includes: 1) Place the graphene / copper foil substrate specimen on the specimen carrier in the focused ion beam instrument, with the graphene facing upwards; 2) Move the specimen carrier of the focused ion beam machine toward the tungsten nanoprobe, stopping at a distance of 1-2 mm from the tungsten nanoprobe. Move the tungsten nanoprobes separately until they touch the four corners of the graphene. 3) Using a focused ion beam machine, platinum was evaporated onto the surface where the tungsten nanoprobe tip contacts the graphene. 4) Move the specimen stage of the focused ion beam instrument away from the tungsten nanoprobe to separate the graphene from the copper foil substrate, leaving the graphene suspended in the air. 5) Place the semiconductor sample with the aluminum oxide layer on the specimen stage of the focused ion beam instrument and move the specimen stage toward the tungsten nanoprobes, stopping at a distance of 0.1-0.2 mm. Then, move the specimen stage to position the semiconductor sample in the middle of the four tungsten nanoprobes. 6) Using a focused ion beam machine, the front 100-150 nanometers of material from four tungsten nanoprobes are sequentially cut off. The graphene falls onto a semiconductor sample wafer with an aluminum oxide layer, conforming to the surface contours of the semiconductor sample wafer to form a graphene layer.

3. The method for protecting advanced semiconductor sample structures in material analysis according to claim 1, wherein: The thickness of the aluminum oxide layer is 1-2 nanometers.

4. The method for protecting advanced semiconductor sample structures in material analysis according to claim 1, wherein: The size of graphene sheets is 1×1~5×5 mm 2 , the copper foil thickness is about 15-20 microns.

5. The method for protecting advanced semiconductor sample structures in material analysis according to claim 2, wherein: The area of platinum vapor deposition is 100×100~200×200 square nanometers.

6. The method for protecting advanced semiconductor sample structures in material analysis according to claim 1, wherein: In step S5, the action of step S4 is repeated 10-15 times, and the graphene is sequentially covered on the upper surface of the graphene layer prepared in the previous step.

7. The method for protecting advanced semiconductor sample structures in material analysis according to claim 1, wherein: The tip of the tungsten nanoprobe configured in the focused ion beam instrument is 30-50 nanometers.

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