Ultra-high-speed FPGA (Field Programmable Gate Array) chip and ultra-high-speed data acquisition processing method

Abstract

The invention discloses an ultra-high-speed FPGA (Field Programmable Gate Array) chip and an ultra-high-speed data acquisition and processing method. The FPGA chip comprises a main control module, a data processing module, a first data transmission module and a memory control module, the main control module comprises four serial interfaces and a data rearrangement unit, each serial interface is used for simultaneously receiving ultra-high-rate data output by the ADC chip to obtain four 512-bit data blocks, and the data rearrangement unit is used for decomposing the four 512-bit data blocks received by each serial interface into 256 8-bit data units; the data processing module is used for carrying out data processing on each data unit, and the first data transmission module is used for converting 256 8-bit data units into 320 8-bit data units and transmitting the 320 8-bit data units to the memory control module; and the memory control module comprises four DDR (Double Data Rate) units and is used for writing, reading and storing 320 8-bit data units. Therefore, the acquisition, the processing and the storage of the 640Gbps ultra-high-speed data are realized.

Description

Technical Field

[0001] The present application relates to the field of signal acquisition technology, and in particular to an ultra-high-speed FPGA chip and an ultra-high-speed data acquisition and processing method. Background Art

[0002] With the rapid development of chip and material processing technologies, the real-time analysis bandwidth and data sampling rate of modern broadband data acquisition equipment are constantly increasing. High-bandwidth, high-sampling-rate data acquisition systems are widely used in fields such as ultra-wideband communication RF signal measurement, high-speed serial bus protocol analysis (such as USB4.0, HDMI, and DDR4), and optical communication module testing. They can capture and analyze key parameters such as high-speed clock signal jitter and bus signal jitter, and test the transmission quality of optical signals.

[0003] As sampling rates increase, the data rate collected by ADCs increases significantly. The high-speed communication interface between the ADC and the FPGA needs to support even higher transmission rates, placing higher demands on the real-time digital signal processing capabilities within the FPGA. Traditional methods often face data transmission bottlenecks, insufficient real-time processing capabilities, and complex cache management when processing ultra-high-rate data. Summary of the Invention

[0004] The main purpose of this application is to provide an ultra-high-speed FPGA chip and an ultra-high-speed data acquisition and processing method to realize the acquisition, processing and storage of 640Gbps ultra-high-speed data.

[0005] To achieve the above-mentioned object, the present application provides an ultra-high-speed FPGA chip, comprising a main control module, a data processing module, a first data transmission module, and a memory control module connected in sequence;

[0006] The main control module includes four serial interfaces and a data reordering unit, each of the serial interfaces is used to simultaneously receive ultra-high-speed data output by the ADC chip to obtain four 512-bit data blocks, and the data reordering unit is used to decompose the four 512-bit data blocks received by each serial interface into 256 8-bit first data units;

[0007] The data processing module is used to perform data processing on each of the first data units, and the first data transmission module is used to convert the 256 8-bit first data units into 320 8-bit second data units, and transmit the 320 8-bit second data units to the memory control module;

[0008] The memory control module includes four DDR chips for writing, reading and storing 320 8-bit second data units.

[0009] Optionally, each of the serial interfaces is used to receive ultra-high-speed data and a synchronization signal output by the ADC chip to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align the data blocks.

[0010] Optionally, the memory control module also includes a data write unit and a data read unit connected to each of the DDR chips; the data write unit is used to receive 320 8-bit second data units, divide the 320 8-bit second data units into 4 data groups, and write each of the data groups into each of the DDR chips respectively; each of the DDR chips is used to store data groups; the data read unit is used to receive data groups read from each of the DDR chips.

[0011] Optionally, the FPGA chip also includes a second data transmission module and a PCIe module, the second data transmission module is connected to the memory control module and the PCIe module, and the PCIe module is connected to the host computer; the second data transmission module is used to receive each data group output by the data read-out unit, and convert each data group into DAM format and then output it to the PCIe module; the PCIe module is used to upload each data group in DAM format to the host computer.

[0012] Optionally, the FPGA chip also includes a configuration module, which is connected to the PCIe module; the PCIe module is also used to receive control instructions and / or configuration parameters sent by the host computer, and send the control instructions and / or configuration parameters to the configuration module; the configuration module is used to send the control instructions and / or configuration parameters to the remaining corresponding modules.

[0013] Optionally, the FPGA chip also includes a first phase-locked loop module, which is connected to the PCIe module; the PCIe module is also used to output a first signal to the first phase-locked loop module; the first phase-locked loop module is used to receive the first signal and initialize the clock configuration of the clock phase-locked loop chip when the first signal is at a high level.

[0014] Optionally, the FPGA chip also includes a second phase-locked loop module, which is connected to the first phase-locked loop module; the first phase-locked loop module is also used to send a second signal to the second phase-locked loop module after initializing the clock configuration of the first clock phase-locked loop chip; the second phase-locked loop module is used to receive the second signal and, when the second signal is at a high level, initialize the clock configuration of the clock multiplication chip.

[0015] Optionally, the FPGA chip also includes an ADC control module, which is connected to the second phase-locked loop module and the main control module; the second phase-locked loop module is also used to send a third signal to the ADC control module after initializing the clock configuration of the clock multiplication chip; the ADC control module is used to receive the third signal, and when the third signal is at a high level, initialize the configuration of the ADC chip, and send a fourth signal to the main control module; the main control module is used to receive the fourth signal, and start working when the fourth signal is at a high level.

[0016] In addition, to achieve the above-mentioned purpose, the present application also provides an ultra-high-rate data acquisition and processing method based on an FPGA chip, which is applied to the ultra-high-rate FPGA chip as described above. The method includes: simultaneously receiving ultra-high-rate data output by the ADC chip to obtain 4 512-bit data blocks, and decomposing the 4 512-bit data blocks into 256 8-bit first data units; performing data processing on each of the first data units, and converting the 256 8-bit first data units into 320 8-bit second data units; and writing, reading and storing the 320 8-bit second data units.

[0017] Optionally, the simultaneously receiving ultra-high-rate data output by the ADC chip to obtain four 512-bit data blocks includes: receiving the ultra-high-rate data output by the ADC chip and a synchronization signal to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align the data blocks.

[0018] The ultra-high-speed FPGA chip of the present application is configured with four serial interfaces on a main control module, so that the four serial interfaces can simultaneously collect 640Gbps ultra-high-speed data to obtain four 512-bit data blocks; a data rearrangement unit is then used to decompose the four 512-bit data blocks received by each of the serial interfaces into 256 8-bit first data units to facilitate subsequent data processing of each first data unit; a first data transmission module is used to convert the 256 8-bit first data units into 320 8-bit second data units, and four DDR chips are configured in a memory control module, so that the four DDR chips can respectively store 80 8-bit second data units, thereby realizing the collection, processing and storage of 640Gbps ultra-high-speed data. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure of an ultra-high-speed FPGA chip according to an embodiment of the present application;

[0020] Figure 2 is a flow chart of the data ultra-high rate acquisition and processing method according to an embodiment of the present application;

[0021] In the figure, 110 is a main control module; 120 is a data processing module; 130 is a first data transmission module; 140 is a memory control module; 150 is a second data transmission module; 160 is a PCIe module; 170 is a configuration module; 180 is a first phase-locked loop module; 190 is a second phase-locked loop module; and 200 is an ADC control module.

[0022] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] Continuous advances in semiconductor processing technology, chip design, and materials science have significantly improved the performance of modern broadband data acquisition equipment, particularly in terms of real-time analysis bandwidth and data sampling rate. These technological advancements enable data acquisition systems to support higher bandwidths and sampling rates, meeting increasingly complex signal measurement requirements. Applications such as ultra-wideband communication RF signal measurement, high-speed serial bus protocol analysis, and the development and testing of optical communication modules all place higher demands on the performance of data acquisition systems.

[0025] In the communications field, broadband data acquisition equipment can capture and analyze the parameters of random, sporadic signals, such as the jitter of high-speed clock signals and high-speed bus signals. Accurate measurement of these parameters is crucial for the stability and performance optimization of communication systems. Furthermore, in terms of protocol analysis, signal analysis of high-speed serial buses (such as USB4.0, HDMI, DDR4, etc.) requires data acquisition systems with extremely high sampling rates and real-time processing capabilities to ensure signal integrity and accuracy. In the development and testing of optical communication modules and optical transmission equipment, data acquisition systems also need to be able to test the transmission quality of optical signals to ensure the efficiency and reliability of optical communication systems.

[0026] As sampling rates continue to increase, the data rate collected by analog-to-digital converters (ADCs) has also increased significantly. This requires the high-speed communication interface between the ADC and the field-programmable gate array (FPGA) to support higher data transmission rates. At the same time, the digital signal processing capabilities within the FPGA chip also face higher real-time requirements. Traditional data acquisition and processing methods often struggle to meet real-time and bandwidth requirements when processing ultra-high-rate data, especially in scenarios where data rates reach 640Gbps and above.

[0027] Existing FPGA chips typically face the following challenges when processing ultra-high-rate data:

[0028] 1. Data transmission bottleneck: The interface bandwidth between the ADC chip and the FPGA chip is limited, making it difficult to support real-time transmission of ultra-high-speed data.

[0029] 2. Insufficient real-time processing capabilities: The digital signal processing module inside the FPGA chip is prone to performance bottlenecks when processing ultra-high-speed data, resulting in data processing delays or loss.

[0030] 3. Complex cache management: Cache management of ultra-high-rate data requires efficient design to ensure data continuity and integrity.

[0031] Based on this, the present invention provides an ultra-high-speed FPGA chip and an ultra-high-speed data sampling and processing method. By optimizing the functional modules of the FPGA chip, it is possible to receive, cache, and process the 640Gbps ultra-high-speed data output by the ADC chip, thereby meeting the high bandwidth, high sampling rate, and real-time processing requirements of modern broadband data acquisition equipment.

[0032] Figure 1 Schematic diagram of the structure of the ultra-high-speed FPGA chip of the embodiment of the present application. Figure 1 As shown, the ultra-high-speed FPGA chip may include a main control module 110, a data processing module 120, a first data transmission module 130 and a memory control module 140 connected in sequence.

[0033] Among them, the main control module 110 includes 4 serial interfaces and a data rearrangement unit. Each serial interface is used to simultaneously receive ultra-high-speed data output by the ADC chip to obtain 4 512-bit data blocks. The data rearrangement unit is used to decompose the 4 512-bit data blocks received by each serial interface into 256 8-bit first data units; the data processing module 120 is used to process each first data unit, and the first data transmission module 130 is used to convert the 256 8-bit first data units into 320 8-bit second data units, and transmit the 320 8-bit second data units to the memory control module 140; the memory control module 140 includes 4 DDR chips for writing, reading and storing the 320 8-bit second data units.

[0034] In this embodiment, the main control module 110 is mainly used to implement the ultra-high-speed data reception and pre-processing functions between the FPGA chip and the ADC chip. The main control module 110 may include four serial interfaces and a data reordering unit.

[0035] Since the ADC chip outputs data at a rate of up to 640Gbps, the serial interface can adopt the JESD204C high-speed serial interface standard to enable the FPGA chip to receive and transmit ultra-high-speed data. Because the JESD204C high-speed serial interface standard has a higher transmission rate, supporting transmission rates of up to 32Gbps per channel; JESD204C also offers higher link efficiency, introducing a 64b / 66b encoding scheme that reduces overhead and increases effective data throughput compared to JESD204B's 8b / 10b encoding. Therefore, JESD204C is more suitable for receiving data at data rates up to 640Gbps.

[0036] It should be noted that the implementation codes of the four serial interfaces are the same, so the functions that can be implemented by these four serial interfaces are also the same.

[0037] In addition, the four serial interfaces are connected to the four serdes (serializers) serdes[7:0], serdes[15:8], serdes[23:16], and serdes[31:24] respectively. These four serializers can convert the parallel data output by the ADC chip into serial data for transmission through a high-speed serial link.

[0038] In this embodiment, when the main control module 110 is turned on, the four serial interfaces simultaneously receive ultra-high-speed data output by the ADC chip, and each serial interface outputs a 512-bit data block. Furthermore, the four 512-bit data blocks are input to the data reordering unit, which converts the four 512-bit data blocks into 256 8-bit first data units and transmits the 256 8-bit first data units to the data processing module 120.

[0039] The specific implementation method of the data rearrangement unit converting four 512-bit data blocks into 256 8-bit first data units can be: splicing four 512-bit data blocks into a 2048-bit continuous data block; dividing the 2048-bit data block into 8-bit data units to obtain 256 8-bit first data units; and finally outputting the 256 8-bit first data units in sequence.

[0040] In this embodiment, after receiving the 256 8-bit first data units output by the data rearrangement unit, the data processing module 120 can perform data processing on each first data unit. Data processing may include: filtering, Fourier transform, modulation and demodulation, data compression, encryption and decryption, data packet processing, etc. It should be noted that the implementation code configured in the data processing module 120 of this embodiment can be replaced according to different application scenarios to implement different data processing functions. It is only necessary to ensure that the input and output of the data processing module 120 are both 256 8-bit first data units. The specific implementation functions and implementation codes of the data processing module 120 are not limited here. As an example, for high-speed radar signal reception applications, the implementation code configured in the data processing module 120 can be radar-related signal processing algorithms; for high-speed oscilloscope applications, the implementation code configured in the data processing module 120 can be oscilloscope-related signal processing algorithms.

[0041] Furthermore, after processing the 256 8-bit first data units, the data processing module 120 transmits the processed 256 8-bit first data units to the first data transmission module 130. The first data transmission module 130 may convert the 256 8-bit first data units into 320 8-bit second data units. Finally, the first data transmission module 130 transmits the 320 8-bit second data units to the memory control module 140, so that the memory control module 140 caches the data in real time.

[0042] It should be noted that the first data transmission module 130 described in this embodiment converts 256 8-bit first data units into 320 8-bit second data units, which does not change the data itself, but is a conversion of the processing method caused by the different data processing methods of the serial interface (JESD204C) and the DDR unit in their working clock domains. Specifically, under the working clock domain of JESD204C, one JESD204C clock cycle processes 256 8-bit first data units at the same time. However, under the working clock domain of the DDR unit, one DDR clock cycle can process 320 8-bit second data units at the same time, so converting 256 8-bit first data units into 320 8-bit second data units only converts the data processing method.

[0043] In this embodiment, after the memory control module 140 receives 320 8-bit second data units, it can use the four DDR chips configured therein to implement real-time caching of the 320 8-bit second data units.

[0044] Therefore, by setting up four serial interfaces in the main control module 110, the four serial interfaces can simultaneously collect 640Gbps ultra-high-speed data to obtain four 512-bit data blocks; then, the four 512-bit data blocks received by each of the serial interfaces are decomposed into 256 8-bit first data units through the data rearrangement unit, so as to facilitate subsequent data processing of each first data unit; the first data transmission module 130 is used to convert the 256 8-bit first data units into 320 8-bit second data units, and four DDR chips are set in the memory control module 140, so that the four DDR chips can respectively store 80 8-bit second data units, thereby realizing the collection, processing and storage of 640Gbps ultra-high-speed data.

[0045] In some implementations, each serial interface is used to receive ultra-high-speed data and a synchronization signal output by the ADC chip to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align the data blocks.

[0046] Specifically, while receiving the ultra-high-speed data output by the ADC chip, each serial interface also receives the same sysref signal to achieve data synchronization between the serial interfaces, ensuring that the ultra-high-speed data received by the FPGA chip is synchronized and aligned. Figure 1 refclk_1, refclk_2, refclk_3, and refclk_4 are four reference clocks of the same source.

[0047] In some embodiments, the memory control module 140 may further include a data write unit and a data read unit connected to each DDR unit. The data write unit is configured to receive 320 8-bit second data units, divide the 320 8-bit second data units into four data groups, and write each data group into each DDR unit; each DDR unit is configured to store a data group; and the data read unit is configured to receive a data group read from each DDR unit.

[0048] Specifically, the memory control module 140 is mainly used to write, read and cache the 320 8-bit second data units after front-end processing. Among them, the data write unit is connected to the first data transmission module 130, and the data write unit can receive the 320 8-bit second data units sent by the first data transmission module 130, and perform a first-level cache on the 320 8-bit second data units. Furthermore, the data write unit can divide the 320 8-bit second data units into 4 data groups, each data group contains 80 8-bit data; the data write unit then transmits these 4 data groups to the above-mentioned 4 DDR units respectively, and the 4 DDR units will output their respective data groups to the corresponding DDR chips for storage. It can be understood that the data bit width of the DDR ipcore inside the FPGA chip is limited. A set of DDR chipsets can accept a maximum of 80 bits. In order to achieve the cache of 640Gbps ultra-high-speed data, 4 sets of DDR chipsets are needed to cache data.

[0049] It should be noted that the process of grouping the 320 8-bit second data units by the data writing unit can refer to the data conversion process in the above embodiment, which will not be repeated here. In addition, the implementation code of each DDR unit is the same, so the functions that can be achieved are also the same.

[0050] Furthermore, when ultra-high-speed data needs to be read out from each DDR chip, the data read-out unit can receive 4 groups of data groups read out from each DDR chip; after the data read-out unit receives the 4 groups of data groups, it can convert the 4 groups of data into 8 8-bit second data units and transmit the 8 8-bit second data units to the next level.

[0051] In some embodiments, the FPGA chip further includes a second data transmission module 150 and a PCIe module 160. The second data transmission module 150 is connected to the memory control module 140 and the PCIe module 160, and the PCIe module 160 is connected to the host computer. The second data transmission module 150 is configured to receive the data groups output by the data readout unit, convert the data groups into a DAM format, and output the converted data groups to the PCIe module 160. The PCIe module 160 is configured to upload the data groups in the DAM format to the host computer.

[0052] Specifically, the second data transmission module 150 can receive eight 8-bit second data units output by the data read unit. After receiving the eight 8-bit second data units output by the data read unit, the second data transmission module 150 converts the eight 8-bit second data units into a DMA (Direct Memory Access) data format. Converting each second data unit into a DMA format can facilitate efficient data transmission, simplify hardware interfaces, unify data formats, and meet protocol requirements.

[0053] After the second data transmission module 150 converts the eight 8-bit second data units into the DMA data format, it sends the converted data to the PCIe module 160. PCIe module 160 establishes a communication link with the host computer via the X8 PCIE interface, and can receive data from the host computer or send data to the host computer. After receiving the data output by the second data transmission module 150, PCIe module 160 uploads the data to the host computer for subsequent processing.

[0054] It should be noted that in this embodiment, the host computer can be a personal computer (PC), an industrial control computer (IPC), an embedded system, a microcontroller unit (MCU), dedicated hardware, a cloud service, etc., and the host computer is not specifically limited here.

[0055] In some embodiments, the FPGA chip also includes a configuration module 170, which is connected to the PCIe module 160; the PCIe module 160 is also used to receive control instructions and / or configuration parameters sent by the host computer, and send the control instructions and / or configuration parameters to the configuration module 170; the configuration module 170 is used to send the control instructions and / or configuration parameters to the remaining corresponding modules.

[0056] In this embodiment, configuration module 170 is connected to PCIe module 160. When PCIe module 160 receives all control instructions and configuration parameters from the host computer, it sends them to configuration module 170. Configuration module 170 stores the register addresses of each functional module in the FPGA chip. Configuration module 170 can distribute control instructions and configuration parameters to different functional modules through different register addresses.

[0057] Specifically, the host computer generates control instructions and configuration parameters through software tools or custom applications. These instructions and parameters may be configuration settings for specific functional modules, start / stop commands, or other operation requests. The host computer sends these instructions and parameters to the PCIe module 160 in the FPGA via the PCIE interface. The PCIe module 160 receives all control instructions and configuration parameters issued by the host computer. Because PCIe supports high-bandwidth data transmission, this step can be completed efficiently. Furthermore, the PCIe module 160 needs to parse the received data packets to extract the specific control instructions and configuration parameters.

[0058] Once PCIe module 160 successfully parses a data packet, it forwards the extracted control instructions and configuration parameters to configuration module 170. Configuration module 170 may internally store a mapping table that records the register addresses corresponding to each functional module. Upon receiving the control instructions and configuration parameters, configuration module 170 searches for the corresponding register addresses based on the instruction content. Furthermore, configuration module 170 distributes the control instructions and configuration parameters to the corresponding functional modules using the found register addresses.

[0059] In some embodiments, the FPGA chip also includes a first phase-locked loop module 180, which is connected to the PCIe module 160; the PCIe module 160 is also used to output a first signal to the first phase-locked loop module 180; the first phase-locked loop module 180 is used to receive the first signal and initialize the clock configuration of the clock phase-locked loop chip when the first signal is at a high level.

[0060] When the data acquisition system is powered on, the FPGA chip in the data acquisition system is powered on, and the PCIe module 160 in the FPGA chip establishes a communication link with the host computer through the X8 PCIE interface. After the link is established, the PCIe module 160 outputs a first signal to the configuration module 170, the second data transmission module 150, and the first phase-locked loop module 180, thereby simultaneously enabling the configuration module 170, the second data transmission module 150, and the first phase-locked loop module 180, thereby enabling the transmission of register control commands and DMA data.

[0061] Taking the first PLL module 180 as an example, while the first signal is low, the first PLL module 180 remains in a reset state, waiting for the PCIe module 160 to successfully establish a link with the host computer and output a high-level first signal. When the first signal received by the first PLL module 180 is high, the first PLL module 180 begins operation. At this point, the first PLL module 180 initializes the clock configuration of the clock PLL chip in the data acquisition system hardware via the SPI interface.

[0062] It should be noted that the clock configuration initialization process is the process of configuring a register of the clock chip through the SPI interface of the FPGA chip. The register value can be configured according to the register definition in the data manual and the required output clock frequency, so that the clock chip can output the required clock frequency.

[0063] After receiving the high-level first signal, the configuration module 170 and the second data transmission module 150 both start working to implement the register control command and DMA data transmission functions.

[0064] In some embodiments, the FPGA chip may further include a second phase-locked loop module 190, which is connected to the first phase-locked loop module 180; the first phase-locked loop module 180 is also used to send a second signal to the second phase-locked loop module 190 after initializing the clock configuration of the first clock phase-locked loop chip; the second phase-locked loop module 190 is used to receive the second signal and, when the second signal is at a high level, initialize the clock configuration of the clock multiplication chip.

[0065] In this embodiment, after the first PLL module 180 completes clock configuration initialization for the clock PLL chip, the first PLL module 180 outputs a second signal to the second PLL module 190. Specifically, the second PLL module 190 remains in a reset state until the first PLL module 180 completes clock configuration initialization, and waits for the first PLL module 180 to complete initialization.

[0066] After the first phase-locked loop module 180 completes the clock configuration initialization of the clock phase-locked loop chip, the first phase-locked loop module 180 will output a high-level second signal to the second phase-locked loop module 190. When the second signal is pulled high, the second phase-locked loop module 190 starts working, and the second phase-locked loop module 190 initializes the clock configuration of the clock multiplication chip on the data acquisition system hardware through the SPI interface.

[0067] In some embodiments, the FPGA chip may further include an ADC control module 200, which is connected to the second phase-locked loop module 190 and the main control module 110. The second phase-locked loop module 190 is further configured to send a third signal to the ADC control module 200 after initializing the clock configuration of the clock multiplication chip. The ADC control module 200 is configured to receive the third signal and, when the third signal is at a high level, initialize the configuration of the ADC chip and send a fourth signal to the main control module 110. The main control module 110 is configured to receive the fourth signal and, when the fourth signal is at a high level, begin operation.

[0068] In this embodiment, the ADC control module 200 is in a reset state until the second phase-locked loop module 190 completes initialization of the clock multiplication chip, and waits for the second phase-locked loop module 190 to complete initialization of the clock multiplication chip.

[0069] After the second phase-locked loop module 190 completes initialization of the clock multiplication chip, it sends a high-level third signal to the ADC control module 200. After the third signal goes high, the ADC control module 200 begins operating and initializes the ADC chip in the data acquisition system hardware via the SPI interface.

[0070] It should be noted that the configuration initialization of the second phase-locked loop module 190 is the same as that of the first phase-locked loop module 180 and will not be repeated here. In addition, the first phase-locked loop module 180 is mainly used to generate multiple synchronized low-frequency clocks. Specifically, it can generate four 312.5MHz clocks and output the four 312.5MHz clocks to the refclk of the FPGA chip main control module 110. It can also generate clocks of 1 to 4,100MHz and output them to the second phase-locked loop module 190, so that the second phase-locked loop module 190 can use them as reference clocks. It can also generate a 125MHz clock and output it to the four DDR units, so that the DDR units can use them as reference clocks. The second phase-locked loop module 190 is mainly used to generate a high-frequency clock and output the high-frequency clock at 20GHz to the ADC chip as the sampling drive clock.

[0071] Furthermore, the main control module 110 is in a reset state until the ADC control module 200 completes the configuration initialization of the ADC chip, and waits for the ADC control module 200 to complete the configuration initialization of the ADC chip.

[0072] After the ADC control module 200 completes the configuration initialization of the ADC chip, the ADC control module 200 sends a high-level fourth signal to the main control module 110. After the fourth signal is pulled high, the main control module 110 starts working.

[0073] Therefore, the FPGA chip of this embodiment can realize the collection, reception, caching and processing of 640Gbps ultra-high rate data.

[0074] Based on the above embodiments, the embodiments of the present application also provide a method for ultra-high-speed data acquisition and processing based on an FPGA chip.

[0075] Figure 2: is a flow chart of the data ultra-high rate acquisition and processing method according to an embodiment of the present application. The data ultra-high rate acquisition and processing method based on an FPGA chip can be implemented by the FPGA chip according to the above embodiment. The data ultra-high rate acquisition and processing method based on an FPGA chip can include the following steps:

[0076] Step 210: simultaneously receive ultra-high-speed data output by the ADC chip to obtain four 512-bit data blocks, and decompose the four 512-bit data blocks into 256 8-bit first data units.

[0077] Step 220: Perform data processing on each first data unit, and convert the 256 8-bit first data units into 320 8-bit second data units.

[0078] Step 230: Write, read, and store 320 8-bit second data units.

[0079] In some embodiments, simultaneously receiving ultra-high-rate data output by the ADC chip to obtain four 512-bit data blocks in step 210 includes: receiving ultra-high-rate data output by the ADC chip and a synchronization signal to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align the data blocks.

[0080] It should be noted that for details not disclosed in the ultra-high-speed data acquisition and processing method based on FPGA chip in this embodiment, please refer to the details disclosed in the embodiment of ultra-high-speed FPGA chip in the embodiment of this specification, and no further details will be given here.

[0081] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0082] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

Claims

1. An ultra-high-speed FPGA chip, characterized in that: It includes a main control module, a data processing module, a first data transmission module and a memory control module connected in sequence; The main control module includes four serial interfaces and a data reordering unit, each of the serial interfaces is used to simultaneously receive ultra-high-speed data output by the ADC chip to obtain four 512-bit data blocks, and the data reordering unit is used to decompose the four 512-bit data blocks received by each serial interface into 256 8-bit first data units; The data processing module is used to perform data processing on each of the first data units, and the first data transmission module is used to convert the 256 8-bit first data units into 320 8-bit second data units, and transmit the 320 8-bit second data units to the memory control module; The memory control module includes four DDR chips for writing, reading and storing 320 8-bit second data units.

2. The ultra-high-speed FPGA chip according to claim 1, characterized in that: Each of the serial interfaces is used to receive ultra-high-speed data and synchronization signals output by the ADC chip to obtain four 512-bit data blocks; The synchronization signal is used to synchronize the data blocks.

3. The ultra-high-speed FPGA chip according to claim 1, characterized in that: The memory control module further includes a data writing unit and a data reading unit connected to each of the DDR chips; The data writing unit is used to receive 320 8-bit second data units, divide the 320 8-bit second data units into 4 data groups, and write each of the data groups into each of the DDR chips respectively; Each of the DDR chips is used to store data groups; The data reading unit is used to receive the data group read out from each of the DDR chips.

4. The ultra-high-speed FPGA chip according to claim 3, characterized in that: The FPGA chip also includes a second data transmission module and a PCIe module, the second data transmission module is connected to the memory control module and the PCIe module, and the PCIe module is connected to the host computer; The second data transmission module is used to receive each data group output by the data reading unit, convert each data group into a DAM format, and then output it to the PCIe module; The PCIe module is used to upload each data group in DAM format to the host computer.

5. The ultra-high-speed FPGA chip according to claim 4, characterized in that: The FPGA chip further includes a configuration module, and the configuration module is connected to the PCIe module; The PCIe module is further configured to receive control instructions and / or configuration parameters sent by the host computer, and send the control instructions and / or configuration parameters to the configuration module; The configuration module is used to send the control instructions and / or the configuration parameters to other corresponding modules.

6. The ultra-high-speed FPGA chip according to claim 4, characterized in that: The FPGA chip further includes a first phase-locked loop module, which is connected to the PCIe module; The PCIe module is further configured to output a first signal to the first phase-locked loop module; The first phase-locked loop module is used to receive the first signal and initialize the clock configuration of the clock phase-locked loop chip when the first signal is at a high level.

7. The ultra-high-speed FPGA chip according to claim 6, characterized in that: The FPGA chip also includes a second phase-locked loop module, and the second phase-locked loop module is connected to the first phase-locked loop module; The first phase-locked loop module is further configured to send a second signal to the second phase-locked loop module after initializing the clock configuration of the first clock phase-locked loop chip; The second phase-locked loop module is used to receive the second signal and initialize the clock configuration of the clock multiplication chip when the second signal is at a high level.

8. The ultra-high-speed FPGA chip according to claim 7, characterized in that: The FPGA chip further includes an ADC control module, which is connected to the second phase-locked loop module and the main control module; The second phase-locked loop module is further configured to send a third signal to the ADC control module after initializing the clock configuration of the clock multiplication chip; The ADC control module is configured to receive the third signal, and when the third signal is at a high level, initialize the configuration of the ADC chip, and send a fourth signal to the main control module; The main control module is used to receive the fourth signal and start working when the fourth signal is at a high level.

9. A data ultra-high rate acquisition and processing method based on FPGA chip, characterized in that: Applied to the ultra-high-speed FPGA chip according to any one of claims 1 to 8, the method comprising: At the same time, the ultra-high-speed data output by the ADC chip is received to obtain four 512-bit data blocks, and the four 512-bit data blocks are decomposed into 256 8-bit first data units; performing data processing on each of the first data units, and converting the 256 8-bit first data units into 320 8-bit second data units; 320 8-bit second data units are written, read, and stored.

10. The method for ultra-high-speed data acquisition and processing based on FPGA chip according to claim 9, characterized in that: The ultra-high-speed data output by the ADC chip is simultaneously received to obtain four 512-bit data blocks, including: The ultra-high-speed data and synchronization signal output by the ADC chip are received to obtain four 512-bit data blocks; wherein the synchronization signal is used to synchronize and align the data blocks.

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