Driving discrete circuit, anti-dazzling rearview mirror and vehicle

Abstract

The invention relates to a driving discrete circuit, an anti-dazzling rearview mirror and a vehicle. The driving discrete circuit comprises a first signal input end used for accessing a first signal, a second signal input end used for accessing a second signal, a first switch and a second switch which are connected in series, and a connection node between the first switch and the second switch is electrically connected with a power supply node of an electrochromic device; the first driving circuit controls the first switch to be turned on when the first signal is the first level and the second signal is the second level, the first level is opposite to the second level, and the second driving circuit controls the second switch to be turned on when the first signal is the second level and the second signal is the first level. Therefore, the anti-dazzling function of the rearview mirror can be quickly started and stopped by inputting the opposite level signal, the problem that the anti-dazzling function cannot be stopped for a long time due to the fact that the electric quantity on the lens can only be released through parasitic resistance of the lens when the anti-dazzling function is stopped in the related technology is solved, and the use experience of a user is improved.

Description

Technical Field

[0001] The present application relates to the field of vehicle technology, and in particular to a driving discrete circuit, an anti-glare rearview mirror and a vehicle. Background Art

[0002] When encountering strong light, the vehicle's rearview mirror will refract the strong light into the user's eyes, which can easily cause glare and affect driving safety and comfort.

[0003] In the related art, an electronic anti-glare rearview mirror is set up. When the anti-glare function of the electronic anti-glare rearview mirror is turned on, a voltage is applied across the lens to change the reflectivity of the rearview mirror, so that strong light cannot be refracted into the user's eyes.

[0004] However, when the anti-glare function is turned off, the electricity on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. It takes a long time to restore the rearview mirror to normal state, affecting the user's experience, and the control reliability is poor, which needs to be solved urgently. Summary of the Invention

[0005] The present application provides a driving discrete circuit, an anti-glare rearview mirror and a vehicle to solve the problem in the related art that when the anti-glare function is turned off, the power on the electronic anti-glare rearview mirror lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time and poor control reliability. By inputting opposite level signals, the anti-glare function of the rearview mirror can be quickly turned on and off, so that the rearview mirror can quickly return to a normal rearview mirror state, thereby improving control reliability and enhancing user experience.

[0006] To achieve the above objectives, a first embodiment of the present application provides a discrete driving circuit, comprising:

[0007] A first signal input terminal, used for receiving a first signal;

[0008] a second signal input terminal, for receiving a second signal, wherein the first signal and the second signal have opposite levels;

[0009] a first switch and a second switch connected in series, wherein a first end of the first switch is electrically connected to a first voltage input node, a first end of the second switch is electrically connected to a ground node, and a connection node between the first switch and the second switch is electrically connected to a power supply node of a load;

[0010] a first drive circuit, electrically connected to the first signal input terminal, the second signal input terminal, and the control terminal of the first switch, respectively, and configured to control the first switch to be turned on when the first signal is at a first level and the second signal is at a second level, the first level and the second level being opposite;

[0011] The second driving circuit is electrically connected to the first signal input terminal, the second signal input terminal, and the control terminal of the second switch, respectively, and is configured to control the second switch to open when the first signal is at the second level and the second signal is at the first level.

[0012] According to one embodiment of the present application, the first driving circuit includes:

[0013] a first enabling circuit electrically connected to the first signal input terminal, the second voltage input node, and the control terminal of the first switch, respectively, and configured to output a first enabling signal for controlling the first switch to be turned on when the first signal is at the first level;

[0014] The first locking circuit is electrically connected to the first enabling circuit, the second signal input terminal, and the control terminal of the first switch, respectively, and is configured to maintain the level state of the first enabling signal when the second signal is at the second level.

[0015] According to an embodiment of the present application, the first locking circuit is further configured to invalidate the first enable signal when the second signal is at the first level.

[0016] According to one embodiment of the present application, the first enabling circuit includes:

[0017] a third switch, wherein a control terminal of the third switch is electrically connected to the first signal input terminal, and a first terminal of the third switch is electrically connected to the ground node;

[0018] a fourth switch, wherein a control end of the fourth switch is electrically connected to the second end of the third switch, a first end of the fourth switch is electrically connected to the second voltage input node, and a second end of the fourth switch is electrically connected to the control end of the first switch.

[0019] According to one embodiment of the present application, the third switch is a first NPN transistor, the control end of the third switch is the base of the first NPN transistor, the first end of the third switch is the emitter of the first NPN transistor, and the second end of the third switch is the collector of the first NPN transistor;

[0020] The fourth switch is a first PNP transistor, the control end of the third switch is the base of the first PNP transistor, the first end of the third switch is the emitter of the first PNP transistor, and the second end of the third switch is the collector of the first PNP transistor.

[0021] According to one embodiment of the present application, the first locking circuit includes:

[0022] a fifth switch, wherein a control end of the fifth switch is electrically connected to the second signal input end, a first end of the fifth switch is electrically connected to the ground node, and a second end of the fifth switch is electrically connected to the second end of the fourth switch and the control end of the first switch, respectively.

[0023] According to one embodiment of the present application, the fifth switch is a second NPN-type transistor, the control end of the fifth switch is the base of the second NPN-type transistor, the first end of the fifth switch is the emitter of the second NPN-type transistor, and the second end of the fifth switch is the collector of the second NPN-type transistor.

[0024] According to one embodiment of the present application, the second driving circuit includes:

[0025] a second enabling circuit electrically connected to the second signal input terminal, the second voltage input node, and the control terminal of the second switch, respectively, and configured to output a second enabling signal for controlling the second switch to be turned on when the second signal is at the first level;

[0026] The second locking circuit is electrically connected to the second enabling circuit, the first signal input terminal, and the control terminal of the second switch, respectively, and is configured to maintain the level state of the second enabling signal when the first signal is at the second level.

[0027] According to an embodiment of the present application, the second locking circuit is further configured to invalidate the second enable signal when the second signal is at the first level.

[0028] According to one embodiment of the present application, the second enabling circuit includes:

[0029] a sixth switch, wherein a control end of the sixth switch is electrically connected to the second signal input end, and a first end of the sixth switch is electrically connected to the ground node;

[0030] a seventh switch, wherein the control end of the seventh switch is electrically connected to the second end of the sixth switch, the first end of the seventh switch is electrically connected to the second voltage input node, and the second end of the seventh switch is electrically connected to the control end of the second switch.

[0031] According to one embodiment of the present application, the sixth switch is a third NPN transistor, the control end of the sixth switch is the base of the third NPN transistor, the first end of the sixth switch is the emitter of the third NPN transistor, and the second end of the sixth switch is the collector of the third NPN transistor;

[0032] The seventh switch is a second PNP transistor, the control end of the seventh switch is the base of the second PNP transistor, the first end of the seventh switch is the emitter of the second PNP transistor, and the second end of the seventh switch is the collector of the second PNP transistor.

[0033] According to one embodiment of the present application, the second locking circuit includes:

[0034] an eighth switch, wherein a control end of the eighth switch is electrically connected to the first signal input end, a first end of the eighth switch is electrically connected to the ground node, and a second end of the eighth switch is electrically connected to the second end of the seventh switch and the control end of the second switch element, respectively.

[0035] According to one embodiment of the present application, the eighth switch is a fourth NPN-type transistor, the control end of the eighth switch is the base of the fourth NPN-type transistor, the first end of the eighth switch is the emitter of the fourth NPN-type transistor, and the second end of the eighth switch is the collector of the fourth NPN-type transistor.

[0036] According to one embodiment of the present application, the first driving circuit further includes:

[0037] a first resistor, one end of the first resistor being electrically connected to the second voltage input node and the first end of the fourth switch, respectively, and the other end of the first resistor being electrically connected to the control end of the fourth switch;

[0038] a second resistor, one end of the second resistor being electrically connected to the control end of the fourth switch, and the other end of the second resistor being electrically connected to the second end of the third switch;

[0039] a third resistor, one end of the third resistor being electrically connected to the first signal input end, and the other end of the third resistor being electrically connected to the control end of the third switch;

[0040] a fourth resistor, one end of the fourth resistor being electrically connected to the other end of the third resistor and the control end of the third switch, respectively, and the other end of the fourth resistor being electrically connected to the ground node;

[0041] a fifth resistor, one end of the fifth resistor being electrically connected to the second end of the fourth switch, and the other end of the fifth resistor being electrically connected to the second end of the fourth switch and the control end of the first switch, respectively;

[0042] a sixth resistor, one end of the sixth resistor being electrically connected to the other end of the fifth resistor, the second end of the fifth switch, and the control end of the first switch respectively;

[0043] a seventh resistor, one end of the seventh resistor being electrically connected to the second signal input end, and the other end of the seventh resistor being electrically connected to the control end of the fifth switch;

[0044] an eighth resistor, one end of the eighth resistor being electrically connected to the control end of the fifth switch and the other end of the seventh resistor, respectively, and the other end of the seventh resistor being electrically connected to the ground node.

[0045] According to one embodiment of the present application, the second driving circuit further includes:

[0046] a ninth resistor, one end of the ninth resistor being electrically connected to the second voltage input node and the first end of the seventh switch, respectively, and the other end of the ninth resistor being electrically connected to the control end of the seventh switch;

[0047] a tenth resistor, one end of the tenth resistor being electrically connected to the control end of the seventh switch, and the other end of the tenth resistor being electrically connected to the second end of the sixth switch;

[0048] an eleventh resistor, one end of the eleventh resistor being electrically connected to the second signal input end, and the other end of the eleventh resistor being electrically connected to the control end of the sixth switch;

[0049] a twelfth resistor, one end of the twelfth resistor being electrically connected to the other end of the eleventh resistor and the control end of the sixth switch, respectively, and the other end of the twelfth resistor being electrically connected to the ground node;

[0050] a thirteenth resistor, one end of the thirteenth resistor being electrically connected to the second end of the seventh switch, and the other end of the thirteenth resistor being electrically connected to the second end of the eighth switch and the control end of the second switch respectively;

[0051] a fourteenth resistor, one end of the fourteenth resistor being electrically connected to the other end of the thirteenth resistor, the second end of the eighth switch, and the control end of the second switch;

[0052] a fifteenth resistor, one end of the fifteenth resistor being electrically connected to the first signal input end, and the other end of the fifteenth resistor being electrically connected to the control end of the eighth switch;

[0053] a sixteenth resistor, one end of the sixteenth resistor being electrically connected to the control end of the eighth switch and the other end of the fifteenth resistor, respectively, and the other end of the sixteenth resistor being electrically connected to the ground node.

[0054] According to one embodiment of the present application, the first level is a high level, and the second level is a low level.

[0055] According to one embodiment of the present application, the above-mentioned discrete driving circuit further includes:

[0056] a ninth switch, wherein a first end of the ninth switch is electrically connected to the control end of the second switch, and a second end of the ninth switch is electrically connected to the ground node;

[0057] The third driving circuit is electrically connected to the power supply node of the load, the control end of the ninth switch and the ground node respectively, and is configured to control the ninth switch to open when the voltage of the power supply node of the load is greater than a preset voltage.

[0058] According to one embodiment of the present application, the third driving circuit includes:

[0059] a seventeenth resistor, one end of the seventeenth resistor being electrically connected to a connection node between the first switch and the second switch;

[0060] an eighteenth resistor, one end of the eighteenth resistor being electrically connected to the other end of the seventeenth resistor, and the other end of the eighteenth resistor being electrically connected to the ground node.

[0061] According to one embodiment of the present application, the above-mentioned discrete driving circuit further includes:

[0062] A diode, wherein an anode of the diode is electrically connected to the first voltage input node, and a cathode of the diode is electrically connected to the first end of the first switch.

[0063] According to one embodiment of the present application, the above-mentioned discrete driving circuit further includes:

[0064] A voltage detection output terminal, used for outputting the voltage of the power supply node of the load;

[0065] A filter circuit, one end of the filter circuit is electrically connected to a connection node between the first switch and the second switch, and the other end of the filter circuit is electrically connected to the voltage detection output end.

[0066] According to one embodiment of the present application, the filtering circuit includes:

[0067] a nineteenth resistor, one end of the nineteenth resistor being electrically connected to a connection node between the first switch and the second switch, and the other end of the nineteenth resistor being electrically connected to the voltage detection output terminal;

[0068] A first capacitor, one end of the first capacitor is electrically connected to the other end of the nineteenth resistor and the voltage detection output end respectively, and the other end of the first capacitor is electrically connected to the ground node.

[0069] According to one embodiment of the present application, the above-mentioned discrete driving circuit further includes:

[0070] A second capacitor, one end of the second capacitor is electrically connected to a connection node between the first switch and the second switch, and the other end of the second capacitor is electrically connected to the ground node.

[0071] According to an embodiment of the present application, the first switch is a first NMOS transistor, the second switch is a second NMOS transistor, and the ninth switch is a third NMOS transistor, wherein:

[0072] The control end of the first switch is the gate of the first NMOS transistor, the first end of the first switch is the drain of the first NMOS transistor, and the second end of the first switch is the source of the first NMOS transistor;

[0073] The control end of the second switch is the gate of the second NMOS transistor, the first end of the second switch is the source of the second NMOS transistor, and the second end of the second switch is the drain of the second NMOS transistor;

[0074] The control end of the ninth switch is the gate of the third NMOS transistor, the first end of the ninth switch is the drain of the third NMOS transistor, and the second end of the ninth switch is the source of the third NMOS transistor.

[0075] According to the driving discrete circuit proposed in the embodiment of the present application, when the anti-glare function of the rearview mirror is turned on, a high level can be connected through the first signal input terminal, and a low level can be connected through the second signal input terminal, so that the first driving circuit controls the first switch to open when the first signal is the first level and the second signal is the second level, so that the power supply externally connected to the first voltage input node corresponding to the first switch provides voltage to the load; when the anti-glare function of the rearview mirror is turned off, a low level can be connected through the first signal input terminal, and a high level can be connected through the second signal input terminal, so that the second driving circuit controls the second switch to open when the first signal is the second level and the second signal is the first level, and discharges the power of the load through the ground node corresponding to the second switch, thereby solving the problem in the related art that when the anti-glare function is turned off, the power on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function cannot be turned off for a long time. While improving the control reliability, it also enhances the user experience.

[0076] To achieve the above-mentioned purpose, the second embodiment of the present application proposes an anti-glare rearview mirror, which includes: the driving discrete circuit and the load proposed in the above-mentioned first embodiment, and the output end of the driving discrete circuit is electrically connected to the power supply end of the load.

[0077] According to the anti-glare rearview mirror proposed in the embodiment of the present application, the above-mentioned discrete driving circuit is used to solve the problem in the related art that when the anti-glare function is turned off, the electricity on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves the control reliability while enhancing the user experience.

[0078] To achieve the above-mentioned objectives, a third embodiment of the present application proposes a vehicle, which includes the anti-glare rearview mirror proposed in the second embodiment.

[0079] The vehicle proposed in the embodiment of the present application uses the above-mentioned anti-glare rearview mirror to solve the problem in the related art that when the anti-glare function is turned off, the power on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves control reliability while enhancing the user experience.

[0080] To achieve the above-mentioned objectives, a fourth embodiment of the present application provides an anti-dizziness method for an anti-glare rearview mirror, which adopts the driving discrete circuit proposed in the first embodiment, wherein the method includes the following steps:

[0081] Get the current demand for anti-glare rearview mirrors;

[0082] If the current requirement is to enable the anti-glare function, configure the first signal to be the first level and the second signal to be the second level; otherwise, configure the first signal to be the second level and the second signal to be the first level; and

[0083] sending the first signal to the first driving circuit and simultaneously sending the second signal to the second driving circuit;

[0084] The first level and the second level are opposite.

[0085] According to one embodiment of the present application, the anti-dizziness method for the anti-glare rearview mirror further includes:

[0086] Acquire a first detection voltage at a voltage detection output terminal;

[0087] If the first detection voltage is greater than a first preset voltage, or the first detection voltage is less than the first preset voltage, configuring the first signal to be the second level and the second signal to be the second level;

[0088] sending the first signal to the first driving circuit and simultaneously sending the second signal to the second driving circuit;

[0089] Wherein, the first preset voltage is greater than the second preset voltage.

[0090] According to the anti-dizziness method for an anti-glare rearview mirror proposed in an embodiment of the present application, the current demand of the anti-glare rearview mirror is obtained. When the current demand is to turn on the anti-glare function, the first signal is configured to be the first level and the second signal is the second level. When the current demand is to turn off the anti-glare function, the first signal is configured to be the second level and the second signal is configured to be the first level. The first signal is sent to the first drive circuit, and the second signal is sent to the second drive circuit at the same time. Thus, by inputting signals of opposite levels to control the opening and closing of the first switch and the second switch, rapid charging and rapid discharging of the load are achieved, thereby achieving rapid turning on and off of the anti-glare function of the rearview mirror. This solves the problem in the related art that when the anti-glare function is turned off, the power on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves control reliability while enhancing the user experience.

[0091] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0093] Figure 1 A block diagram of a discrete driving circuit provided according to an embodiment of the present application;

[0094] Figure 2 This is a schematic diagram of the current curve and voltage curve when the anti-glare function of the electronic anti-glare rearview mirror is turned on;

[0095] Figure 3 Schematic diagram of current and voltage curves when the anti-glare function of an electronic anti-glare rearview mirror is turned off in the related art;

[0096] Figure 4 A schematic diagram of a current curve and a voltage curve when the anti-glare function of an electronic anti-glare rearview mirror is turned off according to an embodiment of the present application;

[0097] Figure 5 This is a circuit diagram of a discrete driving circuit according to a specific embodiment of the present application;

[0098] Figure 6 This is a block diagram of an electronic anti-glare rearview mirror according to one embodiment of the present application;

[0099] Figure 7 The present invention provides a flowchart of an anti-dizziness method for an anti-glare rearview mirror according to an embodiment of the present application. DETAILED DESCRIPTION

[0100] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0101] The following describes the driving discrete circuit, anti-glare rearview mirror and vehicle proposed according to the embodiments of the present application with reference to the accompanying drawings. First, the driving discrete circuit proposed according to the embodiments of the present application will be described with reference to the accompanying drawings.

[0102] Figure 1 1 is a block diagram of a discrete driving circuit according to an embodiment of the present application.

[0103] Before introducing the discrete driving circuit of the embodiment of the present application, the anti-glare principle of the electronic anti-glare rearview mirror is briefly introduced.

[0104] Specifically, the anti-glare principle of the electronic anti-glare rearview mirror is to change the voltage across the lens, causing chemical changes inside the lens and changing the color of the lens to achieve a change in the reflection effect of external light and achieve anti-glare.

[0105] Specifically, the lenses of electronic anti-glare rearview mirrors generally use electrochromic devices, which can be equivalent to a capacitive load. When the anti-glare function needs to be turned on, a voltage is applied across the lens (generally 1.2V), that is, the lens is charged, and the color of the lens will become darker; when the anti-glare function needs to be turned off, the voltage across the lens is adjusted back to zero voltage difference, even if the lens is discharged, the color of the lens will become lighter, restoring the effect of an ordinary rearview mirror.

[0106] To further facilitate understanding, the following is a detailed explanation based on the current and voltage curves of the electronic anti-glare rearview mirror with the anti-glare function turned on and off.

[0107] like Figure 2 As shown, Figure 2 This is a schematic diagram of the current curve and voltage curve when the anti-glare function of the electronic anti-glare rearview mirror is turned on. When the anti-glare function of the electronic anti-glare rearview mirror needs to be turned on, the lens of the electronic anti-glare rearview mirror is equivalent to a capacitor. When voltage is applied across the lens, there will be spike voltage and spike current, which will gradually become stable after a certain period of time.

[0108] like Figure 3 As shown, Figure 3This is a schematic diagram of the current and voltage curves of an electronic anti-glare rearview mirror in the related art when the anti-glare function is turned off. When the anti-glare function of the electronic anti-glare rearview mirror is turned off, the lens of the electronic anti-glare rearview mirror acts as a capacitor, and the charge on the rearview lens cannot be discharged quickly, which is manifested as a decrease in current and a slow decrease in voltage. This shows that when the anti-glare function is turned off, the charge on the lens can only be discharged through the lens itself, and it takes a long time to restore the rearview mirror to normal state.

[0109] Based on the above problems, the present application changes the driving circuit of the electronic anti-glare rearview mirror. When the anti-glare function of the electronic anti-glare rearview mirror needs to be turned off, the power on the lens can be quickly released. The current will have a reverse current, but the voltage can drop rapidly. The current curve and voltage curve diagram when the anti-glare function of the electronic anti-glare rearview mirror is turned off can be shown as follows: Figure 4 As shown, this solves the problem in the related art that when the anti-glare function is turned off, the power on the electronic anti-glare rearview mirror lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. The anti-glare function of the rearview mirror can be quickly turned on and off, so that the rearview mirror can quickly return to a normal rearview mirror state, thereby improving the user experience.

[0110] The following combination Figure 1 The discrete driving circuit of the embodiment of the present application is described in detail.

[0111] like Figure 1 As shown, the discrete driving circuit 10 includes: a first signal input terminal CONTROL_SIGNAL1 , a second signal input terminal CONTROL_SIGNAL2 , a first switch Q1 , a second switch Q2 , a first driving circuit 100 and a second driving circuit 200 .

[0112] The first signal input terminal CONTROL_SIGNAL1 is used to receive a first signal; the second signal input terminal CONTROL_SIGNAL2 is used to receive a second signal, and the first signal and the second signal have opposite voltage levels. A first switch Q1 and a second switch Q2 are connected in series, with a first terminal of the first switch Q1 electrically connected to a first voltage input node, a first terminal of the second switch Q2 electrically connected to a ground node, and a connection node between the first switch Q1 and the second switch Q2 electrically connected to a power supply node of a load. The first driver circuit 100 is electrically connected to the first signal input terminal CONTROL_SIGNAL1, the second signal input terminal CONTROL_SIGNAL2, and a control terminal of the first switch Q1, respectively, and is configured to control the first switch Q1 to turn on when the first signal is at a first voltage level and the second signal is at a second voltage level, the first voltage level and the second voltage level being opposite. The second driver circuit 200 is electrically connected to the first signal input terminal CONTROL_SIGNAL1, the second signal input terminal CONTROL_SIGNAL2, and a control terminal of the second switch Q2, respectively, and is configured to control the second switch Q2 to turn on when the first signal is at the second voltage level and the second signal is at the first voltage level.

[0113] Among them, the load can be an electrochromic device, which is a device made of electrochromic material. The electrochromic material has electrochromic properties. Electrochromism is a phenomenon in which the optical properties (reflectivity, transmittance, absorptivity, etc.) of the material undergo stable and reversible color changes under the action of an external electric field, which is manifested in appearance as reversible changes in color and transparency; the power supply externally connected to the first voltage input node can be a vehicle power supply or other power supply; the first level can be a high level, and the second level can be a low level; the first switch Q1 and the second switch Q2 can both be NMOS tubes, for example, the first switch Q1 can be a first NMOS tube, and the second switch Q2 can be a second NMOS tube.

[0114] It should be understood that both the first signal and the second signal may be level signals, wherein the level signals have a high level and a low level. For example, if the first level is a high level and the second level is a low level, then when the first signal is at the first level, the second signal is at the second level, and when the first signal is at the second level, the second signal is at the first level.

[0115] Specifically, when the voltage differential across the load needs to be changed, embodiments of the present application can change the voltage differential across the load by adjusting the voltage provided to the load. For example, embodiments of the present application can connect a first voltage level to the first signal input terminal CONTROL_SIGNAL1 and a second voltage level to the second signal input terminal CONTROL_SIGNAL2. In this case, the first switch Q1 is turned on and the second switch Q2 is turned off. In this embodiment, the load can be supplied with voltage via a power supply externally connected to the first voltage input node. When the load needs to be discharged quickly, embodiments of the present application can connect a second voltage level to the first signal input terminal CONTROL_SIGNAL1 and a first voltage level to the second signal input terminal CONTROL_SIGNAL2. In this case, the first switch Q1 is turned off and the second switch Q2 is turned on. In this embodiment, the load can be discharged via the ground node.

[0116] Thus, when the rearview mirror anti-glare function is enabled, a high level is connected to the first signal input terminal CONTROL_SIGNAL1, and a low level is connected to the second signal input terminal CONTROL_SIGNAL2. This allows the first driver circuit 100 to control the first switch Q1 to open when the first signal is at the first level and the second signal is at the second level, thereby providing voltage to the load through the external power supply connected to the first voltage input node corresponding to the first switch Q1. When the rearview mirror anti-glare function is disabled, a low level is connected to the first signal input terminal CONTROL_SIGNAL1, and a high level is connected to the second signal input terminal CONTROL_SIGNAL2. This allows the second driver circuit 200 to control the second switch Q2 to open when the first signal is at the second level and the second signal is at the first level, thereby discharging power from the load through the ground node corresponding to the second switch Q2. In other words, when the first and second driver circuits 100 and 200 are turned on, the corresponding signal levels are opposite. Therefore, at any given moment, at most one driver circuit is active, preventing damage to the switch tube caused by both switches being turned on simultaneously. This improves control reliability and enhances the user experience.

[0117] In order for those skilled in the art to further understand the discrete driving circuit 10 of the embodiment of the present application, a detailed description is given below in conjunction with specific embodiments.

[0118] According to one embodiment of the present application, Figure 5As shown, the first driving circuit 100 includes: a first enabling circuit and a first locking circuit. The first enabling circuit is electrically connected to the first signal input terminal CONTROL_SIGNAL1, the second voltage input node, and the control terminal of the first switch Q1, and is configured to output a first enabling signal that controls the first switch Q1 to turn on when the first signal is at a first level. The first locking circuit is electrically connected to the first enabling circuit, the second signal input terminal CONTROL_SIGNAL2, and the control terminal of the first switch Q1, and is configured to maintain the level of the first enabling signal when the second signal is at a second level.

[0119] It should be understood that if Figure 5 As shown, to control the first switch to open, a high level needs to be input to the control terminal of the first switch Q1. Therefore, in the embodiment of the present application, a high level (i.e., a first level) can be connected to the first signal input terminal CONTROL_SIGNAL1, so that the first drive circuit 100 outputs a first enable signal, and a low level (i.e., a second level) is connected to the second signal input terminal CONTROL_SIGNAL2, so that the first locking circuit can maintain the level state of the first enable signal, thereby controlling the first switch Q1 to open through the first drive circuit 100, so that the load can be provided with voltage through the power supply externally connected to the first voltage input node.

[0120] Furthermore, according to an embodiment of the present application, the first locking circuit is further configured to disable the first enable signal when the second signal is at the first level.

[0121] It should be understood that in order to prevent the second switch Q2 from being turned on at the same time as the first switch Q1 is turned on, causing a short circuit in the circuit, the embodiment of the present application can use the first locking circuit to input the second signal at the second signal input terminal CONTROL_SIGNAL2 at a high level (i.e., the first level), so that the first enable signal output by the first enable circuit is invalid, thereby effectively protecting the driving discrete circuit 10.

[0122] The following describes in detail how to control the first switch Q1 to turn on in conjunction with the circuit structures of the first enabling circuit and the first locking circuit.

[0123] According to one embodiment of the present application, Figure 5 As shown, the first enabling circuit includes: a third switch Q3 and a fourth switch Q4. The control terminal of the third switch Q3 is electrically connected to the first signal input terminal CONTROL_SIGNAL1, and the first terminal of the third switch Q3 is electrically connected to the ground node. The control terminal of the fourth switch Q4 is electrically connected to the second terminal of the third switch Q3, the first terminal of the fourth switch Q4 is electrically connected to the second voltage input node, and the second terminal of the fourth switch Q4 is electrically connected to the control terminal of the first switch Q1.

[0124] According to one embodiment of the present application, the third switch Q3 may be a first NPN transistor, the control end of the third switch Q3 being the base of the first NPN transistor, the first end of the third switch Q3 being the emitter of the first NPN transistor, and the second end of the third switch Q3 being the collector of the first NPN transistor; the fourth switch Q4 may be a first PNP transistor, the control end of the third switch Q3 being the base of the first PNP transistor, the first end of the third switch Q3 being the emitter of the first PNP transistor, and the second end of the third switch Q3 being the collector of the first PNP transistor.

[0125] According to one embodiment of the present application, Figure 5 As shown, the first locking circuit includes a fifth switch Q5. A control terminal of the fifth switch Q5 is electrically connected to the second signal input terminal CONTROL_SIGNAL2. A first terminal of the fifth switch Q5 is electrically connected to the ground node. A second terminal of the fifth switch Q5 is electrically connected to the second terminal of the fourth switch Q4 and the control terminal of the first switch Q1, respectively.

[0126] In which, according to one embodiment of the present application, the fifth switch Q5 is a second NPN-type transistor, the control end of the fifth switch Q5 is the base of the second NPN-type transistor, the first end of the fifth switch Q5 is the emitter of the second NPN-type transistor, and the second end of the fifth switch Q5 is the collector of the second NPN-type transistor.

[0127] According to one embodiment of the present application, the control end of the first switch Q1 may be the gate of the first NMOS transistor, the first end of the first switch Q1 may be the drain of the first NMOS transistor, and the second end of the first switch Q1 may be the source of the first NMOS transistor; the control end of the second switch Q2 may be the gate of the second NMOS transistor, the first end of the second switch Q2 may be the source of the second NMOS transistor, and the second end of the second switch Q2 may be the drain of the second NMOS transistor.

[0128] According to one embodiment of the present application, the first driving circuit 100 further includes: a first resistor R1, one end of the first resistor R1 being electrically connected to the second voltage input node and the first end of the fourth switch Q4, respectively, and the other end of the first resistor R1 being electrically connected to the control end of the fourth switch Q4; a second resistor R2, one end of the second resistor R2 being electrically connected to the control end of the fourth switch Q4, and the other end of the second resistor R2 being electrically connected to the second end of the third switch Q3; a third resistor R3, one end of the third resistor R3 being electrically connected to the first signal input terminal CONTROL_SIGNAL1, and the other end of the third resistor R3 being electrically connected to the control end of the third switch Q3; a fourth resistor R4, one end of the fourth resistor R4 being electrically connected to the other end of the third resistor R3 and the control end of the third switch Q3, respectively. 4 is electrically connected to the ground node; a fifth resistor R5, one end of the fifth resistor R5 is electrically connected to the second end of the fourth switch Q4, and the other end of the fifth resistor R5 is electrically connected to the second end of the fourth switch Q4 and the control end of the first switch Q1, respectively; a sixth resistor R6, one end of the sixth resistor R6 is electrically connected to the other end of the fifth resistor R5, the second end of the fifth switch Q5, and the control end of the first switch Q1, respectively; a seventh resistor R7, one end of the seventh resistor R7 is electrically connected to the second signal input terminal CONTROL_SIGNAL2, and the other end of the seventh resistor R7 is electrically connected to the control end of the fifth switch Q5; an eighth resistor R8, one end of the eighth resistor R8 is electrically connected to the control end of the fifth switch Q5 and the other end of the seventh resistor R7, respectively, and the other end of the seventh resistor R7 is electrically connected to the ground node.

[0129] For example, taking an electronic anti-glare rearview mirror as an example, the lens of the electronic anti-glare rearview mirror is the load.

[0130] When the electronic anti-glare rearview mirror activates the anti-glare function, in the embodiment of the present application, a first voltage level can be connected to the first signal input terminal CONTROL_SIGNAL1. Since the first voltage level is high, current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned on. Since the third switch Q3 is turned on, the external power supply VCC_5V at the second voltage input node forms a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3, and the fourth switch Q4 is turned on. Since the embodiment of the present application also connects the second voltage level to the second signal input terminal CONTROL_SIGNAL2, no current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is turned off.

[0131] In the embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is simultaneously connected to the second voltage level, no current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is closed. Because the sixth switch Q6 is closed, the external power supply VCC_5V at the second voltage input node cannot form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is closed. Since the first signal input terminal CONTROL_SIGNAL1 is connected to the first voltage level in the embodiment of the present application, current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is opened.

[0132] As a result, the external power supply VCC_5V at the second voltage input node can form a loop through the fifth resistor R5 and the sixth resistor R6. Current flows through the sixth resistor R6, creating a voltage difference between the gate and source of the first switch Q1, turning on the first switch Q1. The external power supply VCC_5V at the second voltage input node cannot form a loop through the thirteenth resistor R13 and the fourteenth resistor R14. Current cannot flow through the fourteenth resistor R14, resulting in no voltage difference between the gate and source of the second switch Q2. The gate of the second switch Q2 is grounded, turning off the second switch Q2. Therefore, the first switch Q1 is turned on, the second switch Q2 is turned off, and the external power supply VCC_1V2 at the first voltage input node can provide voltage to the load through the second switch Q2.

[0133] Furthermore, according to one embodiment of the present application, Figure 5 As shown, the second driving circuit 200 includes: a second enabling circuit and a second locking circuit. The second enabling circuit is electrically connected to the second signal input terminal CONTROL SIGNAL2, the second voltage input node, and the control terminal of the second switch Q2, and is configured to output a second enabling signal that controls the second switch Q2 to turn on when the second signal is at a first level. The second locking circuit is electrically connected to the second enabling circuit, the first signal input terminal CONTROL_SIGNAL1, and the control terminal of the second switch Q2, and is configured to maintain the level of the second enabling signal when the first signal is at a second level.

[0134] It should be understood that if Figure 5As shown, to control the second switch to open, a high level needs to be input to the control terminal of the second switch Q2. Therefore, in the embodiment of the present application, a high level (i.e., a first level) can be connected to the second signal input terminal CONTROL_SIGNAL2, so that the second drive circuit 200 outputs a second enable signal, and a low level (i.e., a second level) is connected to the first signal input terminal CONTROL_SIGNAL1, so that the second locking circuit can maintain the level state of the second enable signal, thereby controlling the second switch Q2 to open through the second drive circuit 200, so that the load power can be discharged through the ground node.

[0135] Furthermore, according to an embodiment of the present application, the second locking circuit is further configured to disable the second enable signal when the second signal is at the first level.

[0136] It should be understood that in order to prevent the second switch Q2 from being turned on at the same time as the first switch Q1 is turned on, causing a short circuit in the circuit, the embodiment of the present application can use the second locking circuit to input the second signal at the second signal input terminal CONTROL_SIGNAL2 at a high level (i.e., the first level), so that the second enable signal output by the second enable circuit is invalid, thereby effectively protecting the driving discrete circuit 10.

[0137] How to control the first switch Q1 to turn on will be described in detail below in conjunction with the circuit structures of the second enabling circuit and the second locking circuit.

[0138] According to one embodiment of the present application, Figure 5 As shown, the second enabling circuit includes: a sixth switch Q6, wherein the control terminal of the sixth switch Q6 is electrically connected to the second signal input terminal CONTROL_SIGNAL2, and the first terminal of the sixth switch Q6 is electrically connected to the ground node; and a seventh switch Q7, wherein the control terminal of the seventh switch Q7 is electrically connected to the second terminal of the sixth switch Q6, the first terminal of the seventh switch Q7 is electrically connected to the second voltage input node, and the second terminal of the seventh switch Q7 is electrically connected to the control terminal of the second switch Q2.

[0139] According to one embodiment of the present application, the sixth switch Q6 is a third NPN transistor, the control end of the sixth switch Q6 is the base of the third NPN transistor, the first end of the sixth switch Q6 is the emitter of the third NPN transistor, and the second end of the sixth switch Q6 is the collector of the third NPN transistor; the seventh switch Q7 is a second PNP transistor, the control end of the seventh switch Q7 is the base of the second PNP transistor, the first end of the seventh switch Q7 is the emitter of the second PNP transistor, and the second end of the seventh switch Q7 is the collector of the second PNP transistor.

[0140] According to one embodiment of the present application, the second locking circuit includes an eighth switch Q8 , wherein a control terminal of the eighth switch Q8 is electrically connected to the first signal input terminal CONTROL_SIGNAL1 , a first terminal of the eighth switch Q8 is electrically connected to the ground node, and a second terminal of the eighth switch Q8 is electrically connected to the second terminal of the seventh switch Q7 and the control terminal of the second switch Q2 , respectively.

[0141] In which, according to one embodiment of the present application, the eighth switch Q8 is a fourth NPN-type transistor, the control end of the eighth switch Q8 is the base of the fourth NPN-type transistor, the first end of the eighth switch Q8 is the emitter of the fourth NPN-type transistor, and the second end of the eighth switch Q8 is the collector of the fourth NPN-type transistor.

[0142] According to one embodiment of the present application, the second driving circuit 200 further includes: a ninth resistor R9, one end of the ninth resistor R9 being electrically connected to the second voltage input node and the first end of the seventh switch Q7, respectively, and the other end of the ninth resistor R9 being electrically connected to the control end of the seventh switch Q7; a tenth resistor R10, one end of the tenth resistor R10 being electrically connected to the control end of the seventh switch Q7, and the other end of the tenth resistor R10 being electrically connected to the second end of the sixth switch Q6; an eleventh resistor R11, one end of the eleventh resistor R11 being electrically connected to the second signal input terminal CONTROL_SIGNAL2, and the other end of the eleventh resistor R11 being electrically connected to the control end of the sixth switch Q6; and a twelfth resistor R12, one end of the twelfth resistor R12 being electrically connected to the other end of the eleventh resistor R11 and the control end of the sixth switch Q6, respectively, and the other end of the twelfth resistor R12 being electrically connected to the second end of the eleventh resistor R11 and the control end of the sixth switch Q6, respectively. a thirteenth resistor R13, one end of the thirteenth resistor R13 being electrically connected to the second end of the seventh switch Q7, and the other end of the thirteenth resistor R13 being electrically connected to the second end of the eighth switch Q8 and the control end of the second switch Q2, respectively; a fourteenth resistor R14, one end of the fourteenth resistor R14 being electrically connected to the other end of the thirteenth resistor R13, the second end of the eighth switch Q8, and the control end of the second switch Q2, respectively; a fifteenth resistor R15, one end of the fifteenth resistor R15 being electrically connected to the first signal input terminal CONTROL_SIGNAL1, and the other end of the fifteenth resistor R15 being electrically connected to the control end of the eighth switch Q8; and a sixteenth resistor R16, one end of the sixteenth resistor R16 being electrically connected to the control end of the eighth switch Q8 and the other end of the fifteenth resistor R15, respectively, and the other end of the sixteenth resistor R16 being electrically connected to the ground node.

[0143] For example, taking an electronic anti-glare rearview mirror as an example, the lens of the electronic anti-glare rearview mirror is the load.

[0144] When the electronic anti-glare rearview mirror turns off the anti-glare function, in the embodiment of the present application, the second voltage level can be connected to the first signal input terminal CONTROL_SIGNAL1. Since the second voltage level is low, no current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is closed. Since the third switch Q3 is closed, the external power supply VCC_5V at the second voltage input node cannot form a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3, and the fourth switch Q4 is closed. Since the embodiment of the present application also connects the first voltage level to the second signal input terminal CONTROL_SIGNAL2, current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is opened.

[0145] In the embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is simultaneously connected to the first level, current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is turned on. Because the sixth switch Q6 is turned on, the external power supply VCC_5V at the second voltage input node can form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is turned on. Because the first signal input terminal CONTROL_SIGNAL1 is connected to the second level in the embodiment of the present application, no current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is turned off.

[0146] Therefore, the external power supply VCC_5V at the second voltage input node can form a loop through the thirteenth resistor R13 and the fourteenth resistor R14. Current flows through the fourteenth resistor R14, generating a voltage difference between the gate and source of the second switch Q2, turning on the second switch Q2. The external power supply VCC_5V at the second voltage input node cannot form a loop through the fifth resistor R5 and the sixth resistor R6. Current cannot flow through the sixth resistor R6, resulting in no voltage difference between the gate and source of the first switch Q1. The gate of the first switch Q1 is grounded, and the first switch Q1 is turned off. As a result, the first switch Q1 is turned off and the second switch Q2 is turned on. In this embodiment of the present application, the load power can be discharged through the ground node.

[0147] It should be noted that the discrete driving circuit 10 of the embodiment of the present application may also control the first switch Q1 and the second switch Q2 to be turned off when the same signal is input to the first signal input terminal CONTROL_SIGNAL1 and the second signal input terminal CONTROL_SIGNAL2.

[0148] As a possible implementation method, if the first signal input terminal CONTROL_SIGNAL1 is connected to the first level, the second signal input terminal CONTROL_SIGNAL2 is also connected to the first level;

[0149] Because the first signal input terminal CONTROL_SIGNAL1 is connected to the first voltage level in the embodiment of the present application, current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned on. Because the third switch Q3 is turned on, the external power supply VCC_5V at the second voltage input node forms a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3, and the fourth switch Q4 is turned on. Because the second signal input terminal CONTROL_SIGNAL2 is also connected to the first voltage level in the embodiment of the present application, current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is turned on.

[0150] Since the second signal input terminal CONTROL_SIGNAL2 is connected to the first level in the embodiment of the present application, current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is turned on; since the sixth switch Q6 is turned on, the external power supply VCC_5V of the second voltage input node can form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10 and the sixth switch Q6, and the seventh switch Q7 is turned on; since the first signal input terminal CONTROL_SIGNAL1 is connected to the first level in the embodiment of the present application, current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is turned on.

[0151] Therefore, the opening of the fifth switch Q5 causes the gate of the first switch Q1 to be grounded, turning the first switch Q1 off. Simultaneously, the opening of the eighth switch Q8 causes the gate of the second switch Q2 to be grounded, turning the second switch Q2 off. Therefore, although the external power supply VCC_5V at the second voltage input node forms a current path, the gates of the first and second switches Q1, Q2, and Q2 are both off because there is no voltage difference between their sources.

[0152] As a possible implementation, if the first signal input terminal CONTROL_SIGNAL1 is connected to the second voltage level, the second signal input terminal CONTROL_SIGNAL2 is also connected to the second voltage level. Since the embodiment of the present application connects the second voltage level to the first signal input terminal CONTROL_SIGNAL1, and since the second voltage level is low, no current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned off. Since the third switch Q3 is turned off, the external power supply VCC_5V at the second voltage input node cannot form a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3. Therefore, the fourth switch Q4 is turned off. Since the embodiment of the present application connects the second voltage level to the second signal input terminal CONTROL_SIGNAL2 at the same time, no current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5. Therefore, the fifth switch Q5 is turned off.

[0153] Because in this embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is connected to the second voltage level, no current flows through the eleventh resistor R11 or the base and emitter of the sixth switch Q6, and the sixth switch Q6 is closed. Because the sixth switch Q6 is closed, the external power supply VCC_5V connected to the second voltage input node cannot form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is closed. Because in this embodiment of the present application, the first signal input terminal CONTROL_SIGNAL1 is connected to the second voltage level, no current flows through the fifteenth resistor R15 or the base and emitter of the eighth switch Q8, and the eighth switch Q8 is closed.

[0154] Therefore, the external power supply VCC_5V of the second voltage input node does not form a current path, and there is no voltage difference between the gate and source of the first switch Q1 and the second switch Q2. The first switch Q1 and the second switch Q2 are both turned off.

[0155] Furthermore, in order to protect the discrete driving circuit 10 , the embodiment of the present application may further provide a corresponding protection circuit.

[0156] According to one embodiment of the present application, Figure 5 As shown, the above-mentioned discrete driving circuit 10 further includes: a ninth switch Q9 and a third driving circuit. A first terminal of the ninth switch Q9 is electrically connected to the control terminal of the second switch Q2, and a second terminal of the ninth switch Q9 is electrically connected to the ground node. The third driving circuit is electrically connected to the power supply node of the load, the control terminal of the ninth switch Q9, and the ground node, respectively, and is configured to control the ninth switch Q9 to turn on when the voltage of the power supply node of the load is greater than a preset voltage.

[0157] According to one embodiment of the present application, the third driving circuit includes a seventeenth resistor R17 and an eighteenth resistor R18. One end of the seventeenth resistor R17 is electrically connected to the connection node between the first switch Q1 and the second switch Q2; one end of the eighteenth resistor R18 is electrically connected to the other end of the seventeenth resistor R17, and the other end of the eighteenth resistor R18 is electrically connected to the ground node.

[0158] According to one embodiment of the present application, the ninth switch Q9 is a third NMOS transistor, the control end of the ninth switch Q9 is the gate of the third NMOS transistor, the first end of the ninth switch Q9 is the drain of the third NMOS transistor, and the second end of the ninth switch Q9 is the source of the third NMOS transistor.

[0159] It should be understood that if Figure 5 As shown, in order to prevent damage to the second switch Q2 when a short circuit occurs to the power supply at the output terminal VOUT of the driving discrete circuit 10, the embodiment of the present application can be provided with a ninth switch Q9 and a third driving circuit. When a short circuit occurs to the power supply at the output terminal VOUT of the driving discrete circuit 10, the embodiment of the present application can divide the short-circuited power supply voltage by the seventeenth resistor R17 and the eighteenth resistor R18, and at the same time drive the ninth switch Q9 to open, so that the gate voltage of the second switch Q2 is pulled to ground and the second switch Q2 is turned off, thereby effectively protecting the second switch Q2. Moreover, the protection can be achieved more quickly through hardware action.

[0160] According to one embodiment of the present application, Figure 5 As shown, the above-mentioned discrete driving circuit 10 further includes a diode D1 , wherein an anode of the diode D1 is electrically connected to the first voltage input node, and a cathode of the diode D1 is electrically connected to the first end of the first switch Q1 .

[0161] It should be understood that when the output terminal VOUT of the driving discrete circuit 10 is short-circuited to the power supply, the voltage of the power supply node of the load will suddenly change. In order to prevent damage to the components in the driving discrete circuit 10, the embodiment of the present application can be protected by a diode D1 set between the first voltage input node and the first end of the first switch Q1. When the anti-glare function is turned on (that is, the first switch is turned on), the external power supply is prevented from forming a reverse current to the external power supply VCC_1V2 of the first voltage input node, thereby effectively protecting the driving discrete circuit 10.

[0162] According to one embodiment of the present application, Figure 5As shown, the above-mentioned discrete driver circuit 10 further includes: a voltage detection output terminal TO_MCU_ADC and a filter circuit. The voltage detection output terminal TO_MCU_ADC is used to output the voltage of the power supply node of the load; one end of the filter circuit is electrically connected to the connection node between the first switch Q1 and the second switch Q2, and the other end of the filter circuit is electrically connected to the voltage detection output terminal TO_MCU_ADC.

[0163] According to one embodiment of the present application, the filtering circuit includes: a nineteenth resistor R19 and a first capacitor C1. One end of the nineteenth resistor R19 is electrically connected to the connection node between the first switch Q1 and the second switch Q2, and the other end of the nineteenth resistor R19 is electrically connected to the voltage detection output terminal TO_MCU_ADC; one end of the first capacitor C1 is electrically connected to the other end of the nineteenth resistor R19 and the voltage detection output terminal TO_MCU_ADC, respectively, and the other end of the first capacitor C1 is electrically connected to the ground node.

[0164] It should be understood that in order to promptly detect whether the output terminal VOUT of the driver discrete circuit 10 is short-circuited to the power supply or short-circuited to the ground, the embodiment of the present application can set a voltage detection output terminal TO_MCU_ADC. When it is detected that the voltage of the power supply node of the load is greater than the first preset voltage, it indicates that the output terminal VOUT of the driver discrete circuit 10 is short-circuited to the power supply, or when it is detected that the voltage of the power supply node of the load is less than the second preset voltage, it indicates that the output terminal VOUT of the driver discrete circuit 10 is short-circuited to the ground.

[0165] When the output terminal VOUT of the driving discrete circuit 10 is short-circuited to the power supply or short-circuited to the ground, the embodiment of the present application can feed back the short circuit to the power supply or short circuit to the ground to the external control module, so that the control module adjusts the first signal input to the first signal input terminal CONTROL_SIGNAL1 and the second signal input to the second signal input terminal CONTROL_SIGNAL2. For example, when the anti-glare function is turned on, the embodiment of the present application can, when the output terminal VOUT of the driving discrete circuit 10 is short-circuited to the power supply or short-circuited to the ground, the first signal input to the first signal input terminal CONTROL_SIGNAL1 is at the second level, and the second signal input to the second signal input terminal CONTROL_SIGNAL2 is also at the second level. At this time, the first switch Q1 and the second switch Q2 can be controlled to be closed, effectively protecting the driving discrete circuit 1. 0; For another example, when the anti-glare function is turned off, in the embodiment of the present application, when a short circuit to the power supply occurs at the output terminal VOUT of the driving discrete circuit 10, the first signal input to the first signal input terminal CONTROL_SIGNAL1 is at the second level, and the second signal input to the second signal input terminal CONTROL_SIGNAL2 is also at the second level. At this time, the first switch Q1 and the second switch Q2 can be controlled to be closed, effectively protecting the driving discrete circuit 10. Since the anti-glare function is turned off, even if a short circuit to the ground occurs, the driving discrete circuit 10 will not be damaged. Therefore, the first switch Q1 can be kept closed and the second switch Q2 can be opened. Alternatively, the first signal input to the first signal input terminal CONTROL_SIGNAL1 can be at the second level, and the second signal input to the second signal input terminal CONTROL_SIGNAL2 can also be at the second level.

[0166] According to one embodiment of the present application, the discrete driving circuit 10 further includes a second capacitor C2 , one end of which is electrically connected to the connection node between the first switch Q1 and the second switch Q2 , and the other end of which is electrically connected to the ground node.

[0167] It should be understood that the embodiment of the present application may further be provided with a second capacitor C2 to implement electrostatic protection to prevent damage to the driving discrete circuit 10 caused by static electricity.

[0168] Therefore, the driving discrete circuit 10 of the embodiment of the present application adds voltage detection to the output terminal VOUT of the driving discrete circuit 10, and is provided with a diode, which can prevent current backflow when the output terminal VOUT of the driving discrete circuit 10 is short-circuited to the power supply or short-circuited to the ground, thereby protecting the driving discrete circuit 10 and greatly improving the reliability of the driving discrete circuit 10.

[0169] In addition, if Figure 6 As shown, Figure 6This is a block diagram of an electronic anti-glare rearview mirror according to an embodiment of the present application. In other words, the driving discrete circuit 10 according to the embodiment of the present application can be applied to Figure 6 In the electronic anti-glare rearview mirror shown.

[0170] Specifically, if Figure 6 As shown, the electronic anti-glare rearview mirror 20 includes: a control module 21, a first drive circuit 100, a second drive circuit 200, a protection module 22, a power module 23 and a load 24. The load 24 can be a load, and the protection module 22 can include Figure 5 The embodiment shown includes a diode D1, a ninth switch Q9, a third drive circuit, a voltage detection output terminal, a filter circuit, and a second capacitor C2. The control module can output first and second signals to the first and second drive circuits 100 and 200, and receive a monitoring voltage at the output terminal VOUT of the discrete drive circuit 10 outputted from the voltage detection output terminal. It should be noted that the aforementioned explanation of the discrete drive circuit 10 embodiment also applies to the electronic anti-glare rearview mirror of this embodiment and, to avoid redundancy, is not further described here.

[0171] According to the discrete driver circuit proposed in an embodiment of the present application, when the rearview mirror anti-glare function is on, a high level is connected to the first signal input terminal and a low level is connected to the second signal input terminal. This allows the first driver circuit to control the first switch to open when the first signal is at the first level and the second signal is at the second level, thereby providing voltage to the load through a power supply connected to the first voltage input node corresponding to the first switch. When the rearview mirror anti-glare function is off, a low level is connected to the first signal input terminal and a high level is connected to the second signal input terminal. This allows the second driver circuit to control the second switch to open when the first signal is at the second level and the second signal is at the first level, thereby discharging power from the load through the ground node corresponding to the second switch. Thus, by inputting signals of opposite levels to control the opening and closing of the first and second switches, rapid charging and discharging of the load is achieved, thereby enabling rapid turning on and off of the rearview mirror anti-glare function. This solves the problem in related arts where, when the anti-glare function is off, the power on the lens can only be discharged through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves control reliability and enhances user experience.

[0172] Next, the anti-dizziness method of the anti-glare rearview mirror proposed in the embodiment of the present application is described with reference to the accompanying drawings.

[0173] In this embodiment, the anti-dizziness method of the anti-dazzling rearview mirror adopts the following method: Figure 1 The embodiment shown drives a discrete circuit.

[0174] like Figure 7As shown, the anti-dizziness method of the anti-dazzling rearview mirror includes the following steps:

[0175] In step S701, the current demand for the anti-glare rearview mirror is obtained;

[0176] It should be understood that the current demand may be a demand to turn on the anti-glare function or a demand to turn off the anti-glare function.

[0177] In step S702, if the current requirement is to turn on the anti-glare function, the first signal is configured to be the first level and the second signal is configured to be the second level; otherwise, the first signal is configured to be the second level and the second signal is configured to be the first level, wherein the first level and the second level are opposite.

[0178] It is understandable that, combined with Figure 5 As shown, if the current requirement is to enable the anti-glare function, it means that the voltage differential across the load needs to be changed. This embodiment of the present application can change the voltage differential of the load by adjusting the voltage supplied to the load. For example, this embodiment of the present application can connect a first voltage level to the first signal input terminal CONTROL_SIGNAL1 and a second voltage level to the second signal input terminal CONTROL_SIGNAL2. At this time, the first switch Q1 is turned on and the second switch Q2 is turned off. This embodiment of the present application can adjust the voltage supplied to the load via the power supply externally connected to the first voltage input node, thereby enabling the anti-glare function.

[0179] If the current requirement is to turn off the anti-glare function, it means that the power of the load needs to be discharged quickly. In this embodiment of the application, the first signal input terminal CONTROL_SIGNAL1 can be connected to the second level, and the second signal input terminal CONTROL_SIGNAL2 can be connected to the first level. At this time, the first switch Q1 is closed and the second switch Q2 is opened. In this embodiment of the application, the power of the load can be discharged through the ground node.

[0180] In step S703 , a first signal is sent to the first driving circuit, and a second signal is sent to the second driving circuit at the same time.

[0181] After configuring the first and second signals based on current requirements, the embodiment of the present application can directly send the first signal to the first drive circuit and simultaneously send the second signal to the second drive circuit. Thus, when the current requirement is to enable the anti-glare function, the power supply connected to the first voltage input node provides voltage to the load; when the current requirement is to disable the anti-glare function, the load's power is discharged through the ground node. Thus, by inputting signals of opposite voltage levels to control the opening and closing of the first and second switches, rapid charging and discharging of the load is achieved, thereby enabling rapid activation and deactivation of the rearview mirror's anti-glare function. This solves the problem in related arts where, when the anti-glare function is disabled, the power on the lens can only be discharged through the lens's own parasitic resistance, resulting in the anti-glare function being unable to be disabled for a long time. This improves control reliability while enhancing the user experience.

[0182] According to one embodiment of the present application, the anti-dizziness method of the above-mentioned anti-glare rearview mirror also includes: obtaining a first detection voltage at the voltage detection output end; if the first detection voltage is greater than a first preset voltage, or the first detection voltage is less than the first preset voltage, then configuring the first signal to be a second level and the second signal to be a second level; sending the first signal to the first drive circuit, and sending the second signal to the second drive circuit at the same time; wherein the first preset voltage is greater than the second preset voltage.

[0183] It can be understood that in order to promptly detect whether the output end of the driving discrete circuit is short-circuited to the power supply or short-circuited to the ground, the embodiment of the present application can set a voltage detection output end. When it is detected that the voltage of the power supply node of the load is greater than the first preset voltage, it indicates that the output end of the driving discrete circuit is short-circuited to the power supply, or when it is detected that the voltage of the power supply node of the load is less than the second preset voltage, it indicates that the output end of the driving discrete circuit is short-circuited to the ground.

[0184] When a short circuit to the power supply or a short circuit to the ground occurs at the output end of the driving discrete circuit, the embodiment of the present application can feed back the short circuit to the power supply or the short circuit to the ground to an external control module, so that the first signal input to the first signal input end and the second signal input to the second signal input end are adjusted by the control module. For example, when the anti-glare function is turned on, the embodiment of the present application can, when a short circuit to the power supply or a short circuit to the ground occurs at the output end of the driving discrete circuit, the first signal input to the first signal input end is at the second level, and the second signal input to the second signal input end is also at the second level. At this time, the first switch and the second switch can be controlled to be closed, thereby effectively protecting the driving discrete circuit. For example, when the anti-glare function is turned off, in the embodiment of the present application, when a short circuit to the power supply occurs at the output end of the driving discrete circuit, the first signal input to the first signal input end is at the second level, and the second signal input to the second signal input end is also at the second level. At this time, the first switch and the second switch can be controlled to be closed, thereby effectively protecting the driving discrete circuit. Since the anti-glare function is turned off, even if a short circuit to the ground occurs, the driving discrete circuit will not be damaged. Therefore, the first switch can be kept closed and the second switch can be opened. Alternatively, the first signal input to the first signal input end can be at the second level, and the second signal input to the second signal input end can also be at the second level.

[0185] In order to facilitate those skilled in the art to understand in detail the anti-dizziness method of the anti-dazzling rearview mirror of the embodiment of the present application, the following is combined with Figure 5 The driving discrete circuit shown in the figure describes in detail the control logic when the electronic anti-glare rearview mirror turns on the anti-glare function, turns off the anti-glare function, and inputs the same level at the first signal input terminal and the second signal input terminal.

[0186] (1) When the electronic anti-glare rearview mirror turns on the anti-glare function, the embodiment of the present application can connect the first signal input terminal CONTROL_SIGNAL1 to the first level. Since the first level is a high level, current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned on. Since the third switch Q3 is turned on, the external power supply VCC_5V of the second voltage input node forms a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2 and the third switch Q3, and the fourth switch Q4 is turned on. Since the embodiment of the present application simultaneously connects the second signal input terminal CONTROL_SIGNAL2 to the second level, no current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is turned off.

[0187] In the embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is simultaneously connected to the second voltage level, no current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is closed. Because the sixth switch Q6 is closed, the external power supply VCC_5V at the second voltage input node cannot form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is closed. Since the first signal input terminal CONTROL_SIGNAL1 is connected to the first voltage level in the embodiment of the present application, current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is opened.

[0188] As a result, the external power supply VCC_5V at the second voltage input node can form a loop through the fifth resistor R5 and the sixth resistor R6. Current flows through the sixth resistor R6, creating a voltage difference between the gate and source of the first switch Q1, turning on the first switch Q1. The external power supply VCC_5V at the second voltage input node cannot form a loop through the thirteenth resistor R13 and the fourteenth resistor R14. Current cannot flow through the fourteenth resistor R14, resulting in no voltage difference between the gate and source of the second switch Q2. The gate of the second switch Q2 is grounded, turning off the second switch Q2. Therefore, the first switch Q1 is turned on, the second switch Q2 is turned off, and the external power supply VCC_1V2 at the first voltage input node can provide voltage to the load through the second switch Q2.

[0189] (2) When the electronic anti-glare rearview mirror turns off the anti-glare function, the embodiment of the present application can connect the second level to the first signal input terminal CONTROL_SIGNAL1. Since the second level is a low level, no current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned off. Since the third switch Q3 is turned off, the external power supply VCC_5V of the second voltage input node cannot form a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2 and the third switch Q3, and the fourth switch Q4 is turned off; since the embodiment of the present application simultaneously connects the first level to the second signal input terminal CONTROL_SIGNAL2, current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is turned on;

[0190] In the embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is simultaneously connected to the first level, current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is turned on. Because the sixth switch Q6 is turned on, the external power supply VCC_5V at the second voltage input node can form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is turned on. Because the first signal input terminal CONTROL_SIGNAL1 is connected to the second level in the embodiment of the present application, no current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is turned off.

[0191] Therefore, the external power supply VCC_5V at the second voltage input node can form a loop through the thirteenth resistor R13 and the fourteenth resistor R14. Current flows through the fourteenth resistor R14, generating a voltage difference between the gate and source of the second switch Q2, turning on the second switch Q2. The external power supply VCC_5V at the second voltage input node cannot form a loop through the fifth resistor R5 and the sixth resistor R6. Current cannot flow through the sixth resistor R6, resulting in no voltage difference between the gate and source of the first switch Q1. The gate of the first switch Q1 is grounded, and the first switch Q1 is turned off. As a result, the first switch Q1 is turned off and the second switch Q2 is turned on. In this embodiment of the present application, the load power can be discharged through the ground node.

[0192] (3) When the first signal input terminal and the second signal input terminal input the same level, there are two cases.

[0193] As a possible implementation method, if the first signal input terminal CONTROL_SIGNAL1 is connected to the first level, the second signal input terminal CONTROL_SIGNAL2 is also connected to the first level;

[0194] Because the first signal input terminal CONTROL_SIGNAL1 is connected to the first voltage level in the embodiment of the present application, current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned on. Because the third switch Q3 is turned on, the external power supply VCC_5V at the second voltage input node forms a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3, and the fourth switch Q4 is turned on. Because the second signal input terminal CONTROL_SIGNAL2 is also connected to the first voltage level in the embodiment of the present application, current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5, and the fifth switch Q5 is turned on.

[0195] Since the second signal input terminal CONTROL_SIGNAL2 is connected to the first level in the embodiment of the present application, current flows through the eleventh resistor R11 and the base and emitter of the sixth switch Q6, and the sixth switch Q6 is turned on; since the sixth switch Q6 is turned on, the external power supply VCC_5V of the second voltage input node can form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10 and the sixth switch Q6, and the seventh switch Q7 is turned on; since the first signal input terminal CONTROL_SIGNAL1 is connected to the first level in the embodiment of the present application, current flows through the fifteenth resistor R15 and the base and emitter of the eighth switch Q8, and the eighth switch Q8 is turned on.

[0196] Therefore, the opening of the fifth switch Q5 causes the gate of the first switch Q1 to be grounded, turning the first switch Q1 off. Simultaneously, the opening of the eighth switch Q8 causes the gate of the second switch Q2 to be grounded, turning the second switch Q2 off. Therefore, although the external power supply VCC_5V at the second voltage input node forms a current path, the gates of the first and second switches Q1, Q2, and Q2 are both off because there is no voltage difference between their sources.

[0197] As a possible implementation, if the first signal input terminal CONTROL_SIGNAL1 is connected to the second voltage level, the second signal input terminal CONTROL_SIGNAL2 is also connected to the second voltage level. Since the embodiment of the present application connects the second voltage level to the first signal input terminal CONTROL_SIGNAL1, and since the second voltage level is low, no current flows through the third resistor R3 and the base and emitter of the third switch Q3. At this time, the third switch Q3 is turned off. Since the third switch Q3 is turned off, the external power supply VCC_5V at the second voltage input node cannot form a path through the first resistor R1, the base and emitter of the fourth switch Q4, the second resistor R2, and the third switch Q3. Therefore, the fourth switch Q4 is turned off. Since the embodiment of the present application connects the second voltage level to the second signal input terminal CONTROL_SIGNAL2 at the same time, no current flows through the seventh resistor R7 and the base and emitter of the fifth switch Q5. Therefore, the fifth switch Q5 is turned off.

[0198] Because in this embodiment of the present application, when the second signal input terminal CONTROL_SIGNAL2 is connected to the second voltage level, no current flows through the eleventh resistor R11 or the base and emitter of the sixth switch Q6, and the sixth switch Q6 is closed. Because the sixth switch Q6 is closed, the external power supply VCC_5V connected to the second voltage input node cannot form a path through the ninth resistor R9, the base and emitter of the seventh switch Q7, the tenth resistor R10, and the sixth switch Q6, and the seventh switch Q7 is closed. Because in this embodiment of the present application, the first signal input terminal CONTROL_SIGNAL1 is connected to the second voltage level, no current flows through the fifteenth resistor R15 or the base and emitter of the eighth switch Q8, and the eighth switch Q8 is closed.

[0199] Therefore, the external power supply VCC_5V of the second voltage input node does not form a current path, and there is no voltage difference between the gate and source of the first switch Q1 and the second switch Q2. The first switch Q1 and the second switch Q2 are both turned off.

[0200] It should be noted that the above explanation of the embodiment of the driving discrete circuit is also applicable to the anti-dizziness method of the anti-glare rearview mirror of this embodiment, and will not be repeated here.

[0201] According to the anti-dizziness method for an anti-glare rearview mirror proposed in an embodiment of the present application, the current demand of the anti-glare rearview mirror is obtained. When the current demand is to turn on the anti-glare function, the first signal is configured to be the first level and the second signal is the second level. When the current demand is to turn off the anti-glare function, the first signal is configured to be the second level and the second signal is configured to be the first level. The first signal is sent to the first drive circuit, and the second signal is sent to the second drive circuit at the same time. Thus, by inputting signals of opposite levels to control the opening and closing of the first switch and the second switch, rapid charging and rapid discharging of the load are achieved, thereby achieving rapid turning on and off of the anti-glare function of the rearview mirror. This solves the problem in the related art that when the anti-glare function is turned off, the power on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves control reliability while enhancing the user experience.

[0202] In addition, the embodiment of the present application further provides an anti-glare rearview mirror, which includes: Figure 1 In the embodiment shown in the driving discrete circuit and the load (such as the electrochromic device), the output end of the driving discrete circuit is electrically connected to the power supply end of the load.

[0203] According to the anti-glare rearview mirror proposed in the embodiment of the present application, the above-mentioned discrete driving circuit is used to solve the problem in the related art that when the anti-glare function is turned off, the electricity on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves the control reliability while enhancing the user experience.

[0204] In addition, an embodiment of the present application also provides a vehicle, which includes the above-mentioned anti-glare rearview mirror.

[0205] The vehicle proposed in the embodiment of the present application uses the above-mentioned anti-glare rearview mirror to solve the problem in the related art that when the anti-glare function is turned off, the power on the lens can only be released through the parasitic resistance of the lens itself, resulting in the anti-glare function being unable to be turned off for a long time. This improves control reliability while enhancing the user experience.

[0206] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0207] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0208] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A discrete driving circuit, characterized in that: include: A first signal input terminal, used for receiving a first signal; a second signal input terminal, for receiving a second signal, wherein the first signal and the second signal have opposite levels; a first switch and a second switch connected in series, wherein a first end of the first switch is electrically connected to a first voltage input node, a first end of the second switch is electrically connected to a ground node, and a connection node between the first switch and the second switch is electrically connected to a power supply node of a load; a first drive circuit, electrically connected to the first signal input terminal, the second signal input terminal, and the control terminal of the first switch, respectively, and configured to control the first switch to be turned on when the first signal is at a first level and the second signal is at a second level, the first level and the second level being opposite; The second driving circuit is electrically connected to the first signal input terminal, the second signal input terminal, and the control terminal of the second switch, respectively, and is configured to control the second switch to open when the first signal is at the second level and the second signal is at the first level.

2. The discrete driving circuit according to claim 1, wherein: The first driving circuit includes: a first enabling circuit electrically connected to the first signal input terminal, the second voltage input node, and the control terminal of the first switch, respectively, and configured to output a first enabling signal for controlling the first switch to be turned on when the first signal is at the first level; a first locking circuit, electrically connected to the first enabling circuit, the second signal input terminal, and the control terminal of the first switch, respectively, and configured to maintain the level state of the first enabling signal when the second signal is at the second level, and to invalidate the first enabling signal when the second signal is at the first level; The second driving circuit includes: a second enabling circuit electrically connected to the second signal input terminal, the second voltage input node, and the control terminal of the second switch, respectively, and configured to output a second enabling signal for controlling the second switch to be turned on when the second signal is at the first level; The second locking circuit is electrically connected to the second enabling circuit, the first signal input terminal, and the control terminal of the second switch, respectively, and is configured to maintain the level state of the second enabling signal when the first signal is at the second level, and to invalidate the second enabling signal when the second signal is at the first level.

3. The driving discrete circuit according to claim 2, characterized in that: The first enabling circuit includes: a third switch, wherein a control terminal of the third switch is electrically connected to the first signal input terminal, and a first terminal of the third switch is electrically connected to the ground node; a fourth switch, wherein a control end of the fourth switch is electrically connected to the second end of the third switch, a first end of the fourth switch is electrically connected to the second voltage input node, and a second end of the fourth switch is electrically connected to the control end of the first switch; The first locking circuit includes: a fifth switch, wherein a control end of the fifth switch is electrically connected to the second signal input end, a first end of the fifth switch is electrically connected to the ground node, and a second end of the fifth switch is electrically connected to the second end of the fourth switch and the control end of the first switch, respectively; The third switch is a first NPN transistor, the control end of the third switch is the base of the first NPN transistor, the first end of the third switch is the emitter of the first NPN transistor, and the second end of the third switch is the collector of the first NPN transistor; The fourth switch is a first PNP transistor, the control end of the third switch is the base of the first PNP transistor, the first end of the third switch is the emitter of the first PNP transistor, and the second end of the third switch is the collector of the first PNP transistor; The fifth switch is a second NPN transistor, the control end of the fifth switch is the base of the second NPN transistor, the first end of the fifth switch is the emitter of the second NPN transistor, and the second end of the fifth switch is the collector of the second NPN transistor.

4. The discrete driving circuit according to claim 3, wherein: The second enabling circuit includes: a sixth switch, wherein a control end of the sixth switch is electrically connected to the second signal input end, and a first end of the sixth switch is electrically connected to the ground node; a seventh switch, wherein a control end of the seventh switch is electrically connected to the second end of the sixth switch, a first end of the seventh switch is electrically connected to the second voltage input node, and a second end of the seventh switch is electrically connected to the control end of the second switch; The second locking circuit includes: an eighth switch, wherein a control end of the eighth switch is electrically connected to the first signal input end, a first end of the eighth switch is electrically connected to the ground node, and a second end of the eighth switch is electrically connected to the second end of the seventh switch and the control end of the second switch element, respectively; The sixth switch is a third NPN transistor, the control end of the sixth switch is the base of the third NPN transistor, the first end of the sixth switch is the emitter of the third NPN transistor, and the second end of the sixth switch is the collector of the third NPN transistor; The seventh switch is a second PNP transistor, the control end of the seventh switch is the base of the second PNP transistor, the first end of the seventh switch is the emitter of the second PNP transistor, and the second end of the seventh switch is the collector of the second PNP transistor; an eighth switch, wherein a control end of the eighth switch is electrically connected to the first signal input end, a first end of the eighth switch is electrically connected to the ground node, and a second end of the eighth switch is electrically connected to the second end of the seventh switch and the control end of the second switch element, respectively.

5. The discrete driving circuit according to claim 4, characterized in that: The first driving circuit further includes: a first resistor, one end of the first resistor being electrically connected to the second voltage input node and the first end of the fourth switch, respectively, and the other end of the first resistor being electrically connected to the control end of the fourth switch; a second resistor, one end of the second resistor being electrically connected to the control end of the fourth switch, and the other end of the second resistor being electrically connected to the second end of the third switch; a third resistor, one end of the third resistor being electrically connected to the first signal input end, and the other end of the third resistor being electrically connected to the control end of the third switch; a fourth resistor, one end of the fourth resistor being electrically connected to the other end of the third resistor and the control end of the third switch, respectively, and the other end of the fourth resistor being electrically connected to the ground node; a fifth resistor, one end of the fifth resistor being electrically connected to the second end of the fourth switch, and the other end of the fifth resistor being electrically connected to the second end of the fourth switch and the control end of the first switch, respectively; a sixth resistor, one end of the sixth resistor being electrically connected to the other end of the fifth resistor, the second end of the fifth switch, and the control end of the first switch respectively; a seventh resistor, one end of the seventh resistor being electrically connected to the second signal input end, and the other end of the seventh resistor being electrically connected to the control end of the fifth switch; an eighth resistor, one end of the eighth resistor being electrically connected to the control end of the fifth switch and the other end of the seventh resistor, respectively, and the other end of the seventh resistor being electrically connected to the ground node.

6. The discrete driving circuit according to claim 5, characterized in that: The second driving circuit further includes: a ninth resistor, one end of the ninth resistor being electrically connected to the second voltage input node and the first end of the seventh switch, respectively, and the other end of the ninth resistor being electrically connected to the control end of the seventh switch; a tenth resistor, one end of the tenth resistor being electrically connected to the control end of the seventh switch, and the other end of the tenth resistor being electrically connected to the second end of the sixth switch; an eleventh resistor, one end of the eleventh resistor being electrically connected to the second signal input end, and the other end of the eleventh resistor being electrically connected to the control end of the sixth switch; a twelfth resistor, one end of the twelfth resistor being electrically connected to the other end of the eleventh resistor and the control end of the sixth switch, respectively, and the other end of the twelfth resistor being electrically connected to the ground node; a thirteenth resistor, one end of the thirteenth resistor being electrically connected to the second end of the seventh switch, and the other end of the thirteenth resistor being electrically connected to the second end of the eighth switch and the control end of the second switch respectively; a fourteenth resistor, one end of the fourteenth resistor being electrically connected to the other end of the thirteenth resistor, the second end of the eighth switch, and the control end of the second switch; a fifteenth resistor, one end of the fifteenth resistor being electrically connected to the first signal input end, and the other end of the fifteenth resistor being electrically connected to the control end of the eighth switch; a sixteenth resistor, one end of the sixteenth resistor being electrically connected to the control end of the eighth switch and the other end of the fifteenth resistor, respectively, and the other end of the sixteenth resistor being electrically connected to the ground node.

7. The discrete driving circuit according to claim 1, wherein: The first level is a high level, and the second level is a low level.

8. The discrete driving circuit according to any one of claims 1 to 7, characterized in that: Also includes: a ninth switch, wherein a first end of the ninth switch is electrically connected to the control end of the second switch, and a second end of the ninth switch is electrically connected to the ground node; a third driving circuit, electrically connected to the power supply node of the load, the control terminal of the ninth switch, and the ground node, respectively, and configured to control the ninth switch to be turned on when the voltage of the power supply node of the load is greater than a preset voltage; a diode, an anode of the diode being electrically connected to the first voltage input node, and a cathode of the diode being electrically connected to the first end of the first switch; A voltage detection output terminal, used for outputting the voltage of the power supply node of the load; A filter circuit, one end of the filter circuit is electrically connected to a connection node between the first switch and the second switch, and the other end of the filter circuit is electrically connected to the voltage detection output end.

9. The discrete driving circuit according to claim 8, characterized in that: The third driving circuit includes: a seventeenth resistor, one end of the seventeenth resistor being electrically connected to a connection node between the first switch and the second switch; an eighteenth resistor, one end of the eighteenth resistor being electrically connected to the other end of the seventeenth resistor, and the other end of the eighteenth resistor being electrically connected to the ground node.

10. The discrete driving circuit according to claim 8, wherein: The filtering circuit comprises: a nineteenth resistor, one end of the nineteenth resistor being electrically connected to a connection node between the first switch and the second switch, and the other end of the nineteenth resistor being electrically connected to the voltage detection output terminal; A first capacitor, one end of the first capacitor is electrically connected to the other end of the nineteenth resistor and the voltage detection output end respectively, and the other end of the first capacitor is electrically connected to the ground node.

11. The discrete driving circuit according to claim 10, wherein: Also includes: A second capacitor, one end of the second capacitor is electrically connected to a connection node between the first switch and the second switch, and the other end of the second capacitor is electrically connected to the ground node.

12. The discrete driving circuit according to claim 11, wherein: The first switch is a first NMOS transistor, the second switch is a second NMOS transistor, and the ninth switch is a third NMOS transistor, wherein: The control end of the first switch is the gate of the first NMOS transistor, the first end of the first switch is the drain of the first NMOS transistor, and the second end of the first switch is the source of the first NMOS transistor; The control end of the second switch is the gate of the second NMOS transistor, the first end of the second switch is the source of the second NMOS transistor, and the second end of the second switch is the drain of the second NMOS transistor; The control end of the ninth switch is the gate of the third NMOS transistor, the first end of the ninth switch is the drain of the third NMOS transistor, and the second end of the ninth switch is the source of the third NMOS transistor. 13.An anti-glare rearview mirror, characterized in that: include: The discrete driving circuit and load according to any one of claims 1 to 12, wherein the output end of the discrete driving circuit is electrically connected to the power supply end of the load.

14. A vehicle, characterized in that: include: The anti-glare rearview mirror according to claim 13.

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