Three-dimensional chip structure integrated with TSV (Through Silicon Via) and phase inverter, layout method and chip

Abstract

The invention provides a three-dimensional chip structure integrated with a TSV (Through Silicon Via) and an inverter, a layout method and a chip, and the layout method comprises the steps: providing a silicon substrate with the TSV, and obtaining the stress distribution of the silicon substrate under a thermal load parameter; establishing a nanoring gate-all-around transistor model, sequentially arranging a plurality of N-type and P-type nanoring gate-all-around transistors on the silicon substrate around the silicon through hole, and respectively obtaining each electrical characteristic; according to a preset electrical characteristic range and electrical characteristics, obtaining a first region conforming to the N-type nanoring ring gate transistor and a second region conforming to the P-type nanoring ring gate transistor; establishing an inverter model, arranging a plurality of inverters on the silicon substrate around the silicon through hole, and obtaining direct current characteristics of the inverters; obtaining a third area according to a preset DC characteristic range and DC characteristics; and obtaining an intersection of the first region, the second region and the third region as a region in which an inverter is arranged on the silicon substrate. The performance of the three-dimensional integrated circuit can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional chip structure and layout method integrating TSV and inverter, and a chip. Background Art

[0002] 3D-IC (three-dimensional integrated circuit) technology is a semiconductor manufacturing technique that vertically stacks multiple chips or wafer layers using TSVs (through-silicon vias), microbumps, and hybrid bonding to achieve higher functional density, lower power consumption, and faster data transmission speeds. In 3D-IC technology, TSVs play a crucial role in connecting different chip layers. However, the thermal stress generated by the difference in thermal expansion coefficient (CTE) between the metal material filling the TSVs and the silicon can affect the electrical properties of adjacent devices.

[0003] Inverters, as the most fundamental functional unit of digital integrated circuits and the most typical device in digital electronic systems, play a crucial role. The key is how to rationally layout inverters composed of N-type and P-type nanosheet gate-all-around field-effect transistors (NSFETs) within three-dimensional integrated circuits (including within TSV substrates) while ensuring integration density and inverter performance. Summary of the Invention

[0004] The object of the present invention is to provide a three-dimensional chip structure and layout method and chip integrating TSV and inverter, so as to improve the performance of three-dimensional integrated circuits.

[0005] To solve the above technical problems, the present invention provides a layout method for a three-dimensional chip structure integrating TSVs and inverters, comprising:

[0006] Providing a silicon substrate having a through-silicon via and thermal load parameters, and obtaining a stress distribution of the silicon substrate around the through-silicon via under the thermal load parameters;

[0007] Establishing an N-type nano-ring-gate transistor model and a P-type nano-ring-gate transistor model, sequentially disposing a plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors on the silicon substrate around the through-silicon via, and obtaining electrical characteristics of each of the N-type nano-ring-gate transistors and the P-type nano-ring-gate transistors based on the stress distribution, the N-type nano-ring-gate transistor model, and the P-type nano-ring-gate transistor model;

[0008] According to the preset electrical characteristic range and the electrical characteristic, a first region and a second region are obtained, wherein the electrical characteristic of the N-type nano-ring gate transistor in the first region meets the preset electrical characteristic range, and the electrical characteristic of the P-type nano-ring gate transistor in the second region meets the preset electrical characteristic range;

[0009] Establishing an inverter model constructed by the N-type nano-ring gate transistor model and the P-type nano-ring gate transistor model, disposing a plurality of inverters on the silicon substrate around the through silicon via, and obtaining a DC characteristic of each inverter based on the stress distribution and the inverter model;

[0010] Obtaining a third region according to a preset DC characteristic range and the DC characteristic, wherein the DC characteristic of the inverter in the third region meets the preset DC characteristic range;

[0011] An intersection of the first region, the second region, and the third region is obtained as a region on the silicon substrate around the through silicon via for arranging an inverter.

[0012] Optionally, after obtaining the stress distribution of the silicon substrate around the silicon via under the thermal load parameters, the mobility distribution of N-type carriers and P-type carriers of the silicon substrate is also obtained based on the stress distribution, and the N-type nano-ring gate transistor, the P-type nano-ring gate transistor and the inverter are set in the area around the silicon via based on the mobility distribution.

[0013] Optionally, the electrical characteristic includes leakage current, and the first region and the second region are set according to the leakage current of the N-type nano-ring gate transistor and the P-type nano-ring gate transistor, respectively.

[0014] Optionally, the stress distribution of the silicon substrate around the silicon via under the thermal load parameters is in the shape of a cross petal, and the stress distribution includes stress components along a first direction and a second direction, the first direction and the second direction are orthogonal, and the positive and negative signs of the two stress components are opposite.

[0015] Optional,

[0016] The N-type nano-ring-gate transistor includes a first N-type nano-ring-gate transistor, wherein the first N-type nano-ring-gate transistor is composed of the N-type nano-ring-gate transistors arranged along the first direction, and the electrical characteristics of each of the first N-type nano-ring-gate transistors and the corresponding first region are obtained;

[0017] The N-type nano-ring-gate transistor includes a second N-type nano-ring-gate transistor, wherein the second N-type nano-ring-gate transistor is composed of the N-type nano-ring-gate transistors arranged along the second direction, and the electrical characteristics of each second N-type nano-ring-gate transistor and the corresponding first region are obtained;

[0018] An intersection of the first region of the first N-type nano-ring gate transistor and the first region of the second N-type nano-ring gate transistor is obtained as the first region of the N-type nano-ring gate transistor.

[0019] Optional,

[0020] The P-type nano-ring-gate transistor includes a first P-type nano-ring-gate transistor, wherein the first P-type nano-ring-gate transistor is composed of the P-type nano-ring-gate transistors arranged along the first direction, and the electrical characteristics of each of the first P-type nano-ring-gate transistors and the corresponding second region are obtained;

[0021] The P-type nano-ring-gate transistor includes a second P-type nano-ring-gate transistor, wherein the second P-type nano-ring-gate transistor is composed of the P-type nano-ring-gate transistors arranged along the second direction, and the electrical characteristics of each second P-type nano-ring-gate transistor and the corresponding second region are obtained;

[0022] An intersection of the second region of the first P-type nano-ring gate transistor and the second region of the second P-type nano-ring gate transistor is obtained as the second region of the P-type nano-ring gate transistor.

[0023] Optional,

[0024] The inverter includes a first inverter, wherein the first inverter is composed of the P-type nano-ring gate transistor and the N-type nano-ring gate transistor arranged along the first direction, and a DC characteristic of each first inverter and a corresponding third region are obtained;

[0025] The inverter includes a second inverter, wherein the second inverter is composed of the P-type nano-ring gate transistor and the N-type nano-ring gate transistor arranged along the second direction, and a DC characteristic of each second inverter and a corresponding third region are obtained;

[0026] The third region of the first inverter and the third region of the second inverter are intersected to form the third region of the inverter.

[0027] Optionally, the DC characteristics of the inverter include a voltage transition point, a high-level noise margin, and a low-level noise margin.

[0028] Based on another aspect of the present invention, a three-dimensional chip structure integrating TSV and inverter is also provided, including a silicon substrate, a through-silicon via and an inverter, wherein the inverter is composed of an N-type nano-ring gate transistor and a P-type nano-ring gate transistor, and the through-silicon via and the inverter are arranged on the silicon substrate using the layout method as described above.

[0029] According to another aspect of the present invention, a chip is provided, comprising the three-dimensional integrated chip structure as described above.

[0030] In summary, the present invention provides a three-dimensional chip structure and layout method for integrating TSVs and inverters, and a chip. The layout method includes providing a silicon substrate with through-silicon vias and thermal load parameters, obtaining a stress distribution of the silicon substrate around the through-silicon via under the thermal load parameters; sequentially arranging a plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors on the silicon substrate around the through-silicon vias, and obtaining electrical characteristics of each N-type nano-ring-gate transistor and each P-type nano-ring-gate transistor based on the stress distribution; obtaining a first region conforming to the N-type nano-ring-gate transistor and a second region conforming to the P-type nano-ring-gate transistor on the silicon substrate based on a preset electrical characteristic range and electrical characteristics; arranging a plurality of inverters composed of P-type nano-ring-gate transistors and N-type nano-ring-gate transistors on the silicon substrate around the through-silicon vias, and obtaining DC characteristics of each inverter based on the stress distribution; obtaining a third region conforming to the layout requirements of the inverter on the silicon substrate based on the preset DC characteristic range and DC characteristics; and obtaining the intersection of the first region, the second region, and the third region as the region for arranging the inverter on the silicon substrate around the through-silicon vias. In the present invention, a stress distribution of a silicon substrate around a through-silicon via (TSV) is obtained from TSV and thermal load parameters. The stress distribution is then used in combination with an N-type nano-gate-all-around transistor model, a P-type nano-gate-all-around transistor model, and an inverter model to obtain characteristic parameters of devices around the TSV. The intersection of the first, second, and third regions corresponding to respective preset ranges is then used as the region for arranging an inverter. This not only considers the effect of thermal stress on the performance of the inverter, but also the effect of thermal stress on the performance of each transistor in the inverter. This reduces the probability of erroneous logic outputs in the entire circuit, thereby improving the performance and reliability of a three-dimensional integrated circuit composed of inverters around the TSV, thereby enabling the three-dimensional integrated circuit to operate more stably and efficiently in various application scenarios (such as high-performance computing, communications, and other fields). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0032] Figure 1 is a flow chart of a layout method for a three-dimensional chip structure integrating TSVs and inverters provided in an embodiment of the present application;

[0033] Figure 2a is a schematic diagram of stress distribution provided in an embodiment of the present application;

[0034] Figure 2b Schematic diagram of arranging N-type nano-ring gate transistors around through-silicon vias according to an embodiment of the present application;

[0035] Figure 2c Schematic diagram of the boundaries of the first region and the second region around the through silicon via provided in an embodiment of the present application.

[0036] In the attached figure:

[0037] 10 - silicon substrate; 11 - through silicon via; 12 - N-type nano-ring gate transistor; 21 - first boundary; 22 - second boundary; Z - first direction; Y - second direction. DETAILED DESCRIPTION

[0038] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0039] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0040] An embodiment of the present application provides a layout method for a three-dimensional chip structure integrating TSVs and inverters.

[0041] Figure 1 This is a flow chart of a layout method for a three-dimensional chip structure integrating TSVs and inverters provided in an embodiment of the present application.

[0042] like Figure 1 As shown, the layout method of the three-dimensional chip structure integrating TSV and inverter provided in this embodiment includes:

[0043] S01: providing a silicon substrate having a through silicon via and thermal load parameters, and obtaining a stress distribution of the silicon substrate around the through silicon via under the thermal load parameters;

[0044] S02: establishing an N-type nano-ring-gate transistor model and a P-type nano-ring-gate transistor model, sequentially placing a plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors on the silicon substrate around the through-silicon via, and obtaining electrical characteristics of each of the N-type nano-ring-gate transistors and the P-type nano-ring-gate transistors according to the stress distribution, the N-type nano-ring-gate transistor model, and the P-type nano-ring-gate transistor model;

[0045] S03: obtaining a first region and a second region according to a preset electrical characteristic range and the electrical characteristic, wherein the electrical characteristic of the N-type nano-ring gate transistor in the first region meets the preset electrical characteristic range, and the electrical characteristic of the P-type nano-ring gate transistor in the second region meets the preset electrical characteristic range;

[0046] S04: establishing an inverter model constructed by the N-type nano-gate-all-around transistor model and the P-type nano-gate-all-around transistor model, disposing a plurality of inverters on the silicon substrate around the through-silicon via, and obtaining a DC characteristic of each inverter according to the stress distribution and the inverter model;

[0047] S05: obtaining a third region according to a preset DC characteristic range and the DC characteristic, wherein the DC characteristic of the inverter in the third region meets the preset DC characteristic range;

[0048] S06: obtaining an intersection of the first region, the second region, and the third region as a region for arranging an inverter on the silicon substrate around the through silicon via.

[0049] Figure 2a to Figure 2c The schematic diagram corresponding to the corresponding steps of the layout method of the three-dimensional chip structure integrating TSV and inverter provided in this embodiment is shown in FIG. Figure 2a to Figure 2c A layout method for a three-dimensional chip structure integrating TSVs and inverters is described in detail.

[0050] First, please refer to Figure 2a , executing step S01, providing a silicon substrate having a through silicon via and a thermal load parameter, and obtaining a stress distribution of the silicon substrate around the through silicon via under the thermal load parameter.

[0051] The silicon substrate can be made of any suitable single-crystal silicon. The structure of the through-silicon via (TSV) in the silicon substrate can include a silicon oxide layer, a metal barrier layer, and a metal fill layer disposed in sequence. In this embodiment, the conductive material of the TSV is copper, meaning the metal fill layer is made of copper, and the metal barrier layer can be made of tantalum nitride. In other examples, the conductive material of the TSV can also be tungsten, and the metal barrier layer can be made of titanium nitride. Of course, the silicon substrate can also be provided with multiple TSVs, arranged in an array, with devices on the silicon substrate disposed between the TSVs. In this embodiment, after obtaining the device layout on the silicon substrate surrounding a single TSV, the device layout on the entire silicon substrate can be obtained using this device layout.

[0052] During specific execution, simulation software (simulation software) can be used to model and simulate the layout method in this embodiment to obtain the corresponding layout area, and then verify the above layout area in the actual silicon substrate. Among them, the relevant parameters of the silicon substrate and array unit in the software can be referred to the actual needs. In this embodiment, the thickness of the silicon substrate (the height of the silicon via) can be 30 microns, the radius of the silicon via is 2.5 microns, the thickness of the silicon oxide layer in the silicon via is 125 nanometers, and the thickness of the tantalum nitride layer is 50 nanometers. The thermal load parameters (for example, 250°C) can be set according to actual needs, and the thermal load parameters, various parameters of the silicon substrate and the silicon via are input into the simulation software for simulation, so as to obtain the stress distribution of the areas around each silicon via on the silicon substrate under the thermal load parameters. Since the silicon substrate is a single crystal structure (cubic structure), the silicon substrate area around the silicon via has different stress performance in two orthogonal directions. For details, please continue to refer to Figure 2a The stress distribution may be in the shape of a cross petal, and the stress distribution includes stress components along the first direction Z and the second direction Y. The first direction Z and the second direction Y are orthogonal, and the positive and negative signs of the two stress components are opposite. The dotted box around the through silicon via 11 is a region with relatively large stress (stress concentration area). The stress along the first direction Z is greater than 0, and the stress along the second direction Y is less than 0. In terms of the distance relative to the center of the through silicon via 11, the closer the silicon substrate 10 region is to the through silicon via 11, the greater the absolute value of the stress. Therefore, in terms of the circumference of the through silicon via 11, the closer the silicon substrate 10 region is to the first direction Z or the second direction Y (the smaller the angle with the first direction Z or the second direction Y), the greater the absolute value of the stress.

[0053] Next, step S02 is executed to establish an N-type nano-ring-gate transistor model and a P-type nano-ring-gate transistor model. A plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors are sequentially arranged on the silicon substrate around the through-silicon via. The electrical characteristics of each N-type nano-ring-gate transistor and P-type nano-ring-gate transistor are respectively obtained based on the stress distribution, the N-type nano-ring-gate transistor model and the P-type nano-ring-gate transistor model.

[0054] According to the design requirements, N-type nano-ring gate transistor models can be established separately, such as Figure 2b As shown, multiple N-type nano-ring-gate transistors 12 are arranged in an array on a silicon substrate 10 around a through-silicon via (TSV) 11. The stress distribution of the N-type nano-ring-gate transistors 12 at different locations is used to obtain the average stress of the area, which is used as the stress of the N-type nano-ring-gate transistor 12 at that location. The stress at each location is input into a model of the N-type nano-ring-gate transistor 12, and the electrical characteristics of the N-type nano-ring-gate transistor 12 at each location are calculated. All of the N-type nano-ring-gate transistors can have the same orientation, meaning that the channels of the N-type nano-ring-gate transistors are arranged along the same direction (e.g., a first direction or a second direction). The spacing between adjacent N-type nano-ring-gate transistors can be determined as required. When obtaining the stress based on the stress distribution, the stress in the N-type nano-ring-gate transistors in multiple directions can be decomposed (simplified) into a first component along the first direction and a second component along the second direction, which are then applied to the channel of the N-type nano-ring-gate transistor model for ease of calculation. The N-type nano-gate-all-around transistor model is a high-precision model based on a standard N-type nano-gate-all-around transistor, fully incorporating physical simulation models such as drift-diffusion transport models, mobility models, coincidence models, and Fermi statistics. The derived electrical characteristics include multiple parameters such as Ioff (off-state current), Idsat (saturated drain current), and Vth (threshold voltage).

[0055] A P-type nano-gate-all-around transistor model is established, and the electrical characteristics of the P-type nano-gate-all-around transistor arranged around a through-silicon via can be obtained using a method similar to the above. The P-type nano-gate-all-around transistor can be positioned at the same location as the N-type nano-gate-all-around transistor, and both have the same channel orientation.

[0056] It should be noted that after obtaining the stress distribution of the silicon substrate around the through-silicon via under the thermal load parameters, the mobility distribution of N-type carriers (electrons) and P-type carriers (holes) of the silicon substrate can also be obtained based on the stress distribution, and N-type nano-ring gate transistors are set in the area around the through-silicon via based on the mobility distribution of N-type carriers, and P-type nano-ring gate transistors are set in the area around the through-silicon via based on the mobility distribution of P-type carriers. In one example, the electron mobility in a standard N-type nano-ring gate transistor is used as a standard, and the area in the mobility distribution where the electron mobility varies within, for example, 10% relative to the above standard is used as a reference for the subsequent arrangement of N-type nano-ring gate transistors. The electron mobility in a standard N-type nano-ring gate transistor is used as a standard, and the area in the mobility distribution where the electron mobility varies within, for example, 10% relative to the above standard is used as a reference for the subsequent arrangement of N-type nano-ring gate transistors.

[0057] Next, step S03 is executed to obtain a first region and a second region according to a preset electrical characteristic range and electrical characteristics. The electrical characteristics of the N-type nano-ring gate transistor in the first region meet the preset electrical characteristic range, and the electrical characteristics of the P-type nano-ring gate transistor in the second region meet the preset electrical characteristic range.

[0058] Each electrical characteristic within the preset electrical characteristic range may include a range centered around the electrical characteristics corresponding to a standard N-type nano-ring-gate transistor, with fluctuation limits of, for example, 10%. Specifically, taking the first region as an example, N-type nano-ring-gate transistors arranged around a through-silicon via (TSV) may be screened for N-type nano-ring-gate transistors whose electrical characteristics fall within the preset electrical characteristic range. The region encompassed by the selected N-type nano-ring-gate transistors is then designated as the first region, i.e., the region that meets the layout requirements for the N-type nano-ring-gate transistors. The electrical characteristics may include multiple parameters, each responding to different degrees to the distance from the TSV (stress). The first region is the region (intersection) that simultaneously meets the requirements for each of the aforementioned parameters. Among the electrical characteristics, leakage current is the most sensitive to stress compared to other parameters. Therefore, the first region may be determined based on the leakage current of the N-type nano-ring-gate transistor. A similar method to that used to obtain the first region is used to obtain the second region corresponding to the layout requirements for the P-type nano-ring-gate transistors.

[0059] It is understandable that the farther away from the TSV, the less impact the nano-ring-gate transistor is on the TSV. Therefore, areas not provided with nano-ring-gate transistors but relatively far from the TSV also fall within the first and second regions. Furthermore, since the stress components in the first and second directions in the silicon substrate surrounding the TSV are in opposite directions—one direction is positive stress (tensile stress) and the other is negative stress (compressive stress)—we can obtain a first region of an N-type nano-ring-gate transistor whose channel direction extends along the first direction and a first region of an N-type nano-ring-gate transistor whose channel direction extends along the second direction, respectively. The intersection of these first regions extending along the first and second directions is then used to determine the first region of the N-type nano-ring-gate transistor. Similarly, the second region of a P-type nano-ring-gate transistor whose channel direction extends along the first direction and a second region of the P-type nano-ring-gate transistor whose channel direction extends along the second direction are then used to determine the second region of the P-type nano-ring-gate transistor.

[0060] In one example, if Figure 2cAs shown, the edges (contours) of the first and second regions near the TSV 11 obtained by simulation based on the transistor model, stress distribution, and preset electrical characteristic range are not circular, but are roughly in the shape of cross petals (e.g., first boundary 21). However, in practice, the above contours can usually be expanded to circles (e.g., second boundary 22) to facilitate calculation and layout. The setting parameters of the TSV can be as described above. The first region can be a region outside the edge of the TSV, for example, 5 microns, and the second region can be a region outside the edge of the TSV, for example, 10 microns.

[0061] Next, step S04 is executed to establish an inverter model constructed by the N-type nano-ring gate transistor model and the P-type nano-ring gate transistor model, and several inverters are set on the silicon substrate around the silicon via. The DC characteristics of each inverter are obtained based on the stress distribution and the inverter model.

[0062] In combination with design requirements, an inverter model can be constructed using the aforementioned N-type nano-ring-gate transistor model and P-type nano-ring-gate transistor model. Multiple inverters are arranged in an array on the silicon substrate around the through-silicon via (TSV). The average stress corresponding to the N-type nano-ring-gate transistor and the P-type nano-ring-gate transistor of the inverter is then obtained by measuring the area occupied by the inverters at different positions in the stress distribution. The stresses at different positions are then input into the inverter model to obtain the DC characteristics of the inverter models at different positions.

[0063] Among them, all the above-mentioned inverters can have the same arrangement, that is, the channels of the N-type and P-type nano-ring gate transistors in all inverters are arranged along the same direction (for example, the first direction or the second direction). When obtaining stress based on the above-mentioned stress distribution, the stress of the transistors in multiple directions in the inverter can be decomposed (simplified) into a first component along the first direction and a second component along the second direction, and applied to the channels of the N-type and P-type nano-ring gate transistor models for ease of calculation. The DC characteristics of the inverter obtained may include voltage transition point, high-level noise margin and low-level noise margin, which are used to evaluate the stability of the circuit. Of course, the inverter may also include AC characteristics, which include conversion time and propagation delay, etc.

[0064] It should be noted that, the plurality of inverters mentioned above can be arranged on the silicon substrate around the through silicon via according to the distribution of the P-type carrier mobility, and the spacing between adjacent inverters can be determined according to requirements.

[0065] Next, step S05 is executed to obtain a third region according to the preset DC characteristic range and the DC characteristic, wherein the DC characteristic of the inverter in the third region meets the preset DC characteristic range.

[0066] The parameters within the preset DC characteristic range may include the allowable ranges for various parameters of an inverter constructed from standard N-type and P-type nano-gate-all-around transistors. Inverters whose parameters meet the preset DC characteristic range are screened from the inverters arranged around the TSV, and the area encompassed by the selected inverters is used as the third zone, i.e., the area that meets the inverter layout requirements. The voltage transition point within the preset DC characteristic range may fluctuate within a range of, for example, 1% around Vdd / 2. Specifically, inverters whose voltage transition points fluctuate within a 1% range around Vdd / 2 are screened from the inverters arranged around the TSV, and the area encompassed by the selected inverters is used as the third zone that meets the voltage transition point requirements. The high-level noise margin and the low-level noise margin have good symmetry within the preset DC characteristic range, and the difference between the high-level noise margin and the low-level noise margin is within the preset range (closer to the difference between the two at a greater distance). Specifically, inverters whose difference between the high-level noise margin and the low-level noise margin is within the preset range are selected from the inverters arranged around the through-silicon via (TSV). The area covered by these selected inverters is then used as a third region that meets the high-level noise margin and the low-level noise margin. The intersection of these third regions that meet the aforementioned parameters is then determined as the layout region that meets the DC characteristics of the inverters. Based on this, the AC characteristics of the third region can be verified (ensured) to determine whether they meet the corresponding requirements. If not, the third region can be fine-tuned based on the distribution of the inverter's AC characteristics.

[0067] It is understandable that the farther the inverter is from the TSV, the less affected it is by the TSV. Therefore, even areas not equipped with inverters but relatively far from the TSV also fall within the third region. Furthermore, because the stress components in the first and second directions in the silicon substrate surrounding the TSV are in opposite directions—i.e., one direction is positive (tensile) and the other is negative (compressive)—a third region can be obtained for an inverter whose channel extends in the first direction and a third region for an inverter whose channel extends in the second direction. The intersection of these third regions extending in the first and second directions is then performed to determine the final third region of the inverter.

[0068] In one example, as described above, the third region near the edge (contour) of the through-silicon via is enlarged into a circle. The setting parameters of the through-silicon via can be as described above. The third region along the first direction of the channel can be a region outside the edge of the through-silicon via, for example, 5 microns. The third region along the second direction of the channel can be a region outside the edge of the through-silicon via, for example, 7.5 microns. Therefore, the final third region is a region outside the edge of the through-silicon via, for example, 7.5 microns.

[0069] Next, step S06 is performed to obtain the intersection of the first region, the second region, and the third region as a region for arranging an inverter on the silicon substrate around the through silicon via.

[0070] An intersection operation is performed on the first area, the second area and the third area on the silicon substrate around the through silicon via, and the obtained intersection area is the area on the silicon substrate around the through silicon via where the inverter is arranged.

[0071] The present application further provides a three-dimensional chip structure integrating TSV and inverter, which includes a silicon substrate, a through-silicon via and an inverter. The inverter is composed of an N-type nano-ring gate transistor and a P-type nano-ring gate transistor. The through-silicon via and the inverter are arranged on the silicon substrate using the layout method as described above.

[0072] An embodiment of the present application further provides a chip, which includes the above-mentioned three-dimensional integrated chip structure, that is, the chip includes at least two layers of the above-mentioned three-dimensional integrated chip structure stacked vertically.

[0073] In summary, the present invention provides a three-dimensional chip structure and layout method for integrating TSVs and inverters, and a chip. The layout method includes providing a silicon substrate with through-silicon vias and thermal load parameters, obtaining a stress distribution of the silicon substrate around the through-silicon via under the thermal load parameters; sequentially arranging a plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors on the silicon substrate around the through-silicon vias, and obtaining electrical characteristics of each N-type nano-ring-gate transistor and each P-type nano-ring-gate transistor based on the stress distribution; obtaining a first region conforming to the N-type nano-ring-gate transistor and a second region conforming to the P-type nano-ring-gate transistor on the silicon substrate based on a preset electrical characteristic range and electrical characteristics; arranging a plurality of inverters composed of P-type nano-ring-gate transistors and N-type nano-ring-gate transistors on the silicon substrate around the through-silicon vias, and obtaining DC characteristics of each inverter based on the stress distribution; obtaining a third region conforming to the layout requirements of the inverter on the silicon substrate based on the preset DC characteristic range and DC characteristics; and obtaining the intersection of the first region, the second region, and the third region as the region for arranging the inverter on the silicon substrate around the through-silicon vias. In the present invention, a stress distribution of a silicon substrate around a through-silicon via (TSV) is obtained from TSV and thermal load parameters. The stress distribution is then used in combination with an N-type nano-gate-all-around transistor model, a P-type nano-gate-all-around transistor model, and an inverter model to obtain characteristic parameters of devices around the TSV. The intersection of the first, second, and third regions corresponding to respective preset ranges is then used as the region for arranging an inverter. This not only considers the effect of thermal stress on the performance of the inverter, but also the effect of thermal stress on the performance of each transistor in the inverter. This reduces the probability of erroneous logic outputs in the entire circuit, thereby improving the performance and reliability of a three-dimensional integrated circuit composed of inverters around the TSV, thereby enabling the three-dimensional integrated circuit to operate more stably and efficiently in various application scenarios (such as high-performance computing, communications, and other fields).

[0074] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A layout method for a three-dimensional chip structure integrating TSVs and inverters, characterized in that: include: Providing a silicon substrate having a through-silicon via and thermal load parameters, and obtaining a stress distribution of the silicon substrate around the through-silicon via under the thermal load parameters; Establishing an N-type nano-ring-gate transistor model and a P-type nano-ring-gate transistor model, sequentially disposing a plurality of N-type nano-ring-gate transistors and P-type nano-ring-gate transistors on the silicon substrate around the through-silicon via, and obtaining electrical characteristics of each of the N-type nano-ring-gate transistors and the P-type nano-ring-gate transistors based on the stress distribution, the N-type nano-ring-gate transistor model, and the P-type nano-ring-gate transistor model; According to the preset electrical characteristic range and the electrical characteristic, a first region and a second region are obtained, wherein the electrical characteristic of the N-type nano-ring gate transistor in the first region meets the preset electrical characteristic range, and the electrical characteristic of the P-type nano-ring gate transistor in the second region meets the preset electrical characteristic range; Establishing an inverter model constructed by the N-type nano-ring gate transistor model and the P-type nano-ring gate transistor model, disposing a plurality of inverters on the silicon substrate around the through silicon via, and obtaining a DC characteristic of each inverter based on the stress distribution and the inverter model; obtaining a third region according to a preset DC characteristic range and the DC characteristic, wherein the DC characteristic of the inverter in the third region meets the preset DC characteristic range; An intersection of the first region, the second region, and the third region is obtained as a region on the silicon substrate around the through silicon via for arranging an inverter.

2. The layout method of a three-dimensional chip structure integrating TSV and inverter according to claim 1, characterized in that: After obtaining the stress distribution of the silicon substrate around the through silicon via under the thermal load parameters, the mobility distribution of N-type carriers and P-type carriers of the silicon substrate is also obtained based on the stress distribution, and the N-type nano-ring gate transistor, the P-type nano-ring gate transistor and the inverter are set in the area around the through silicon via based on the mobility distribution.

3. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 2, characterized in that: The electrical characteristic includes leakage current, and the first region and the second region are respectively set according to the leakage current of the N-type nano-ring gate transistor and the P-type nano-ring gate transistor.

4. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 1, wherein: The stress distribution of the silicon substrate around the silicon via under the thermal load parameters is in the shape of a cross petal, and the stress distribution includes stress components along a first direction and a second direction, the first direction and the second direction are orthogonal, and the positive and negative signs of the two stress components are opposite.

5. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 4, characterized in that: The N-type nano-ring-gate transistor includes a first N-type nano-ring-gate transistor, wherein the first N-type nano-ring-gate transistor is composed of the N-type nano-ring-gate transistors arranged along the first direction, and the electrical characteristics of each of the first N-type nano-ring-gate transistors and the corresponding first region are obtained; The N-type nano-ring-gate transistor includes a second N-type nano-ring-gate transistor, wherein the second N-type nano-ring-gate transistor is composed of the N-type nano-ring-gate transistors arranged along the second direction, and the electrical characteristics of each second N-type nano-ring-gate transistor and the corresponding first region are obtained; An intersection of the first region of the first N-type nano-ring gate transistor and the first region of the second N-type nano-ring gate transistor is obtained as the first region of the N-type nano-ring gate transistor.

6. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 4, wherein: The P-type nano-ring-gate transistor includes a first P-type nano-ring-gate transistor, wherein the first P-type nano-ring-gate transistor is composed of the P-type nano-ring-gate transistors arranged along the first direction, and the electrical characteristics of each of the first P-type nano-ring-gate transistors and the corresponding second region are obtained; The P-type nano-ring-gate transistor includes a second P-type nano-ring-gate transistor, wherein the second P-type nano-ring-gate transistor is composed of the P-type nano-ring-gate transistors arranged along the second direction, and the electrical characteristics of each second P-type nano-ring-gate transistor and the corresponding second region are obtained; An intersection of the second region of the first P-type nano-ring gate transistor and the second region of the second P-type nano-ring gate transistor is obtained as the second region of the P-type nano-ring gate transistor.

7. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 4, characterized in that: The inverter includes a first inverter, wherein the first inverter is composed of the P-type nano-ring gate transistor and the N-type nano-ring gate transistor arranged along the first direction, and a DC characteristic of each first inverter and a corresponding third region are obtained; The inverter includes a second inverter, wherein the second inverter is composed of the P-type nano-ring gate transistor and the N-type nano-ring gate transistor arranged along the second direction, and a DC characteristic of each second inverter and a corresponding third region are obtained; The third region of the first inverter and the third region of the second inverter are intersected to form the third region of the inverter.

8. The layout method of a three-dimensional chip structure integrating TSVs and inverters according to claim 1, wherein: The DC characteristics of the inverter include a voltage transition point, a high-level noise margin, and a low-level noise margin.

9. A three-dimensional chip structure integrating TSV and inverter, characterized in that: The invention comprises a silicon substrate, a through silicon via and an inverter, wherein the inverter is composed of an N-type nano-ring gate transistor and a P-type nano-ring gate transistor, and the through silicon via and the inverter are arranged on the silicon substrate using the layout method according to any one of claims 1 to 8.

10. A chip, characterized in that: Comprising the three-dimensional integrated chip structure as claimed in claim 9.

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