Intelligent lock debugging information output method based on time division multiplexing and intelligent lock

Abstract

The invention relates to the technical field of locks, in particular to an intelligent lock debugging information output method based on time division multiplexing and an intelligent lock. According to the intelligent lock debugging information output method based on time division multiplexing, intelligent switching between the debugging mode and the service interface mode is achieved by dynamically configuring the sending pin function of the hardware serial port. When a system is initialized, a hardware serial port is preferentially mapped to a debugging pin to output debugging information; when it is detected that the service function needs to occupy the hardware serial port, the hardware serial port is switched to the service pin, the debugging function is closed, meanwhile, debugging information is output through a software simulation serial port protocol by adopting a simulation serial port, and conflict-free operation of service data transmission and debugging log output is ensured. The error code problem caused by insufficient simulation serial port time sequence precision is avoided, and the integrity and accuracy of debugging information are ensured; and meanwhile, the occupation of the simulation serial port on system resources is reduced, the system operation is smoother, and the user experience is improved.

Description

Technical Field

[0001] The present application relates to the technical field of locks, and in particular to a method for outputting debugging information of an intelligent lock based on time division multiplexing and an intelligent lock. Background Art

[0002] In smart lock development, debugging is not only a functional verification tool but also a core component of system reliability design (DFR). By outputting debugging information in real time and analyzing critical path performance bottlenecks, developers can optimize resource allocation strategies and eliminate hardware and software coupling defects, thereby improving system MTBF (mean time between failures) and reducing after-sales maintenance costs. This, in turn, improves the user experience to a certain extent.

[0003] In traditional smart lock development, the debugging process generally uses a single-channel hardware serial communication interface (UART) architecture. Multiple functional modules compete for resources on the physical serial bus, which can cause the debugging data channel to be blocked. Once the serial port resources are exhausted by related functional services, the system will be forced to use a software-emulated virtual serial communication interface as an alternative output path. However, this technical solution has the following significant drawbacks:

[0004] 1. Due to the lack of hardware-level error checking mechanisms, virtual serial interfaces are prone to bit synchronization deviations during asynchronous data transmission, resulting in an increased rate of data verification failures at the transport layer and compromised integrity of critical debugging information.

[0005] 2. Software-simulated communication protocols occupy central processing unit (CPU) computing resources, triggering system-level resource competition and increasing real-time task scheduling delays. Specifically, the input response cycle of the human-machine interface (HMI) is prolonged, resulting in perceptible operational hysteresis and affecting user experience.

[0006] The above technical defects restrict the debugging efficiency and operating performance during the development of smart locks. Summary of the Invention

[0007] The present application provides a smart lock debugging information output method and a smart lock based on time division multiplexing to solve the problems of poor debugging efficiency and operating performance during the development of smart locks.

[0008] The technical solutions adopted in this application are as follows:

[0009] On the one hand, an embodiment of the present invention provides a method for outputting debugging information of a smart lock based on time division multiplexing, comprising the following steps:

[0010] When the system is initialized, the sending end of the hardware serial port is configured as the debug serial port mode, the sending end of the hardware serial port is mapped to the debug pin, and the debug information transmission channel is initialized to the hardware serial port;

[0011] If it is detected that business information needs to be transmitted through the hardware serial port, dynamic switching operations are performed, including:

[0012] Switch the sending end of the hardware serial port from debug serial port mode to target service interface mode, map the sending end of the hardware serial port to the service pin, and disable the debug serial port mode function;

[0013] Switch the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port;

[0014] If the service information transfer is complete, the recovery operation is performed, including:

[0015] Switch the sending end of the hardware serial port from the target business interface mode back to the debug serial port mode, map the sending end of the hardware serial port to the debug pin, and disable the function of the target business interface mode;

[0016] Switch the debugging information transmission channel from the analog serial port back to the hardware serial port so that the debugging information can be output through the hardware serial port again.

[0017] In some embodiments of the present invention, the hardware serial port is a service multiplexing serial port, the activation times of the service multiplexing serial port is ≤20 times / day, the single service occupancy time is <500ms, and the idle interval is >1s.

[0018] In some embodiments of the present invention, the debugging information is encrypted before being output.

[0019] In some embodiments of the present invention, the method further includes disabling the debug pin via a fuse bit or an option byte.

[0020] In some embodiments of the present invention, the simulated serial port implements data output by simulating a serial port protocol through software.

[0021] In some embodiments of the present invention, when an abnormality occurs in the debugging information transmission channel, the system automatically switches to a backup storage medium to temporarily store the logs, and uploads them after the connection is restored.

[0022] In some embodiments of the present invention, after the step of switching the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port, the method further includes:

[0023] Perform level conversion and isolation on the debugging information output by the analog serial port.

[0024] In some embodiments, the method further includes: performing frame error detection, parity check, and overflow error flag detection on the transmission process of the debugging information, and marking abnormal transmission events.

[0025] On the other hand, an embodiment of the present invention further provides a smart lock, comprising:

[0026] The status detection module is used to detect whether the hardware serial port has a business information transmission requirement. If so, it performs a dynamic switching operation to switch the sending end of the hardware serial port from the debug serial port mode to the target business interface mode, so that the sending end of the hardware serial port is mapped to the business pin and the debug serial port mode function is disabled;

[0027] The channel selection module selects the hardware serial port or the simulated serial port as the transmission channel of the debugging information in response to the detection result of the status detection module;

[0028] The pin switching module maps the debug information to the corresponding service pin or debug pin according to the transmission channel selected by the channel selection module.

[0029] On the other hand, an embodiment of the present invention further provides a smart lock, comprising:

[0030] processor;

[0031] a memory for storing at least one program;

[0032] When at least one program is executed by the processor, the processor implements the smart lock debugging information output method based on time division multiplexing as described in the above embodiment.

[0033] The beneficial effects of adopting the technical solution of this application are as follows:

[0034] By replacing the asynchronous timing generation method of the software-emulated serial port with the physical layer data verification mechanism of the hardware serial port, the bit synchronization deviation problem caused by the insufficient accuracy of the software-emulated timing is effectively eliminated, the debug information transmission layer bit error rate is effectively reduced, the integrity of the debug information data frame is guaranteed, and to a certain extent, the distortion of key debug information caused by the lack of hardware-level error checking in the virtual serial port is avoided. In addition, by reducing the system resource usage of the simulated serial port, the system runs more smoothly and the user experience is improved. At the same time, relying on the remapping technology and time-division multiplexing mechanism of the hardware serial port's transmitting pin, the debug information output channel is dynamically switched according to the usage status of the business serial port, which not only ensures the output of debug information but also does not affect the normal operation of business functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1Flowchart of a method for outputting debugging information of a smart lock based on time division multiplexing provided by an embodiment of the present invention;

[0037] Figure 2 This is a block diagram of the principles of the smart lock provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The following embodiments are described in detail, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following embodiments are not intended to represent all possible implementations consistent with the present application. They are merely examples of systems and methods consistent with certain aspects of the present application, as detailed in the claims.

[0039] At present, there are three main methods for debugging existing smart locks. The first is to use an analog serial port to transmit debugging data, but it has the disadvantages of slow data transmission rate, high bit error rate and system jamming; the second is to forward the debugging information to other chips, and then output it through the serial port of other chips or the network (such as WIFI). When transmitting a large amount of logs for debugging, the system jams more obviously; the third is to use the business serial port multiplexing method, which relies solely on the business serial port. Although the business data and debugging data are processed in parallel in a multiplexed manner, it is easy to have the disadvantages of debugging information loss and debugging information incoherence.

[0040] See also Figure 1 In order to solve the problems of poor debugging efficiency and poor operating performance during the development of the smart lock, an embodiment of the present invention provides a method for outputting smart lock debugging information based on time division multiplexing, comprising the following steps:

[0041] S110, when the system is initialized, the sending end of the hardware serial port is configured to the debug serial port mode, the sending end of the hardware serial port is mapped to the debug pin, and the debug information transmission channel is initialized to the hardware serial port;

[0042] S120, if it is detected that business information needs to be transmitted through the hardware serial port, a dynamic switching operation is performed;

[0043] S130: If the business information transmission is completed, perform the recovery operation.

[0044] The dynamic switching operation is performed in step S120, specifically including:

[0045] Switch the sending end of the hardware serial port from debug serial port mode to target service interface mode, map the sending end of the hardware serial port to the service pin, and disable the debug serial port mode function;

[0046] Switch the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port;

[0047] The recovery operation performed in step S130 specifically includes:

[0048] Switch the sending end of the hardware serial port from the target business interface mode back to the debug serial port mode, map the sending end of the hardware serial port to the debug pin, and disable the function of the target business interface mode;

[0049] Switch the debugging information transmission channel from the analog serial port back to the hardware serial port so that the debugging information can be output through the hardware serial port again.

[0050] In this specific embodiment, different from the existing smart locks that simply rely on the time-division multiplexing debugging method of the hardware serial port, the performance advantages of the hardware serial port and the virtual serial port are combined, and the sending pin function of the hardware serial port is dynamically reconfigured to realize the intelligent switching between the debugging mode and the business interface mode. When the system is initialized, the hardware serial port is preferentially mapped to the debug pin to output debugging information; when it is detected that a business function (such as face recognition) needs to occupy the hardware serial port, the hardware serial port is immediately switched to the business pin and the debugging function is turned off. At the same time, the debugging information is migrated to the general GPIO pin output through software simulation of the serial port protocol to ensure conflict-free operation of business data transmission and debug log output. This embodiment reduces hardware costs through dynamic multiplexing of hardware resources and uses simulated serial ports to ensure debugging continuity.

[0051] In some embodiments of the present invention, the hardware serial port is a service multiplexing serial port, the activation times of the service multiplexing serial port is ≤20 times / day, the single service occupancy time is <500ms, and the idle interval is >1s.

[0052] In this specific embodiment, for low-frequency, short-term business scenarios of smart locks (such as temporary Bluetooth unlocking or face recognition command transmission), by accurately controlling the duration and interval of the business occupying the serial port, it is ensured that the hardware serial port quickly switches to the target business interface mode when the business is triggered, and completes the data transmission of business information in a very short time (such as sending an encrypted instruction packet within 300ms), and then immediately releases the serial port resources and restores the debugging channel; because the time occupied by a single business is much smaller than the idle window for debugging information output (usually >1s), and the business trigger interval is sufficient, the hardware serial port can serve the debugging information output more than 99% of the time. This embodiment achieves zero-conflict coexistence of business and debugging through a time slice allocation strategy, avoids debugging interruptions caused by frequent business occupation in traditional solutions, and enables efficient reuse of hardware resources; low-power optimization: In addition, short-term switching reduces the energy consumption overhead of pin function reconfiguration, achieves low-power optimization, and adapts to battery-powered smart lock application scenarios; the debugging channel is quickly restored during business intervals, ensuring continuous recording and real-time analysis of fault logs.

[0053] In some embodiments of the present invention, the debugging information is encrypted before being output.

[0054] In this specific embodiment, before debugging information is output through the hardware serial port or simulated serial port, an encryption algorithm is used to encrypt the data packet in real time. The generated ciphertext is then output to the target serial port. Simultaneously, a pre-set key or dynamic key negotiation mechanism ensures that the decryption end (such as an authorized debugging device) can legally restore the information. This prevents potential system vulnerabilities and user operation records in the debug log from being intercepted or tampered with during transmission. Only authorized devices holding the key can decrypt the debugging information, preventing unauthorized terminals from illegally accessing it, further ensuring data security during the debugging process.

[0055] In some embodiments of the present invention, the method further includes disabling the debug pin via a fuse bit or an option byte.

[0056] In this specific embodiment, a hardware-level access control strategy is implemented for the debug pins by configuring non-volatile storage units (such as fuses or option bytes). For example, in the mass production stage, by burning the built-in fuses or option byte registers of the chip, the physical function of the debug pins (such as the SWD / JTAG interface) is permanently locked to the general I / O mode or its electrical drive capability is directly disabled, thereby cutting off the access path of the external debug probe to the internal bus of the system, eliminating the risk of firmware reverse engineering caused by the exposure of the debug interface, and preventing injection attacks or data theft through physical pins. In addition, the fuse bit burning status can be used as a hardware version identifier, and by reading the option byte content, it can be verified whether the product is authorized for debugging, thereby realizing supply chain security management and control.

[0057] In some embodiments of the present invention, the simulated serial port implements data output by simulating a serial port protocol through software.

[0058] In this specific embodiment, the simulated serial port controls the level change timing of the general GPIO pin through software programming, accurately simulating the signal waveform of the asynchronous serial communication protocol to achieve data output. The principle is: after the debugging information transmission channel is switched to the simulated serial port, the microcontroller core or coprocessor generates a timer interrupt according to the preset baud rate (such as 9600bps), driving the specified GPIO pin to output the start bit (low level), 8 data bits (LSB first) and stop bit (high level) in sequence according to the UART protocol specification, while ensuring the continuity of the data stream through the buffer management mechanism; for high real-time scenarios, DMA direct memory access technology can be used to automatically move data to the GPIO port to reduce the CPU load. The advantage of this embodiment is that it can realize the transparent transmission of debugging information without relying on dedicated serial port hardware, and adapt to different baud rates and data formats by dynamically adjusting software parameters. In the smart lock system with limited hardware resources, it not only reduces the material cost, but also avoids the blocking of business functions caused by the exclusive use of hardware serial ports. At the same time, after combining with level conversion or isolation circuit expansion, it can be compatible with the needs of long-distance industrial-grade debugging environment.

[0059] In some embodiments of the present invention, when an abnormality occurs in the debugging information transmission channel, the system automatically switches to a backup storage medium to temporarily store the logs, and uploads them after the connection is restored.

[0060] In this specific embodiment, when an abnormality occurs in the debugging information transmission channel (such as hardware serial port signal interruption or analog serial port level distortion), the system determines the connection interruption by real-time monitoring of signal quality indicators (such as bit error rate, level stability) or heartbeat packet response timeout, immediately triggering the storage switching logic to temporarily store the debug log to a non-volatile storage medium such as onboard Flash or EEPROM. The storage process adopts a circular buffer management strategy, cyclically overwriting old data in timestamp order to ensure the integrity of key logs; at the same time, a low-power mode is activated to reduce the impact of storage operations on the system's main tasks. After the channel is restored, the system automatically detects the reconstruction of the communication link, prioritizes uploading the temporary log to the debugging terminal, and clears the storage area after confirming the data is correct through a verification mechanism. This embodiment avoids the loss of debugging information due to network fluctuations or hardware failures through fault-adaptive switching and offline storage mechanisms. It is particularly suitable for scenarios without permanent power supply or remote maintenance. It is also compatible with the expansion access of various storage media such as SD cards and FRAM, improving the robustness and applicability of the solution.

[0061] In some embodiments of the present invention, after the step of switching the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port, the method further includes:

[0062] Perform level conversion and isolation on the debugging information output by the analog serial port.

[0063] In this specific embodiment, after the debug information transmission channel switches to the analog serial port, a level conversion module and isolation circuit are introduced to perform physical layer enhancement processing on the output signal. A level conversion chip (such as the TXB0108) adapts the TTL / CMOS levels output by the microcontroller's I / O pins to the standard interface levels of the target debug device (such as RS-232 or RS-485), eliminating signal amplitude attenuation or logical misjudgments caused by level mismatch. Simultaneously, an optocoupler isolator (such as the HCPL-063A) or a digital isolator (such as the ADuM1201) establishes an electrical isolation barrier on the analog serial port output path, blocking common-mode noise, ground loop interference, and surge voltage from coupling back into the main control circuit. This dual processing mechanism improves the common-mode noise rejection ratio (CMRR) of the debug interface, ensuring the logical integrity of debug information in strong electromagnetic interference environments. It also mitigates electrostatic discharge (ESD) damage introduced by the debug device, improving system robustness while extending the debug interface's electrical life and reducing the frequency of maintenance due to physical layer anomalies.

[0064] In some embodiments, the method further includes: performing frame error detection, parity check, and overflow error flag detection on the transmission process of the debugging information, and marking abnormal transmission events.

[0065] In this specific embodiment, when debugging information is transmitted through a hardware serial port or an analog serial port, a frame error detection, parity check, and overflow error flag detection mechanism are embedded to improve transmission reliability. In actual applications, when the sending end encapsulates the debugging information, it adds a start bit, a stop bit, and a parity check bit according to a preset protocol. The receiving end determines the frame error by real-time monitoring of the abnormal level jump of the start / stop bit, verifies the parity error by the XOR operation result of the check bit and the data bit, and identifies the overflow error by cyclically detecting the status of the sending buffer; once any of the above abnormalities is detected, an error flag is immediately inserted into the debugging information stream and an interrupt is triggered, and the abnormal event type, timestamp, and associated data packet index are recorded in the system log. This embodiment significantly reduces the risk of data transmission distortion caused by signal interference, clock offset, or resource competition through multi-dimensional error detection and active marking mechanisms, enabling operation and maintenance personnel to quickly locate physical layer communication failures or software logic defects, while providing structured error data support for subsequent debugging information integrity analysis. Combined with automatic retransmission or redundancy check strategies, the system's fault tolerance and robustness can be further optimized.

[0066] On the other hand, an embodiment of the present invention further provides a smart lock, comprising:

[0067] The status detection module is used to detect whether the hardware serial port has a business information transmission requirement. If so, it performs a dynamic switching operation to switch the sending end of the hardware serial port from the debug serial port mode to the target business interface mode, so that the sending end of the hardware serial port is mapped to the business pin and the debug serial port mode function is disabled;

[0068] The channel selection module selects the hardware serial port or the simulated serial port as the transmission channel of the debugging information in response to the detection result of the status detection module;

[0069] The pin switching module maps the debug information to the corresponding service pin or debug pin according to the transmission channel selected by the channel selection module.

[0070] In this specific embodiment, intelligent scheduling of hardware resources is achieved through the collaborative architecture of the status detection module, the channel selection module and the pin switching module. The status detection module monitors the bus activity status based on the hardware serial port interrupt vector table. When a service transmission request is captured, the priority preemptive bus arbitration strategy is triggered, and the pin switching module is driven to perform the sending end remapping operation in the hardware abstraction layer (HAL), so that the sending end of the hardware serial port is mapped to the service pin; the channel selection module synchronously activates the adaptive routing algorithm, and seamlessly migrates the debugging information to the pre-allocated GPIO virtual serial port channel according to the service priority weight, and dynamically adjusts the baud rate pre-division coefficient to match the target transmission mode. This embodiment ensures the complete isolation of the debugging information flow and the service data flow at the physical layer and protocol layer by flexibly and dynamically switching the transmission channel of the debugging data, thereby avoiding the packet truncation phenomenon caused by bus conflicts. The system adopts a double-buffer queue mechanism to maintain the continuity of the debugging information output and maintain signal integrity during the switching process.

[0071] See also Figure 2 On the other hand, an embodiment of the present invention further provides a smart lock, comprising:

[0072] Processor 210;

[0073] Memory 220, used to store at least one program;

[0074] When at least one program is executed by the processor 210, the processor 210 implements the smart lock debugging information output method based on time division multiplexing as described in the above embodiment.

[0075] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0076] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without expending creative work shall fall within the scope of protection of this application.

Claims

1. A method for outputting debugging information of a smart lock based on time division multiplexing, characterized in that: The following steps are involved: When the system is initialized, the sending end of the hardware serial port is configured as the debug serial port mode, the sending end of the hardware serial port is mapped to the debug pin, and the debug information transmission channel is initialized to the hardware serial port; If it is detected that business information needs to be transmitted through the hardware serial port, a dynamic switching operation is performed, including: Switching the sending end of the hardware serial port from the debug serial port mode to the target service interface mode, mapping the sending end of the hardware serial port to the service pin, and disabling the function of the debug serial port mode; Switching the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port; If the service information transmission is complete, a recovery operation is performed, including: Switching the sending end of the hardware serial port from the target service interface mode back to the debug serial port mode, mapping the sending end of the hardware serial port to the debug pin, and disabling the function of the target service interface mode; The debugging information transmission channel is switched from the analog serial port back to the hardware serial port, so that the debugging information is restored to be output through the hardware serial port.

2. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: The hardware serial port is a service multiplexing serial port, the activation times of the service multiplexing serial port are ≤20 times / day, the single service occupancy time is <500ms, and the idle interval is >1s.

3. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: The debugging information is encrypted before being output.

4. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: Also includes: Disable debug pins via fuses or option bytes.

5. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: The simulated serial port realizes data output by simulating the serial port protocol through software.

6. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: When an exception occurs in the debugging information transmission channel, the system automatically switches to the backup storage medium to temporarily store the logs and upload them after the connection is restored.

7. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: After the step of switching the debugging information transmission channel from the hardware serial port to the simulated serial port so that the debugging information is output through the simulated serial port, the method further includes: Performing level conversion and isolation processing on the debugging information output by the analog serial port.

8. The method for outputting debugging information of a smart lock based on time division multiplexing according to claim 1, characterized in that: Also includes: Frame error detection, parity check, and overflow error flag detection are performed on the transmission process of debugging information, and abnormal transmission events are marked.

9. A smart lock, characterized in that: include: A status detection module is used to detect whether the hardware serial port has a business information transmission requirement. If so, it performs a dynamic switching operation to switch the sending end of the hardware serial port from the debug serial port mode to the target business interface mode, so that the sending end of the hardware serial port is mapped to the business pin, and the debug serial port mode function is disabled; a channel selection module, in response to the detection result of the status detection module, selecting a hardware serial port or an analog serial port as a transmission channel for debugging information; The pin switching module maps the debugging information to the corresponding service pin or debugging pin according to the transmission channel selected by the channel selection module.

10. A smart lock, characterized in that: include: processor; a memory for storing at least one program; When the at least one program is executed by the processor, the processor implements the smart lock debugging information output method based on time division multiplexing as described in any one of claims 1 to 8.

Images