Semiconductor device and forming method thereof

Abstract

A semiconductor device and a method of forming the same are provided. A method of forming a semiconductor device includes the following steps. A thick bonding layer is formed over a surface of the semiconductor wafer such that a top surface of the bonding layer in an edge region is located at a higher vertical height than a bottom surface of the bonding layer in a non-edge region of the semiconductor wafer. A photoresist material is then deposited and patterned over the entire surface of the semiconductor wafer such that the photoresist material remains only on the edge regions of the semiconductor wafer. The bonding layer in the non-edge region is etched according to the photoresist material such that a top surface of the bonding layer is substantially flat and uniform across the edge region and the non-edge region of the semiconductor wafer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] Semiconductor dies may be bonded to one another at a bonding interface to form a vertically stacked three-dimensional integrated circuit (3DIC) semiconductor device. The semiconductor dies may be bonded to one another using a wafer-to-wafer bonding method, wherein the semiconductor dies are fabricated on separate semiconductor wafers and the semiconductor wafers are bonded to one another in a face-to-face manner. Alternatively, the semiconductor dies may be directly bonded to one another using a die-to-wafer bonding method and / or other bonding methods. Summary of the Invention

[0003] One embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming an electrically insulating layer on a surface of a semiconductor chip, wherein a first portion of the electrically insulating layer is formed on an edge region of the semiconductor chip; forming a barrier layer on the first portion of the electrically insulating layer located on the edge region of the semiconductor chip, wherein the barrier layer comprises a photoresist material; and removing material from a second portion of the electrically insulating layer located on a non-edge region of the semiconductor chip, wherein the barrier layer protects the first portion of the electrically insulating layer when the material is removed from the second portion of the electrically insulating layer.

[0004] Another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: forming a bonding layer on a surface of a first semiconductor wafer, wherein a first portion of the bonding layer is formed on an edge region of the first semiconductor wafer; forming a first portion of a barrier layer on the first portion of the bonding layer located on the edge region of the first semiconductor wafer, wherein the first portion of the barrier layer fills the first portion of the edge region; forming a second portion of the barrier layer on the first portion of the barrier layer, wherein the second portion of the barrier layer fills the second portion of the edge region; after forming the first and second portions of the barrier layer, removing material of the second portion of the bonding layer located on a non-edge region of the first semiconductor wafer, wherein the barrier layer protects the first portion of the bonding layer when the material is removed from the second portion of the bonding layer, and wherein after removing the material from the second portion of the bonding layer, the thickness of the first portion of the bonding layer is greater than the thickness of the second portion of the bonding layer; and after removing the material from the second portion of the bonding layer, bonding the first semiconductor wafer to a second semiconductor wafer using the bonding layer.

[0005] One embodiment of the present disclosure provides a semiconductor device, comprising: a first semiconductor grain; and a second semiconductor grain bonded to the first semiconductor grain at a bonding interface, such that the first semiconductor grain and the second semiconductor grain are vertically arranged in the semiconductor device, wherein the bonding interface comprises: a first bonding layer of the first semiconductor grain directly bonded to a second bonding layer of the second semiconductor grain, wherein at least one of the first bonding layer or the second bonding layer has a non-uniform thickness at the bonding interface, and wherein the first bonding layer and the second bonding layer are fully bonded across the entire bonding interface between opposite edges of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood by reading the accompanying drawings. In accordance with standard industry practice, please note that the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example of a semiconductor device described herein.

[0008] Figure 2 is a schematic diagram of an example of a semiconductor device described herein.

[0009] Figures 3A to 3E is a schematic diagram of an example embodiment of forming a semiconductor die as described herein.

[0010] Figures 4A to 4U is a schematic diagram of an example embodiment of the edge reconstruction process described herein.

[0011] 5A to 5D is a schematic diagram of an example embodiment of forming a semiconductor device as described herein.

[0012] Figures 6A to 6F is a schematic diagram of an example embodiment of the edge reconstruction process described herein.

[0013] Figure 7 is a schematic diagram of an example of a semiconductor device described herein.

[0014] Figure 8 is a schematic diagram of an example of a semiconductor device described herein.

[0015] Figure 9 is a flow chart of an example process described herein related to reconstructing an edge region of a semiconductor wafer.

[0016] Figure 10 is a flow chart of an example process associated with forming a semiconductor device as described herein. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed on or above a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one component or feature's relationship to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0019] At the bonding interface between the first semiconductor wafer and the second semiconductor wafer, a metal-to-metal bond may be formed between a metal structure in a semiconductor grain on the first semiconductor wafer and a metal structure in a semiconductor grain on the second semiconductor wafer. In addition, a dielectric-to-dielectric bond may be formed between bonding layers on each of the first semiconductor wafer and the second semiconductor wafer. In some cases, unevenness on the surface of one or more semiconductor wafers on which semiconductor grains are formed may cause the bonding layer to be only partially bonded on the semiconductor grains. The unevenness may occur at the peripheral edges of one or more semiconductor wafers. The unevenness may include a slope of the surface at the edge of one or more semiconductor wafers, which may be referred to as edge roll-off. The slope of the surface at the edge may cause the semiconductor wafer to not bond at the edge of the semiconductor wafer. In other words, a gap may appear between the edges of the semiconductor wafers, and the gap may cause a weak point in the bonding interface because moisture may enter the bonding interface through the gap, and / or cracking and delamination of the semiconductor wafer may begin from the gap.

[0020] In some embodiments described herein, before a semiconductor wafer is bonded to another semiconductor wafer, the slope in the surface of the semiconductor wafer at the edge region of the semiconductor wafer is filled to minimize or prevent the possibility of a gap being formed between the edges of the semiconductor wafer. In order to fill the slope in the surface of the semiconductor wafer, a thick bonding layer is formed on the surface of the semiconductor wafer so that the top surface of the bonding layer in the edge region is greater than the bottom surface of the bonding layer in the non-edge region of the semiconductor wafer in vertical height. A photoresist material is then deposited on the entire surface of the semiconductor wafer and patterned so that the photoresist material only remains on the edge region of the semiconductor wafer. The photoresist material is used to etch the bonding layer. The bonding layer is formed so that the top surface of the bonding layer in the edge region is greater than the bottom surface of the bonding layer in the non-edge region of the semiconductor wafer in vertical height, which enables the bonding layer in the non-edge region to be etched based on the photoresist material, so that the top surface of the bonding layer is substantially flat and uniform in the edge region and the non-edge region of the semiconductor wafer. In other words, a bonding layer of sufficient thickness is formed in the edge region so that the bonding layer can be thinned in the non-edge region so that after etching the bonding layer, there is almost no or no slope in the edge region. A photoresist material with little etch selectivity relative to the bonding layer may be used so that when the bonding layer is etched, the photoresist material is completely removed, which may prevent contamination of a subsequent planarization operation to planarize the bonding layer.

[0021] Reconstructing the edge region of a semiconductor wafer using a photoresist material may be faster because fewer processing operations are performed (e.g., fewer deposition operations, fewer etching operations, fewer planarization operations) than other edge reconstruction techniques, such as those that include reconstructing the edge region of a semiconductor wafer by depositing multiple layers of the same material as a bonding layer in the edge region on the semiconductor wafer. Additionally and / or alternatively, reconstructing the edge of a semiconductor wafer using a photoresist material may be less expensive than other edge reconstruction techniques because lower cost processing techniques, such as low-complexity wafer edge exposure (WEE) lithographic patterning and development, may be utilized.

[0022] Figure 1 is a schematic diagram of an example of a semiconductor device 100 described herein. Figure 1As shown, semiconductor device 100 is formed by bonding semiconductor wafer 102 and semiconductor wafer 104. For example, a bonding operation can be performed using a bonding tool to bond semiconductor wafer 102 and semiconductor wafer 104 by forming metal-to-metal bonds and / or dielectric-to-dielectric bonds between semiconductor wafer 102 and semiconductor wafer 104. During the bonding operation, semiconductor die 106 on semiconductor wafer 102 is bonded to associated semiconductor die 108 on semiconductor wafer 104 to form semiconductor device 100 (e.g., a stacked semiconductor device). Semiconductor device 100 is then diced and packaged. Other processing steps may be performed to form semiconductor device 100.

[0023] Semiconductor die 106 and semiconductor die 108 may be bonded at a bonding interface 110. Semiconductor device 100 comprises a stacked semiconductor device because semiconductor die 106 and semiconductor die 108 are stacked or vertically arranged along the z-direction in semiconductor device 100. Semiconductor die 106 may comprise a system on chip (SoC) die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application specific integrated circuit (ASIC) die, and / or other types of SoC die. Additionally and / or alternatively, semiconductor die 106 may comprise a memory die, an input / output (I / O) die, a pixel sensor die, and / or other types of semiconductor die. The memory die may include static random access memory (SRAM) die, dynamic random access memory (DRAM) die, NAND die, high bandwidth memory (HBM) die, and / or other types of memory die. The semiconductor die 108 may include the same type of semiconductor die as the semiconductor die 106, or may include a different type of semiconductor die.

[0024] like Figure 1As further shown, semiconductor die 106 may include a device layer 112, and semiconductor die 108 may include a device layer 114. Device layers 112 and 114 may respectively include integrated circuit devices of semiconductor dies 106 and 108. Integrated circuit devices may include transistors, pixel sensors, capacitors, resistors, other active circuit devices, and / or other passive circuit devices, among other examples.

[0025] Semiconductor die 106 may include an interconnect layer 116 above device layer 112. Semiconductor die 108 may include an interconnect layer 118 below device layer 114. Interconnect layers 116 and 118 may each include conductive structures that interconnect the integrated circuit devices of device layers 112 and 114, respectively. Additionally and / or alternatively, interconnect layers 116 and 118 may each include conductive structures to electrically connect semiconductor die 106 and 108.

[0026] Bonding interface 110 may be located between interconnect layers 116 and 118 and may include portions of each of interconnect layers 116 and 118. Bonding interface 110 may include conductive structures in interconnect layers 116 and 118 bonded to each other via metal-to-metal bonds and / or dielectric layers in interconnect layers 116 and 118 bonded to each other via dielectric-to-dielectric bonds.

[0027] As mentioned above, Figure 1 is provided as an example. Other examples may be Figure 1 Different than described.

[0028] Figure 2 is a schematic diagram of an example embodiment 200 of the semiconductor device 100 described herein. Figure 2 1 shows a cross-sectional view of semiconductor device 100 showing details of semiconductor dies 106 and 108. In particular, Figure 2 Further details of device layers 112 and 114 , details of interconnect layers 116 and 118 , and details of bonding interface 110 are shown.

[0029] like Figure 2 As shown, the device layer 112 of the semiconductor die 106 includes a substrate 202. The substrate 202 may correspond to a portion of the semiconductor wafer 102 on which the semiconductor die 106 is formed. The substrate 202 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (e.g., gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. The substrate 202 may extend in the semiconductor die 106 along the x-direction and / or the y-direction.

[0030] The device layer 112 of the semiconductor die 106 includes integrated circuit devices 204 disposed in and / or on a substrate 202. The integrated circuit devices 204 include transistors (e.g., planar transistors, fin field effect transistors (finFETs), gate all around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of passive and / or active integrated circuit devices.

[0031] A dielectric layer 206 of device layer 112 is located above substrate 202. Dielectric layer 206 may include an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. In some embodiments, portions of integrated circuit device 204 are included in dielectric layer 206. For example, gate structures of transistors of integrated circuit device 204 may be included in dielectric layer 206, while source / drain regions and channel regions of the transistors may be included in substrate 202. Additionally and / or alternatively, contacts 208 of integrated circuit device 204 may be included in dielectric layer 206. Contacts 208 may include plugs, vias, pads, and / or other types of electrical contacts. In some embodiments, integrated circuit device 204 includes one or more source / drain contacts and one or more gate contacts. Contacts 208 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti), among other examples. In some embodiments, one or more liner layers are included between the contacts 208 and the dielectric layer 206 to promote adhesion between the contacts 208 and the dielectric layer 206. The liner layers may include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner layers.

[0032] The dielectric layer 206 includes a dielectric material that enables portions of the substrate 202 and / or the integrated circuit device 204 to be selectively etched or prevents etching, and / or electrically isolates the integrated circuit device 204 from the device layer 112. The dielectric layer 206 includes silicon nitride (SixNy), an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 206 may extend in the semiconductor die 106 along the x-direction and / or the y-direction.

[0033] An interconnect layer 116 of the semiconductor die 106 is located above the substrate 202 and above the integrated circuit devices 204. In some embodiments, one or more integrated circuit devices 204 are included in the interconnect layer 116 (e.g., back-end memory devices, back-end resistors, back-end capacitors, radio frequency (RF) switches, optical modulators, waveguides). The interconnect layer 116 includes a plurality of dielectric layers arranged along a direction substantially perpendicular to the substrate 202 (e.g., the z-direction). The dielectric layers may include back-end dielectric layers 210 (e.g., ILD layers, intermetallic dielectric (IMD) layers) and etch stop layers (ESL) 212, which are arranged alternately in the z-direction. The back-end dielectric layers 210 may each include an oxide (e.g., silicon oxide (SiOx) and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorine-containing silicate glass (FSG), and / or other suitable dielectric materials. In some embodiments, back-end dielectric layer 210 includes an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. ESL 212 may each include silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, back-end dielectric layer 210 and ESL 212 include different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in interconnect layer 116. Back-end dielectric layer 210 and ESL 212 may each extend in the x-direction and / or the y-direction within semiconductor die 106.

[0034] Interconnect layer 116 includes a plurality of conductive interconnects in back-end dielectric layer 210 and ESL 212. The conductive interconnects are electrically and / or physically coupled to one or more integrated circuit devices 204 in device layer 112 and / or interconnect layer 116. The conductive interconnects correspond to circuit wiring that enables signals and / or power to be provided to and / or from integrated circuit devices 204. The conductive interconnects may include a combination of conductive structures 214 (e.g., trenches, conductive lines) interconnected by interconnect structures 216 (e.g., vias). Conductive structures 214 and interconnect structures 216 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, among other examples of conductive materials.

[0035] like Figure 2As shown, the conductive interconnects of the interconnect layer 116 can be arranged in a vertical manner (e.g., in the z-direction) to facilitate routing of electrical signals and / or power between device layers 112, between integrated circuit devices 204 through the interconnect layer 116, and / or between the integrated circuit devices 204 and the semiconductor die 108. The conductive interconnects can be arranged in alternating metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer can include one or more conductive structures 214 arranged laterally in the xy plane in the interconnect layer 116, and each via layer can include one or more interconnect structures 216 arranged laterally in the xy plane in the interconnect layer 116. For example, a metal 0 (M0) layer (including one or more conductive structures 214) can be located at the bottom of the interconnect layer 116 and can be coupled to the contacts 208 of the integrated circuit device 204 in the device layer 112, a via 1 (V1) layer (including one or more interconnect structures 216) can be located above the M1 layer in the interconnect layer 116 and coupled to the M1 layer in the interconnect layer 116, a metal 1 layer (M1) layer can be located above the V1 layer in the interconnect structure 216 and coupled to the V1 layer in the interconnect structure 216, a via 2 (V2) layer can be located above the M1 layer in the interconnect layer 116 and coupled to the M1 layer in the interconnect layer 116, a metal 2 layer (M2) layer can be located above the V2 layer in the interconnect layer 116 and electrically coupled to the V2 layer in the interconnect layer 116, and so on. In some embodiments, the interconnect layer 116 includes nine (9) stacked metallization layers (e.g., M0-M8). In some embodiments, the interconnect layer 116 includes another number of stacked metallization layers.

[0036] Interconnect layer 116 includes a top via layer and a top metallization layer. The top via layer is the topmost via layer in interconnect layer 116 and is the via layer closest to bonding interface 110. Similarly, the top metallization layer is the topmost metallization layer in interconnect layer 116 and is the metallization layer closest to bonding interface 110. The top via layer includes an interconnect structure 218 in back-end dielectric layer 210 and / or in ESL 212. Interconnect structure 218 may include a copper (Cu) structure and / or another type of metal structure. A barrier layer 220 may be included between interconnect structure 218 and back-end dielectric layer 210 and / or ESL 212 and may be used to prevent or minimize diffusion of material from interconnect structure 218 (e.g., copper atoms) into the surrounding back-end dielectric layer 210 and / or ESL 212. Examples of barrier layer 220 include tantalum nitride (TaN) and / or titanium nitride (TiN), among other examples. In some embodiments, an adhesion layer 222 is included between the interconnect structure 218 and the barrier layer 220. The adhesion layer 222 may include a material that promotes adhesion between the interconnect structure 218 and the surrounding back-end dielectric layer 210 and / or the surrounding ESL 212. In some embodiments, the adhesion layer 222 includes a copper seed layer. In some embodiments, the adhesion layer 222 includes another type of adhesion material that promotes adhesion of copper to the dielectric material.

[0037] Back-end dielectric layer 224 may be included over back-end dielectric layer 210 and ESL 212 of interconnect layer 116. Back-end dielectric layer 224 may be partially included in bonding interface 110 between semiconductor die 106 and semiconductor die 108. Back-end dielectric layer 224 may include one or more ELK dielectric materials, such as carbon-doped silicon oxide (C-SiO x ), amorphous fluorinated carbon (aC x F y ), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE) and / or silicon oxycarbide (SiOC) polymer. In some embodiments, the ELK dielectric material of the back-end dielectric layer 224 includes porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE) and / or porous silicon oxide (SiO x ) and other examples. Additionally and / or alternatively, the back-end dielectric layer 224 may include silicon oxide (SiO x, such as SiO2), USG, BSG and / or another suitable dielectric material.

[0038] A top metallization layer 226 is included in the back-end dielectric layer 224. The top metallization layer 226 is located above and electrically coupled to the top via layer in the interconnect layer 116. The top metallization layer 226 includes various types of conductive structures 228. One or more conductive structures 228 in the top metallization layer 226 can be coupled to bonding vias 230 in the back-end dielectric layer 224. Each bonding via 230 includes a via structure extending in the z-direction. Each bonding via 230 can be physically and electrically coupled to an associated bonding pad 232. The bonding pad 232 is included on the bonding via 230 so that the bonding pad 232 and the bonding via 230 are physically and electrically coupled. The bonding via 230 and the bonding pad 232 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, among other examples of conductive metals.

[0039] The bonding pad 232 is included in a bonding layer 234 that is located above and / or on the back-end dielectric layer 224. The bonding layer 234 can be included in the bonding interface 110 and can include one or more electrically insulating materials. For example, the bonding layer 234 can include an oxide-containing dielectric material or a nitride-containing material, such as a high-density plasma (HDP) oxide material, a silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. Alternatively, the bonding layer 234 may include an oxide-containing material (e.g., SiO) formed using one or more precursors including an orthosilicate material. x Examples of such orthosilicate materials include esters of orthosilicate acid, such as tetraethyl orthosilicate (TEOS), among others.

[0040] like Figure 2As further shown, semiconductor die 108 may include a similar combination and / or arrangement of structures and / or layers as semiconductor die 106. For example, semiconductor die 108 may include a combination of substrate 236, integrated circuit devices 238, dielectric layer 240, and contacts 242 in device layer 114 of semiconductor die 108 (similar to device layer 112 of semiconductor die 106). As another example, semiconductor die 108 may include a combination of back-end dielectric layer 244, ESL 246, conductive structures 248, and interconnect structures 250 in interconnect layer 118 of semiconductor die 108 (similar to interconnect layer 116 of semiconductor die 106). These layers and / or structures may have opposite z-direction arrangements relative to semiconductor die 106, which enables semiconductor die 106 and semiconductor die 108 to be bonded at bonding interface 110, such that interconnect layer 116 and interconnect layer 118 face each other.

[0041] In addition, the interconnect layer 118 includes a top via layer and a top metallization layer. The top via layer is the topmost via layer in the interconnect layer 118 and is the via layer closest to the bonding interface 110. Similarly, the top metallization layer is the topmost metallization layer in the interconnect layer 118 and is the metallization layer closest to the bonding interface 110. The top via layer includes an interconnect structure 252 in the back-end dielectric layer 244 and / or in the ESL 246. The interconnect structure 252 may include a copper (Cu) structure and / or another type of metal structure. A barrier layer 254 and / or an adhesion layer 256 may be included between the interconnect structure 252 and the back-end dielectric layer 244 and / or the ESL 246.

[0042] Back-end dielectric layer 258 may be included above (or below) back-end dielectric layer 244 and ESL 246 of interconnect layer 118. Back-end dielectric layer 258 may be partially included in bonding interface 110 between semiconductor die 106 and semiconductor die 108. Back-end dielectric layer 258 may include a similar material to back-end dielectric layer 224 and / or may include a different material.

[0043] A top metallization layer 260 is included in the back-end dielectric layer 258. The top metallization layer 260 is located below one or more interconnect structures 252 in the interconnect layer 118 and can be electrically coupled thereto. The top metallization layer 260 includes various types of conductive structures 262. One or more conductive structures 262 in the top metallization layer 260 can be coupled to bonding vias 266 in the back-end dielectric layer 258. Each bonding via 266 includes a via structure extending in the z-direction. Each bonding via 266 can be physically and electrically coupled to an associated bonding pad 268. The bonding pad 268 is included on the bonding via 266 so that the bonding pad 268 and the bonding via 266 are physically and electrically coupled. The bonding via 266 and the bonding pad 268 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, among other examples of conductive metals.

[0044] Bonding pad 268 is included in a bonding layer 270 below back-end dielectric layer 258. Bonding layer 270 may be included in bonding interface 110 and may include one or more electrically insulating materials. For example, bonding layer 270 may include an oxide-containing dielectric material or a nitride-containing material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials.

[0045] At the bonding interface 110 , the bonding pad 232 of the semiconductor die 106 and the bonding pad 268 of the semiconductor die 108 are directly bonded via a metal-to-metal bond. Furthermore, the bonding layer 234 of the semiconductor die 106 and the bonding layer 270 of the semiconductor die 108 are directly bonded via a dielectric-to-dielectric bond or an insulator-to-insulator bond.

[0046] As mentioned above, Figure 2 is provided as an example. Other examples may be Figure 2 Different from what is described.

[0047] Figures 3A to 3E is a schematic diagram of an example embodiment 300 of forming a semiconductor die 106 as described herein. In some embodiments, one or more semiconductor processing tools may be used to perform Figures 3A to 3E One or more semiconductor processing operations described in example embodiment 300 for forming semiconductor die 106 may also be used to form semiconductor die 108, such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, and / or wafer / die transfer tools, among other examples. In some embodiments, one or more operations and / or techniques described in example embodiment 300 for forming semiconductor die 106 may also be used to form semiconductor die 108.

[0048] Go to Figure 3A, a substrate 202 may be provided. The substrate 202 may be provided in the form of a semiconductor wafer (eg, semiconductor wafer 102 ), such as a silicon (Si) wafer. The semiconductor die 106 may be formed on the substrate 202 along with a plurality of other semiconductor dies 106 .

[0049] like Figure 3B As shown, integrated circuit device 204 can be formed in and / or on substrate 202 in device layer 112 of semiconductor die 106. One or more portions of integrated circuit device 204 can be formed using one or more semiconductor processing tools. For example, a deposition tool can be used to perform various deposition operations to deposit layers of integrated circuit device 204 and / or deposit a photoresist layer for etching portions of substrate 202 and / or deposited layers. As another example, an exposure tool can be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a development tool can be used to develop the pattern in the photoresist layer. As another example, an etching tool can be used to etch portions of substrate 202 and / or deposited layers to form integrated circuit device 204. As another example, a planarization tool can be used to planarize portions of integrated circuit device 204. As another example, an ion implantation tool can be used to implant ions into substrate 202 to dope portions of substrate 202 with one or more types of dopants (e.g., p-type dopants, n-type dopants).

[0050] like Figure 3C As shown, a dielectric layer 206 is deposited on and / or over substrate 202 and on and / or over integrated circuit device 204 using a deposition tool. A patterned mask layer (e.g., a patterned photoresist layer, a patterned hard mask layer) can be formed on dielectric layer 206 using a deposition tool, an exposure tool, and a development tool. A recess can be formed in dielectric layer 206 using an etching tool, and a contact 208 can be formed in the recess using a deposition tool, such that contact 208 is physically and / or electrically coupled to integrated circuit device 204.

[0051] like Figure 3D As shown, a first portion of interconnect layer 116 is formed over device layer 112. Forming the first portion of interconnect layer 116 may include a plurality of alternating layers forming back-end dielectric layer 210 and ESL 212, and alternating layers forming conductive structures 214 and interconnect structures 216.

[0052] The first portion of the interconnect layer 116 can be fabricated in a series of successive layers. For example, a deposition tool can be used to deposit the ESL 212 and the back-end dielectric layer 210, respectively, using physical vapor deposition (PVD) techniques, atomic layer deposition (ALD) techniques, chemical vapor deposition (CVD) techniques, oxidation techniques, and / or other deposition techniques. In some embodiments, a planarization tool is used to planarize the ESL 212 and / or the back-end dielectric layer 210. Recesses can be formed in and / or through the ESL 212 and the back-end dielectric layer 210, and a deposition tool can be used to deposit the interconnect structure 216 and the conductive structure 214 in each recess. The previous set of operations can be repeated for each subsequent layer of the first portion of the interconnect layer 116. In some embodiments, a dual damascene process is used to form the layers of the first portion of the interconnect layer 116.

[0053] like Figure 3D As further shown, another ESL 212 is formed, and a back-end dielectric layer 224 is formed on the ESL 212. Each of the ESL 212 and the back-end dielectric layer 224 can be deposited using a deposition tool using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and / or other types of deposition techniques. In some embodiments, a planarization tool is used to planarize the top surface of the back-end dielectric layer 224.

[0054] Interconnect structures 218 and associated barrier layers 220 and adhesion layers 222 are formed over one or more conductive structures 214, and conductive structures 228 of top metallization layer 226 can be formed in and / or through back-end dielectric layer 224. In some embodiments, dual damascene recesses are formed through back-end dielectric layer 224 and underlying ESL 212, and into the topmost back-end dielectric layer 210. The top surface of one or more topmost conductive structures 214 in interconnect layer 116 is exposed through the one or more recesses. A photoresist layer can be formed over back-end dielectric layer 224 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through back-end dielectric layer 224 and underlying ESL 212, and into the topmost back-end dielectric layer 210 to form recesses. In some embodiments, the photoresist removal tool removes remaining portions of the photoresist layer (eg, using chemical strippers and / or other techniques).

[0055] A deposition tool may be used to conformally deposit barrier layer 220 and / or adhesion layer 222. Barrier layer 220 and / or adhesion layer 222 may be conformally deposited using a conformal deposition technique, such as ALD. Alternatively, barrier layer 220 and / or adhesion layer 222 may be deposited using CVD techniques and / or other suitable deposition techniques. Interconnect structure 218 and conductive structure 228 may be deposited in the recess using a deposition tool. Interconnect structure 218 and conductive structure 228 may be deposited using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, and / or other suitable deposition techniques. In some embodiments, after depositing conductive structure 228, a planarization tool may be used to perform a chemical mechanical planarization (CMP) operation or another type of planarization operation to planarize conductive structure 228.

[0056] like Figure 3E As shown, additional material for the back-end dielectric layer 224 may be deposited. The additional material for the back-end dielectric layer 224 may be deposited using a deposition tool using CVD techniques, PVD techniques, ALD techniques, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, after depositing the additional material for the back-end dielectric layer 224, a planarization tool may be used to planarize the back-end dielectric layer 224.

[0057] Bonding vias 230 may be formed in back-end dielectric layer 224. In some embodiments, one or more bonding vias 230 are formed on conductive structures 228. To form bonding vias 230, recesses may be formed in back-end dielectric layer 224 (e.g., above one or more conductive structures 228). The recesses may extend through back-end dielectric layer 224 to conductive structures 228, such that top surfaces of conductive structures 228 are exposed through the recesses in back-end dielectric layer 224. In some embodiments, overetching may occur to ensure that back-end dielectric layer 224 is completely etched through to the top surfaces of conductive structures 228. In these embodiments, some etching may occur on the top surfaces of conductive structures 228.

[0058] In some embodiments, the back-end dielectric layer 224 is etched using a pattern in the photoresist layer to form a groove. In these embodiments, a deposition tool can be used to form a photoresist layer on the back-end dielectric layer 224. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the back-end dielectric layer 224 according to the pattern to remove portions of the back-end dielectric layer 224. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (for example, using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to etching the back-end dielectric layer 224 based on a pattern.

[0059] The bonding via 230 is then deposited in the recess. The bonding via 230 can be deposited using a deposition tool using CVD technology, PVD technology, ALD technology, electroplating technology, and / or other suitable deposition technology. In some embodiments, after depositing the bonding via 230, a planarization tool is used to planarize the bonding via 230 so that the top surface of the bonding via 230 is substantially coplanar with the top surface of the back-end dielectric layer 224.

[0060] like Figure 3E As further shown, a bonding layer 234 is formed on the back-end dielectric layer 224. The bonding layer 234 may also be formed on the bonding vias 230. The bonding layer 234 may be deposited using a deposition tool using CVD techniques, PVD techniques, ALD techniques, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, after depositing the bonding layer 234, a planarization tool is used to planarize the bonding layer 234.

[0061] The bonding pad 232 may be formed on the bonding through-hole 230 such that the bonding pad 232 extends through the bonding layer 234. To form the bonding pad 232, a groove is formed in the bonding layer 234 above the bonding through-hole 230. The groove may extend through the bonding layer 234 to the bonding through-hole 230 such that the top surface of the bonding through-hole 230 is exposed through the groove in the bonding layer 234.

[0062] In some embodiments, the bonding layer 234 is etched using a pattern in the photoresist layer to form a groove. In these embodiments, a deposition tool can be used to form a photoresist layer on the bonding layer 234. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the bonding layer 234 according to the pattern to remove portions of the bonding layer 234 above the bonding through-hole 230, thereby forming a groove. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for etching the bonding layer 234 based on a pattern.

[0063] Bond pads 232 are then deposited over bonding vias 230 in the recesses. Bond pads 232 may be deposited using a deposition tool using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. In some embodiments, after depositing bond pads 232, a planarization tool is used to planarize bond pads 232 such that the top surface of bond pads 232 is substantially coplanar with the top surface of bonding layer 234.

[0064] As mentioned above, Figures 3A to 3E is provided as an example. Other examples may be Figures 3A to 3E Different than described.

[0065] Figures 4A to 4U FIG2 is a schematic diagram of an example embodiment 400 of an edge reconstruction process described herein. The edge reconstruction process can be used to reconstruct an edge region of a semiconductor wafer. Although example embodiment 400 is illustrated and described with respect to semiconductor wafer 102, the process technique of example embodiment 400 can be used to reconstruct the edge of semiconductor wafer 104. Alternatively, the process technique of example embodiment 400 can be used to reconstruct the edges of individual semiconductor dies 106 and / or individual semiconductor dies 108 for die-to-wafer bonding or die-to-die bonding.

[0066] Go to Figure 4A and Figure 4B , semiconductor grains 106 may be formed on semiconductor wafer 102. In some embodiments, Figures 3A to 3D and / or by performing the techniques described in Figures 3A to 3D The one or more semiconductor dies 106 may be formed by performing the operations described in

[0044] In some embodiments, the one or more semiconductor dies 106 may be formed using other techniques and / or by performing other operations. Figures 4A to 4U The operations described in can be used as Figure 3E 106 is performed as part of the operations described in order to form a bonding layer 234 of the semiconductor die 106 on the semiconductor wafer 102 .

[0067] Figure 4A A top view of a semiconductor wafer 102 and associated semiconductor dies 106 is shown. Figure 4B Shown along Figure 4A 1. The cross-sectional view of the semiconductor wafer 102 is taken along line AA in FIG. The cross-sectional view includes an edge region 402 and a non-edge region 404 around the periphery of the semiconductor wafer 102. The non-edge region 404 is a portion of the semiconductor wafer 102 between the edge region 402 and the center of the semiconductor wafer 102. In the example embodiment 400, the semiconductor grains 106 may be formed in the non-edge region 404 of the semiconductor wafer 102. The example embodiment 600, as Figures 6A to 6F As shown and described, including an example, at least a portion of one or more semiconductor die 106 (referred to as edge die) is formed in an edge region 402 of the semiconductor wafer 102 .

[0068] like Figure 4B As shown, the edge region 402 of the semiconductor wafer 102 may have an inclined top surface, such that there is a height difference (in degrees) between the top surface of the semiconductor wafer 102 in the edge region 402 and the top surface of the semiconductor wafer 102 in the non-edge region 404. Figure 4B 1). This is referred to as edge roll-off. Edge roll-off may occur in edge region 402 of semiconductor wafer 102 due to beveling of the edge of semiconductor wafer 102, variations in planarization operations performed on semiconductor wafer 102, uniformity control of semiconductor processes performed on semiconductor wafer 102, and / or other reasons.

[0069] like Figure 4C and Figure 4D As shown, a thick layer of electrically insulating material is deposited over the top surface of the semiconductor wafer 102 to form a bonding layer 234 on the semiconductor wafer 102 . Figure 4C A top view of the bonding layer 234 on the semiconductor wafer 102 is shown. Figure 4D Shown along Figure 4D A cross-sectional view of the bonding layer 234 taken along line AA.

[0070] like Figure 4C As shown, the bonding layer 234 is formed on the entire semiconductor wafer 102. Figure 4DAs shown, in some embodiments, another dielectric layer 406 is formed on semiconductor wafer 102, and bonding layer 234 is formed on dielectric layer 406. In some embodiments, dielectric layer 406 is included to provide etch selectivity relative to bonding layer 234 so that bonding layer 234 can be etched to form a recess in which bonding pad 232 is formed.

[0071] The electrically insulating material of the bonding layer 234 may include an oxide-containing material, such as silicon oxide (SiO x , such as SiO 2 ). Additionally and / or alternatively, the electrically insulating material may include another type of dielectric material, such as a nitride-containing dielectric material and / or a carbon-containing dielectric material, among other examples.

[0072] The bonding layer 234 can be deposited as a "thick" layer in that the bonding layer 234 can be deposited to a thickness in the micrometer range (in the Figure 4D Dimension D2 is shown in FIG. 2 . For example, the bonding layer 234 can be deposited to a thickness in a range of about 8 microns to about 10 microns in a single deposition operation. This allows the bonding layer 234 to be quickly formed to a certain thickness (dimension D2) such that the top surface of the bonding layer 234 in the edge region 402 of the semiconductor wafer 102 has a greater vertical (z-direction) height on the semiconductor wafer 102 than the bottom surface of the bonding layer 234 in the non-edge region 404 of the semiconductor wafer 102 by a distance (in the z-direction) from the bottom surface. Figure 4D 10). This ensures that sufficient bonding layer 234 material is deposited in edge region 402 to allow the inclined surface of semiconductor wafer 102 in the edge region to be completely filled with bonding layer 234, while allowing bonding layer 234 to be subsequently etched back to a sufficient thickness in non-edge region 404 to bond with semiconductor wafer 104. In some embodiments, bonding layer 234 is formed to a thickness (dimension D2) such that dimension D3 is within a range of approximately 3 microns to approximately 5 microns. However, other values and / or ranges for dimensions D2 and D3 are within the scope of the present disclosure.

[0073] In order to quickly form a sufficient thickness of the bonding layer 234, the bonding layer 234 can be deposited using a TEOS-CVD deposition technique. This can include using one or more silicon oxide precursors containing orthosilicate materials (e.g., TEOS and / or another ester of orthosilicic acid) to deposit the bonding layer 234. Using the TEOS-CVD deposition technique can form the bonding layer 234 to a sufficient thickness (dimension D2) in a single deposition operation, rather than using multiple deposition operations to form the bonding layer 234 using another deposition technique (e.g., HDP-CVD). While this can reduce the processing time, cost, and complexity of forming the bonding layer 234, other techniques for forming the bonding layer 234 (e.g., HPD-CVD) are within the scope of the present disclosure.

[0074] The TEOS-CVD deposition technique may include providing a silicon oxide precursor onto the top surface of the semiconductor wafer 102 using a deposition tool (e.g., a CVD tool) and forming silicon oxide from the silicon oxide precursor by thermal decomposition at a relatively low temperature (e.g., about 400 degrees Celsius to about 600 degrees Celsius). For example, TEOS vapor is deposited onto the top surface of the semiconductor wafer such that the TEOS is adsorbed onto the top surface of the semiconductor wafer. An oxidant, such as oxygen (O2), ozone (O3), and / or water (H2O), is introduced and used to thermally decompose the TEOS to release silicon oxide (SiO2) and related byproducts. Example thermal decompositions may include:

[0075] Si(OC2H5)4+O2→SiO2+CO2+H2O+2C2H4.

[0076] Wherein TEOS (Si(OC2H5)) is decomposed by oxygen (O2) into silicon oxide (SiO2) and byproducts such as carbon dioxide (CO2), water (H2O) and / or ethylene (C2H4). Another example thermal decomposition may include:

[0077] Si(OC2H5)4+H2O→SiO2+4C2H5OH,

[0078] TEOS (Si(OC2H5)) is decomposed by water (H2O) into silicon oxide (SiO2) and byproducts such as ethanol (C2H5OH).

[0079] like Figure 4E and Figure 4F As shown, a photoresist layer 408 is formed over the bonding layer 234 in the edge region 402 and in the non-edge region 404. In other words, the photoresist layer 408 is coated on the top surface of the semiconductor wafer 102. Figure 4E A top view of a photoresist layer 408 on the semiconductor wafer 102 is shown. Figure 4F Shown Figure 4E FIG. 4 is a cross-sectional view of the photoresist layer 408 along line AA.

[0080] The photoresist layer 408 may be deposited using a deposition tool using a spin coating technique and / or other suitable deposition techniques. Figure 4FAs shown, a portion of the photoresist layer 408 in the edge region 402 of the semiconductor wafer 102 is exposed to light or another type of electromagnetic radiation to pattern the photoresist layer 408. The photoresist layer 408 may include a negative photoresist material that crosslinks and becomes insoluble in a developer when exposed to light. Thus, the portion of the photoresist layer 408 in the edge region 402 of the semiconductor wafer 102 is exposed to light so that the portion of the photoresist layer 408 remains in the edge region 402 of the semiconductor wafer 102 after development. Examples of negative photoresist materials that can be used for the photoresist layer 408 include epoxy-type photoresist materials, such as SU-8, NR9-8000PY, and / or S1813, among other examples.

[0081] Using a negative photoresist material as the photoresist layer 408 enables a wafer edge exposure (WEE) lithography patterning tool to be used to expose portions of the photoresist layer 408 in the edge region 402 of the semiconductor wafer 102. However, in other embodiments, a positive photoresist material may be used and portions of the photoresist layer 408 in the non-edge region 404 of the semiconductor wafer 102 may be exposed to light to pattern the photoresist layer 408.

[0082] like Figure 4G and Figure 4H As shown, a developing tool may be used to remove portions of the photoresist layer 408 in the non-edge region 404 of the semiconductor wafer 102, such that portions of the photoresist layer 408 in the edge region 402 remain on the semiconductor wafer 102. The portions of the photoresist layer 408 remaining in the edge region 402 on the semiconductor wafer 102 correspond to portions 410a of the barrier layer 410 formed in the edge region 402 of the semiconductor wafer 102. Figure 4G A top view of a barrier layer 410 on a semiconductor wafer 102 is shown. Figure 4H Shown Figure 4G FIG. 4 is a cross-sectional view of the barrier layer 410 along line AA.

[0083] like Figure 4G As shown, the barrier layer 410 extends around the periphery of the semiconductor wafer 102 in the edge region 402 of the semiconductor wafer 102. Figure 4H As shown, portion 410 a of barrier layer 410 fills a portion of edge region 402 of semiconductor wafer 102 in both the lateral direction (x-direction) and the longitudinal direction (z-direction).

[0084] like Figure 4I and Figure 4J As shown, another photoresist layer 412 can be formed over the bonding layer 234 in the edge region 402 and the non-edge region 404. In other words, the photoresist layer 412 is coated on the top surface of the semiconductor wafer 102. Figure 4I A top view of a photoresist layer 412 on the semiconductor wafer 102 is shown. Figure 4J Shown Figure 4I FIG. 4 is a cross-sectional view of the photoresist layer 412 along line AA.

[0085] The photoresist layer 412 may be deposited using a deposition tool using a spin coating technique and / or other suitable deposition techniques. Figure 4J As shown, the photoresist layer 412 covers the portion 410 a of the barrier layer 410 . In other words, the photoresist layer 412 is formed on the portion 410 a of the barrier layer 410 in the edge region 402 of the semiconductor wafer 102 .

[0086] like Figure 4J As further shown, the part of the photoresist layer 412 in the edge area 402 of semiconductor wafer 102 is exposed to light or another type of electromagnetic radiation, so that photoresist layer 412 is patterned. Photoresist layer 412 can include a negative photoresist material, which can crosslink and become insoluble in developer when exposed to light. Therefore, the part of the photoresist layer 412 in the edge area 402 of semiconductor wafer 102 is exposed to light so that the part of photoresist layer 412 can remain in the edge area 402 of semiconductor wafer 102 after development. Using negative photoresist material as photoresist layer 412, WEE photolithography patterning tool can be used to expose the part of the photoresist layer 412 in the edge area 402 of semiconductor wafer 102. However, in other embodiments, positive photoresist material can be used, and the part of the photoresist layer 412 in the non-edge area 404 of semiconductor wafer 102 is exposed to light, so that photoresist layer 412 is patterned.

[0087] like Figure 4K and Figure 4L As shown, a developing tool may be used to remove a portion of the photoresist layer 412 in the non-edge region 404 of the semiconductor wafer 102, such that a portion of the photoresist layer 412 in the edge region 402 remains on the semiconductor wafer 102. The portion of the photoresist layer 412 in the edge region 402 that remains on the semiconductor wafer 102 corresponds to another portion 410 b of the barrier layer 410 formed in the edge region 402 of the semiconductor wafer 102. Figure 4K A top view of a barrier layer 410 on a semiconductor wafer 102 is shown. Figure 4L Shown Figure 4G FIG. 4 is a cross-sectional view of the barrier layer 410 along line AA.

[0088] like Figure 4KAs shown, forming portion 410b of barrier layer 410 results in barrier layer 410 occupying a larger lateral area in edge region 402 of the peripheral periphery of semiconductor wafer 102 than the lateral area occupied before portion 410b was formed. Figure 4L As shown, portion 410b of barrier layer 410 fills a portion of edge region 402 of semiconductor wafer 102 in both the lateral (x-direction) and longitudinal (z-direction) directions. Portion 410b is formed on portion 410a of barrier layer 410 and covers a larger lateral (x-direction) area of edge region 402 than portion 410a.

[0089] like Figure 4M and Figure 4N As shown, another photoresist layer 414 can be formed over the bonding layer 234 in the edge region 402 and in the non-edge region 404. In other words, the photoresist layer 414 coats the top surface of the semiconductor wafer 102. Figure 4M A top view of a photoresist layer 414 on the semiconductor wafer 102 is shown. Figure 4N Shown Figure 4M FIG. 4 is a cross-sectional view of the photoresist layer 414 along line AA.

[0090] The photoresist layer 414 may be deposited using a deposition tool using a spin coating technique and / or other suitable deposition techniques. Figure 4N As shown, photoresist layer 414 covers portions 410a and 410b of barrier layer 410. In other words, photoresist layer 414 is formed over and / or on portions 410a and 410b of barrier layer 410 in edge region 402 of semiconductor wafer 102.

[0091] like Figure 4N As further shown, the part of the photoresist layer 414 in the edge area 402 of semiconductor wafer 102 is exposed to light or another type of electromagnetic radiation with patterned photoresist layer 414. Photoresist layer 414 can include a negative photoresist material, which crosslinks and becomes insoluble in developer when exposed to light. Therefore, the part of the photoresist layer 414 in the edge area 402 of semiconductor wafer 102 is exposed to light so that the part of photoresist layer 414 can remain in the edge area 402 of semiconductor wafer 102 after development. Using negative photoresist material for photoresist layer 414, it is possible to make WEE photolithography patterning tool be used to expose the part of the photoresist layer 414 in the edge area 402 of semiconductor wafer 102. However, in other embodiments, a positive photoresist material can be used, and the part of the photoresist layer 414 in the non-edge area 404 of semiconductor wafer 102 is exposed to light with patterned photoresist layer 414.

[0092] like Figure 4O and Figure 4PAs shown, a developing tool may be used to remove portions of the photoresist layer 414 in the non-edge region 404 of the semiconductor wafer 102, such that portions of the photoresist layer 414 remain in the edge region 402 of the semiconductor wafer 102. The portion of the photoresist layer 414 remaining in the edge region 402 of the semiconductor wafer 102 corresponds to another portion 410 c of the barrier layer 410 formed in the edge region 402 of the semiconductor wafer 102. Figure 4O A top view of a barrier layer 410 on a semiconductor wafer 102 is shown. Figure 4P Shown Figure 4O FIG. 4 is a cross-sectional view of the barrier layer 410 along line AA.

[0093] like Figure 4O As shown, the formation of portion 410c of barrier layer 410 results in barrier layer 410 occupying substantially the entire lateral area of edge region 402 at the peripheral edge of semiconductor wafer 102. Figure 4P As shown, portion 410c of barrier layer 410 fills a portion of edge region 402 of semiconductor wafer 102 in both the lateral (x-direction) and longitudinal (z-direction) directions. Portion 410c is formed on portion 410b of barrier layer 410 and covers a larger lateral (x-direction) area of edge region 402 than each of portions 410a and 410b.

[0094] Figure 4Q Detailed cross-sectional view of barrier layer 410 is shown. Figure 4Q As shown, each portion 410a to 410c of the barrier layer 410 may have a z-direction thickness and an x-direction width. For example, portion 410a may have a z-direction thickness ( Figure 4Q Dimension D5) and x-width ( Figure 4Q Dimension D6 in the figure), portion 410b may have a z-direction thickness ( Figure 4Q Dimension D7) and x-width ( Figure 4Q Dimension D8 in the figure), portion 410c may have a z-direction thickness ( Figure 4Q Dimension D9) and x-width ( Figure 4Q Dimension D10 in ), and so on.

[0095] In some embodiments, the z-direction thickness (e.g., dimensions D5, D7, and D9) of each of portions 410a to 410c can be approximately the same thickness (e.g., within a range of approximately 5%, within a range of approximately 10%). In some embodiments, the z-direction thickness (e.g., two or more of dimensions D5, D7, and D9) of two or more portions 410a to 410c can be different thicknesses.

[0096] The combination of the z-direction thicknesses of each of the portions 410a to 410c (e.g., dimensions D5, D7, and D9) can result in the barrier layer 410 having an overall z-direction thickness such that the z-direction height of the top surface of the barrier layer 410 in the semiconductor wafer 102 is approximately the same as the z-direction height of the top surface of the bonding layer 234. Alternatively, the top surface of the barrier layer 410 can be a distance (in the region of 0.05 mm) above the top surface of the bonding layer 234 in the non-edge region 404. Figure 4Q This can increase the likelihood that, in a subsequent etch-back operation, barrier layer 410 will not be completely consumed before etching of bonding layer 234 is completed in the etch-back operation.

[0097] The x-direction width (e.g., dimensions D6, D8, and D10) of each of portions 410a through 410c can be based on the x-direction cross-sectional profile of edge region 402 of semiconductor wafer 102, as each of portions 410a through 410c conforms to the x-direction cross-sectional profile of edge region 402. However, in embodiments where the top surface of bonding layer 234 slopes downward toward the outer edge of semiconductor wafer 102 due to edge roll-off in edge region 402, the x-direction width of the portion at the top of barrier layer 410 can be greater than the x-direction width of the portion at the bottom of barrier layer 410. For example, the x-direction width (e.g., dimension D8) of portion 410b can be greater than the x-direction width (e.g., dimension D6) of portion 410a, and the x-direction width (e.g., dimension D10) of portion 410c can be greater than the x-direction width (e.g., dimension D8) of portion 410b.

[0098] The example number of portions 410a-410c of barrier layer 410, and the associated sizes of portions 410a-410c are examples, and the scope of this disclosure includes other numbers of portions and associated sizes of those portions. Figures 4E to 4P The related sequence of operations can be expanded to include a greater number of sections (e.g., 4 sections, 6 sections, 10 sections) for forming the barrier layer 410. As another example, Figures 4E to 4P The sequence of operations involved can be reduced to two parts including the barrier layer 410. In some embodiments, only the operations related to Figures 4E to 4H Related operations are performed to form the barrier layer 410 (eg, a single portion of the barrier layer 410 ) from the photoresist layer 408 .

[0099] In some embodiments, the number of portions included in the barrier layer 410 is based on the amount of edge roll-off (dimension D1) in the edge region 402 of the semiconductor wafer 102. For example, for a larger amount of edge roll-off, a greater number of portions may be formed for the barrier layer 410, while for a smaller amount of edge roll-off, a smaller number of portions may be formed for the barrier layer 410. This is to ensure that each portion formed is fully exposed and cross-linked, and to reduce the likelihood of portions of the barrier layer 410 being underexposed.

[0100] In some embodiments, the number of sections included in barrier layer 410 is based on the capabilities of an exposure tool (e.g., a WEE tool) used to pattern the photoresist layer from which the sections of barrier layer 410 are formed. For example, if the exposure tool is capable of exposing and patterning thicker photoresist layers, barrier layer 410 may be formed using a smaller number of sections for the same amount of edge rolloff than if another exposure tool is used that is capable of exposing and patterning thinner photoresist layers.

[0101] In some embodiments, the number of portions included in the barrier layer 410 is based on the Figure 4R The type of etchant used to etch the bonding layer 234 in the aforementioned etch-back operation. When etching the bonding layer 234 using an etchant that etches the barrier layer 410 at a greater rate than the etch rate of the bonding layer 234, the barrier layer 410 may form a greater number of portions to form a barrier layer 410 having a greater overall z-direction thickness. Conversely, when etching the bonding layer 234 using an etchant that etches the bonding layer 234 at a greater rate than the etch rate of the barrier layer 410, the barrier layer 410 may form a smaller number of portions to form a barrier layer 410 having a smaller overall z-direction thickness.

[0102] like Figure 4R As shown, an etch-back operation is performed based on the barrier layer 410 to etch the bonding layer 234. The etch-back operation can be performed using an etching tool to thin the bonding layer 234 (e.g., reduce the thickness of the bonding layer 234). The etch-back operation can include using a dry etching technique (e.g., a plasma-based etching technique, a gas-based etching technique), a wet etching technique (e.g., a chemical etching technique), and / or other types of etching techniques.

[0103] like Figure 4RAs shown, during the etch-back operation, when etching the bonding layer 234, the barrier layer 410 is consumed. The etchant used has low selectivity to no selectivity between the material of the bonding layer 234 (e.g., silicon dioxide (SiO2)) and the material of the barrier layer 410 (e.g., epoxy-based material). Therefore, the material removed from the barrier layer 410 has an etching rate similar to that of the material of the bonding layer 234. When the etch-back operation is completed, the barrier layer 410 is completely removed from the edge region 402 of the semiconductor wafer 102. This can prevent, minimize and / or reduce the possibility of cross contamination of materials on the semiconductor wafer 102 when flattening the bonding layer 234 in a subsequent flattening operation. Once the barrier layer 410 is completely removed from the edge region 402 of the semiconductor wafer 102, the etch-back operation can be stopped. Alternatively, after the barrier layer 410 is completely removed from the edge region 402 of the semiconductor wafer 102, the etch-back operation can continue to ensure that the barrier layer 410 is completely removed. In these embodiments, a portion of the bonding layer 234 in the edge region 402 is also removed from the semiconductor wafer 102. For example, if the barrier layer has a thickness of approximately 8 microns, an etch-back operation may be performed to remove approximately 8.5 microns of material from the edge region 402 of the semiconductor wafer 102. However, other values are also within the scope of the present disclosure.

[0104] In other embodiments, a portion of the barrier layer 410 may remain on the semiconductor wafer 102 in the edge region, and another technique, such as ashing or chemical stripping, may be used to remove the remaining portion of the barrier layer 410 .

[0105] like Figure 4R As further shown, upon completion of the etch-back operation, the top surface of the bonding layer 234 in the edge region 402 of the semiconductor wafer 102 and the top surface of the bonding layer 234 in the non-edge region 404 of the semiconductor wafer 102 may be substantially coplanar. Alternatively, the top surface of the bonding layer 234 in the edge region 402 of the semiconductor wafer 102 may be located at a higher vertical position (e.g., a higher z-direction height) in the semiconductor wafer 102 than the top surface of the bonding layer 234 in the non-edge region 404 of the semiconductor wafer 102. This may be due to the barrier layer 410 being formed such that the top surface of the barrier layer 410 extends above the top surface of the bonding layer 234 in the non-edge region 404 by a distance (dimension D11), as shown in FIG. Figure 4Q As stated.

[0106] like Figure 4S and Figure 4T As shown, after the etch-back operation, a planarization operation (eg, a CMP operation) may be performed using a planarization tool to planarize the top surface of the bonding layer 234 . Figure 4S A top view of the bonding layer 234 after the planarization operation is shown. Figure 4T Shown Figure 4S FIG. 2 is a cross-sectional view of the bonding layer 234 along line AA. Figure 4T As shown, after the planarization operation, the top surface of the bonding layer 234 in the edge region 402 of the semiconductor wafer 102 and the top surface of the bonding layer 234 in the non-edge region 404 of the semiconductor wafer 102 can be substantially coplanar. Performing the planarization operation can reduce variations in the thickness of the bonding layer 234 across the non-edge region 404 of the semiconductor wafer 102.

[0107] like Figure 4U As shown, the bonding layer 234 in the non-edge region 404 of the semiconductor wafer 102 may have a thickness (in Figure 4U 12), which is less than the thickness of the bonding layer 234 in the edge region 402 of the semiconductor wafer 102 after the planarization operation (in FIG. Figure 4U The difference in thickness of the bonding layer 234 in the edge region 402 and the non-edge region 404 is due to the Figure 4R During the etching back operation, the barrier layer 410 protects the bonding layer 234 in the edge region 402. The bonding layer 234 in the edge region 402 has a greater thickness than the bonding layer 234 in the non-edge region 404 because the bonding layer 234 fills the slope (e.g., edge roll-off) in the edge region 402 of the semiconductor wafer 102.

[0108] In some embodiments, after the planarization operation, a small amount of slope or edge roll-off may still exist in the edge region 402 (at Figure 4U 14). However, a small amount of slope or edge roll-off may have minimal impact on the bonding performance of semiconductor wafer 102 to semiconductor wafer 104. In some embodiments, the amount of remaining slope or edge roll-off is less than the thickness of bonding layer 234 in non-edge region 404 after the planarization operation.

[0109] As mentioned above, Figures 4A to 4U is provided as an example. Other examples may be Figures 4A to 4U Different from what is described.

[0110] 5A to 5D is a schematic diagram of an example embodiment 500 of forming the semiconductor device 100 described herein. In particular, the example embodiment 500 includes an example of bonding the semiconductor die 106 and the semiconductor die 108 to form the semiconductor device 100.

[0111] like Figure 5A As shown, the semiconductor wafer 102 and the semiconductor wafer 104 may be arranged such that the bonding layer 234 on the semiconductor wafer 102 and the bonding layer 270 on the semiconductor wafer 104 face each other. Figure 5A As further shown, the semiconductor wafer 102 and the semiconductor wafer 104 may be arranged such that the semiconductor die 106 on the semiconductor wafer 102 and the semiconductor die 108 on the semiconductor wafer 104 are aligned.

[0112] like Figure 5B As shown, semiconductor die 106 on semiconductor wafer 102 and semiconductor die 108 on semiconductor wafer 104 can be aligned for bonding. Semiconductor die 106 and semiconductor die 108 can be arranged so that bonding pads 232 on semiconductor die 106 and bonding pads 268 on semiconductor die 108 face each other and are generally aligned in the z-direction.

[0113] like Figure 5C As shown, the bonding operation includes bonding the semiconductor wafer 102 and the semiconductor wafer 104 such that the bonding layer 234 and the bonding layer 270 are bonded together in the edge region 402 and the non-edge region 404 of the semiconductor wafer 102 and the semiconductor wafer 104. Figure 5C As further shown, Figures 4A to 4U The described techniques for reconstructing the edge of semiconductor wafer 102 and / or reconstructing the edge of semiconductor wafer 104 enable bonding layer 234 and bonding layer 270 to be fully bonded across semiconductor wafers 102 and 104 .

[0114] like Figure 5D As shown, the bonding operation causes the semiconductor die 106 and the semiconductor die 108 to be bonded at the bonding interface 110, such that the semiconductor die 106 and the semiconductor die 108 are vertically aligned or stacked along the z-direction in the semiconductor device 100. The semiconductor die 106 and the semiconductor die 108 can be vertically aligned or stacked in a wafer-to-wafer (WoW) configuration, a die-to-wafer configuration, a die-to-die configuration, and / or another direct bonding configuration. The bonding operation can be performed using a bonding tool to bond the semiconductor die 106 and the semiconductor die 108 at the bonding interface 110. The bonding operation can include forming a direct bond between the semiconductor die 106 and the semiconductor die 108 by directly physically connecting the bonding pad 232 of the semiconductor die 106 to the bonding pad 268 of the semiconductor die 108, and by directly physically connecting the bonding layer 234 of the semiconductor die 106 to the bonding layer 270 of the semiconductor die 108.

[0115] like Figure 5D As further shown, Figures 4A to 4U The described techniques for reconstructing the edge of the semiconductor wafer 102 and / or reconstructing the edge of the semiconductor wafer 104 enable the bonding layer 234 and the bonding layer 270 to be fully bonded at the bonding interface 110 between the opposing edges of the semiconductor device 100 .

[0116] As mentioned above, 5A to 5D is provided as an example. Other examples may be 5A to 5D Different than described.

[0117] Figures 6A to 6F FIG2 is a schematic diagram of an example embodiment 600 of an edge reconstruction process described herein. The edge reconstruction process can be performed to reconstruct an edge region of a semiconductor wafer. Although example embodiment 600 is illustrated and described with respect to semiconductor wafer 102, the process technique of example embodiment 600 can be performed to reconstruct an edge of semiconductor wafer 104. Alternatively, the process technique of example embodiment 400 can be performed to reconstruct the edges of individual semiconductor dies 106 and / or individual semiconductor dies 108 for die-to-wafer bonding or die-to-die bonding.

[0118] like Figures 6A to 6F As shown, an example embodiment 600 of an edge reconstruction process is Figures 4A to 4U . However, in example embodiment 600, one or more semiconductor die 106 formed on semiconductor wafer 102 are at least partially located in edge region 402 of semiconductor wafer 102. Therefore, at least a portion of the slope (or edge roll-off) of semiconductor wafer 102 in edge region 402 occurs in one or more semiconductor die 106.

[0119] One or more semiconductor dies 106 located at least partially in the edge region 402 of the semiconductor wafer 102 may be referred to as edge dies. Figure 6A and Figure 6B As shown, a bonding layer 234 may be deposited on the semiconductor wafer 102. Figure 6C and Figure 6D As shown, the barrier layer 410 can be formed on the bonding layer 234 in the edge region 402 such that the barrier layer 410 is at least partially formed over the edge grains. Figure 6E and Figure 6F As shown, barrier layer 410 enables bonding layer 234 to be etched back and planarized so that the top surface of bonding layer 234 above the edge die is substantially coplanar with the top surfaces of semiconductor die 106 in the non-edge region 404 of semiconductor wafer 102. Barrier layer 410 is completely removed from over the edge die.

[0120] As mentioned above, Figures 6A to 6F is provided as an example. Other examples may be Figures 6A to 6F Different than described.

[0121] Figure 7 FIG. 7 is a schematic diagram of an example 700 of the semiconductor device 100 described herein. Figure 7As shown, the example 700 of the semiconductor device 100 is Figure 2 However, in example 700 , semiconductor device 100 includes semiconductor die 106 , wherein bonding layer 234 has a non-uniform thickness across bonding interface 110 , and / or includes semiconductor die 108 , wherein bonding layer 270 has a non-uniform thickness across bonding interface 110 .

[0122] The semiconductor die 106 is at least partially located in the edge region 402 of the semiconductor wafer 102. Figures 6A to 6F Therefore, the thickness of the bonding layer 234 on one side of the semiconductor die 106 (e.g., the side located in the edge region 402 of the semiconductor wafer 102) can be greater than the thickness of the bonding layer 234 at the center of the semiconductor die 106 and the opposite side of the semiconductor die 106 (e.g., located in the non-edge region 404 of the semiconductor wafer 102).

[0123] Additionally and / or alternatively, the semiconductor die 108 is at least partially located in the edge region 402 of the semiconductor wafer 104. Therefore, the thickness of the bonding layer 270 on one side of the semiconductor die 108 (e.g., the side located in the edge region 402 of the semiconductor wafer 104) can be greater than the thickness of the bonding layer 270 at the center of the semiconductor die 108 and the opposite side of the semiconductor die 108 (e.g., located in the non-edge region 404 of the semiconductor wafer 104).

[0124] and Figures 6A to 6F The described techniques for reconstructing the edge of the semiconductor wafer 102 and / or reconstructing the edge of the semiconductor wafer 104 enable the bonding layer 234 and the bonding layer 270 to be fully bonded across the entire bonding interface 110 between the opposing edges of the semiconductor device 100 .

[0125] As mentioned above, Figure 7 is provided as an example. Other examples may be Figure 7 Different than described.

[0126] Figure 8 FIG. 8 is a schematic diagram of an example 800 of the semiconductor device 100 described herein. Figure 8 As shown, the example 800 of the semiconductor device 100 is Figure 7106. However, in example 800, the semiconductor device 100 includes a semiconductor die 106 in which the thickness of the bonding layer 234 in an edge region 802 of the outer periphery of the semiconductor die 106 is greater than the thickness of the bonding layer 234 in a non-edge region 804 of the semiconductor die 106. Therefore, the thickness of the bonding layer 234 on the opposite side of the semiconductor die 106 is greater than the thickness of the bonding layer 234 in the center of the semiconductor die 106. This may be due to the fact that the semiconductor die 106 is manufactured separately, so that the edge region 802 of the outer periphery of the semiconductor die 106 is made of the same material as the semiconductor die 106. Figures 4A to 4U The reconstruction was performed using the techniques described above.

[0127] Additionally and / or alternatively, the semiconductor device 100 includes a semiconductor die 108 in which the thickness of the bonding layer 270 in an edge region 802 of the outer periphery of the semiconductor die 108 is greater than the thickness of the bonding layer 270 in a non-edge region 804 of the semiconductor die 108. Thus, the thickness of the bonding layer 270 on opposite sides of the semiconductor die 108 is greater than the thickness of the bonding layer 270 in the center of the semiconductor die 108. This may be due to the semiconductor die 108 being fabricated separately so that the edge region 802 of the outer periphery of the semiconductor die 108 is fabricated using the same Figures 4A to 4U The reconstruction was performed using the techniques described above.

[0128] As mentioned above, Figure 8 is provided as an example. Other examples may be Figure 8 Different than described.

[0129] Figure 9 is a flow chart of an example process 900 associated with reconstructing an edge region of a semiconductor wafer as described herein. In some embodiments, Figure 9 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, bonding tools, and / or other types of semiconductor processing tools.

[0130] like Figure 9 As shown, process 900 may include forming an electrically insulating layer on a surface of a semiconductor wafer (block 910). For example, as described herein, the electrically insulating layer (e.g., bonding layer 234) may be formed on a surface of a semiconductor wafer (e.g., semiconductor wafer 102) using one or more semiconductor processing tools. In some embodiments, a first portion of the electrically insulating layer is formed on an edge region (e.g., edge region 402) of the semiconductor wafer.

[0131] like Figure 9As further shown, process 900 may include forming a barrier layer on a first portion of the electrically insulating layer located on an edge region of the semiconductor wafer (block 920). For example, as described herein, the barrier layer (e.g., barrier layer 410) may be formed on the first portion of the electrically insulating layer located on an edge region of the semiconductor wafer using one or more semiconductor processing tools. In some embodiments, the barrier layer includes a photoresist material.

[0132] like Figure 9 As further shown, process 900 may include removing material from a second portion of the electrically insulating layer located on a non-edge region of the semiconductor wafer (block 930). For example, as described herein, one or more semiconductor processing tools may be used to remove material from the second portion of the electrically insulating layer located on a non-edge region of the semiconductor wafer (e.g., non-edge region 404). In some embodiments, the barrier layer protects the first portion of the electrically insulating layer while removing material from the second portion of the electrically insulating layer.

[0133] Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or embodiments related to one or more other processes described elsewhere herein.

[0134] In a first embodiment, forming the electrically insulating layer includes forming the electrically insulating layer such that a top surface of a first portion of the electrically insulating layer is higher in a vertical (z direction) height relative to a top surface of the semiconductor wafer than a bottom surface of a second portion of the electrically insulating layer.

[0135] In a second embodiment, alone or in combination with the first embodiment, forming the electrically insulating layer includes forming the electrically insulating layer using a precursor containing an orthosilicate material.

[0136] In a third embodiment, alone or in combination with one or more of the first and second embodiments, after removing material from the second portion of the electrically insulating layer, a top surface of the first portion of the electrically insulating layer and a top surface of the second portion of the electrically insulating layer are substantially coplanar.

[0137] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the photoresist material of the blocking layer includes a negative photoresist material.

[0138] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, forming the barrier layer includes forming the barrier layer such that a top surface of the barrier layer is substantially coplanar with, or is higher in vertical (z direction) height than, a top surface of the second portion of the electrically insulating layer.

[0139] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, removing material from the second portion of the electrically insulating layer includes etching the second portion of the electrically insulating layer and, after etching the second portion of the electrically insulating layer, planarizing the second portion of the electrically insulating layer.

[0140] Although Figure 9 Example blocks of process 900 are shown, but in some embodiments, process 900 includes more Figure 9 More blocks, fewer blocks, different blocks, or blocks in a different arrangement than those depicted. Additionally, or alternatively, two or more blocks of process 900 may be performed in parallel.

[0141] Figure 10 is a flow chart of an example process 1000 associated with forming a semiconductor device as described herein. In some embodiments, Figure 10 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0142] like Figure 10 As shown, process 1000 may include forming a bonding layer on a surface of a first semiconductor wafer (block 1010). For example, a bonding layer (e.g., bonding layer 234) may be formed on a surface of a first semiconductor wafer (e.g., semiconductor wafer 102) using one or more semiconductor processing tools, as described herein. In some embodiments, a first portion of the bonding layer is formed on an edge region (e.g., edge region 402) of the first semiconductor wafer.

[0143] like Figure 10 As further shown, process 1000 may include forming a first portion of a barrier layer on a first portion of the bonding layer located on an edge region of the first semiconductor wafer (block 1020). For example, a first portion (e.g., portion 410a, portion 410b) of a barrier layer (e.g., barrier layer 410) may be formed on the first portion of the bonding layer located on the edge region of the first semiconductor wafer using one or more semiconductor processing tools, as described herein. In some embodiments, the first portion of the barrier layer fills the first portion of the edge region. In some embodiments, the barrier layer comprises an epoxy-based material.

[0144] like Figure 10As further shown, process 1000 may include forming a second portion of the barrier layer on the first portion of the barrier layer (block 1030). For example, the second portion of the barrier layer (e.g., second portion 410b, second portion 410c) may be formed on the first portion of the barrier layer using one or more semiconductor processing tools, as described herein. In some embodiments, the second portion of the barrier layer fills the second portion of the edge region.

[0145] like Figure 10 As further shown, process 1000 may include removing material from the second portion of the bonding layer located on the non-edge region of the first semiconductor wafer after forming the first and second portions of the barrier layer (block 1040). For example, after forming the first and second portions of the barrier layer, material may be removed from the second portion of the bonding layer located on the non-edge region (e.g., non-edge region 404) of the first semiconductor wafer using one or more semiconductor processing tools, as described herein. In some embodiments, the barrier layer protects the first portion of the bonding layer while the material is removed from the second portion of the bonding layer. In some embodiments, after removing the material from the second portion of the bonding layer, the thickness of the first portion of the bonding layer (e.g., dimension D13) is greater than the thickness of the second portion of the bonding layer (e.g., dimension D12).

[0146] like Figure 10 As further shown, process 1000 may include bonding the first semiconductor wafer to the second semiconductor wafer using the bonding layer after removing material from the second portion of the bonding layer (block 1050). For example, after removing material from the second portion of the bonding layer, the first semiconductor wafer may be bonded to the second semiconductor wafer (e.g., semiconductor wafer 104) using one or more semiconductor processing tools, as described herein.

[0147] Process 1000 may include additional embodiments, such as any single embodiment or any combination of embodiments described herein and / or in connection with one or more other processes described elsewhere.

[0148] In a first embodiment, during the removal of material from the second portion of the bonding layer, the barrier layer is completely removed from the edge region of the first semiconductor wafer.

[0149] In a second embodiment, alone or in combination with the first embodiment, removing material from the second portion of the bonding layer includes etching the second portion of the bonding layer, and planarizing the second portion of the bonding layer after etching the second portion of the bonding layer, wherein during etching the second portion of the bonding layer, the barrier layer is completely removed from the edge region of the first semiconductor wafer.

[0150] In a third embodiment, alone or in combination with one or more of the first and second embodiments, a first lateral width (eg, dimension D6) of the first portion of the barrier layer is less than a second lateral width (eg, dimension D8) of the second portion of the barrier layer.

[0151] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming a first portion of the barrier layer includes depositing a photoresist layer (e.g., photoresist layer 408, photoresist layer 412) over a first semiconductor wafer, exposing a first portion of the photoresist layer in an edge region to radiation, and removing a second portion of the photoresist layer after exposing the first portion of the photoresist layer to radiation, wherein the first portion of the photoresist layer corresponds to the first portion of the barrier layer.

[0152] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming the second portion of the barrier layer includes depositing another photoresist layer (e.g., photoresist layer 412, photoresist layer 414) over the first semiconductor wafer, exposing a first portion of the another photoresist layer in the edge region to radiation, and removing the second portion of the another photoresist layer after exposing the first portion of the another photoresist layer to radiation, wherein the first portion of the another photoresist layer corresponds to the second portion of the barrier layer.

[0153] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1000 includes forming a third portion of the barrier layer (e.g., portion 410c) on the second portion of the barrier layer, wherein the third portion of the barrier layer fills a third portion of the edge region, and removing material from the second portion of the bonding layer includes removing material from the second portion of the bonding layer after forming the third portion of the barrier layer.

[0154] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the first lateral width of the second portion of the barrier layer (eg, dimension D8) is less than the second lateral width of the third portion of the barrier layer (eg, dimension D10).

[0155] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, forming the bonding layer includes forming the first bonding layer using a precursor containing an ester of orthosilicate acid.

[0156] In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, forming the bonding layer includes forming the first bonding layer using a precursor containing tetraethylorthosilicate (TEOS).

[0157] Although Figure 10 Example blocks of process 1000 are shown, but in some embodiments, process 1000 includes more Figure 10 More blocks, fewer blocks, different blocks, or blocks in a different arrangement may be shown. Additionally or alternatively, two or more blocks of process 1000 may be performed in parallel.

[0158] In this way, a thick bonding layer is formed on the surface of the semiconductor wafer so that the top surface of the bonding layer in the edge region (there may be edge roll-off) is located at a vertical height higher than the bottom surface of the bonding layer in the non-edge region of the semiconductor wafer. Then a photoresist material is deposited on the entire surface of the semiconductor wafer and patterned so that the photoresist material only remains on the edge region of the semiconductor wafer. The photoresist material is used to etch the bonding layer. The bonding layer is formed so that the top surface of the bonding layer in the edge region is located at a vertical height higher than the bottom surface of the bonding layer in the non-edge region of the semiconductor wafer, which makes it possible to etch the bonding layer in the non-edge region according to the photoresist material, thereby making the top surface of the bonding layer substantially flat and uniform across the edge region and the non-edge region of the semiconductor wafer. In other words, a bonding layer of sufficient thickness is formed in the edge region so that the bonding layer in the non-edge region can be thinned, thereby after etching the bonding layer, there is almost no or no slope in the edge region.

[0159] As described in more detail above, some embodiments described herein provide a method. The method includes forming an electrically insulating layer on a surface of a semiconductor wafer, wherein a first portion of the electrically insulating layer is formed on an edge region of the semiconductor wafer. The method includes forming a barrier layer on the first portion of the electrically insulating layer located on the edge region of the semiconductor wafer, wherein the barrier layer comprises a photoresist material. The method includes removing material from a second portion of the electrically insulating layer located on a non-edge region of the semiconductor wafer, wherein the barrier layer protects the first portion of the electrically insulating layer while removing material from the second portion of the electrically insulating layer.

[0160] As described in more detail above, some embodiments described herein provide a method. The method includes forming a bonding layer on a surface of a first semiconductor wafer, wherein a first portion of the bonding layer is formed on an edge region of the first semiconductor wafer. The method includes forming a first portion of a barrier layer on the first portion of the bonding layer located on the edge region of the first semiconductor wafer, wherein the first portion of the barrier layer fills the first portion of the edge region. The method includes forming a second portion of the barrier layer on the first portion of the barrier layer, wherein the second portion of the barrier layer fills the second portion of the edge region. The method includes, after forming the first and second portions of the barrier layer, removing material from the second portion of the bonding layer located on a non-edge region of the first semiconductor wafer, wherein the barrier layer protects the first portion of the bonding layer when removing material from the second portion of the bonding layer, and after removing material from the second portion of the bonding layer, the thickness of the first portion of the bonding layer is greater than the thickness of the second portion of the bonding layer. The method includes, after removing material from the second portion of the bonding layer, bonding the first semiconductor wafer to the second semiconductor wafer using the bonding layer.

[0161] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first semiconductor grain. The semiconductor device includes a second semiconductor grain bonded to the first semiconductor grain at a bonding interface, such that the first semiconductor grain and the second semiconductor grain are vertically aligned in the semiconductor device. The bonding interface includes a first bonding layer of the first semiconductor grain directly bonded to a second bonding layer of the second semiconductor grain. At least one of the first bonding layer and the second bonding layer has a non-uniform thickness across the bonding interface. The first bonding layer and the second bonding layer are fully bonded at the bonding interface between opposite edges of the semiconductor device. In some embodiments, a first thickness of the first bonding layer in an edge region of the semiconductor device is greater than a second thickness of the first bonding layer in a non-edge region of the semiconductor device. In some embodiments, a third thickness of the second bonding layer in an edge region of the semiconductor device is greater than a fourth thickness of the second bonding layer in a non-edge region of the semiconductor device.

[0162] The terms "approximately" and "substantially" can mean that the value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It should be understood that, in accordance with the present disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0163] The foregoing summarizes the features of multiple embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It will be appreciated by those skilled in the art that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or obtain the same advantages of the embodiments described herein. It will also be appreciated by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that: include: forming an electrically insulating layer on the surface of the semiconductor wafer, wherein a first portion of the electrically insulating layer is formed on an edge region of the semiconductor wafer; forming a barrier layer on the first portion of the electrically insulating layer located on the edge region of the semiconductor wafer, wherein the barrier layer comprises a photoresist material; as well as removing material from a second portion of the electrically insulating layer located on a non-edge area of the semiconductor wafer, wherein the barrier layer protects the first portion of the electrically insulating layer while the material is removed from the second portion of the electrically insulating layer.

2. The method according to claim 1, characterized in that Forming the electrical insulation layer includes: The electrically insulating layer is formed such that a top surface of the first portion of the electrically insulating layer is located at a higher vertical height relative to a top surface of the semiconductor wafer than a bottom surface of the second portion of the electrically insulating layer.

3. The method according to claim 2, characterized in that After removing the material of the second portion of the electrically insulating layer, the top surface of the first portion of the electrically insulating layer and the top surface of the second portion of the electrically insulating layer are substantially coplanar.

4. The method according to claim 1, wherein The photoresist material of the blocking layer includes a negative photoresist material.

5. A method for forming a semiconductor device, characterized in that: include: forming a bonding layer on a surface of a first semiconductor wafer, wherein the first portion of the bonding layer is formed on an edge region of the first semiconductor wafer; forming a first portion of a barrier layer on the first portion of the bonding layer located on the edge region of the first semiconductor wafer, wherein the first portion of the barrier layer fills a first portion of the edge region; forming a second portion of the barrier layer on the first portion of the barrier layer, wherein the second portion of the barrier layer fills a second portion of the edge region; After forming the first and second portions of the barrier layer, removing the material of the second portion of the bonding layer located on the non-edge region of the first semiconductor wafer, wherein the barrier layer protects the first portion of the bonding layer when the material is removed from the second portion of the bonding layer, and wherein after removing the material from the second portion of the bonding layer, the thickness of the first portion of the bonding layer is greater than the thickness of the second portion of the bonding layer; as well as After removing the material from the second portion of the bonding layer, the first semiconductor wafer is bonded to a second semiconductor wafer using the bonding layer.

6. The method according to claim 5, characterized in that The barrier layer comprises an epoxy-based material; and During the removal of the material from the second portion of the bonding layer, the barrier layer is completely removed from the edge region of the first semiconductor wafer.

7. The method according to claim 5, characterized in that A first lateral width of the first portion of the barrier layer is less than a second lateral width of the second portion of the barrier layer.

8. The method according to claim 5, characterized in that Forming the first portion of the barrier layer includes: depositing a photoresist layer on the first semiconductor wafer; exposing a first portion of the photoresist layer in the edge region to radiation; and removing a second portion of the photoresist layer after exposing the first portion of the photoresist layer to the radiation, The first portion of the photoresist layer corresponds to the first portion of the barrier layer.

9. The method according to claim 5, characterized in that Also includes: forming a third portion of the barrier layer on the second portion of the barrier layer, wherein the third portion of the barrier layer fills a third portion of the edge region, and Wherein removing the material from the second portion of the bonding layer comprises: After forming the third portion of the barrier layer, the material is removed from the second portion of the bonding layer.

10. A semiconductor device, characterized in that: include: a first semiconductor grain; as well as a second semiconductor grain bonded to the first semiconductor grain at a bonding interface, such that the first semiconductor grain and the second semiconductor grain are vertically aligned in the semiconductor device; Wherein the bonding interface comprises: a first bonding layer of the first semiconductor crystal grain directly bonded to the second bonding layer of the second semiconductor crystal grain, wherein at least one of the first bonding layer or the second bonding layer has a non-uniform thickness at the bonding interface, and The first bonding layer and the second bonding layer are fully bonded across the entire bonding interface between opposite edges of the semiconductor device.

Images